JP2009272964A - Communication system, host, client, phone body of cellular phone, battery and communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for transmitting/receiving data while preventing power consumption from being increased. <P>SOLUTION: An address signal is transmitted and detected between a host circuit 4 and a plurality of client circuits 6<SB>1</SB>-6<SB>m</SB>, at a first communication speed receivable for a client circuit 6<SB>slow</SB>having a lowest maximum communication speed. Data are transmitted/received between the host circuit 4 and the client circuit 6<SB>a</SB>designated by the address signal, at a maximum communication speed of the client circuit 6<SB>a</SB>. For example, therefore, a client circuit 6<SB>small</SB>with a small volume of communication with the host circuit 4 can transmit and receives data to and from the host at a low communication speed, and a client circuit 6<SB>large</SB>with a large volume of communication with the host circuit 4 can transmit and receive data to and from the host circuit 4 at a high communication speed. Thus, the time required for transmitting/receiving data is shortened while preventing power consumption of the client circuits 6<SB>1</SB>-6<SB>m</SB>, for example, from being increased. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to, for example, a communication system that performs communication between a host and a client, a host, a client, a telephone body of a mobile phone, a battery, and a communication method.

Conventionally, as this type of technology, for example, there is a communication system that transmits and receives data between a host and a client via a single communication line (see, for example, Patent Document 1).
In the communication system described in Patent Document 1, each of a host and a client includes a clock supply circuit that supplies a clock signal having an equal period.
When the host transmits a bit value “0” to the client, the potential of the communication line is set to a high potential over a period of three cycles with the clock signal supplied from its own clock supply circuit. Control. In addition, when the host transmits a bit value “1” to the client, the potential of the communication line is set to a high potential over a period of seven cycles using a clock signal supplied from its own clock supply circuit. Control.

In addition, when the client detects that the potential of the communication line has continued to be a High potential for a period of three cycles with the clock signal supplied from its own clock supply circuit, the client receives a bit value “0” from the host. It is determined that In addition, when the client detects that the potential of the communication line has continued to be a high potential for a period of 7 cycles with the clock signal supplied from its own clock supply circuit, the client receives a bit value “1” from the host. It is determined that
JP 2007-36671 A

  However, in the above-described conventional communication system, the client determines the bit value transmitted from the host by detecting the time during which the potential of the bus 7 continues to be high based on the period of the clock signal. It is like that. Therefore, for example, when a plurality of clients are connected to a communication line and data can be transmitted from the host to an arbitrary client, the cycle of the clock signal supplied to the host and the clock signal supplied to the client are It is conceivable that the period of the generated clock signal is set to the same period in the clock generation circuits of all clients so that the period is equal.

  However, if the period of the clock signal of all clients is set to the same period, for example, all clients are uniformly matched to clients that require a large communication volume and a high communication speed. When a clock signal with a short cycle (that is, a clock signal with a high clock frequency) is used, there is a possibility that power consumption will increase unnecessarily for a client that does not require a high communication speed.

In addition, when a clock with a uniformly long period (that is, a clock signal with a low clock frequency) is used for all clients in accordance with a client that has a small amount of communication with the host and does not require a high communication speed, A client having a large amount of communication may increase the time required for communication.
The present invention has been made in view of the above-described conventional technology. For example, a communication system, a host, a client, and a mobile phone that can reduce the time required for data transmission and reception while preventing an increase in power consumption of the client. It is an object to provide a telephone body, a battery, and a communication method.

In order to solve the above problem, the first invention is:
A communication system comprising a host, a plurality of clients, and a common line serving as a communication path between the host and the plurality of clients, the plurality of clients including clients having different communication speeds; The host sends an address signal for sending to the common line an address signal designating at least one of the plurality of clients at a first communication speed that can be received by a client having the slowest communication speed among the plurality of clients. And a host that transmits and receives data via the common line with the client at a second communication speed that can be received by the client and the client specified by the address signal after transmission of the address signal is completed. Communication means, and each of the plurality of clients includes the common license. When the address signal detection means for detecting the address signal sent to the first communication speed, and the address signal detected by the address signal detection means is an address signal for designating the own client, And a client communication means for transmitting and receiving the data via the common line with the host at a communication speed of 2.

In addition, the second invention,
The first communication speed is a communication speed that can be received by a client having the slowest maximum communication speed among the plurality of clients.
According to such a configuration, for example, a client with a small amount of communication with the host can transmit and receive data with the host at a low communication speed, and a client with a large amount of communication with the host has a high communication speed with the host. May be able to send and receive data.
As a result, for example, data transmission / reception between the host and the client can be shortened compared to a method in which all clients perform the same communication speed, while reducing the time required for data transmission / reception while preventing an increase in power consumption of the client. there is a possibility.

Furthermore, the third invention
The host is a time for transmitting 1 bit from the host to the client having the lowest communication speed through the common line at the first communication speed prior to sending the address signal. And a first time setting signal sending means for sending a first time setting signal continuously to the common line, and the address signal sending means after the sending of the first time setting signal is completed. Each bit value of the address signal is sequentially sent to the common line for each of the first communication times, and the address signal detection means of each of the plurality of clients is configured to send the first time setting signal to the common line. First signal transmission time measuring means for measuring the time during which the signal is transmitted, and after the time measurement by the first signal transmission time measuring means is completed, the first signal transmission time measuring means In in synchronization with the measured time, characterized in that and an address signal bit value detecting means for sequentially detecting the bit value of the address signal sent to the common line.

In addition, the fourth invention is
Each of the plurality of clients includes client clock signal generation means for generating a clock signal, and the first signal transmission time measurement means of each of the plurality of clients is configured to transmit the first time setting signal to the common line. Is counted, the clock signal pulse generated by the client clock signal generating means of the own client is counted,
The address signal bit value detecting means of each of the plurality of clients has the number of pulses counted by the first signal sending time measuring means after the counting of pulses by the first signal sending time measuring means of its own client is completed. The bit value of the address signal sent to the common line is sequentially detected based on the above.
According to such a configuration, for example, there is a possibility that transmission and detection of an address signal between the host and the client can be performed more appropriately at the first communication speed.

Furthermore, the fifth invention provides
The host sends an address reference signal serving as a reference for sending the address signal to the common line after sending the first time setting signal and before sending the address signal. Reference signal transmission means is provided, and the address signal bit value detection means of each of the plurality of clients detects the first signal transmission time of its own client from the time when the address reference signal transmitted to the common line is detected. The bit value of the address signal sent to the common line is sequentially detected in synchronization with the time corresponding to the number of pulses counted by the means.
According to such a configuration, for example, there is a possibility that the client can accurately detect an address signal transmitted from the host.

In addition, the sixth invention,
After the host finishes sending the address signal, the client designates 1 bit by the address signal from the host via the common line at the second communication speed prior to transmission / reception of the data. A second communication time which is a time when transmitting to a second communication time, a second time setting signal sending means for sending a second time setting signal continuously to the common line,
After the transmission of the second time setting signal is completed, the host communication unit sequentially transmits each bit value of the data to the common line for the second communication time, and each of the plurality of clients The client communication means includes: a second signal sending time measuring means for measuring a time during which the second time setting signal is sent to the common line; and a time measurement by the second signal sending time measuring means. Data bit value detecting means for sequentially detecting the bit values of the data sent to the common line in synchronization with the time measured by the second signal sending time measuring means after completion. Features.

Furthermore, the seventh invention
Each of the plurality of clients includes client clock signal generation means for generating a clock signal, and the second signal transmission time measurement means of each of the plurality of clients is configured to transmit the second time setting signal to the common line. Is transmitted, the data bit value detection means of each of the plurality of clients is configured to count the pulses of the clock signal generated by the client clock signal generation means of the client. After the pulse counting by the signal sending time measuring means is completed, the bit value of the data sent to the common line is sequentially detected based on the number of pulses counted by the second signal sending time measuring means. Features.
According to such a configuration, for example, there is a possibility that data transmission / reception between the host and the client can be performed more appropriately at the second communication speed.

Further, the eighth invention is
A data reference signal for sending a data reference signal serving as a reference for sending the data to the common line after starting sending the data after finishing sending the second time setting signal. The address signal bit value detecting means of each of the plurality of clients is detected by the second signal sending time measuring means of its own client from the time when the data reference signal sent to the common line is detected. The bit value of the data sent to the common line is sequentially acquired in synchronization with the time corresponding to the counted number of pulses.
According to such a configuration, for example, there is a possibility that the client can accurately detect data transmitted from the host.

Furthermore, the host of the ninth invention is:
Address signal sending means for sending an address signal designating at least one of the plurality of signals to a common line serving as a communication path with the plurality of clients at a first communication speed that can be received by the slowest client. And a host communication means for transmitting / receiving data to / from the client via the common line at a second communication speed that can be received by the client designated by the address signal after the transmission of the address signal is completed, It is characterized by including.

The client according to the tenth invention is
An address sent to a common line serving as a communication path between the host, another client, and the own client at a first communication speed that can be received by the client having the slowest communication speed among the other clients and the own client An address signal detecting means for detecting a signal at the first communication speed; and an address signal detected by the address signal detecting means is an address signal for designating the own client; And a client communication means for transmitting and receiving data via the common line with the host at the communication speed.

Furthermore, the telephone body of the mobile phone according to the eleventh invention is
A host, a common wiring that is a communication path of a plurality of clients, and a main body wiring that is a communication path between the hosts, and the host receives an address signal that specifies at least one of the plurality of clients. An address signal sending means for sending to the internal wiring and a second communication speed that can be received by the client designated by the address signal after the sending of the address signal is completed via the common line with the client. And host communication means for transmitting and receiving data.

The battery according to the twelfth invention is
A first client capable of communicating with a host at a first communication speed; and a second client capable of communicating with the host at a second communication speed higher than the first communication speed; A first address signal detecting unit configured to receive, at the first communication speed, an address signal for designating one of the first client and the second client from the host; First communication means for receiving data from the host at the first communication speed, wherein the second client receives the address signal at the first communication speed. An address signal detection means and a second communication means for receiving data from the host at the second communication speed are provided.

Furthermore, a communication method according to a thirteenth invention is
A communication method between a host and a plurality of clients that can communicate with each other via a common line serving as a communication path, and when the plurality of clients include those having different communication speeds, An address signal sending step of sending an address signal designating at least one of the plurality of clients to the common line at a first communication speed that can be received by a client having the slowest communication speed among the plurality of clients; Each of the clients detects the address signal transmitted to the common line at the first communication speed, and determines whether or not the detected address signal is an address signal designating its own client. After the detection step and the detection of the address signal, the host and the address signal are used. And the specified client via the common line, and executes a communication step of transmitting and receiving data at a second communication rate the client can receive.

In addition, the fourteenth invention
When the communication speed of each of the plurality of clients is different,
In the address signal sending step, the host is at least one of the plurality of clients at a third communication speed that can be received by the first client that is the slowest communication speed among all of the plurality of clients. When the client specified by the address signal is the first client in the communication step, the host and the client specified by the address signal are sent. Perform communication at the third communication speed via the common line, and the client specified by the address signal is a client other than the first client, the host and the address signal The common client and the specified client Through, and performs communication with the third higher communication speed than the communication speed of.

Furthermore, the fifteenth invention
When the plurality of clients include a first client and a second client capable of communicating at a third communication speed as clients having the slowest communication speed among the plurality of clients, the address signal sending step The host sends an address signal designating at least one of the plurality of clients at the third communication speed, and in the address signal detecting step, each of the plurality of clients is connected to the common line. The sent address signal is detected at the third communication speed.

In addition, the sixteenth invention
As the plurality of clients, a first client capable of communicating at a third communication speed with the slowest communication speed among the plurality of clients, and a fourth communication speed next to the third communication speed. The address signal sending step includes a second client capable of communicating at a communication speed, wherein the first client is in an inactive state and the second client is in an active state. The address signal is transmitted at a third communication speed, and in the address signal detection step, each of the plurality of clients detects the address signal transmitted to the common line at the third communication speed. Features.

Furthermore, the seventeenth invention
As the plurality of clients, a first client capable of communicating at a third communication speed with the slowest communication speed among the plurality of clients, and a fourth communication speed next to the third communication speed. Including a second client capable of communicating at a communication speed, wherein the first client is in an inactive state and the second client is in an active state, the address signal sending step includes: The address signal is transmitted at a fourth communication speed, and in the address signal detection step, each of the plurality of clients detects the address signal transmitted to the common line at the fourth communication speed. Features.

The eighteenth invention
The first communication speed is a communication speed that can be received by a client having the slowest maximum communication speed among the plurality of clients.
Furthermore, the nineteenth invention
Prior to the address signal sending step, a time when the host transmits 1 bit from the host to the client with the slowest communication speed through the common line at the first communication speed is a first time Communication time, a first time setting signal sending step for continuously sending a first time setting signal to the common line, and after the first time setting signal sending step and before the address signal sending step, Each of a plurality of clients executes a first signal transmission time measuring step of measuring a time during which the first time setting signal is transmitted to the common line, and in the address signal transmitting step, the host However, after the transmission of the first time setting signal is completed, each bit value of the address signal is sequentially transferred to the common line by the second communication time. In the address signal detection step, the time measured in the first signal transmission time measurement step after each of the plurality of clients has finished measuring the time in the first signal transmission time measurement step. The bit value of the address signal sent to the common line is sequentially detected in synchronization with the above.

In addition, the twentieth invention
After the address signal sending step and before the communication step, after the host finishes sending the address signal, 1 bit is sent from the host to the address via the common line at the second communication speed. A second communication time which is a time for transmission to the client designated by the signal, a second time setting signal sending step for sending a second time setting signal continuously to the common line, and the second time setting. A second signal transmission time measuring step in which each of the plurality of clients measures a time during which the second time setting signal is transmitted to the common line after the signal transmission step and before the communication step; In the communication step, after the host finishes sending the second time setting signal, each of the bit values of the data is sequentially The second communication time is sent to the common line, and after each of the plurality of clients has finished measuring the time in the second signal sending time measuring step, the second signal sending time measuring step The bit values of the data transmitted to the common line are sequentially detected in synchronization with the measured time.

According to such a configuration, for example, a client with a small amount of communication with the host can transmit and receive data with the host at a low communication speed, and a client with a large amount of communication with the host has a high communication speed with the host. May be able to send and receive data.
As a result, for example, data transmission / reception between the host and the client can be shortened compared to a method in which all clients perform the same communication speed, while reducing the time required for data transmission / reception while preventing an increase in power consumption of the client. there is a possibility.

Embodiments of the present invention will be described below.
In the present embodiment, an example in which the present invention is applied to a mobile phone will be described.
<1-1. About schematic configuration of communication system>
First, a schematic configuration of the mobile phone 1 of the present embodiment will be described.
FIG. 1 is a configuration diagram showing a schematic configuration of the mobile phone 1.
The mobile phone 1 has a phone body 2 and a rechargeable battery 5.
Telephone body 2 includes a host CPU (Central Processing Unit) 3 and the host circuit 4, having the wiring 7 _first body.

The host CPU 3 performs arithmetic processing for realizing various functions such as a call function, a data communication function, and a state management function of the mobile phone 1 itself.
Further, in the arithmetic processing, the host CPU 3 outputs a command for causing the host circuit 4 to communicate with a plurality of client circuits 6 _{1 to} 6 _m (described later) included in the rechargeable battery 5.
The host circuit 4 executes host control processing. The host control process, the host circuit 4 according to the instruction from the host CPU 3, transmission and reception of data between a plurality of client circuits 6 ₁ to 6 _m through a body wire 7 ₁ and the charging Ikeuchi wire 7 ₂ (described later) I do.

The host circuit 4 is broadly defined as “reset signal sending means” “address signal sending means” “host communication means” “first time setting signal sending means” “address reference signal sending means” “second time setting signal”. It constitutes "sending means", "data reference signal sending means", "time setting signal sending means" and "data bit value detecting means".
The wiring 7 _first body has one end connected to the host circuit 4, the other end is connected to the communication terminal of the battery housing portion in the telephone body 2 (not shown) (not shown).
The rechargeable battery 5 is housed in the rechargeable battery housing portion of the telephone body 2 and supplies the stored power to the telephone body 2.
The rechargeable battery 5 has a rechargeable battery wiring 7 ₂ , a pull-up circuit 9, and a plurality of client circuits 6 _{1 to} 6 _m (m is an integer of 2 or more).

Charging Ikeuchi wire 7 ₂ has one end connected to each of the plurality of client circuits 6 ₁ to 6 _m, the other end is connected to the rechargeable battery 5 outer surface communication terminals (not shown).
The communication terminal of the rechargeable battery 5 is formed at a position in contact with the communication terminal of the telephone body 2 when the rechargeable battery 5 is stored in the rechargeable battery storage portion of the telephone body 2.
Therefore, by storing the rechargeable battery 5 in the rechargeable battery storage portion of the telephone body 2, the communication terminal of the telephone body 2 and the communication terminal of the rechargeable battery 5 are connected. When the communication terminal of the telephone body 2 and the communication terminal of the rechargeable battery 5 are connected, the main body wiring 7 ₁ , the communication terminal of the telephone main body 2, the communication terminal of the rechargeable battery 5 and the rechargeable battery wiring 7 ₂ are used. A single communication path is formed between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m .

Hereinafter, this communication path is referred to as a bus 7 (“common line” in a broad sense).
Note that each of the in-main body wiring 7 ₁ , the communication terminal of the telephone body 2, the communication terminal of the rechargeable battery 5, and the rechargeable battery wiring 7 ₂ is formed of a conductor. Therefore, the bus 7 is also formed of a conductor.
Pull-up circuit 9 is constituted by connecting through a pull-up resistor ₈₂ to power supply ₈₁ for supplying a High potential to the charging Ikeuchi wiring 7 _2.
Here, the High potential is the same potential as the High potential set on the bus 7 (described later) when data is transmitted and received between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m .

Each of the plurality of client circuits 6 _{1 to} 6 _m detects various types of information related to the state of the rechargeable battery 5 such as the remaining battery capacity, the number of times of charging, and the temperature of the rechargeable battery 5.
Each of the plurality of client circuits 6 _{1 to} 6 _m executes a client control process. In the client control process, each of the plurality of client circuits 6 _{1 to} 6 _m transmits and receives data to and from the host circuit 4 via the bus 7.
Each of the plurality of client circuits 6 _{1 to} 6 _m is broadly defined as “reset signal detecting means” “address signal detecting means” “client communication means” “first signal transmission time measuring means” “address signal bit value”. It constitutes "detection means", "second signal transmission time measurement means", "data bit value detection means", and "signal transmission time measurement means".
An address is set in each of the plurality of client circuits 6 _{1 to} 6 _m .

In the mobile phone 1 of the present embodiment, the host circuit 4, the plurality of client circuits 6 _{1 to} 6 _m, and the bus 7 are connected to the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m via the bus 7. The communication system which transmits / receives data between is comprised.
The cellular phone 1 does not include a dedicated signal line for synchronizing the clock signal between the host circuit 4 and each of the plurality of client circuits 6 _{1 to} 6 _m . That is, the host circuit 4 and each of the plurality of client circuits 6 _{1 to} 6 _m have their own clock generation means, and communicate according to the clock signal generated by the unique clock generation means.

In the present embodiment, an example in which the bus 7 by the internal wiring 7 _first body and the charging Ikeuchi wiring 7 ₂ are connected via a communication terminal of the rechargeable battery 5 and the communication terminal of the telephone main body 2 Although shown, it is not limited to this. For example, another wiring or conductor may be interposed between the communication terminal of the telephone body 2 and the communication terminal of the rechargeable battery 5.
Moreover, although the example using the rechargeable battery 5 was shown as an object to which the power supply source to the telephone body 2 and the plurality of client circuits 6 _{1 to} 6 _m are attached, the present invention is not limited thereto. For example, a primary battery that cannot be charged may be used.

Furthermore, although an example of connecting the power supply 8 ₁ supplies High potential to body wiring ₇₁ is not limited thereto. For example, power source ₈₁ may be one supplying a Low potential.
Further, as a power supply for the pull-up circuit 9, an example of using the power supply ₈₁ independent, is not limited thereto. For example, using the power stored in the rechargeable battery 5, instead of the power supply ₈₁ may be used in which the rechargeable battery 5 by lowering the available supply voltage.
Furthermore, although the example which mounts the pull-up circuit 9 in the rechargeable battery 5 was shown, it is not restricted to this. For example, the pull-up circuit 9 may be mounted on the telephone body 2. When mounting the pull-up circuit 9 to the telephone main body 2, which utilizes a constant voltage source for supplying power to the host circuit 4, instead of the power source _81, the constant voltage source by stepping down the voltage supplied May be used.

Furthermore, in this embodiment, the descriptions “High potential” and “Low potential” are used everywhere, but these are only examples. For example, even if the descriptions of “High potential” and “Low potential” in the present embodiment are interchanged with each other, there is a possibility that the communication system of the present embodiment can be configured.
Moreover, although the example which forms the bus | bath 7 with a conducting wire was shown, it is not restricted to this. The bus may be a communication path that can take two states corresponding to a low potential and a high potential. For example, an optical cable or a wireless communication circuit may be used.
Furthermore, although an example in which a plurality of client circuits 6 _{1 to} 6 _m are connected to the bus 7 has been shown, the present invention is not limited to this. For example, there may be one client circuit.

<1-2. Outline of operation of communication system>
Next, an outline of the operation of the communication system of the present embodiment will be described using the above-described schematic configuration.
First, the host circuit 4 executes host control processing. When the host CPU 3 outputs a command for sending data to the client circuit 6 _a (a is any number from 1 to m) from the host CPU 3 to the host circuit 4 during execution of the host control process, the host circuit 4 Sends a reset signal to the bus 7.
Here, the reset signal is a signal that causes each of the plurality of client circuits 6 _{1 to} 6 _m to detect an address signal (described later) sent to the bus 7 after the reset signal.

In this embodiment, a communication register reset signal and a hardware reset signal, which will be described later, are used as the reset signal.
The host circuit 4 sends an address signal to the bus 7 after finishing sending the reset signal.
Here, the address signal is a signal for designating the address of the client circuit _6a .
The speed at which the address signal is transmitted from the host circuit 4 to the client circuit _6a (that is, the speed at which the address signal is transmitted from the host circuit 4 to the bus 7) is the maximum communication specified among the plurality of client circuits 6 _{1 to} 6 _m. This is the first communication speed at which the slowest client circuit 6 _slow (slow is any one of 1 to n) can be received.

In other words, the first communication speed is the slowest communication speed among the communication speeds of the plurality of client circuits 6 _{1 to} 6 _m .
Here, the prescribed maximum communication speed is 1 bit determined from the frequency of the clock signal of the host circuit 4 and the frequency of the clock signals of the client circuits 6 _{1 to} 6 _m connected to the host circuit 4. It is calculated by the time required for the communication process.
In the present embodiment, the prescribed maximum communication speed is based on the frequency of the clock signal of the host circuit 4 and the frequency of the clock signal of each of the client circuits 6 _{1 to} 6 _m connected to the host circuit 4. Although the example using what is calculated was shown, it is not restricted to this. For example, the maximum communication speed defined in the specification can be used.

The address signal is transmitted from the host circuit 4 to the bus 7 by the host circuit 4 controlling the potential of the bus 7 according to the bit value of the address specified by the address signal.
Specifically, the address signal is sent from the host circuit 4 to the bus 7 by sequentially applying the potential corresponding to each bit value of the address signal to 1 GBT (when performing 1-bit communication processing at the first communication speed). This is done by outputting to the bus 7 in increments of 1 GlobalBitTime).

In other words, 1 GBT is a time when 1 bit is transmitted from the host circuit 4 to the slowest client circuit 6 _slow via the bus 7 at the first communication speed.
The time required for 1-bit communication processing is, for example, that the host circuit 4 prepares for data transmission, sends 1-bit data from the host circuit 4 to the bus 7, and the data on the bus 7 is determined (stable). The time required for the entire period of the 1-bit communication cycle in which the client circuit 6 _slow takes in data from the bus 7.

The high potential is used as the potential corresponding to the bit value “1” of the address signal, and the low potential is used as the potential corresponding to the bit value “0” of the address signal.
The same applies to potentials “High potential” and “Low potential” corresponding to bit values “1” and “0” of other signals, instructions, and data.
In this embodiment, a high potential is used as the potential corresponding to the bit value “1” of the signal, command and data, and a low potential is used as the potential corresponding to the bit value “0” of the signal, command and data. Although shown, it is not limited to this. For example, a low potential may be used as the potential corresponding to the bit value “1” of the signal, command and data, and a high potential may be used as the potential corresponding to the bit value “0” of the signal, command and data.

On the other hand, each of the plurality of client circuits 6 _{1 to} 6 _m executes client control processing. When the client control process is executed, each of the plurality of client circuits 6 _{1 to} 6 _m starts detecting a reset signal sent from the host circuit 4 to the bus 7.
Further, when each of the plurality of client circuits 6 _{1 to} 6 _m detects a reset signal sent to the bus 7, it starts detecting an address signal sent from the host circuit 4 to the bus 7 after the reset signal.

Further, when each of the plurality of client circuits 6 _{1 to} 6 _m detects the address signal sent to the bus 7 at the first communication speed, the address designated by the detected address signal matches the address of its own circuit. It is determined whether or not.
The detection of the address signal from the bus 7 by each of the plurality of client circuits 6 _{1 to} 6 _m is performed when the client circuits 6 _{1 to} 6 _m detect a change in the potential of the bus 7.
When the detection and determination of the address signal by each of the plurality of client circuits 6 _{1 to} 6 _m is completed, data transmission / reception is started between the host circuit 4 and the client circuit 6 _a via the bus 7. Rate that the host circuit 4 and the client circuit 6 _a performs the transmission and reception of data is a second communication speed is the maximum transmission speed of the client circuit 6 _a.

In the present embodiment, as the second communication speed, although an example of using the maximum communication speed of the client circuit 6 _a, is not limited thereto. For example, when the client circuit 6 _a specified by the address signal is the slowest client circuit 6 _slow , the maximum communication speed is used as the second communication speed, and the client circuit 6 _a uses the other client circuit 6 _fast ( If fast is any number from 1 to m), a communication speed that is equal to or lower than the maximum communication speed of the client circuit 6 _fast and faster than the first communication speed may be used as the second communication speed. .
The transmitting and receiving data between the host circuit 4 and a client circuit 6 _a is either one of the host circuits 4 and client circuit 6 _a controls the potential of the bus 7 in response to the bit value of the data is transmitted , carried by the other host circuit 4 and the client circuit 6 _a detects a change in potential of the bus 7 in response to the bit value of the data.

Specifically, the transmission of data from either the host circuit 4 and the client circuits 6 _a to the other host circuit 4 and the client circuit 6 _a sequentially a potential corresponding to each bit value of the data, 1CBT ( performed by the second host circuit 4 and a client circuit 6 via the bus 7 in the communication speed of _a is output to the time at which 1ClientBitTime) by bus 7 required when performing 1-bit communication process.
In other words, 1 CBT is the time when 1 bit is transmitted from the host circuit 4 to the client circuit 6 _a via the bus 7 at the second communication speed.
Note that 1 ClientBitTime, which is the time required for the host circuit 4 and the client circuit 6 _a to perform 1-bit communication processing via the bus 7 at the second communication speed, is hereinafter also referred to as 1 CBT of the client circuit 6 _a .

<2-1. Configuration of host circuit 4>
Next, the configuration of the host circuit 4 will be described.
FIG. 2 is a block diagram showing the internal configuration of the host circuit.
As shown in FIG. 2, the host circuit 4 includes a main body I / O 10, a host control unit 11, a bus I / O 12, and a clock generation unit 13.
The host control unit 11 includes a CPU communication unit 14, a control command generation unit 15, a bus communication unit 16, and a power supply control unit 17.

The CPU communication unit 14 acquires a command from the host CPU 3 via the main body I / O 10 and outputs the acquired command to the control command generation unit 15.
In addition, when data is output from the control command generation unit 15 to the CPU communication unit 14, the CPU communication unit 14 outputs the output data to the host CPU 3.
The control command generation unit 15 generates a signal, a command, and data (for example, a reset signal, an address signal) for realizing the command in accordance with a command output from the CPU communication unit 14, and the generated signal, command, and data Is output to the bus communication unit 16.

The control command generation section 15, the detection result from the bus communication unit 16 of the bus 7 potential is output, based on the change in the potential to detect the data transmitted from the client circuit 6 _a, the detection Data as a result is transmitted to the CPU communication unit 14.
When the signal, command and data are output from the control command generator 15, the bus communication unit 16 sets potentials corresponding to the bit values of the output signal, command and data via the bus I / O 12. Sequentially output to the bus 7 by 1GBT or 1CBT.
When receiving a signal and data transmitted from the client circuit 6 _a to the host circuit 4, the bus communication unit 16 detects the potential of the bus 7 via the bus I / O 12 and displays the detection result. Output to the control command generator 15.

Further, the bus communication unit 16 includes an internal memory 32, a first counter 35, and a second counter 36.
The internal memory 32 is information (hereinafter, “1 GBT equivalent”) indicating how many pulses (how many cycles) the length of 1 GBT corresponds to the pulse of the clock signal generated by the clock generation unit 13 of the host circuit 4. It is also called “pulse number NGH”).
Here, the 1 GBT equivalent number of pulses NGH stored in the internal memory 32 is based on the frequency of the clock signal of the host circuit 4 and the frequency of the clock signals of all the client circuits 6 _{1 to} 6 _m connected to the host circuit 4. The value to be determined.

Further, the internal memory 32 is information indicating how many pulses of the clock signal pulse generated by the clock generator 13 corresponds to the length of ₁ CBT of each of the plurality of client circuits 6 _{1 to} 6 _m. (Hereinafter also referred to as “ ₁ CBT equivalent number of pulses NCH _{1 to} NCH _m ”).
Here, the number of pulses corresponding to ₁ CBT NCH _{1 to} NCH _m stored in the internal memory 32 is the frequency of the clock signal of the host circuit 4 and the clock of the communication target client circuits 6 _{1 to} 6 _m connected to the host circuit 4. It is a value determined from the frequency of the signal.
The first counter 35 sequentially counts the pulses of the clock signal generated by the clock generator 13. The pulse counting is performed in synchronization with the rising edge of the pulse.

Further, when the pulse counting result reaches the 1 GBT equivalent pulse number NGH stored in the internal memory 32, the first counter 35 synchronizes with the pulse when counting the next pulse, and outputs the pulse counting result. Return to "1".
As a result, the first counter 35 repeats the pulse counting between “1” and the 1 GBT equivalent pulse number NGH in synchronization with the clock signal generated by the clock generator 13.
The second counter 36 sequentially counts the pulses of the clock signal supplied from the clock generation unit 13 to the bus communication unit 16. The pulse counting is performed in synchronization with the rising edge of the pulse.
The second counter 36, the counting result of the pulses, of 1CBT corresponding pulse number NCH ₁ ~NCH _m stored in the internal memory 32, at a 1CBT corresponding pulse number NCH _a client circuit 6 _a, the following When counting the pulse, the pulse count result is returned to “1” in synchronization with the pulse.

As a result, the second counter 36 repeats the pulse counting between “1” and the number of pulses corresponding to 1 CBT NCH _a in synchronization with the clock signal generated by the clock generator 13.
The power supply control unit 17 generates a command for controlling the clock generation unit 13 and outputs the command to the clock generation unit 13.
In the host circuit 4, the main body I / O 10, the host control unit 11, and the bus I / O 12 operate in cooperation with each other to execute host control processing.
The clock generation unit 13 is driven by the oscillation circuit 31 and generates a clock signal.
In addition, the clock generation unit 13 supplies the generated clock signal to each unit 14 to 17 of the host circuit 4 in accordance with a command output from the power supply control unit 17.

<2-2. Configuration of bus I / O 12>
Next, the configuration of the bus I / O 12 of the host circuit 4 will be described.
FIG. 3 is a block diagram showing the internal configuration of the bus I / O 12, the control command generation unit 15, and the bus communication unit 16.
The control command generation unit 15 and the bus communication unit 16 function as an output data generation unit A and an input data analysis unit B.
The output data generation unit A generates signals, commands and data to be transmitted from the host circuit 4 to the client circuits 6 _{1 to} 6 _m, and sets the potential corresponding to the generated signal, command and data bit values to the bus I / O 12. Output to.

The input data analysis unit B receives the potential of the bus 7 via the bus I / O 12 and outputs the input potential to the reset terminal R as it is.
The bus I / O 12 includes a D flip-flop (in the broad sense, “host-value-corresponding potential output means”) 18, a control signal generation unit (in the broad sense, “host control signal generation means”) 19, and an I / O buffer. (In a broad sense, “host common line potential control means”) 20.
The D flip-flop 18 has an input terminal D and a reset terminal R.
A signal output from the output data generation unit A is input to the input terminal D.
A signal output from the input data analysis unit B is input to the reset terminal R.

The D flip-flop 18 outputs a signal input to the input terminal D from the output terminal Q to the control signal generator 19 and the I / O buffer 20 while the high potential is input to the reset terminal R.
The D flip-flop 18 outputs a low potential from the output terminal Q to the control signal generation unit 19 and the I / O buffer 20 while the low potential is input to the reset terminal R.
The control signal generation unit 19 includes a delay element 21 and an AND gate 22.
The delay element 21 receives the potential output from the D flip-flop 18, delays the potential by a predetermined time, and outputs it to the input Y of the AND gate 22.

Here, the predetermined time for which the delay element 21 delays the output of the potential is, for example, when the potential output from the I / O buffer 20 to the bus 7 is switched from the low potential to the high potential, the potential of the bus 7 is in a predetermined state. This is the time it takes to become.
The time required for the potential of the bus 7 to be in a predetermined state is, for example, the time until the potential of the bus 7 becomes a high potential and stabilizes, and a set value where the potential of the bus 7 is lower than the high potential. There is a possibility that the time required for exceeding the time may be used.
The AND gate 22 has an input X and an input Y.
The potential output from the D flip-flop 18 is input to the input X.
The potential output from the delay element 21 is input to the input Y.

When the high potential is input to both the input X and the input Y, the AND gate 22 outputs the high potential to the I / O buffer 20.
The AND gate 22 outputs a low potential to the I / O buffer 20 when a low potential is input from at least one of the input X and the input Y.
The I / O buffer 20 has a three-state bus buffer 23 and a bus buffer 24.
The three-state bus buffer 23 has an input terminal A and a control terminal B.

The potential output from the D flip-flop 18 is input to the input terminal A.
The potential output from the AND gate 22 is input to the control terminal B.
The three-state bus buffer 23 outputs the potential input to the input terminal A from the output terminal C to the bus 7 while the low potential is input to the control terminal B.
The three-state bus buffer 23 is in a high impedance state while the high potential is input to the control terminal B.
The bus buffer 24 receives the potential of the bus 7 and outputs the potential to the input data analysis unit B.

<2-3. Operation of bus I / O 12>
Next, the operation of the bus I / O 12 will be described using the configuration of the bus I / O 12 described above.
FIG. 4 is a time chart showing the operation of the bus I / O.
First, as shown at time t0 in FIG. 4, it is assumed that the output data generation unit A (Loout) and the input data analysis unit B (Loin) output a low potential. Further, it is assumed that the delay element 21 receives a low potential and the delay element 21 (dlySLout) outputs a low potential.

  Next, it is assumed that only the output from the output data generation unit A (Loout) has changed to the high potential as shown at time t1 in FIG. Then, in the D flip-flop 18, a high potential is input to the input terminal D, a low potential is input to the reset terminal R, and a high potential is output from the output terminal Q (SLout). As a result, the delay element 21 receives the high potential, but outputs the low potential (dlySLout) for a predetermined time. Therefore, the AND gate 22 (xSLoe) outputs a low potential because a high potential is input to the input X but a low potential is input to the input Y. As a result, in the three-state bus buffer 23, the low potential is input to the control terminal B, the high potential output from the D flip-flop 18 (SL) is output to the bus 7, and the potential of the bus 7 rises to increase the high potential. It becomes.

  Further, it is assumed that a predetermined time has elapsed after the potential (Loout) output from the output data generation unit A and the potential (dlySLout) input to the delay element 21 change from the low potential to the high potential. Then, the delay element 21 (dlySLout) outputs the High potential to the input Y of the AND gate 22 as shown at time t2. As a result, the AND gate 22 (xSLoe) receives the high potential at both the input X and the input Y and outputs the high potential. Therefore, the three-state bus buffer 23 has a high impedance when the high potential is input to the control terminal B (xSLoe). As a result, the output of the high potential to the bus 7 by the three-state bus buffer 23 is stopped, but the potential of the bus 7 is pulled up by the pull-up circuit 9 and maintained at the high potential.

FIG. 18 is a block diagram showing an internal configuration of a comparative example of bus I / O.
As shown in FIG. 18, the bus I / O 12 ′ that directly outputs the potential output from the output data generation unit A to the bus 7 has the following problems. For example, first, when any client circuit 6 _Low (Low is any number from 1 to m) outputs a low potential to the bus 7, the output data generation unit A erroneously outputs a high potential. And Then, the high potential is continuously output to the bus 7 by the bus I / O 12 '. Therefore, an overcurrent flows from the host circuit 4 side that outputs the high potential to the client circuit 6 _low side that outputs the low potential, and the client circuit 6 _low may burn out due to overheating due to the overcurrent.

On the other hand, in the bus I / O 12 of the present embodiment, for example, even if the output data generation unit A erroneously outputs a high potential, a high potential is output to the bus 7 immediately after the output. The output of is immediately stopped. Therefore, for example, even if the client circuit 6 _Low outputs a low potential to the bus 7, it is possible to prevent an overcurrent from flowing from the host circuit 4 to the client circuit 6 _Low, and to prevent the client circuit 6 _Low from being burned out. is there.
Further, when the potential of the bus 7 is switched from the low potential to the high potential, for example, the three-state bus buffer 23 is always in a high impedance state, and the potential of the bus 7 is changed from the low potential to the high potential only by pull-up by the pull-up circuit 9. There is a possibility that the potential of the bus 7 can be changed to a high potential in a short time as compared with the method of changing to high.

<3. Configuration of client circuit 6 _{1 to} 6 _m >
Next, the configuration of the client circuits 6 _{1 to} 6 _m will be described.
In the present embodiment, the client circuits 6 _{1 to} 6 _m adopt the same configuration regarding the configuration related to data transmission / reception with the host circuit 4.
Therefore, here, the configuration of the client circuit 6 _b (b is any number of _{1 to m} ) among the plurality of client circuits 6 _{1 to} 6 _m will be described as an example.
FIG. 5 is a block diagram showing an internal configuration of the client circuit _6b .
As shown in FIG. 5, the client circuit 6 _b includes a bus I / O 25, a client control unit 26, and a clock generation unit 27 (in a broad sense, “client clock signal generation means”).

FIG. 6 is a block diagram showing the internal configuration of the bus I / O of the host circuit.
The bus I / O 25 has the same configuration as the bus I / O 12 of the host circuit 4 as shown in FIG.
That is, the bus I / O 25 includes a D flip-flop (in a broad sense, “client bit value corresponding potential output means”) 18, a control signal generation unit (in a broad sense, “client control signal generation means”) 19, and an I / O. O buffer (in a broad sense, “common line potential control means for clients”) 20 and the like.
The client control unit 26 includes a bus communication unit 28, a control command detection unit 29, and a power supply control unit 30.

When the bus communication unit 28 receives a signal, a command, and data (for example, a reset signal or an address signal) transmitted from the host circuit 4 to the client circuit 6 _b , the bus communication unit 28 is connected to the bus 7 via the bus I / O 25. A change in potential is detected, and a signal, a command, and data as detection results are output to the control command detection unit 29.
Further, when the signal and data are output from the control command detection unit 29, the bus communication unit 28 sequentially outputs the potential of the bus 7 to the bus 7 one CBT at a potential corresponding to the bit value of the output signal and data. To do.

Further, the bus communication unit 28 includes an internal memory 34, a first counter 37, a second counter 38, and a plurality of registers 39 _{1 to} 39 _n (n is an integer of 2 or more).
The internal memory 34 indicates information indicating how many pulses (how many cycles) the length of 1 GBT corresponds to the time of the clock signal generated by the clock generation unit 27 of the client circuit 6 _b (the number of pulses corresponding to 1 GBT). NGC _b ) is stored.
Here, the 1 GBT equivalent pulse number NGC _b is stored in the internal memory 34 by the client control process as described later.

Further, the internal memory 34, the length of 1CBT client circuit 6 _b is, whether to correspond to what pulses (what period) of time pulse of the clock signal generated by the clock generator 27 of the client circuit 6 _b Information to be represented (1 CBT equivalent pulse number NCC _b ) is stored.
Here, 1CBT equivalent pulse number NCC _b is stored in the internal memory 34 by the client control process as will be described later.
The first counter 37 sequentially counts the pulses of the clock signal generated by the clock generator 27. The pulse counting is performed in synchronization with the rising edge of the pulse.
Further, when the pulse count result reaches the 1 GBT equivalent pulse number NGC _b stored in the internal memory 34, the first counter 37 synchronizes with the pulse when the next pulse is counted, and the pulse count result To “1”.

As a result, the first counter 37 repeats counting pulses between “1” and the number of pulses equivalent to 1 GBT NGC _b in synchronization with the clock signal generated by the clock generator 27.
The second counter 38 sequentially counts the clock signal pulses generated by the clock generator 27. The pulse counting is performed in synchronization with the rising edge of the pulse.
Further, when the pulse counting result reaches the 1CBT equivalent pulse number N CC _b stored in the internal memory 34, the second counter 38 synchronizes with the pulse when counting the next pulse, and the pulse counting result. To “1”.
As a result, the second counter 38 repeats the pulse counting between “1” and the number of pulses corresponding to 1 CBT NCC _b in synchronization with the clock signal generated by the clock generator 27.

Each of the plurality of registers 39 _{1 to} 39 _n stores various types of information such as information on the operating state of the client circuit 6 _b .
The plurality of registers 39 _{1 to} 39 _n includes a communication register 39 ₁ .
Communication register 39 ₁ stores information about the transmission and reception of data between the client circuit 6 _b and the host circuit 4.
Control command detection unit 29, the detection result from the bus communication unit 28 of the bus 7 potential is input, based on the change of the potential, signals the host circuit 4 is transmitted to the client circuit 6 _b, instruction and Detect data.

In addition, when transmitting a signal and data to the host circuit 4, the control command detection unit 29 generates data to be transmitted and outputs the generated signal and data to the bus communication unit 28.
The power supply control unit 30 generates a command for controlling the clock generation unit 27 and outputs the command to the clock generation unit 27.
Then, the client circuit 6 _b, by these buses for I / O25 and client control unit 26 operates in cooperation with each other, the client control process is executed.
The clock generator 27 is driven by the oscillation circuit 32 and generates a clock signal.
In addition, the clock generation unit 27 supplies the generated clock signal to each unit 28 to 30 of the client circuit 6 _b in accordance with a command output from the power supply control unit 30.

<4-1. About host control processing>
Next, host control processing executed by the host circuit 4 (main body I / O 10, host control unit 11 and bus I / O 12 in FIG. 2) will be described.
7 and 8 are explanatory diagrams for explaining a period during which the host control process is performed.
As shown in FIGS. 7 and 8, the period during which the host control process is performed is composed of an idle period (IDLE, RESET, GAP0), an address period (ADRS, GAP1), and a data period (WR, RD, GAP1). .
The idle period is a period in which data transmission / reception between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m is stopped.
The address period is the host circuit 4 specifies at least one client circuit 6 _a of the plurality of client circuits 6 ₁ to 6 _m.
Data period is a period to perform transmission and reception of data between the client circuit 6 _a and the specified host circuit 4.

<4-2. About the idle period>
First, the idle period will be described.
FIG. 9 is an explanatory diagram for explaining signals, instructions, and data transmitted from the host circuit 4 or the plurality of client circuits 6 _{1 to} 6 _m to the bus 7 in the idle period, the address period, and the data period.
In the idle period, as shown in FIG. 9 (1), the host circuit 4 sends a gap signal, a hardware reset signal, and a communication register reset signal to the bus 7.

Specifically, first, the host circuit 4 outputs a gap signal to the bus 7.
The gap signal is a signal sent to the bus 7 when there is no command and data to be transmitted from the host circuit 4 to the plurality of client circuits 6 _{1 to} 6 _m .
The gap signal is sent to the bus 7 by holding the potential of the bus 7 at a high potential for a predetermined time or more. The high potential is held by pull-up by the pull-up circuit 9.
Here, as the predetermined time for holding the potential of the bus 7 at the high potential, 1 GBT is used in the idle period and the address period. In addition, 1 CBT is used in the data period.

In the idle period and the address period, the host circuit 4 sets 1 GBT as the time corresponding to the 1 GBT equivalent pulse number NGH stored in the internal memory 33. That is, the host circuit 4 controls the potential of the bus 7 with 1 GBT as the time from when the count result by the first counter 35 is switched to a predetermined number to the next switch to the predetermined number.
In the idle period and the address period, the host circuit 4 starts controlling the potential of the bus 7 in synchronization with the timing at which the counting result of the first counter 35 is switched from the 1 GBT equivalent pulse number NGH to “1”.
The host circuit 4 sends a hardware reset signal or a communication register reset signal to the bus 7 when a command for sending data from the host CPU 3 to the client circuit 6 _a is output to the host circuit 4.

The hardware reset signal (“first reset signal” in a broad sense) is a signal that causes each of the plurality of client circuits 6 _{1 to} 6 _m to perform hardware reset.
Here, the hardware reset is an operation of initializing all the registers 39 _{1 to} 39 _n of each of the plurality of client circuits 6 _{1 to} 6 _m .
Also, the initialization of all registers 39 ₁ ~ 39 _n, the information stored in all the registers 39 ₁ ~ 39 _n respectively, all registers 39 ₁ ~ 39 _n respectively the client circuits 6 ₁ - It is to return to the information written first when _6m is activated.

Further, the hardware reset signal is transmitted by the host circuit 4 holding the potential of the bus 7 at a low potential for a predetermined time longer than 8 GBT (hereinafter referred to as “hardware reset time”).
Communication register reset signal (broadly, "a second reset signal") is a signal for initializing the communication register 39 ₁ in each of the plurality of client circuits 6 ₁ to 6 _m.
Here, the initialization of the communication register 39 ₁ and is written the information stored in the communication register 39 _1, to the communication register 39, the first time you start the client circuit 6 ₁ to 6 _m It is to return to information.

The communication register reset signal is transmitted when the host circuit 4 holds the potential of the bus 7 at a low potential that is 8 GBT (in a broad sense, “first set time”) or more and less than the hardware reset time. .
In this embodiment, the communication register reset signal is transmitted by holding the potential of the bus 7 at a low potential for 8 GBT or more. This is because in the communication system of this embodiment, the potential of the bus 7 does not continue to be a low potential for 6 GBT or more except when the hardware reset signal and the communication register reset signal are transmitted, and the bus 7 This is defined in consideration of a margin when a potential is erroneously detected.
When the transmission of the communication reset signal or the hardware reset signal is completed, the host circuit 4 transmits the gap signal to the bus 7 and then shifts from the idle period to the address period.

<4-3. Address period>
Next, the address period will be described.
In the address period, as shown in FIG. 9 (2), the host circuit 4 sequentially sends the addressing signal, the first reference signal, the address signal, the gap detection auxiliary signal, and the gap signal to the bus 7, and then the data. Transition to a period.
Specifically, first, the host circuit 4 sends an addressing signal to the bus 7.
The addressing signal is a signal that conveys the length of ₁ GBT to each of the plurality of client circuits 6 _{1 to} 6 _m .

This addressing signal is represented by 2 bits having a bit value “01”.
Therefore, the addressing signal is transmitted by the host circuit 4 by first setting the potential of the bus 7 to a low potential for 1 GBT and then to a high potential for the next 1 GBT.
Next, the host circuit 4 sends a first reference signal to the bus 7.
The first reference signal (in a broad sense, “host reference signal” and “address reference signal”) is generated by the clock signal generated by the clock generation unit 13 of the host circuit 4 for each of the plurality of client circuits 6 _{1 to} 6 _m. This is a signal for starting the clock signal generated by the unit 27 in synchronization.
The first reference signal is represented by 1 bit having a bit value “0”.

For this reason, the first reference signal is transmitted by the host circuit 4 holding the potential of the bus 7 at a low potential for 1 GBT.
Next, the host circuit 4 sends an address signal to the bus 7.
The address signal is a signal that designates the address of the client circuit 6 _a that transmits and receives data to and from the host circuit 4.
The address of the address signal designates is not within the address of the client circuit 6 _a, a set address to each of a plurality of client circuits 6 ₁ to 6 _m.

This address signal is a signal including a plurality of bits representing an address to be designated.
For this reason, the address signal is transmitted by controlling the potential of the bus 7 in accordance with the bit value of the designated address.
Specifically, the bit value of the address signal is transmitted as follows. Here, an example having first to third bits as the address signal will be described.
First, the host circuit 4 controls the potential of the bus 7 based on the value of the first bit. Then, potential control is performed for 1 GBT based on the value of the first bit.
Next, the host circuit 4 controls the potential of the bus 7 based on the value of the second bit. Then, potential control is performed for 1 GBT based on the value of the second bit.

Next, the host circuit 4 controls the potential of the bus 7 based on the value of the third bit. Then, the potential control based on the value of the third bit is performed for 1 GBT.
For example, when the address of the client circuit 6 _a is “010” (because “0” is a high potential and “1” is a low potential), the potential of the bus 7 is first set to a low potential for 1 GBT, and then The 1 GBT high potential is set to the next 1 GBT low potential.
By sequentially outputting the potential corresponding to each bit value of the address signal to the bus 7 by 1 GBT, the address signal is sent to the bus 7 at the first communication speed.

FIG. 10 is an explanatory diagram for explaining a modification of the address signal.
In the present embodiment, the example in which each of the plurality of client circuits 6 _{1 to} 6 _m is individually specified by the address specified by the address signal is shown, but the present invention is not limited to this. For example, a common address “000” is associated with each of the plurality of client circuits 6 _{1 to} 6 _m in addition to an individual address, and an address “000” is designated by an address signal, so that all clients Circuits 6 _{1 to} 6 _m or a plurality of client circuits 6 _{d to} 6 _e included in the plurality of client circuits 6 _{1 to} 6 _m (d is any number from 1 to _m −1, and e is any one of d to _m) May be specified.

In addition, an address expansion function that increases the address by 3 bits to 6 bits is associated with the address “111”, and the lower 3 bits of the expanded address can be specified by specifying the address “111” by the address signal. You may do it.
An address for selecting one client circuit 6 _a plurality of client circuits 6 ₁ to 6 _m by 6 bits, "111000", can address such as "111010" ... "111111", The maximum number of client circuits 6 _{a that} can be specified is 14. That is, the number of addresses that can be designated by the upper 3 bits of the expanded address is 23, of which two addresses "111" and "000" are the designation of all the client circuits 6 _{1 to} 6 _m and the address expansion function, respectively. It is used for. When the upper 3 bits are set to “111”, the number of addresses that can be specified by the lower 3 bits is 23. Therefore, the maximum number of client circuits 6 _{a that} can be specified is 14 (= 23−2 + 23). When the address expansion function is used, as shown in FIG. 10, the first reference signal is also sent to the bus 7 between the period for transmitting the upper 3 bits and the period for transmitting the lower 3 bits of the expanded address. Send it out.

Next, the host circuit 4 sends a gap detection auxiliary signal to the bus 7.
The gap detection auxiliary signal is a signal for enabling easy detection of a gap signal to be subsequently transmitted.
This gap detection auxiliary signal is represented by one bit having a bit value “0”.
Therefore, the transmission of the gap detection auxiliary signal is performed by the host circuit 4 by setting the potential of the bus 7 to the low potential for 1 GBT.
Next, after sending the gap signal to the bus 7, the host circuit 4 shifts from the address period to the data period.

<4-4. About data period>
Next, the data period will be described.
Data period, data transmission period host circuit 4 transmits the 8-bit data to the client circuit 6 _a, and, and a data reception period host circuit 4 receives the 8-bit data from the client circuit 6 _a.
Then, in the data period, by repeating the data transmission period and the data reception period, to send and receive more than 8 bits of data between the host circuit 4 and a client circuit 6 _a, the transmission and reception of data is completed, The data period shifts to the idle period again.

<4-4 (1). Data transmission period>
First, the data transmission period will be described.
In the data transmission period, as shown in FIG. 9 (3), the host circuit 4 is configured to write the command, the second reference signal, the host transmission first half data, the third reference signal, the host transmission second half data, and the gap detection auxiliary signal. The gap signal is sent to the bus 7 in order.
Specifically, first, the host circuit 4 sends a write command to the bus 7.
The write command (“first time setting signal” “time setting signal” in a broad sense) is a command for causing the client circuit 6 _a to receive data. The write command also acts as a signal to convey the length of 1CBT client circuit 6 _a.

This write command is represented by 3 bits having a bit value “010”.
Therefore, the write command is transmitted by the host circuit 4 by setting the potential of the bus 7 first to the low potential between 1 CBT, the next high potential between 1 CBT, and the next low potential between 1 CBT.
Next, the host circuit 4 sends a second reference signal to the bus 7.
In the data period, the host circuit 4 sets the time corresponding to the number of pulses equivalent to 1 CBT NCH _{a of the} client circuit 6 _a stored in the internal memory 33 as 1 CBT. That is, the host circuit 4 detects and controls the potential of the bus 7 with 1 CBT as the time from when the count result by the second counter 36 is switched to a predetermined number to the next switch to the predetermined number.

In the data period, the host circuit 4 starts controlling the potential of the bus 7 in synchronization with the timing at which the counting result of the first counter 35 is switched from the 1CBT equivalent pulse number NCH _a to “1”.
The second reference signal (“host reference signal” and “data reference signal” in a broad sense) is a clock signal generated by the clock generation unit 27 of the client circuit 6 _a and a clock signal generated by the clock generation unit 13 of the host circuit 4. Is a signal that is started in synchronization.

This second reference signal is represented by one bit having a bit value “1”.
Therefore, the transmission of the second reference signal is performed by the host circuit 4 holding the potential of the bus 7 at the high potential for 1 CBT.
Next, the host circuit 4 sends the host transmission first half data to the bus 7.
The first half of host transmission data (“host transmission data” in a broad sense) is 4-bit data of the first half of 8-bit data transmitted from the host circuit 4 to the client circuit _6a .
Therefore, the first half of host transmission data is transmitted by controlling the potential of the bus 7 according to the first to fourth bits included in the first half of host transmission data.

Specifically, the transmission of the first half of host transmission data is performed as follows.
First, the voltage of the bus 7 is controlled by the host circuit 4 based on the value of the first bit. Then, voltage control based on the value of the first bit is performed for 1 CBT.
Next, the voltage of the bus 7 is controlled by the host circuit 4 based on the value of the second bit. Then, voltage control based on the value of the second bit is performed for 1 CBT.
Next, the voltage of the bus 7 is controlled by the host circuit 4 based on the value of the third bit. Then, voltage control based on the value of the third bit is performed for 1 CBT.
Next, the voltage of the bus 7 is controlled by the host circuit 4 based on the value of the fourth bit. Then, voltage control based on the value of the fourth bit is performed for 1 CBT.

By outputting the potential corresponding to each bit value of the host transmission first half data to the bus 7 sequentially by 1 CBT, the host transmission first half data is sent to the bus 7 at the second communication speed.
Next, the host circuit 4 sends a third reference signal to the bus 7.
The third reference signal (in a broad sense, “host reference signal” and “data reference signal”) is a clock signal generated by the clock generation unit 27 of the client circuit 6 _a and a clock signal generated by the clock generation unit 13 of the host circuit 4. Is a signal that is started in synchronization.
The third reference signal is represented by 1 bit that is a bit value different from the bit value of the fourth bit of the host transmission first half data.

For example, when the bit value of the fourth bit of the host transmission first half data is “1”, the bit value of the third reference signal is “0”.
When the bit value of the fourth bit of the host transmission first half data is “0”, the bit value of the third reference signal is “1”.
Therefore, the third reference signal is transmitted when the potential corresponding to the fourth bit of the host transmission first half data is the high potential, the host circuit 4 holds the potential of the bus 7 at the low potential for 1 CBT. Do that.
The third reference signal is transmitted when the host circuit 4 holds the potential of the bus 7 at the high potential between 1 CBT when the potential corresponding to the fourth bit of the first half of host transmission data is the low potential. To do.

Next, the host circuit 4 sends the host transmission latter half data to the bus 7.
The host transmission latter half data (“host transmission data” in a broad sense) is the latter half 4-bit data among the 8-bit data transmitted from the host circuit 4 to the client circuit 6 _a .
The method for sending host transmission latter half data is the same as that for host transmission first half data.
Note that, as the time required for transmission of 8-bit data from the host circuit 4 to the client circuit 6 _a is equal to or less than a predetermined time, in 8-bit data transmission in the data transmission period, the host circuit 4 and the client circuits 6 _a Prohibits execution of interrupt processing.
Next, the host circuit 4 sends a gap detection auxiliary signal to the bus 7.
Next, the host circuit 4 sends a gap signal to the bus 7 and then ends this data transmission period.

<4-4 (2). About data reception period>
Next, a description will be given of a data reception period host circuit 4 receives the 8-bit data from the client circuit 6 _a.
In the data reception period, as shown in FIG. 9 (4), first, the host circuit 4 sequentially sends a read command and a gap signal to the bus 7.
Next, as will be described later, the fourth reference signal, the first client transmission data, the fifth reference signal, the second client transmission data, the gap detection auxiliary signal, and the gap signal are sequentially transmitted from the client circuit 6 _a to the bus 7.

Therefore, the host circuit 4 detects a signal sent from the client circuit _6a to the bus 7, and performs various operations according to the detected signal.
Specifically, first, the host circuit 4 sends a read command to the bus 7.
The read command (“second time setting signal” “time setting signal” in a broad sense) is a command for causing the client circuit 6 _a to transmit data. Further, the read command also acts as a signal to convey the length of 1CBT client circuit 6 _a.
This read command is represented by 3 bits having a bit value “011”.
Therefore, the read command is sent by the host circuit 4 by first setting the potential of the bus 7 to the low potential between 1 CBT, the next high potential between 1 CBT, and the next high potential between 1 CBT.

Next, the host circuit 4 sends a gap signal to the bus 7.
Next, the fourth reference signal is sent from the client circuit 6 _a to the bus 7. As a result, the potential of the bus 7 that has been set to the high potential by the gap signal is set to the low potential for 1 CBT.
Therefore, the host circuit 4 detects a change in the potential of the bus 7 from the high potential to the low potential that appears after sending the read command. Then, when the change in the potential is detected, the host circuit 4 returns the pulse count result of the second counter 36 to “1”.
During the data reception period, the host circuit 4 detects the potential of the bus 7 in synchronization with the rising edge of the clock signal pulse generated by the clock generator 13.

Thus, after the fourth reference signal is transmitted from the client circuit _6a to the bus 7, the second counter 36 sets the count result of the first rising pulse to “1” and continues counting pulses. The host circuit 4 can synchronize the potential of the bus 7 with the clock signal generated by the clock generation unit 13 and can synchronize the data transfer timing.
In the present embodiment, an example is shown in which the count result of the pulses by the second counter 36 is returned to “1” in response to the transmission of the fourth reference signal, but the present invention is not limited to this. For example, a mechanism for adjusting the rising timing of the clock signal generated by the clock generation unit 13 of the host circuit 4 is provided, and the fourth reference signal is sent to the rising edge of the clock signal generated by the clock generation unit 13. You may make it approach timing.

Next, client transmission first half data, which is 4-bit data, is sent from the client circuit 6 _a to the bus 7. The transmission of the first half of client transmission data is performed by controlling the potential of the bus 7 according to the first to fourth bits included in the first half of client transmission data.
Therefore, the host circuit 4 detects the potential of the bus 7 and detects the bit value of the first half data of the client transmission based on the detected potential change.
Here, a method for detecting the bit value of the first half data of the client transmission will be described.
First, the host circuit 4 calculates a parameter used for detecting the bit value of the first half of client transmission data.

Specifically, the host circuit 4 determines whether or not the 1CBT equivalent pulse number NCH _{a of the} client circuit 6 _a stored in the internal memory 33 is an odd number. When the host circuit 4 determines that the 1CBT equivalent pulse number NCH _a is an odd number, (NCH _a +1) / 2 is set as the first pulse number, and (NCH _a +1) / 2 + 1 is set as the second pulse number. The number of pulses.
Further, when the host circuit 4 determines that the 1CBT equivalent pulse number NCH _a is an even number, NCH _a / 2 is set as the first pulse number, and NCH _a / 2 + 1 is set as the second pulse number.
Next, the host circuit 4 detects the potential of the bus 7 using the calculated first pulse number and second pulse number, and based on the detected potential change, the bit value of the first half of the client transmission data is detected. To detect.

FIG. 11 is an explanatory diagram for explaining a method of detecting the bit value of the client transmission first half data.
First, the host circuit 4 is set to indicate the time t0 _h in FIG. 11, the counting result of the second counter 36 by a fourth reference signal to "1". Then, the pulse counting from “1” is continued by the second counter 36, and as shown at time t1 _h in FIG. 11, the pulse counting result by the second counter 36 is 1CBT equivalent pulse number NCH _a (for example, 6). Then, the pulse counting by the second counter 36 is started again from “1”.

Then, the counting of pulses by the second counter 36 is continued from “1” again, and the host circuit 4 determines that the counting result of the pulses by the second counter 36 is the first number of pulses as shown at time t2 _h in FIG. The potential of the bus 7 is detected in synchronization with (for example, 3). Further, as shown at time t3 _h in FIG. 11, the host circuit 4 detects the potential of the bus 7 synchronously when the count result of the second counter 36 becomes the second pulse number (for example, 4). .
Further, the host circuit 4 determines the first half of client transmission based on the potential of the bus 7 (first detection potential) detected at the time t2 _h and the potential of the bus 7 (second detection potential) detected at the time t3 _h. Get the bit value of the first bit of data.

  Specifically, the host circuit 4 determines whether or not both the first detection potential and the second detection potential are high potentials or both are low potentials. When the host circuit 4 determines that both are high potentials or both are low potentials, the bit value corresponding to the first detection potential is detected as the bit value of the first bit of the client first half data. Adopt as a result. When the host circuit 4 determines that one of the first detection potential and the second detection potential is the high potential and the other is the low potential, the bit value of the first bit of the client transmission first half data is Suppose that it was not obtained.

When the second counter 36 continues counting pulses, and the count result of the second counter 36 reaches 1 CBT equivalent pulse number NCH _a , as shown at time t4 _h in FIG. Starts again from “1”. Then, as shown at time t5 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generator 13 when the pulse counting result by the second counter 36 becomes the first pulse number. Thus, the potential of the bus 7 is detected. Further, as shown at time t6 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generator 13 when the count result of the second counter 36 becomes the second number of pulses. The potential of the bus 7 is detected.

Further, the host circuit 4 determines the first half of client transmission based on the potential of the bus 7 (first detection potential) detected at the time t5 _h and the potential of the bus 7 (second detection potential) detected at the time t6 _h. Get the bit value of the second bit of data.
The method for detecting the bit value of the third bit of the first half data of the client transmission is the same as the method of detecting the bit value of the second bit of the first half data of the client transmission.

The pulse counting a continued by the second counter 36, the count result of the second counter 36 becomes 1CBT corresponding number of pulses NCH _a, as shown at time t7 _h in FIG. 11, the pulse count of the second counter 36 Starts again from “1”. Then, as shown at time t8 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generator 13 when the pulse counting result by the second counter 36 becomes the first pulse number. Thus, the potential of the bus 7 is detected. Further, as shown at time t9 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generator 13 when the count result of the second counter 36 becomes the second number of pulses. The potential of the bus 7 is detected.

Further, the host circuit 4 determines the first half of client transmission based on the potential of the bus 7 (first detection potential) detected at the time t8 _h and the potential of the bus 7 (second detection potential) detected at the time t9 _h. The bit value of the third bit of data is acquired.
The method for detecting the bit value of the third bit of the client first half data is the same as that for the first bit value of the client first half data.

The pulse counting a continued by the second counter 36, the counting result of the second counter 36 becomes the 1CBT equivalent number of pulses, as shown at time t10 _h in FIG. 11, the counting of pulses by the second counter 36 is again It starts from “1”. Then, as shown at time t11 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generator 13 when the pulse counting result by the second counter 36 becomes the first pulse number. Thus, the potential of the bus 7 is detected. Further, as shown at time t12 _h in FIG. 11, the host circuit 4 synchronizes with the clock signal generated by the clock generation unit 13 when the count result of the second counter 36 becomes the second number of pulses. The potential of the bus 7 is detected.

Further, the host circuit 4 determines the first half of client transmission based on the potential of the bus 7 detected at the time t11 _h (first detection potential) and the potential of the bus 7 detected at time t12 _h (second detection potential). The bit value of the fourth bit of data is acquired.
Note that the method for detecting the bit value of the fourth bit of the first half data of the client transmission is the same as that of the first bit value of the first half data of the client transmission.

As described above, the host circuit 4 sequentially detects the bit values of the first half of client transmission data sent to the bus 7 in synchronization with the time corresponding to the number of pulses corresponding to 1 CBT of the client circuit 6 _a NCH _a . As a result, the first half of the client transmission data is received at the second communication speed.
In the present embodiment, the example in which the potential of the bus 7 is detected twice during 1 CBT is shown, but the present invention is not limited to this. For example, the potential of the bus 7 may be detected three times or more during 1 CBT. In the case of detecting three or more times, the host circuit 4 determines whether or not those detection results are all at a high potential or all at a low potential. The host circuit 4 adopts the bit value corresponding to the detection result of the potential of the bus 7 as the detection result of the bit value of the first half data of the client transmission when all are the high potential or all the low potential.

  If those detection results include both high and low potentials, the detection results include many high potentials or low potentials. Judge whether a lot of things are included. If a large number of high potentials are included, the bit value corresponding to the high potential is used as the detection result of the bit value of the data. If many low potentials are included, the bit value corresponding to the low potential is used as the detection result of the bit value of the first half of client transmission data.

In other words, when the potential of the bus 7 is detected n times during 1 CBT (n is an integer of 2 or more), the client circuit 6 _b first detects the potential of the bus 7 n times, and the detection results are obtained. The i-th detection result (i is a natural number equal to or less than n) is acquired. Next, the client circuit 6 _b determines whether or not those detection results are all at a high potential or all at a low potential. When the client circuit 6 _b is all at the high potential or all at the low potential, the bit value corresponding to the detection result of the potential of the bus 7 is transmitted to the client circuit 6 _b from the host circuit 4. Adopted as a bit value detection result.

  If those detection results include both high and low potentials, the detection results include many high potentials or low potentials. Judge whether a lot of things are included. If a large number of high potentials are included, the bit value corresponding to the high potential is used as the detection result of the bit value of the data. If many low potentials are included, the bit value corresponding to the low potential is used as the detection result of the bit value of the first half of client transmission data.

Further, when the potential of the bus 7 is detected a plurality of times during 1 CBT, the host circuit 4 synchronizes with the rising and falling edges of the clock signal pulse generated by the clock generator 13. The potential may be detected sequentially.
Next, the fifth reference signal is sent from the client circuit 6 _a to the bus 7. As a result, the potential of the bus 7 is switched to a potential different from the previous potential.
Therefore, the host circuit 4 detects this potential change that appears after the transmission of the first half of client transmission data. When the change in the potential is detected, the host circuit 4 sets the pulse count result of the second counter 36 to “1”.

As a result, the host circuit 4 can synchronize the potential of the bus 7 with the clock signal generated by the clock generator 13 and can synchronize the timing of data transfer again.
Next, client transmission latter half data, which is 4-bit data, is sent from the client circuit 6 _a to the bus 7. The client transmission latter half data is transmitted by controlling the potential of the bus 7 in accordance with the client transmission latter half data.
Therefore, the host circuit 4 detects the potential of the bus 7 and detects the bit value of the client transmission latter half data based on the detected potential change.

The method of detecting the bit value of the client transmission latter half data is the same as that of the client transmission first half data.
Next, the gap detection auxiliary signal and the gap signal are sequentially transmitted from the client circuit 6 _a to the bus 7. As a result, the potential of the bus 7 is changed to the high potential after being set to the low potential for 1 CBT.
Therefore, the host circuit 4 detects a change in the potential of the bus 7 from the low potential to the high potential that appears after the transmission of the client transmission latter half data. The host circuit 4 detects the change, thereby detecting a gap signal sent from the client circuit _6a to the bus 7 at the end of the data reception period, and ends this data reception period.

<5-1. About client control processing>
Next, client control processing executed in each of the plurality of client circuits 6 _{1 to} 6 _m (the bus I / O 25 and the client control unit 26 in FIG. 5) will be described.
In the present embodiment, each of the plurality of client circuits 6 _{1 to} 6 _m executes the same client control process.
Therefore, here, among the plurality of client circuits 6 ₁ to 6 _m, it is described the client control process client circuit 6 _b is running.
12 and 13 are explanatory diagrams for explaining a period during which the client control process is performed.
The period during which the client control process is performed is composed of an idle period (IDLE), an address period (ADRS, EXTADR), and a data period (WR, RD, RdWr) as shown in FIGS. Is done.

<5-2. About the idle period>
First, the idle period will be described.
In the idle period, as shown in FIG. 9 (1), the host circuit 4 sends a gap signal, a communication register reset signal, and a hardware reset signal to the bus 7.
Therefore, the client circuit 6 _b detects a signal sent from the host circuit 4 to the bus 7 and performs various operations according to the detected signal.
Specifically, first, a gap signal is sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is held at a high potential for 1 GBT or more.

Further, in response to a command from the host CPU 3, a communication register reset signal or a hardware reset signal is sent from the host circuit 4 to the bus 7, and subsequently, a gap signal is sent from the host circuit 4 to the bus 7.
When a communication register reset signal is sent to the bus 7, the potential of the bus 7 is kept at a low potential of 8 CBT or more and less than the hardware reset time.
When a hardware reset signal is sent to the bus 7, the potential of the bus 7 is held at a low potential for a hardware reset time or longer.

Therefore, the client circuit 6 _b counts the pulses of the clock signal generated by the clock generation unit 27 while the potential of the bus 7 is set to the low potential. When the potential of the bus 7 changes from the low potential to the high potential, the counting result is 8 times or more the 1 GBT equivalent number of pulses NGC _b stored in the internal memory 34 and less than the number of pulses corresponding to the hardware reset time. It is determined whether or not. If the client circuit 6 _b determines that the pulse count result is 8 times or more the 1 GBT equivalent pulse number NGC _b and less than the pulse number for the hardware reset time, the client circuit 6 _b has detected the communication register reset signal. judgment, initializes the communication register 39 _1.
Here, the number of pulses corresponding to the hardware reset time is a value determined based on the frequency of the clock signal of the client circuit _6b .
During the client control process, the client circuit 6 _b detects the potential of the bus 7 in synchronization with the rising edge of the clock signal pulse generated by the clock generator 27.

Further, when the potential of the bus 7 changes to the low potential, the client circuit 6 _b checks whether the pulse counting result while the potential of the bus 7 is the low potential is equal to or greater than the number of pulses corresponding to the hardware reset time. Determine whether or not. If it is determined that the number of pulses is equal to or greater than the number of pulses corresponding to the hardware reset time, the client circuit 6 _b determines that a hardware reset signal has been detected, and performs a hardware reset on all the registers 39 _{1 to} 39 _n. .
In the hardware reset, all the registers 39 _{1 to} 39 _n of the client circuit 6 _b are initialized.
The client circuit 6 _b, when the information potential of the bus 7 is stored the Low potential to communication register 39 ₁ is initialized, the transition from the idle period in the address period.

FIG. 14 is an explanatory diagram for explaining a method for detecting a communication register reset signal.
By the way, in the communication system of the present embodiment, for example, as shown in FIG. 14, even when the potential of the bus 7 frequently fluctuates, in the client circuit 6 _b , the low potential continues as the potential of the bus 7. May be detected. Therefore, for example, even when the client circuit 6 _b does not send a communication register reset signal from the host circuit 4 to the bus 7, the client circuit 6 _b continuously detects the low potential by a value eight times the 1 GBT equivalent pulse number NGC _b. There is a possibility of erroneous determination that a communication register reset signal has been detected.

For the possibility of such a misjudgment, for example, the client circuit 6 _b monitors the rise of the potential of the bus 7 to the high potential, and if such a rise is detected, the client circuit 6 _b uses the potential of the bus 7 as the potential. A configuration in which a high potential is detected may be employed. By doing so, for example, when the potential of the bus 7 frequently fluctuates between the high potential and the low potential, there is a possibility that the high potential can be reliably detected. Therefore, the client circuit 6 _b may be able to prevent the erroneous determination that detects a communication register reset signal.

<5-3. Address period>
Next, the address period will be described.
In the address period, as shown in FIG. 9 (2), the host circuit 4 sequentially sends an addressing signal, a first reference signal, an address signal, a second reference signal, and a gap signal to the bus 7.
Therefore, the client circuit 6 _b detects a signal sent from the host circuit 4 to the bus 7 and performs various operations according to the detected signal.

Specifically, first, an addressing signal is sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is first set to the low potential for 1 GBT and then set to the high potential for the next 1 GBT.
Therefore, the client circuit 6 _b counts the pulses of the clock signal generated by the clock generator 27 while the potential of the bus 7 is set to the low potential by the addressing signal, and the counted result is the number of pulses corresponding to 1 GBT NGC _b Is stored in the internal memory 34.

As a result, the length of 1 GBT is transmitted from the host circuit 4 to the client circuit 6 _b .
In the idle period and the address period, the client circuit 6 _b detects the potential of the bus 7 with 1 GBT as the time from when the count result of the first counter 37 is switched to a predetermined number to the next predetermined number. I do.
Next, the first reference signal is output from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 that has been set to the high potential by the addressing signal is set to the low potential for 1 GBT.
Therefore, the client circuit 6 _b detects a change in the potential of the bus 7 from the high potential to the low potential that appears after sending the addressing signal. When the change in the potential is detected, the client circuit 6 _b sets the pulse count result of the second counter 36 to “1”.

Thus, the client circuit 6 _b can synchronize the potential of the bus 7 with the clock signal generated by the clock generation unit 27 and can synchronize the timing of data transfer.
Next, an address signal is sent from the host circuit 4 to the bus 7. The address signal is transmitted by controlling the potential of the bus 7 according to each of the first to third bits included in the address designated by the address signal.
Therefore, the client circuit 6 _b detects the potential of the bus 7 and detects the bit value of the address designated by the address signal based on the detected potential change.

Here, a method for detecting the bit value of the address signal will be described.
First, the client circuit 6 _b calculates a parameter used for detecting the bit value of the address signal.
Specifically, the client circuit 6 _b determines whether or not the 1 GBT equivalent pulse number NGC _{b of the} client circuit b stored in the internal memory 34 is an odd number. When the client circuit 6 _b determines that the 1 GBT equivalent pulse number NGC _b is an odd number, (NGC _b +1) / 2 is set as the first pulse number, and (N ′ + 1) / 2 + 1 is set as the second pulse number. The number of pulses.

If the client circuit 6 _b determines that the 1 GBT equivalent pulse number NGC _b is an even number, NGC _b / 2 is set as the first pulse number and NGC _b / 2 + 1 is set as the second pulse number.
Next, the client circuit 6 _b detects the potential of the bus 7 using the calculated first pulse number and second pulse number, and detects the bit value of the address signal based on the detected potential change. To do.

FIG. 15 is an explanatory diagram for explaining a method of detecting the bit value of the address signal.
First, as shown at time t0 _c ′ in FIG. 15, the client circuit 6 _b sets the count result of the first counter 37 to the initial value “1” by the first reference signal. Then, continue the counting from "1" pulse of the first counter 37, as shown at time t1 _c 'in FIG. 15, the counting result of the pulses of the first counter 37 is 1GBT equivalent pulse number NGC _b (e.g., 6 ), The counting of pulses by the first counter 37 starts again from “1”.

Then, the counting of pulses by the first counter 37 is continued from “1” again, and the client circuit 6 _b indicates that the counting result of the pulses by the first counter 37 is the first as shown at time t2 _c ′ in FIG. When the number of pulses (for example, 3) is reached, the potential of the bus 7 is detected in synchronization with the clock signal generated by the clock generator 27. The client circuit 6 _b, as shown at time t3 _c 'in FIG. 15, the counting result of the first counter 37 is a second pulse number (e.g., 4) in synchronization with when it comes to the potential of the bus 7 To detect.

Further, the client circuit 6 _b is based on the potential of the bus 7 (first detection potential) detected at the time t2 _c ′ and the potential of the bus 7 (second detection potential) detected at the time t3 _c ′. The bit value of the first bit of the address signal is acquired.
Specifically, the client circuit 6 _b determines whether or not both the first detection potential and the second detection potential are high potentials or both are low potentials. When the client circuit _6b determines that both are high potentials or both are low potentials, the bit value corresponding to the first detection potential is converted to the detection result of the bit value of the first bit of the address signal. Adopt as. Further, when the client circuit _6b determines that one of the first detection potential and the second detection potential is the high potential and the other is the low potential, the bit value of the first bit of the address signal is obtained. Suppose that it was not.

Further, when counting of pulses by the first counter 37 is continued again from “1” and the counting result of the first counter 37 reaches the 1 GBT equivalent pulse number NGC _b , as shown at time t4 _c ′ in FIG. The counting of pulses by the counter 37 starts again from “1”. Then, as shown at time t 5 _c ′ in FIG. 15, when the count result of the first counter 37 reaches the first pulse number, the client circuit 6 _b synchronizes with the clock signal generated by the clock generator 13. Thus, the potential of the bus 7 is detected. The client circuit 6 _b is synchronized with the clock signal generated by the clock generator 13 as shown at time t6 _c ′ in FIG. 15 when the count result of the first counter 37 reaches the second pulse number. Thus, the potential of the bus 7 is detected.

Further, the client circuit 6 _b is based on the potential of the bus 7 (first detection potential) detected at the time t5 _c ′ and the potential of the bus 7 (second detection potential) detected at the time t6 _c ′. The bit value of the second bit of the address signal is acquired.
The method for detecting the bit value of the second bit of the address signal is the same as that for the bit value of the first bit of the address signal.

Further, when the counting of the pulse by the first counter 37 is continued from “1” again, and the counting result of the first counter 37 reaches the 1 GBT equivalent pulse number NGC _b , as shown at time t7 _c ′ in FIG. The counting of pulses by the counter 37 starts again from “1”. Then, as shown at time t 7 _c ′ in FIG. 15, when the count result of the first counter 37 reaches the first pulse number, the client circuit 6 _b is synchronized with the clock signal generated by the clock generator 13. Thus, the potential of the bus 7 is detected. Further, the client circuit 6 _b synchronizes with the clock signal generated by the clock generator 13 as shown at time t9 _c ′ in FIG. 15 when the count result of the first counter 37 reaches the second pulse number. Thus, the potential of the bus 7 is detected.

Further, the client circuit 6 _b is based on the potential of the bus 7 (first detection potential) detected at the time t8 _c ′ and the potential of the bus 7 (second detection potential) detected at the time t9 _c ′. The bit value of the third bit of the address signal is acquired.
The method for detecting the bit value of the third bit of the address signal is the same as that for the bit value of the first bit of the address signal.
As described above, the client circuit 6 _b sequentially detects the bit value of the address signal sent to the bus 7 in synchronization with the time corresponding to the 1 GBT equivalent pulse number NGC _b . Thereby, the address signal is received at the first communication speed.
When the client circuit _6b acquires all the bit values of the address signal, the client circuit 6b determines whether or not the address specified by the detected address signal matches the address of its own circuit.

Next, the second reference signal and the gap signal are sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is changed to the high potential after being set to the low potential for 1 GBT.
Therefore, when the client circuit _6b determines that the address specified by the address signal matches the address of its own circuit, the client circuit 6b detects the switching from the low potential to the high potential that appears after the address signal is transmitted. At the end of the address period, a gap signal sent from the host circuit 4 is detected, and the address period is shifted to the data period.
When the client circuit _6b determines that the address specified by the address signal does not match the address of its own circuit, the client circuit 6b detects the switching from the low potential to the high potential, thereby detecting the host at the end of the address period. The gap signal transmitted from the circuit 4 is detected, and the address period is terminated without shifting to the data period.

<5-4. About data period>
Next, the data period will be described.
The data period includes a data transmission period in which the host circuit 4 transmits 8-bit data to the client circuit 6 _b , and a data reception period in which the host circuit 4 receives 8-bit data from the client circuit 6 _b . In the data period, data is transmitted and received between the host circuit 4 and the client circuit 6 _b by repeating the data transmission period and the data reception period, and when the data transmission / reception ends, the period again enters the idle period. To do.

<5-4 (1). Data transmission period>
First, the data transmission period will be described.
In the data transmission period, as shown in FIG. 9 (3), from the host circuit 4, the write command, the second reference signal, the host transmission first half data, the third reference signal, the host transmission second half data, and the fifth reference signal. And a gap signal are sequentially sent to the bus 7.
Therefore, the client circuit 6 _b, detects instructions and signals are sent from the host circuit 4 to the bus 7, performs various operations according to the detected instruction and signals.

Specifically, first, a write command is sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is first set to a low potential between 1 CBTs, then set to a high potential between the next 1 CBTs, and set to a low potential between the next 1 CBTs.
For this reason, the client circuit 6 _b counts the pulses of the clock signal generated by the clock generation unit 27 while the potential of the bus 7 is the low potential at the first low potential of the write command, and the counted result is 1 CBT. The number of equivalent pulses Ncc _b is stored in the internal memory 34. Thus, the length of 1CBT from the host circuit 4 to the client circuit 6 _b is transmitted.
Then, during the data transmission period, the client circuit 6 _b detects the potential of the bus 7 with 1 CBT as the time from when the count result of the first counter 37 is switched to a predetermined number to the next switching to the predetermined number. .

Next, the second reference signal is sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 which has been set to the low potential by the write command is set to the high potential for 1 CBT.
Therefore, the client circuit 6 _b detects the change in the potential of the bus 7 from the low potential to the high potential, which appears after sending the write command, in synchronization with the clock signal generated by the clock generation unit 27. Then, when the change in the potential is detected, the client circuit 6 _b sets the pulse count result of the second counter 38 to the initial value “1”.
Thus, the client circuit 6 _b can synchronize the potential of the bus 7 with the clock signal generated by the clock generation unit 27 and can synchronize the timing of data transfer.

Next, the host transmission first half data is sent from the host circuit 4 to the bus 7. The transmission of the first half of host transmission data is performed by controlling the potential of the bus 7 in accordance with each of the first to fourth bits included in the first half of host transmission data.
Therefore, the client circuit 6 _b detects the potential of the bus 7 and detects the bit value of the host transmission first half data based on the detected potential change.
Here, a method for detecting the bit value of the host transmission first half data will be described.
First, the client circuit 6 _b calculates a parameter used to detect the bit value of the host transmission first half data.

Specifically, the client circuit 6 _b determines whether or not the 1 CBT equivalent pulse number N CC _b stored in the internal memory 34 is an odd number. When the client circuit 6 _b determines that the 1CBT equivalent pulse number NCC _b is an odd number, (NCC _b +1) / 2 is set as the first pulse number, and (NCC _b +1) / 2 + 1 is set as the second pulse number. The number of pulses.
Further, when the client circuit 6 _b determines that the 1CBT equivalent pulse number NCC _b is an even number, NCC _b / 2 is set as the first pulse number and NCC _b / 2 + 1 is set as the second pulse number.
Next, the client circuit 6 _b detects the potential of the bus 7 using the calculated first pulse number and second pulse number, and the bit value of the host transmission first half data based on the detected potential change. Is detected.

FIG. 16 is an explanatory diagram for explaining a method of detecting the bit value of the host transmission first half data.
First, the client circuit 6 _b is set to indicate the time T0C "in FIG. 16, the counting result of the second counter 38 by the second reference signal to" 1 ". Then, the second counter 38 continues counting pulses from “1”, and when the pulse counting result by the second counter 38 reaches the number of pulses equivalent to 1 CBT N CC _b (for example, 6), the time t 1 _c ″ in FIG. As shown in FIG. 8, the second counter 38 starts counting pulses again from “1”.

Then, the counting of pulses by the second counter 38 is continued, and the client circuit 6 _b determines that the counting result of the pulses by the second counter 38 is a first pulse number (for example, as shown at time t2 _c ″ in FIG. 16). in synchronization with when it comes to 3) for detecting the potential of the bus 7. the client circuit 6 _b, as shown at time t3 _c "in FIG. 16, the counting result is the second number of pulses of the second counter 38 The potential of the bus 7 is detected in synchronization with (for example, 4).
The client circuit 6 _b, based on their time t2 _c "potential of the bus 7 detected (first detection potential) and time t3 _c" to the detected potential of the bus 7 (the second detection potential), The bit value of the first bit of the host transmission first half data is acquired.

Specifically, the client circuit 6 _b receives the potential of the bus 7 detected at the time t2 _c ″ (first detection potential) and the potential of the bus 7 detected at the time t3 _c ″ (second detection potential). It is determined whether both are high potentials or both are low potentials. When the client circuit _6b determines that both are the high potential or both are the low potential, the bit value corresponding to the first detection potential is set to the bit value of the first bit of the host transmission first half data. Adopt as a detection result. When the client circuit _6b determines that one of the first detection potential and the second detection potential is the high potential and the other is the low potential, the bit value of the first bit of the host transmission first half data Was not obtained.

When the second counter 38 continues to count pulses, and the count result of the second counter 38 reaches 1 CBT equivalent pulse number N CC _b , as shown at time t4 _c "in FIG. Counting starts again from “1”. Then, as shown at time t5 _c "in FIG. 16, when a pulse of the counting result by the second counter 38 becomes the number first pulse, the client circuit 6 _b, the clock signal generated by the clock generator 13 in synchronization with detecting the potential of the bus 7. the client circuit 6 _b, as shown at time t6 _c "in FIG. 16, when the counting result of the second counter 38 becomes the number second pulse, The potential of the bus 7 is detected in synchronization with the clock signal generated by the clock generator 13.

The client circuit 6 _b, based on their time t5 _c "potential of the bus 7 detected (first detection potential) and time t6 _c" to the detected potential of the bus 7 (the second detection potential), The bit value of the second bit of the host transmission first half data is acquired.
The method for detecting the bit value of the second bit of the host transmission first half data is the same as the case of the bit value of the first bit of the host transmission first half data.

When the second counter 38 continues to count pulses, and the counting result of the second counter 38 reaches the number of pulses corresponding to 1 CBT, NCC _b , the pulse of the second counter 38 is counted as shown at time t7 _c "in FIG. Counting starts again from “1”. Then, as shown at time t8 _c "in FIG. 16, when a pulse of the counting result by the second counter 38 becomes the number first pulse, the client circuit 6 _b, the clock signal generated by the clock generator 13 in synchronization with detecting the potential of the bus 7. the client circuit 6 _b, as shown at time t9 _c "in FIG. 16, when the counting result of the second counter 38 becomes the number second pulse, The potential of the bus 7 is detected in synchronization with the clock signal generated by the clock generator 13.

Further, the client circuit 6 _b is based on the potential of the bus 7 detected at the time t8 _c ″ (first detection potential) and the potential of the bus 7 detected at the time t9 _c ″ (second detection potential). The bit value of the third bit of the host transmission first half data is acquired.
The method of detecting the bit value of the third bit of the host transmission first half data is the same as that of the bit value of the first bit of the host transmission first half data.

When the second counter 38 continues to count pulses, and the count result of the second counter 38 reaches 1 CBT equivalent pulse number N CC _b , as shown at time t10 _c ″ in FIG. Counting starts again from “1”. Then, as shown at time t11 _c "in FIG. 16, when a pulse of the counting result by the second counter 38 becomes the number first pulse, the client circuit 6 _b, the clock signal generated by the clock generator 13 in synchronization with detecting the potential of the bus 7. the client circuit 6 _b, as shown at time t12 _c "in FIG. 16, when the counting result of the second counter 38 becomes the number second pulse, The potential of the bus 7 is detected in synchronization with the clock signal generated by the clock generator 13.

Further, the client circuit 6 _b determines the potential of the bus 7 detected at the time t11 _c ″ (first detection potential) and the potential of the bus 7 detected at the time t12 _c ″ (second detection potential). The bit value of the fourth bit of the host transmission first half data is acquired.
The method for detecting the bit value of the second bit of the host transmission first half data is the same as the case of the bit value of the first bit of the host transmission first half data.
As described above, the client circuit 6 _b sequentially detects the bit values of the host transmission first half data sent to the bus 7 in synchronization with the time corresponding to the number of pulses corresponding to 1 CBT NCC _b . Thereby, the host transmission first half data is received at the second communication speed.

Next, the third reference signal is sent from the client circuit 6 _a to the bus 7. As a result, the potential of the bus 7 is switched to a potential different from the previous potential.
Therefore, the client circuit 6 _b detects this potential change that appears after the transmission of the host transmission first half data. Then, when the potential change is detected, the host circuit 4 sets the count result of the pulses of the second counter 38 to “1”.
As a result, the client circuit 6 _b can synchronize the potential of the bus 7 with the clock signal generated by the clock generation unit 27 and synchronize the data transfer timing again.

Next, the host transmission latter half data is sent from the host circuit 4 to the bus 7. The transmission of the host transmission latter half data is performed by controlling the potential of the bus 7 in accordance with each of the first to fourth bits included in the host transmission latter half data.
The method for detecting the bit value of the host transmission second half data is the same as that for the host transmission first half data.
Next, the fifth reference signal and the gap signal are sequentially sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is changed to the high potential after being set to the low potential for 1 CBT.
Therefore, the client circuit 6 _b detects the switching from the low potential to the high potential that appears after the transmission of the host transmission second half data, so that the gap signal transmitted from the host circuit 4 to the bus 7 at the end of the data transmission period. Is detected, and the data transmission period ends.

<5-4 (2). About data reception period>
Next, a description will be given of a data reception period host circuit 4 receives the 8-bit data from the client circuit 6 _b.
In the data reception period, as shown in FIG. 9 (4), first, a read command and a gap signal are sequentially sent from the host circuit 4 to the bus 7.
Therefore, the client circuit 6 _b, detects the instruction and signals sent from the host circuit 4 to the bus 7, performs various operations according to the detected instruction and signals.
Next, the client circuit 6 _b sequentially sends the fourth reference signal, the first client transmission data, the fifth reference signal, the second client transmission data, the gap detection auxiliary signal, and the gap signal to the bus 7 in order.

Specifically, first, a read command is sent from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is first set to the low potential between 1 CBT and then set to the next high potential between 1 CBT, and is set to the next high potential between 1 CBT.
Therefore, the client circuit 6 _b counts the clock signal pulses generated by the clock generation unit 27 while the potential of the bus 7 is set to the low potential by the read command, and internally counts the count result as the number of pulses equivalent to 1 CBT. It is stored in the memory 34.

Thus, the length of 1CBT from the host circuit 4 to the client circuit 6 _b is transmitted.
In the data reception period, the client circuit 6 _b switches the count result of the first counter 37 from “1” to the 1 CBT equivalent pulse number NCC _b stored in the internal memory 34, and then the 1 CBT equivalent pulse. Detection and control of the potential of the bus 7 is performed by setting the time until the number NCC _b is switched to “1” as 1 CBT.

In the data reception period, the client circuit 6 _b starts controlling the potential of the bus 7 in synchronization with the timing at which the counting result of the second counter 38 is switched from the 1 CBT equivalent pulse number NCC _b to “1”.
Next, a gap signal is output from the host circuit 4 to the bus 7. As a result, the potential of the bus 7 is switched to the high potential.
Next, the client circuit 6 _b sends the fourth reference signal to the bus 7.

The fourth reference signal (“client reference signal” in a broad sense) is the clock signal supplied to the client circuit 6 _b by the clock generator 27 and the clock signal supplied to the host circuit 4 by the clock generator 13. It is a signal that starts in synchronization.
The fourth reference signal is represented by 1 bit having a bit value “0”.
Therefore, the fourth reference signal is transmitted by the client circuit 6 _b holding the bus 7 potential at the low potential for 1 CBT.
Next, the client circuit 6 _b sends the client transmission first half data to the bus 7.
The first half of client transmission data (“client transmission data” in a broad sense) is 4-bit data of the first half of 8-bit data transmitted from the client circuit 6 _b to the host circuit 4.

Therefore, the first half transmission data of the client is transmitted by controlling the potential of the bus 7 according to the first to fourth bits included in the first half transmission data of the host.
Specifically, the transmission of the first half of the client transmission data is performed as follows.
First, the voltage of the bus 7 is controlled by the client circuit _6b based on the value of the first bit. Then, voltage control based on the value of the first bit is performed for 1 CBT.
Next, the voltage of the bus 7 is controlled by the client circuit _6b based on the value of the second bit. Then, voltage control based on the value of the second bit is performed for 1 CBT.

Next, the voltage of the bus 7 is controlled by the client circuit _6b based on the value of the third bit. Then, voltage control based on the value of the third bit is performed for 1 CBT.
Next, the voltage of the bus 7 is controlled by the client circuit _6b based on the value of the fourth bit. Then, voltage control based on the value of the fourth bit is performed for 1 CBT.
Next, the client circuit 6 _b sends the fifth reference signal to the bus 7.
The fifth reference signal (“client reference signal” in a broad sense) is the clock signal supplied from the clock generator 27 to the client circuit 6 _b and the clock signal supplied from the clock generator 13 to the host circuit 4. It is a signal that starts in synchronization.
The fifth reference signal is represented by 1 bit having a bit value different from the bit value of the fourth bit of the first half of client transmission data.

For example, when the bit value of the fourth bit of the first half of client transmission data is “1”, the bit value of the fifth reference signal is “0”.
Further, when the bit value of the fourth bit of the client first half data is “0”, the bit value of the fifth reference signal is “1”.
Therefore, the fifth reference signal is transmitted when the potential corresponding to the fourth bit of the first half of the client transmission data is the high potential, the client circuit 6 _b holds the potential of the bus 7 at the low potential for 1 CBT. To do.

The fifth reference signal is transmitted when the potential corresponding to the fourth bit of the first half of client transmission data is a low potential, the client circuit 6 _b holds the potential of the bus 7 at the high potential between 1 CBT. To do.
Next, the client circuit 6 _b sends the client transmission latter half data to the bus 7.
The latter half of client transmission data (“client transmission data” in a broad sense) is the latter half of 4 bits of the 8 bits of data transmitted from the client circuit 6 _b to the host circuit 4.

The method for sending client transmission latter half data is the same as that for client transmission first half data.
It should be noted that the host circuit 4 and the client circuit 6 _b during the 8-bit data transmission in the data reception period so that the time required for transmitting the 8-bit data from the client circuit 6 _b to the host circuit 4 is less than a predetermined time. Prohibits execution of interrupt processing.
Next, the client circuit 6 _b sequentially sends the gap detection auxiliary signal and the gap signal to the bus 7 and then ends this data reception period.

<6. Specific operation of communication system>
Next, the operation of the communication system of the present embodiment will be described based on a specific situation.
First, host control processing is executed by the host circuit 4. When execution of the host control process is started, as shown in FIG. 9A, first, the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m enter an idle period. In the idle period, first, the host circuit 4 sends a gap signal to the bus 7. In the gap signal, the potential of the bus 7 is set to the high potential.
Here, it is assumed that a command for transmitting data to the client circuit 6 ₁ (for example, a coulomb counter) is output from the host CPU 3 to the host circuit 4. Then, the host circuit 4 sends a communication register reset signal and a gap signal to the bus 7.

When the communication register reset signal (the c any number of 1 to m) client circuit 6 _c is received by the client circuit 6 _c initializes the communication register 39 ₁ of its own circuit.
When the initialization of the communication register 39 ₁ stored value is completed, the host circuit 4 and the client circuit 6 _c is, transition from idle period in the address period.
In the address period, as shown in FIG. 9 (2), the host circuit 4 first sends an addressing signal to the bus 7. In the addressing signal, the potential of the bus 7 is first made low for 1 GBT and then made high for the next 1 GBT.

When an addressing signal is sent to the bus 7, first, the potential of the bus 7 changes to a low potential. If the change to the Low potential of the potential of the bus 7 is detected by the client circuit 6 _c, the client circuit 6 _c starts the pulse count of the clock signal generated by the clock generator 27. The counting of pulses by the client circuit _6c is continued while the potential of the bus 7 is set to the low potential by the addressing signal.

When the pulse counting is completed, the client circuit 6 _c stores the counting result in the internal memory 34 of its own circuit as the 1 GBT equivalent pulse number NGCc. When the 1 GBT equivalent pulse number NGCc is stored in the internal memory 34, each time the first counter 37 of the client circuit 6 _c reaches the stored 1 GBT equivalent pulse number NGCc, the pulse count result is It starts from the initial value “1”.
When the sending of the addressing signal is completed, the host circuit 4 sends the first reference signal to the bus 7. In the first reference signal, the potential of the bus 7 is held at a low potential for 1 GBT.

When a client circuit 6 _c changes to the Low potential of the potential of the bus 7 is detected, the client circuit 6 _c is, return the counting result of the pulses of the first counter 37 to "1".
When transmission of the first reference signal is ended, the host circuit 4 sends out an address signal designating the address of the client circuit ₆₁ to the bus 7. In sending the address signal, the host circuit 4 first performs potential control based on the value of the first bit of the address signal for 1 GBT as shown at times t1 _h 'to t4 _h ' in FIG. Next, the host circuit 4 performs potential control based on the value of the second bit of the address signal for 1 GBT as shown at times t4 _h 'to t7 _h ' in FIG. Next, the host circuit 4 performs potential control based on the value of the third bit of the address signal for 1 GBT as shown at times t7 _h 'to t10 _h ' in FIG.

As a result, the address signal is sent to the bus 7 at the first communication speed.
When the address signal is sent to the bus 7, the client circuit 6 _c is, as shown at time t1 _h '~t4 _h' in FIG. 15, the counting result of the pulses of the first counter 37 is "1" (time t1 _h The potential of the bus 7 is detected twice until it becomes “1” (time t 4 _h ′) after becoming “)”. Then, the client circuit 6 _c acquires the bit value of the first bit of the address signal based on the detection results.

The client circuit 6 _c is, as shown at time t4 _c '~t7 _c' in FIG. 15, 'pulse counting result by the first counter 37 from again "1" (time t7 _c' time t4 _c) and Until then, the potential of the bus 7 is detected twice. Then, the client circuit 6 _c acquires the bit value of the second bit of the address signal based on the detection results.
Further, as shown at time t7 _c ′ to t10 _c ′ in FIG. 15, the client circuit 6 _{c determines} that the pulse counting result by the first counter 37 again becomes “1” (time t10 _c ′) from time t7 _c ′. Until then, the potential of the bus 7 is detected twice. Then, the client circuit 6 _c acquires the bit value of the third bit of the address signal based on these detection results.

Thereby, an address signal is acquired from the bus 7 at the first communication speed.
When all the bit values of the address signal are acquired, the client circuit 6 _c determines whether or not the address specified by the acquired address signal matches the address of its own circuit. In this determination, obtaining a judgment result that only the client circuit ₆₁ matches the address of the circuit.
When the transmission of the address signal is completed, the host circuit 4 transmits the gap detection auxiliary signal and the gap signal to the bus 7, and then shifts to the data transmission period.

In addition, of the client circuit 6 _c having received the gap detection auxiliary signal and gap signals, only the client circuit 6 _1, shifts to the data transmission period.
In the data transmission period, as shown in FIG. 9 (3), first, the host circuit 4 sends a write command to the bus 7. In the write command, the bus potential is first set to the low potential during ₁ CBT of the client circuit 61 (hereinafter simply referred to as “1 CBT” in this data transmission period), and is set to the high potential between the next 1 CBT and between the next 1 CBT. Low potential.

When a write command is sent to the bus 7, first, the potential of the bus 7 changes to a low potential. If the change to the Low potential of the potential of the bus 7 is detected by the client circuit _61, the client circuit ₆₁ starts the pulse count of the clock signal generated by the clock generator 27. Counting pulses by the client circuit ₆₁ is continued by the write command to the potential of the bus 7 becomes High potential.

When the count of the pulse is completed, the client circuit ₆₁ is, and stores the count result in the internal memory 34 of the self circuit as 1CBT corresponding pulse number NCC _1. When 1CBT corresponding pulse number NCC ₁ is stored, the second counter 38 of the client circuit ₆₁ is, each time a pulse count result is 1CBT corresponding pulse number NCC _1, the counting result of the pulses from the initial value "1" To be started.
When the sending of the write command is completed, the host circuit 4 sends the second reference signal to the bus 7. In the second reference signal, the potential of the bus 7 is held at the high potential for 1 CBT.
If a change to the High potential of the potential of the bus 7 client circuit 6 ₁ is detected, the client circuit ₆₁ is returned to the counting result of the pulses of the second counter 38 to "1".

When the transmission of the second reference signal is completed, the host circuit 4 transmits the host transmission first half data to the bus 7. In sending the first half data of the host transmission, the host circuit 4 first performs the potential control based on the value of the first bit of the first half data of the host transmission between 1 CBT, as shown at times t1 _h "to t4 _h " in FIG. Do. Next, the host circuit 4 performs potential control for 1 CBT based on the value of the second bit of the host transmission first half data as shown at times t4 _h "to t7 _h " in FIG. Next, the host circuit 4 performs potential control for 1 CBT based on the value of the third bit of the host transmission first half data as shown at times t7 _h "to t10 _h " in FIG. Next, the host circuit 4 performs potential control for 1 CBT based on the value of the fourth bit of the host transmission first half data, as shown at times t10 _h "to t14 _h " in FIG.

As a result, the host transmission first half data is sent to the bus 7 at the second communication speed.
When the host transmits the first half data is sent to the bus 7, ₁ client circuit 6, as shown at time t1 _c "~ t4 _c" in FIG. 16, the pulse of the counting result by the second counter 38 is "1" (time t1 _c to ") from sounding again" 1 "(time t4 _c" until) detected twice the potential of the bus 7. Then, the client circuit ₆₁ is, the host transmits the first half data based on these detection results The bit value of the first bit of is obtained.

The client circuit 6 _c is, as shown at time t4 _c "~ t7 _c" in FIG. 16, "pulse counting result is again" 1 "of the second counter 38 from (time t7 _c" time t4 _c and) in until detected twice the potential of the bus 7. Then, the client circuit ₆₁ obtains a bit value of the second bit of the host transmission half data based on those detection results.
Furthermore, the client circuit 6 _c is, as shown at time t7 _c "~ t10 _c" in FIG. 16, "pulse counting result is again" 1 "of the second counter 38 from (time t10 _c" time t7 _c and) detected twice the potential of the bus 7 by the time made. Then, the client circuit ₆₁ obtains a bit value of the third bit of the host transmission half data based on those detection results.

The client circuit 6 _c is, as shown at time t10 _c "~ t13 _c" in FIG. 16, "pulse counting result is again" 1 "of the second counter 38 from (time t13 _c" time t10 _c and) in until detected twice the potential of the bus 7. Then, the client circuit ₆₁ obtains a bit value of the fourth bit of the host transmission half data based on those detection results.
When the transmission of the first half of the host transmission data is completed, the host circuit 4 transmits the third reference signal to the bus 7. In the third reference signal, the potential of the bus 7 is set to a potential different from the potential corresponding to the fourth bit of the host transmission first half data.

When the change in the potential of the bus 7 client circuit 6 ₁ is detected, the client circuit ₆₁ is returned to the counting result of the pulses of the second counter 38 to "1".
When the transmission of the third reference signal is completed, the host circuit 4 transmits the host transmission latter half data to the bus 7. Late host transmission data, as well as the host transmission early data, is received by the client circuit 6 _1.

When the transmission of the host transmission latter half data is completed, the host circuit 4 transmits the gap detection auxiliary signal and the gap signal to the bus 7 and then ends this data transmission period.
Further, when the gap detection auxiliary signal and gap signal client circuit 6 ₁ receives, the client circuit _61, and ends the data transmission period.
When the client circuit 6 ₁ receives 8-bit data transmitted from the host circuit 4, the client circuit 6 ₁ (that is, a coulomb counter) detects the remaining battery level using the received data.

On the other hand, the host circuit 4 from the host CPU 3, a command for acquiring the data from the client circuit ₆₁ is output. Then, the host circuit 4 and the client circuit _61, after the address period, in place of the data transmission period, the process proceeds to the data reception period.
In the data reception period, as shown in FIG. 9 (4), first, the host circuit 4 sends a read command to the bus 7. In the read command, the potential of the bus 7 is first set to the low potential between ₁ CBT of the client circuit 61 (hereinafter simply referred to as “1 CBT” in this data reception period) and then set to the high potential between the next 1 CBT. It is set to High potential.

When a read command is sent to the bus 7, first, the potential of the bus 7 changes to a low potential. If the change to the Low potential of the potential of the bus 7 is detected by the client circuit _61, the client circuit ₆₁ starts the pulse count of the clock signal generated by the clock generator 27. Counting pulses by the client circuit ₆₁ is continued by the read command to the potential of the bus 7 becomes High potential.

When the count of the pulse is completed, the client circuit ₆₁ is, and stores the count result in the internal memory 34 of the self circuit as 1CBT corresponding pulse number NCC _1. When 1CBT corresponding pulse number NCC ₁ is stored, the second counter 38 of the client circuit ₆₁ is, each time a pulse count result is 1CBT corresponding pulse number NCC _1, the counting result of the pulses from the initial value "1" To be started.
When the sending of the read command is completed, the host circuit 4 sends a gap signal to the bus 7.
When transmission of the gap signal is completed, the client circuit ₆₁ sends out the fourth reference signal to the bus 7. In the fourth reference signal, the potential of the bus 7 is set to a low potential for 1 CBT.
When the host circuit 4 detects the change of the potential of the bus 7 to the low potential, the host circuit 4 returns the pulse counting result by the second counter 36 to “1”.

When transmission of the fourth reference signal is ended, the client circuit ₆₁ sends out a client sends the first half data to the bus 7. The delivery client sending the first half data, the client circuit ₆₁ is, first, as shown at time t1 _c t4 _c of FIG. 11 is performed among 1CBT potential control based on the value of the first bit of the client sending the first half data . Next, the client circuit ₆₁ is, as shown at time t4 _c ~t7 _c in FIG. 11 is performed among 1CBT potential control based on the value of the second bit of the client sending the first half data. Next, the client circuit ₆₁ is, as shown at time t7 _c ~t11 _c in FIG. 11 is performed among 1CBT potential control based on the value of the third bit of the client sending the first half data. Next, the client circuit ₆₁ is, as shown at time t10 _c ~t13 _c in FIG. 11 is performed among 1CBT potential control based on the value of the fourth bit of the client sending the first half data.

As a result, the client first half data is sent to the bus 7 at the second communication speed.
Here, the client circuit ₆₁ is counted result by the first counter 37, after switching to "1" from 1CBT corresponding pulse number NCC _b, then the time from 1CBT corresponding pulse number NCC _b to switch to "1" Is set to 1 CBT, and the potential of the bus 7 is controlled.
When the first half of the client transmission data is sent to the bus 7, the host circuit 4 determines that the count result of the pulses by the second counter 35 is “1” (time t1 _h ) as shown at times t1 _{h to} t4 _h in FIG. Then, the potential of the bus 7 is detected twice until it becomes “1” (time t4 _h ) again. Then, the host circuit 4 acquires the bit value of the first bit of the client transmission first half data based on the detection result.

Further, as shown in the time t4 _{h to} t7 _h in FIG. 11, the host circuit 4 starts the bus 7 from the time t4 _h until the pulse counting result by the second counter 36 again becomes “1” (time t7 _h ). Is detected twice. Then, the host circuit 4 acquires the bit value of the second bit of the client transmission first half data based on the detection result.
Furthermore, as shown in the time t7 _{h to} t10 _h in FIG. 11, the host circuit 4 starts the bus 7 from the time t7 _h until the pulse counting result by the second counter 36 becomes “1” (time t11 _h ) again. Is detected twice. Then, the host circuit 4 acquires the bit value of the third bit of the client transmission first half data based on the detection result.

Further, as shown in the time t10 _{h to} t13 _h in FIG. 11, the host circuit 4 starts from the time t4 _h until the pulse counting result by the second counter 36 becomes “1” (time t13 _h ) again. Is detected twice. Then, the host circuit 4 acquires the bit value of the fourth bit of the client transmission first half data based on the detection result.
Thereby, the first half of client transmission data is acquired from the bus 7 at the second communication speed.
When sending client transmits the first half data is completed, the client circuit ₆₁ sends out the fifth reference signal to the bus 7. In the fifth reference signal, the potential of the bus 7 is set to a potential different from the potential corresponding to the fourth bit of the host transmission first half data.

When the host circuit 4 detects the change in the potential of the bus 7, the host circuit 4 causes the second counter 36 to return the pulse count result to “1”.
When transmission of the fifth reference signal is ended, the client circuit ₆₁ sends out the second half client sends data to the bus 7. The client transmission second half data is received by the host circuit 4 in the same manner as the client transmission first half data.
When the client sends the late data delivery is completed, the client circuit ₆₁ is, after sending the gap detection auxiliary signal and gap signal to the bus 7, to end the data reception period.
Further, when the host circuit 4 receives the gap detection auxiliary signal and the gap signal, the host circuit 4 ends this data reception period.
When the 8-bit data sent from the client circuit 6 ₁ host circuit 4 receives the host circuit 4, the received data is transmitted to the host CPU 3.

As described above, in the present embodiment, the host circuit 4 in FIG. 1 constitutes the host described in the claims, and similarly, the client circuits 6 _{1 to} 6 _{m in} FIG. 1 constitute the client. 1 comprises a common line, the host circuit 4 in FIGS. 1 and 2, the control command generator 15 and the bus communication unit 16 in FIG. 2 are address signal sending means, host communication means, and first time setting signal. The sending means, the address reference signal sending means, the second time setting signal sending means, and the data reference signal sending means are configured, and the client circuit 6 _a shown in FIGS. 1 and 2, the bus communication unit 28 shown in FIG. Constitutes address signal acquisition means, client communication means, first signal transmission time measurement means, address signal bit value detection means, second signal transmission time detection means and data bit value detection means. Addressing signals constitute a first time setting signal, a clock generator 27 of FIG. 5 constitute a clock signal generating means for a client, a write instruction of FIG. 8 corresponds to a second time setting signal.

<7. About action and effect>
(1) As described above, in the present embodiment, the sending and detection of the address signal between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m are performed by the client circuit 6 _slow having the slowest maximum communication speed. Is performed at the first communication speed that can be received.
Furthermore, the transmission and reception of data between the client circuit 6 _a that is specified by the host circuit 4 and the address signal and to perform at a maximum communication speed of the client circuit 6 _a.
Therefore, for example, the client circuit 6 _small (small is any number from 1 to m) having a _small amount of communication with the host circuit 4 can transmit / receive data to / from the host circuit 4 at a low communication speed. The client circuit 6 _large (large is any number from 1 to m, which is different from small) can transmit and receive data to and from the host circuit 4 at a high communication speed. there is a possibility.

Therefore, for example, transmission and reception of data between the host circuit 4 and a plurality of clients circuits 6 ₁ to 6 _m, all the client circuit 6 ₁ to 6 _m as compared to the method performed in the same communication speed, the client circuits 6 ₁ - There is a possibility that the time required for data transmission / reception can be shortened while preventing an increase in power consumption of 6 _m .
In the present embodiment, an example in which the host circuit 4 that is dedicated hardware is used as the host of the communication system has been described. However, the present invention is not limited to this. For example, as shown in FIG. 15, a host CPU 3 that implements the function of the host circuit 4 with software may be used.

(2) Also, as shown in FIG. 9, the host circuit 4 holds the potential of the bus 7 at a low potential for 1 GBT prior to sending the address signal.
Further, the host circuit 4 sequentially sends each bit value of the address signal to the bus 7 by 1 GBT at the time of sending the address signal.
Further, each of the plurality of client circuits 6 _{1 to} 6 _m measures the time during which the bus 7 is held at the low potential.
Each of the plurality of client circuits 6 _{1 to} 6 _m sequentially detects the bit value of the address signal sent to the bus 7 in synchronization with the measured time.
Therefore, for example, there is a possibility that transmission and detection of an address signal between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m can be performed more appropriately at the first communication speed.
Further, even if the pulse width of the clock signal supplied from the clock generation unit 27 to the client circuits 6 _{1 to} 6 _m changes due to a change in environment or the like, the address signal can be acquired more appropriately.

(3) Also, the host circuit 4 sends a first reference signal to the bus 7 as a reference for sending the address signal before sending the address signal.
Furthermore, each of the plurality of client circuits 6 _{1 to} 6 _m detects the first reference signal sent to the bus 7 and synchronizes with the time corresponding to the number of pulses NGC _{1 to} NGC _{m for 1} GBT, The bit value of the address signal sent to 7 is sequentially detected.
Therefore, for example, there is a possibility that each of the plurality of client circuits 6 _{1 to} 6 _m can accurately detect an address signal transmitted from the host circuit 4.

(4) Further, the host circuit 4 holds the potential of the bus 7 at the low potential for 1 CBT prior to the communication with the client circuit 6 _a specified by the address signal.
In addition, the host circuit 4 sequentially sends each bit value of data (host transmission first half data and host transmission second half data) to the bus 7 one CBT at a time.
Further, the client circuit 6 _a measures the time during which the low potential is sent to the bus 7.
Further, the client circuit 6 _a sequentially receives the bit values of the data sent to the bus 7 in synchronization with the measured time.
Therefore, for example, there is a possibility that data transmission / reception between the host circuit 4 and the plurality of client circuits 6 _{1 to} 6 _m can be performed more appropriately at the second communication speed.
Further, due to changes in the environment, even if the pulse width of the clock signal supplied from the clock generator 27 to the client circuit 6 _a is changed, retrieve data more appropriately.

(5) Further, the host circuit 4 precedes the transmission of data (first half of host transmission data and second half of host transmission data), and a reference signal (second reference signal and third reference signal) that serves as a reference when sending data. Is sent to the bus 7.
Further, the client circuit 6 _a detects the reference signal (second reference signal and third reference signal) sent to the bus 7, and synchronizes with the time corresponding to the number of pulses NCC _{a for 1} CBT, to the bus 7. The bit value of the data sent to is sequentially detected.
Therefore, for example, there is a possibility that the client circuit _6a can accurately detect the data transmitted from the host circuit 4.

(6) Furthermore, in the communication system of this embodiment, the slowest communication speed among the communication speeds of the plurality of client circuits 6 _{1 to} 6 _m is employed as the first communication speed.
Therefore, when all the client circuits 6 _{1 to} 6 _m have different communication speeds, the host circuit 4 causes the client circuit 6 _{slow with} the slowest communication speed among all the client circuits 6 _{1 to} 6 _m. The address signal is sent to the bus 7 at the third communication speed A ₃ that can be received. When the client circuit 6 _a is designated by the address signal, the host circuit 4 and the client circuit 6 _a perform communication at the third communication speed A ₃ via the bus 7. On the other hand, if the client circuit 6 _a specified by the address signal is other than the client circuit 6slow a client circuit 6 _other (other designated by the host circuit 4 and the address signal is the number of either 1~m Therefore, communication is performed via the bus 7 at a communication speed faster than the third communication speed A ₃ .

(7) Further, as the client circuit having the slowest communication speed among the plurality of client circuits 6 _{1 to} 6 _m , the first client circuit 6 _slow1 (slow1 is 1 to n) capable of communication at the third communication speed A _3. ) And the second client circuit 6 _slow2 (slow2 is any number from 1 to n and is different from slow1). Then, the host circuit 4 sends an address signal at the third communication speed A ₃ . The address signal sent to the bus 7 is detected at the communication speed A by the client circuits 6 _{1 to} 6 _m .

(8) Further, as the plurality of client circuits 6 _{1 to} 6 _m , the first client circuit 6 ₁ capable of communication at the third communication speed A ₃ having the slowest communication speed, and the third communication speed A ₃ next to the communication speed included slow fourth communication speed a ₄ second client circuit 6 ₂ can communicate with the. The first client circuit ₆₁ is inactive, the second client circuit 6 ₂ was active. In such a case, the host circuit 4 may send an address signal at the third communication speed A ₃ . The address signal sent to the bus 7 may be detected at the _third communication speed A ₃ by each of the plurality of client circuits 6 _{1 to} 6 _m .
Here, the first client circuit ₆₁ is in an active state, the first client circuit ₆₁ refers to a state capable of transmitting and receiving data to and from the host circuit 4.
The second client circuit 6 ₂ being in an inactive state means that the second client circuit 6 ₂ is in a state in which data transmission / reception with the host circuit 4 is prohibited.

(9) As the plurality of client circuits 6 _{1 to} 6 _m , the first client capable of communication at the third communication speed A ₃ having the slowest communication speed, and the third communication speed A ₃ communication speed included slow fourth communication speed a ₄ second client circuit 6 ₂ can communicate with the. The first client circuit ₆₁ is inactive, the second client circuit 6 ₂ was active. In such a case, the host circuit 4 may send an address signal at the fourth communication speed A ₄ . The address signal sent to the bus 7 may be detected at the _fourth communication speed A ₄ by each of the plurality of client circuits 6 _{1 to} 6 _m .

It is a block diagram which shows schematic structure of a communication system. It is a block diagram which shows the internal structure of a host circuit. It is a block diagram which shows the internal structure of bus I / O of a host circuit. It is a time chart which shows operation | movement of bus I / O. It is a block diagram which shows the internal structure of a client circuit. It is a block diagram which shows the internal structure of bus I / O of a client circuit. It is explanatory drawing for demonstrating the period when a host control process is performed. It is explanatory drawing for demonstrating the period when a host control process is performed. FIG. 6 is an explanatory diagram for explaining signals, instructions, and data sent to the bus 7 in an idle period, an address period, and a data period. It is explanatory drawing for demonstrating the modification of an address signal. It is explanatory drawing for demonstrating the detection method of client transmission first half data. It is explanatory drawing for demonstrating the period when a client control process is performed. It is explanatory drawing for demonstrating the period when a client control process is performed. It is explanatory drawing for demonstrating the detection method of a communication register reset signal. It is explanatory drawing for demonstrating the detection method of the bit value of an address signal. It is explanatory drawing for demonstrating the detection method of the bit value of host transmission first half data. It is a block diagram which shows schematic structure of the modification of a communication system. It is a block diagram which shows the internal structure of the comparative example of bus I / O.

Explanation of symbols

1 is a mobile phone, 2 is a telephone body, 3 is a host CPU, 4 is a host circuit, 5 is a rechargeable battery, 6 _{1 to} 6 _m are client circuits, 7 is a bus, 8 ₁ is a power supply, 8 ₂ is a pull-up resistor, 9 is a pull-up circuit, 10 is a main body I / O, 11 is a host control unit, 12 is a bus I / O, 13 is a clock generation unit, 14 is a CPU communication unit, 15 is a control command generation unit, and 16 is a bus. Communication unit, 17 power supply control unit, 18 D flip-flop, 19 control signal generation unit, 20 I / O buffer, 21 delay element, 22 AND gate, 23 three-state bus buffer, 24 bus buffer 25 is a bus I / O, 26 is a client control unit, 27 is a clock generation unit, 28 is a bus communication unit, 29 is a control command detection unit, 30 is a power supply control unit, 31 is an oscillation circuit, 32 is an oscillation circuit, 33 is an internal memory, 34 is an internal memory 35 the first counter, the second counter 36, 37 is first counter, the 38 second counter, 39 ₁ ~ 39 _n are register

Claims (20)

A communication system comprising a host, a plurality of clients, and a common line serving as a communication path between the host and the plurality of clients,
The plurality of clients include clients having different communication speeds,
The host sends an address signal for sending at least one of the plurality of clients to the common line at a first communication speed that can be received by the slowest client among the plurality of clients. Means,
Host communication means for transmitting / receiving data to / from the client via the common line at a second communication speed that can be received by the client and the client specified by the address signal after the transmission of the address signal is completed. And comprising
Each of the plurality of clients is
Address signal detection means for detecting the address signal sent to the common line at the first communication speed;
If the address signal detected by the address signal detecting means is an address signal that designates the client, the client communication that transmits and receives the data through the common line with the host at the second communication speed. And a communication system.   The communication system according to claim 1, wherein the first communication speed is a communication speed that can be received by a client having the slowest maximum communication speed among the plurality of clients. The host is a time for transmitting 1 bit from the host to the client having the lowest communication speed through the common line at the first communication speed prior to sending the address signal. A first time setting signal transmitting means for continuously transmitting the first time setting signal to the common line,
The address signal sending means sends each bit value of the address signal to the common line sequentially for the first communication time after the sending of the first time setting signal is finished,
The address signal detection means of each of the plurality of clients is
First signal transmission time measuring means for measuring a time during which the first time setting signal is transmitted to the common line;
After the time measurement by the first signal transmission time measuring unit is completed, the bit values of the address signals transmitted to the common line are sequentially synchronized with the time measured by the first signal transmission time measuring unit. The communication system according to claim 1, further comprising an address signal bit value detection unit for detecting. Each of the plurality of clients includes client clock signal generation means for generating a clock signal,
The first signal transmission time measuring means of each of the plurality of clients is a clock generated by the client clock signal generating means of the own client while the first time setting signal is being transmitted to the common line. Count the pulses of the signal,
The address signal bit value detecting means of each of the plurality of clients has the number of pulses counted by the first signal sending time measuring means after the counting of pulses by the first signal sending time measuring means of its own client is completed. 4. The communication system according to claim 3, wherein the bit value of the address signal transmitted to the common line is sequentially detected based on the information. The host sends an address reference signal, which is a reference for sending the address signal, to the common line after sending the first time setting signal and before sending the address signal. A reference signal sending means;
The address signal bit value detecting means of each of the plurality of clients is configured to count the number of pulses counted by the first signal sending time measuring means of the client from the time when the address reference signal sent to the common line is detected. 5. The communication system according to claim 4, wherein the bit value of the address signal transmitted to the common line is sequentially detected in synchronization with a minute time. After the host finishes sending the address signal, the client designates 1 bit by the address signal from the host via the common line at the second communication speed prior to transmission / reception of the data. A second communication time which is a time when transmitting to a second communication time, a second time setting signal sending means for sending a second time setting signal continuously to the common line,
The host communication means, after finishing sending the second time setting signal, sequentially sends each bit value of the data to the common line by the second communication time,
The client communication means of each of the plurality of clients is:
Second signal transmission time measuring means for measuring a time during which the second time setting signal is transmitted to the common line;
After the time measurement by the second signal transmission time measuring unit is completed, the bit values of the data transmitted to the common line are sequentially detected in synchronization with the time measured by the second signal transmission time measuring unit. 6. The communication system according to claim 1, further comprising: a data bit value detecting unit that performs the operation. Each of the plurality of clients includes client clock signal generation means for generating a clock signal,
The second signal sending time measuring means of each of the plurality of clients is a clock generated by the client clock signal generating means of the own client while the second time setting signal is sent to the common line. Count the pulses of the signal,
The data bit value detecting means of each of the plurality of clients, after the counting of pulses by the second signal sending time measuring means of its own client is completed, calculates the number of pulses counted by the second signal sending time measuring means. 7. The communication system according to claim 6, wherein the bit value of the data sent to the common line is sequentially detected. A data reference signal for sending a data reference signal serving as a reference for sending the data to the common line after starting sending the data after finishing sending the second time setting signal. A delivery means,
The address signal bit value detection means of each of the plurality of clients has the number of pulses counted by the second signal transmission time measurement means of its own client from the time when the data reference signal sent to the common line is detected. The communication system according to claim 7, wherein the bit value of the data sent to the common line is sequentially acquired in synchronization with a minute time. Address signal sending means for sending an address signal designating at least one of the plurality of signals to a common line serving as a communication path with the plurality of clients at a first communication speed that can be received by the slowest client. When,
A host communication means for transmitting and receiving data to and from the client via the common line at a second communication speed that can be received by the client designated by the address signal after transmission of the address signal is completed. A host characterized by that. An address sent to a common line serving as a communication path between the host, another client, and the own client at a first communication speed that can be received by the client having the slowest communication speed among the other clients and the own client. Address signal detecting means for detecting a signal at the first communication speed;
When the address signal detected by the address signal detecting means is an address signal designating the own client, data is transmitted / received through the common line with the host at a second communication speed that can be received by the own client. A client communication means for performing A host, a common wiring that is a communication path of a plurality of clients, and a wiring in the main body that is a communication path between the hosts,
The host is
Address signal sending means for sending an address signal designating at least one of the plurality of clients to the internal wiring;
A host communication means for transmitting and receiving data to and from the client via the common line at a second communication speed that can be received by the client designated by the address signal after transmission of the address signal is completed; A mobile phone main body characterized by the above. A first client capable of communicating with a host at a first communication speed;
A second client capable of communicating with the host at a second communication speed higher than the first communication speed;
The first client is
First address signal detection means for receiving an address signal for designating one of the first client and the second client from the host at the first communication speed;
First communication means for receiving data from the host at the first communication speed,
The second client is
Second address signal detection means for receiving the address signal at the first communication speed;
And a second communication means for receiving data from the host at the second communication speed. A communication method between a host and a plurality of clients that can communicate with each other via a common line serving as a communication path,
When the plurality of clients include ones having different communication speeds,
Sending out an address signal for sending an address signal designating at least one of the plurality of clients to the common line at a first communication speed at which the host having the slowest communication speed among the plurality of clients can receive the host. Steps,
Each of the plurality of clients detects the address signal transmitted to the common line at the first communication speed, and determines whether or not the detected address signal is an address signal designating its own client. An address signal detection step to perform,
A communication step in which, after the detection of the address signal is completed, the host and the client specified by the address signal transmit and receive data at a second communication speed that can be received by the client via the common line; The communication method characterized by performing these. When the communication speed of each of the plurality of clients is different,
In the address signal sending step, the host is at least one of the plurality of clients at a third communication speed that can be received by the first client that is the slowest communication speed among all of the plurality of clients. Send an address signal to the common line,
In the communication step,
When the client specified by the address signal is the first client, the host and the client specified by the address signal communicate at the third communication speed via the common line. ,
When the client specified by the address signal is a client other than the first client, the host and the client specified by the address signal are connected to the third communication speed via the common line. The communication method according to claim 13, wherein communication is performed at a higher communication speed. When the plurality of clients include a first client and a second client capable of communicating at a third communication speed as clients having the slowest communication speed among the plurality of clients,
In the address signal sending step, the host sends an address signal designating at least one of the plurality of clients at the third communication speed;
14. The communication method according to claim 13, wherein in the address signal detection step, each of the plurality of clients detects the address signal transmitted to the common line at the third communication speed. As the plurality of clients, a first client capable of communicating at a third communication speed with the slowest communication speed among the plurality of clients, and a fourth communication speed next to the third communication speed. Including a second client capable of communicating at a communication speed;
Also when the first client is inactive and the second client is active,
Sending the address signal at the third communication speed in the address signal sending step;
14. The communication method according to claim 13, wherein, in the address signal detection step, each of the plurality of clients detects the address signal transmitted to the common line at the third communication speed. As the plurality of clients, a first client capable of communicating at a third communication speed with the slowest communication speed among the plurality of clients, and a fourth communication speed next to the third communication speed. Including a second client capable of communicating at a communication speed;
If the first client is inactive and the second client is active,
Sending the address signal at the fourth communication speed in the address signal sending step;
14. The communication method according to claim 13, wherein, in the address signal detection step, each of the plurality of clients detects the address signal transmitted to the common line at the fourth communication speed.   The communication method according to claim 13, wherein the first communication speed is a communication speed that can be received by a client having the slowest communication speed among the plurality of clients. Prior to the address signal sending step, a time when the host transmits 1 bit from the host to the client with the slowest communication speed through the common line at the first communication speed is a first time A first time setting signal sending step for continuously sending a first time setting signal to the common line,
After the first time setting signal transmission step and before the address signal transmission step, each of the plurality of clients measures a time during which the first time setting signal is transmitted to the common line. Performing a signal transmission time measurement step of
In the address signal sending step, after the host finishes sending the first time setting signal, each bit value of the address signal is sequentially sent to the common line by the second communication time,
In the address signal detection step, each of the plurality of clients is synchronized with the time measured in the first signal transmission time measurement step after the measurement of the time in the first signal transmission time measurement step is completed. The communication method according to claim 13, wherein bit values of the address signals transmitted to the common line are sequentially detected. After the address signal sending step and before the communication step, after the host finishes sending the address signal, 1 bit is sent from the host to the address via the common line at the second communication speed. A second communication time which is a time when transmitting to the client designated by the signal, a second time setting signal sending step for sending a second time setting signal continuously to the common line;
After the second time setting signal sending step, before the communication step, each of the plurality of clients measures a time during which the second time setting signal is sent to the common line. A delivery time measuring step, and
In the communication step,
After the host finishes sending the second time setting signal, the host sequentially sends each bit value of the data to the common line by the second communication time,
After the time measurement by the second signal transmission time measurement step is completed, each of the plurality of clients transmits to the common line in synchronization with the time measured in the second signal transmission time measurement step. 20. The communication system according to claim 13 or 19, wherein bit values of the received data are sequentially detected.

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