JP6493044B2 - Multiprocessor system - Google Patents

Description

  The present invention relates to a multiprocessor system including a storage device such as a dual port memory.

  Patent Document 1 discloses a digital protection control apparatus suitable for performing settling change, setting change, and data transfer inside the apparatus at high speed without affecting the protection control calculation. This digital protection control device has a real-time processing operation block and a network processing block that are tightly coupled by a dual port memory. The real-time processing arithmetic block includes an arithmetic CPU for real-time processing arithmetic and a dual-port memory control circuit that executes dual-port memory write control. The network processing block includes a network CPU for network processing and a dual port memory control circuit for controlling access from the network CPU side of the dual port memory.

  By the way, a dual-port memory built in an application specific integrated circuit (ASIC) or FPGA (Field-Programmable Gate Array) is generally divided into a plurality of blocks. When the number of blocks of the dual port memory to be used is small, one dual port memory and one dual port memory control circuit may be configured on a one-to-one basis. However, when the number of blocks of the dual port memory to be used is large, if the dual port memory and the dual port memory control circuit are configured on a one-to-one basis, the number of dual port memory control circuits increases in proportion to the number of blocks. This causes a problem that a lot of ASIC and FPGA resources are consumed.

  In an ASIC or FPGA, read data read from the dual port memories of a plurality of blocks is input to a selection circuit connected to the output side of the plurality of blocks, and only the read data selected by the selection circuit is stored. In general, it is output to a dual port memory control circuit via an output data bus. As described above, in the method in which one of the read data read from the plurality of dual port memories is selected by the selection circuit and input to the dual port memory control circuit, the wiring of the dual port memory becomes long. Furthermore, the number of stages of gate circuits constituting the selection circuit increases. As a result, the delay of the read data output to the data bus increases. When the read data is multi-bit data, if the delay time is different for each bit, there is a problem that the dual port memory control circuit holds read data having an indefinite value different from normal data.

JP 2004-64892 A

If data with an indefinite value different from the regular data to be transmitted is sent to a processing block such as a real-time processing operation block or network processing block provided with a dual port memory control circuit, the processing block malfunctions. There is a problem that it may end up.
An object of the present invention is to provide a multiprocessor system capable of preventing malfunction of applied equipment.

In order to achieve the above object, a multiprocessor system according to an aspect of the present invention includes a plurality of dual port memories each having two input / output ports from which data is input / output and independent of each other, and the plurality of dual port memories. A processing device that processes input / output data, a memory access controller that controls access of the processing device to a plurality of the dual port memories, and a clock signal generator that transmits a clock signal input to the memory access controller The memory access controller includes a plurality of read data read from one of the plurality of dual port memories as held data in synchronization with the clock signal, and a plurality of the held data The processing device from the data It has a data determination unit that determines the data of the regular outputs, the data determination unit, based on the plurality of difference of the held data to each other, whether the one of the plurality of the holding data to said regular data A determination unit for determining is provided .

  According to one embodiment of the present invention, malfunction of an applied device can be prevented.

1 is a block diagram showing a schematic configuration of a multiprocessor system according to an embodiment of the present invention. 1 is a block diagram showing a schematic configuration of a first memory access controller provided in a multiprocessor system according to an embodiment of the present invention. FIG. It is a figure which shows the timing chart of the data write-in operation | movement in the multiprocessor system by one Embodiment of this invention. It is a figure which shows the timing chart of the data read-out operation | movement in the multiprocessor system by one Embodiment of this invention. It is a figure explaining the signal delay between the bit signals of the read data in the multiprocessor system by one Embodiment of this invention. It is a figure which shows the determination table which the determination circuit with which the 1st memory access controller of the multiprocessor system by one Embodiment of this invention was equipped has memorize | stored. It is a figure which shows the timing chart by the other example of the data read operation by the multiprocessor system by one Embodiment of this invention. FIG. 8 is a diagram showing a determination table corresponding to the data read operation shown in FIG. 7 in the multiprocessor system according to the embodiment of the present invention.

  A multiprocessor system according to an embodiment of the present invention will be described with reference to FIGS. The multiprocessor system according to the present embodiment is applied to, for example, industrial equipment, and can exchange data between two processing devices using, for example, a plurality of dual port memories.

[Schematic configuration of multiprocessor system]
As shown in FIG. 1, the multiprocessor system 1 includes a plurality of dual-port memories 33-1 each having first and second input / output ports (an example of two input / output ports) that receive and input data and are independent of each other. , 33-2,..., 33-n (n is a natural number of 2 or more). Hereinafter, “dual port memories 33-1, 33-2,..., 33-n” may be collectively referred to as “dual port memory 33”. In FIG. 1, the first input / output port is illustrated as “first I / O port”, the second input / output port is illustrated as “second I / O port”, and a dual port memory (Dual Port Random Access Memory). Is illustrated as “DP-RAM”.

  The dual port memory 33-1 is provided independently of the first input / output port 331-1 and the first input / output port 331-1 to / from which the first data is input / output. 2 input / output port 332-1 and a storage unit 333-1 for storing the first data and the second data. The dual port memory 33-2 is provided independently of the first input / output port 331-2 and the first input / output port 331-2, through which the first data is input / output. 2 input / output port 332-2 and a storage unit 333-2 for storing the first data and the second data. The dual port memory 33-n is provided independently of the first input / output port 331-n and the first input / output port 331-n, through which the first data is input / output, and the second data is input / output. A second input / output port 332-n and a storage unit 333-n for storing the first data and the second data.

  The storage unit 333-1 provided in the dual port memory 33-1 has memory cells having an array structure. In response to the first data write signal L_WR2 and the first address signal L_ADR input via the first input / output port 331-1, the dual port memory 33-1 receives the first write input together with these signals. Data (an example of first data) L_DT1 is written to a memory cell provided in the storage unit 333-1. Further, the dual port memory 33-1 receives the second write input with these signals in response to the second data write signal R_WR2 and the second address signal R_ADR input through the second input / output port 332. Data (an example of second data) R_DT1 is written to a memory cell provided in the storage unit 333-1. Further, the dual port memory 33-1 receives first read data (1) from the memory cell provided in the storage unit 333-1 according to the first address signal L_ADR input through the first input / output port 331-1. Example of first data) L_DT2-1 is read out. Further, the dual port memory 33-1 receives the second read data (from the memory cell provided in the storage unit 333-1 according to the second address signal R_ADR input via the second input / output port 332-1). Example of second data) R_DT2-1 is read out.

  The first input / output port 331-1 is provided with an input terminal (not shown) to which the first address signal L_ADR and the first data write signal L_WR2 are input. The first input / output port 331-1 is provided with an input / output terminal (not shown) through which the first write data L_DT1 is input and the first read data L_DT2-1 is output. The second input / output port 332-1 is provided with an input terminal (not shown) to which the second address signal R_ADR and the second data write signal R_WR2 are input. The second input / output port 332-1 is provided with an input / output terminal (not shown) through which the second write data R_DT1 is input and the second read data R_DT2-1 is output.

  The first input / output ports 331-2,... 331-n provided in the dual port memories 33-2,..., 33-n are the first input / output ports provided in the dual port memory 33-1. Since it has the same configuration as 331-1, the description thereof is omitted. Further, the second input / output ports 332-2,... 332-n provided in the dual port memory 33-2,..., 33-n are the second inputs provided in the dual port memory 33-1. Since the configuration is the same as that of the output port 332-1, description thereof is omitted. Further, the storage units 333-2,..., 333-n provided in the dual port memories 33-2,..., 33-n are the storage units 333-1 provided in the dual port memory 33-1. Since the configuration is the same as in FIG.

  The multiprocessor system 1 includes a first central processing unit (CPU) (an example of a processing device) 11 that processes first data input and output in a plurality of dual port memories 33, and a plurality of dual port memories 33. 2 has a second CPU (an example of a processing device) 12 that processes the second data input / output.

  Further, the multiprocessor system 1 transmits a clock signal CLK for transmitting the first memory access controller 31 and the second memory access controller 32 and the clock signal CLK input to the first memory access controller 31 and the second memory access controller 32, respectively. And 14. The first memory access controller 31 controls access of the first CPU 11 to the plurality of dual port memories 33. The second memory access controller 32 controls access of the second CPU 12 to the plurality of dual port memories 33.

  The first CPU 11 is connected to the plurality of dual port memories 33 and the first memory access controller 31. The first CPU 11 outputs a first address signal L_ADR for designating the address of the memory cell to which the first write data L_DT 1 is written or the memory cell to be read to each of the plurality of dual port memories 33. The first address signal L_ADR is input to the storage units 333-1, 333-2,..., 333-n via the first input / output ports 331-1, 331-2,. Is done. Hereinafter, “first input / output ports 331-1, 331-2,..., 331 -n” are collectively referred to as “first input / output ports 331”, and “storage units 333-1, 333-2,. ., 333-n ”may be collectively referred to as“ storage unit 333 ”.

  The first address signal L_ADR is also input to the first memory access controller 31. The first address signal L_ADR is transmitted through the first address bus line 21 provided between the first CPU 11 and the plurality of dual port memories 33 and between the first CPU 11 and the first memory access controller 31. Each is transmitted to the first memory access controller 31.

  The first CPU 11 also outputs a first data write instruction signal L_WR1 for instructing data writing and a first data read instruction signal L_RD1 for instructing data reading to the first memory access controller 31. In addition, the first CPU 11 outputs first write data L_DT 1 for writing to any one of the plurality of dual port memories 33 to the first memory access controller 31. Further, the first CPU 11 receives the first read data L_DT2 read from any one of the plurality of dual port memories 33 and output from the first memory access controller 31.

  The multiprocessor system 1 includes a CPU-side first data bus line 22 provided between the first CPU 11 and the first memory access controller 31. First write data L_DT1 as first data output from the first CPU 11 and written to any one of the plurality of dual port memories 33 is transmitted to the CPU-side first data bus line 22. Further, the first read data L_DT2 as the first data read from any one of the plurality of dual port memories 33 and input to the first CPU 11 is also transmitted to the first data bus line 22 on the CPU side. Thus, the first data bus line 22 on the CPU side can transmit the first data bidirectionally.

  The multiprocessor system 1 is provided between the first memory access controller 31 and the plurality of dual port memories 33, and is capable of transmitting the first data written to any one of the plurality of dual port memories 33. The memory side first data bus line 23w is provided. The write memory side first data bus line 23 w is provided between the first memory access controller 31 and the first input / output port 331. The first input / output ports 331-1, 331-2,..., 331 -n are connected to each other via the write memory side first data bus line 23 w.

  The first write data L_DT1 is transmitted to the first memory access controller 31 through the CPU side first data bus line 22. The first write data L_DT1 transmitted to the first memory access controller 31 is transmitted to the plurality of dual port memories 33 through the memory side first data bus line 23w. The first write data L_DT1 is stored through the first input / output port in the storage unit of one dual port memory selected according to the value of the first address signal L_ADR among the plurality of dual port memories 33. .

  The multiprocessor system 1 includes a read memory provided between the first memory access controller 31 and the plurality of dual port memories 33 and capable of individually transmitting the first data read from the plurality of dual port memories 33. Side first data bus lines 23r-1, 23r-2,..., 23r-n. Read memory side first data bus lines 23r-2, 23r-2,..., 23r-n are provided independently of each other.

  The read memory side first data bus line 23r-1 is provided between the first memory access controller 31 and the first input / output port 331-1. First read data L_DT2-1 (an example of first data) read from the dual port memory 33-1 through the first input / output port 331-1 is transmitted through the read memory side first data bus line 23r-1. Input to the first memory access controller 31.

  The read memory side first data bus line 23r-2 is provided between the first memory access controller 31 and the first input / output port 331-2. The first read data L_DT2-2 (an example of first data) read from the dual port memory 33-2 via the first input / output port 331-2 passes through the read memory side first data bus line 23r-2. Input to the first memory access controller 31.

  The read memory side first data bus line 23r-n is provided between the first memory access controller 31 and the first input / output port 331-n. The first read data L_DT2-n (an example of first data) read from the dual port memory 33-n via the first input / output port 331-n passes through the read memory side first data bus line 23r-n. Input to the first memory access controller 31.

  The first memory access controller 31 outputs the first data write signal L_WR2 to the plurality of dual port memories 33 based on the first data write instruction signal L_WR1 input from the first CPU 11. Further, the first memory access controller 31 clocks the read data read from one of the plurality of dual port memories 33 based on the first data read instruction signal L_RD1 input from the first CPU 11. A plurality of data are held in synchronization with the signal CLK sequentially. The first memory access controller 31 determines regular data to be output to the first CPU 11 from the plurality of retained data, and outputs the retained data determined to be regular data to the first CPU 11. The internal configuration of the first memory access controller 31 will be described later.

  The second CPU 12 is connected to a plurality of dual port memories 33 and a second memory access controller 32. The second CPU 12 outputs a second address signal R_ADR for designating the address of the memory cell to which the second write data R_DT 1 is written or the memory cell to be read to each of the plurality of dual port memories 33. The second address signal R_ADR is input to the storage units 333-1, 333-2,..., 333-n via the second input / output ports 332-1, 332-2,. Is done. Hereinafter, the “second input / output ports 332-1, 332-2,... 332-n” may be collectively referred to as “second input / output ports 332”.

  The second address signal R_ADR is also input to the second memory access controller 32. The second address signal R_ADR is transmitted through the second address bus line 41 provided between the second CPU 12 and the plurality of dual port memories 33 and between the second CPU 12 and the second memory access controller 32. Each is transmitted to the second memory access controller 32.

  The second CPU 12 outputs a second data write instruction signal R_WR1 for instructing data writing and a second data read instruction signal R_RD1 for instructing data reading to the second memory access controller 32. Further, the second CPU 12 outputs the second write data R_DT 1 for writing to any one of the plurality of dual port memories 33 to the second memory access controller 32. Further, the second CPU 12 receives the second read data R_DT2 read from any one of the plurality of dual port memories 33 and output from the second memory access controller 32.

  The multiprocessor system 1 has a CPU-side second data bus line 42 provided between the second CPU 12 and the second memory access controller 32. Second write data R_DT1 as second data output from the second CPU 12 and written to any one of the plurality of dual port memories 33 is transmitted to the second data bus line 42 on the CPU side. Further, second read data R_DT2 as second data read from any one of the plurality of dual port memories 33 and input to the second CPU 12 is also transmitted to the second data bus line 42 on the CPU side. As described above, the CPU-side second data bus line 42 can transmit the second data bidirectionally.

  The multiprocessor system 1 is provided between the second memory access controller 32 and the plurality of dual port memories 33, and is capable of transmitting the second data written to any one of the plurality of dual port memories 33. Memory side second data bus line 43w. The write memory side second data bus line 43w is provided between the second memory access controller 32 and the second input / output ports 332-1, 332-2, ..., 332-n. The second input / output ports 332-1, 332-2,..., 332-n are connected to each other via the write memory side second data bus line 43w.

  The second write data R_DT1 is transmitted to the second memory access controller 32 through the CPU-side second data bus line 42. The second write data R_DT1 transmitted to the second memory access controller 32 is transmitted to the plurality of dual port memories 33 through the memory-side second data bus line 43w. The second write data R_DT1 is stored via the second input / output port in the storage unit of one dual port memory selected according to the value of the second address signal R_ADR among the plurality of dual port memories 33. .

  The multiprocessor system 1 includes a read memory provided between the second memory access controller 32 and the plurality of dual port memories 33 and capable of individually transmitting second data read from the plurality of dual port memories 33. Side second data bus lines 43r-1, 43r-2,..., 43r-n. Read memory side second data bus lines 43r-2, 43r-2,..., 43r-n are provided independently of each other.

  The read memory side second data bus line 43r-1 is provided between the second memory access controller 32 and the second input / output port 332-1. Second read data R_DT2-1 (an example of second data) read from the dual port memory 33-1 through the second input / output port 332-1 is transmitted through the read memory side second data bus line 43r-1. Input to the second memory access controller 32.

  The read memory side second data bus line 43r-2 is provided between the second memory access controller 32 and the second input / output port 332-2. Second read data R_DT2-2 (an example of second data) read from the dual port memory 33-2 via the second input / output port 332-2 is transmitted through the read memory side second data bus line 43r-2. Input to the second memory access controller 32.

  The read memory side second data bus line 43r-n is provided between the second memory access controller 32 and the second input / output port 332-n. Second read data R_DT2-n (an example of second data) read from the dual port memory 33-n via the second input / output port 332-n passes through the read memory side second data bus line 43r-n. Input to the second memory access controller 32.

  The second memory access controller 32 outputs the second data write signal R_WR2 to the plurality of dual port memories 33 based on the second data write instruction signal R_WR1 input from the second CPU 12. Further, the second memory access controller 32 clocks the read data read from one of the plurality of dual port memories 33 based on the second data read instruction signal R_RD1 input from the second CPU 12. A plurality of data are held in synchronization with the signal CLK sequentially. The second memory access controller 32 determines regular data to be output to the second CPU 12 from the plurality of retained data, and outputs the retained data determined to be regular data to the second CPU 12. The internal configuration of the second memory access controller 32 will be described later.

  In the present embodiment, the first memory access controller 31, the second memory access controller 32, and the plurality of dual port memories 33 are incorporated in an FPGA (Field-Programmable Gate Array) 13, as shown in FIG. . The first memory access controller 31, the second memory access controller 32, and the plurality of dual port memories 33 may be incorporated in an application specific integrated circuit (ASIC) or may be independent of each other. It may be configured by a circuit. Further, the first memory access controller 31, the second memory access controller 32, and the plurality of dual port memories 33 have a part of the configuration (for example, a plurality of dual port memories 33) incorporated in the FPGA or ASIC, The remaining configuration (for example, the first and second memory access controllers 31 and 32) may be configured by an independent circuit connected to the FPGA or ASIC.

  In industrial equipment to which the multiprocessor system 1 is applied, for example, the first CPU 11 is used as a processing apparatus for main processing, and the second CPU 12 is used as a processing apparatus for external communication with external equipment. The first CPU 11 transmits and stores a large amount of data to the plurality of dual port memories 33. The second CPU 12 reads the data stored in the plurality of dual port memories 33 and transmits it to the external device. A certain amount of time is required from when the second CPU 12 transmits data to the external device until it receives a predetermined result from the external device. Therefore, the first CPU 11 can continue another data process until the second CPU 12 transmits data based on the result received from the external device to the plurality of dual port memories 33. Thereby, industrial equipment to which the multiprocessor system 1 is applied can realize high-speed processing.

[Internal configuration of first and second memory access controllers]
Next, the internal configuration of the first and second memory access controllers 31 and 32 will be described with reference to FIG.
As shown in FIG. 2, the first memory access controller 31 generates the access signal for controlling the access of the first CPU 11 based on the first instruction signal input from the first CPU 11. It has.

  The first access signal generator 131 receives the first address signal L_ADR and the clock signal CLK. Incidentally, FIG. 1 shows a plurality of dual port memories 33 as access destinations of the first CPU 11. Actually, other parts (such as a communication circuit) (not shown) exist as the access destination of the first CPU 11. The multiprocessor system 1 is configured to input the first address signal L_ADR to the first memory access controller 31 only when accessing the plurality of dual port memories 33, and to operate the first memory access controller 31 only in this case. Has been.

  The first access signal generator 131 outputs the first data write signal L_WR2 whose signal state is invalid, that is, negated, to the first input / output ports 331 of the plurality of dual port memories 33 in the non-access state. ing. The first access signal generator 131 receives at least one cycle of the clock signal CLK in synchronization with the clock signal CLK when the first address signal L_ADR is input and the first data write instruction signal L_WR1 is enabled, that is, asserted. The first data write signal L_WR2 in the minute asserted state is output to the plurality of dual port memories 33.

  The first access signal generator 131 also stores first data holding signals RDL1, RDL2 for holding the first selection data L_DT2s selected by reading from one of the dual port memories 33. ,..., RDLi (i is a natural number of 3 or more). Further, the first access signal generator 131 generates a first data read control signal ROE for switching whether or not the first output buffer circuit 132e (details will be described later) is in a high impedance state. The first data read control signal ROE and the first data holding signals RDL1, RDL2,..., RDLi correspond to the access signals generated by the first access signal generator 131.

  The first access signal generation unit 131 outputs the first data holding signals RDL1, RDL2,..., RDLi whose signal state is invalid, ie, negated, in the non-access state to the first data determination unit 132 (details will be described later). Is output. When the first data read instruction signal L_RD1 is valid, that is, asserted, the first access signal generator 131 is synchronized with the clock signal CLK and is asserted for one cycle of the clock signal CLK. RDL2,..., RDLi are sequentially output to the first data determination unit 132.

The first access signal generator 131 outputs the first data read control signal ROE whose signal state is invalid, ie, negated, to the first output buffer circuit 132e in the non-access state. When the first data read instruction signal L_RD1 is in the asserted state, the first access signal generating unit 131 receives the first data read control signal ROE that is in the asserted state for at least one cycle of the clock signal CLK in synchronization with the clock signal CLK. The data is output to the first output buffer circuit 132e.
The first data holding signals RDL1, RDL2,..., RDLi and the first data read control signal ROE correspond to the first instruction signal generated by the first access signal generator 131.

(Configuration of the first data determination unit)
The first memory access controller 31 uses the first read data L_DT2-k (k is a natural number between 1 and n) read from one of the plurality of dual port memories 33 as the clock signal CLK. , L_DT2h-2,..., L_DT2h-i, and a plurality of first holding data L_DT2h-1, L_DT2h-2,..., L_DT2s-n Is provided with a first data determination unit 132 that determines first read data (an example of regular data) L_DT2 to be output to the first CPU 11.

  The first memory access controller 31 includes first read data L_DT2- of the read memory side first data bus lines 23r-1, 23r-2,..., 23r-n connected to the plurality of dual port memories 33. Read memory side first data bus line (an example of one data bus line) 23r-k (k is a natural number between 1 and n) to which k is transmitted is input to the plurality of dual port memories 33. A first line selection circuit (an example of a line selection unit) 132a that is selected based on the first address signal L_ADR is provided. In the present embodiment, the first line selection circuit 132 a is provided in the first data determination unit 132. The first line selection circuit 132a may be provided inside the first memory access controller 31 and independently from the first data determination unit 132. The first line selection circuit 132a may be provided outside the first memory access controller 31.

  The first line selection circuit 132a includes a plurality of input terminals (not shown). The plurality of input terminals are provided in the same number as the read memory side first data bus lines 23r-1, 23r-2,..., 23r-n. The plurality of input terminals are connected to the read memory side first data bus lines 23r-1, 23r-2,..., 23r-n so as to satisfy a one-to-one relationship.

  The first address bus line 21 is connected to the first line selection circuit 132a. A first address signal L_ADR is input to the first line selection circuit 132a through the first address bus line 21. The first line selection circuit 132a has an input connected to the read memory side first data bus line 23r-k to which the first read data L_DT2-k is transmitted in accordance with the value of the input first address signal L_ADR. Connect the terminal to the output terminal. The first line selection circuit 132a is provided with one output terminal (not shown) for outputting the first selection data L_DT2s. The first line selection circuit 132a outputs the first read data L_DT2-k from the output terminal as the first selection data L_DT2s.

  The first data determination unit 132 includes a plurality of first holding circuits 132b-1, 132b-2,..., 132b-i that hold the first selection data L_DT2s. Each input terminal IN of the plurality of first holding circuits 132b-1, 132b-2, ..., 132b-i is connected to the output terminal of the first line selection circuit 132a. The first selection data L_DT2s output from the output terminal of the first line selection circuit 132a is input to the input terminals IN of the plurality of first holding circuits 132b-1, 132b-2, ..., 132b-i. The

  The plurality of first holding circuits 132b-1, 132b-2,..., 132b-i are provided with holding signal input terminals LT. The first data holding signals RDL1, RDL2,..., RDLi are input to the holding signal input terminal LT. The first data holding signal RDL1 is input to the holding signal input terminal LT of the first holding circuit 132b-1, and the first data holding signal RDL2 is input to the holding signal input terminal LT of the first holding circuit 132b-2. The first data holding signal RDLi is input to the holding signal input terminal LT of the first holding circuit 132b-i. The first access signal generator 131 generates the first data holding signals RDL1, RDL2,..., RDLi corresponding to the number of first holding circuits provided in the first data determining unit 132, and the generated first data The holding signals RDL1, RDL2, ..., RDLi are sequentially output to the first holding circuits 132b-1, 132b-2, ..., 132b-i in synchronization with the clock signal CLK.

  The first holding circuit 132b-1 receives the first selection data inputted to the input terminal IN in synchronization with the first data holding signal RDL1 inputted to the holding signal input terminal LT switching from the asserted state to the negated state. L_DT2s is held as the first holding data L_DT2-1. Further, the first holding circuit 132b-1 outputs the held first holding data L_DT2-1 from the output terminal Q. The first holding circuit 132b-2 receives the first selection data input to the input terminal IN in synchronization with the first data holding signal RDL2 input to the holding signal input terminal LT switching from the asserted state to the negated state. L_DT2s is held as the first holding data L_DT2-2. Further, the first holding circuit 132b-2 outputs the held first holding data L_DT2-2 from the output terminal Q. The first holding circuit 132b-i synchronizes with the first data holding signal RDLi input to the holding signal input terminal LT switching from the asserted state to the negated state, and the first selection data input to the input terminal IN. L_DT2s is held as the first holding data L_DT2-i. Further, the first holding circuit 132b-i outputs the held first holding data L_DT2-i from the output terminal Q. The first data holding signals RDL1, RDL2,..., RDLi are switched from the asserted state to the negated state in synchronization with the clock signal transmitted from the clock signal transmitter 14. Therefore, the first data determination unit 132 holds the first selection data L_DT2s in the plurality of first holding circuits 132b-1, 132b-2,..., 132b-i in synchronization with the clock signal.

  The first data determination unit 132 determines the plurality of first holding data L_DT2h-1, L_DT2h-2,..., L_DT2h-i based on the difference between the plurality of first holding data L_DT2h-1, L_DT2h-2, .., L_DT2h-i includes a first determination circuit (an example of a first determination unit) 132c that determines which one of the first read data L_DT2 (that is, regular data) is to be used.

  The first determination circuit 132c is provided with the same number of data input terminals (not shown) as the first holding circuit and one holding signal input terminal (not shown). The data input terminals are connected so as to satisfy a one-to-one relationship with the output terminals Q of the plurality of first holding circuits 132b-1, 132b-2,..., 132b-n. Thereby, the first determination circuit 132c includes the first holding data L_DT2h-1, L_DT2h-2,..., 132b-n held in the first holding circuits 132b-1, 132b-2,. .., L_DT2h-i is input to different input terminals. In addition, the holding signal input terminal of the first determination circuit 132c has the last first data holding generated by the first access signal generating unit 131 among the plurality of first data holding signals RDL1, RDL2,. A signal, i.e., the first data holding signal RDLi having the maximum value of i is input.

  The first determination circuit 132c stores a determination table (details will be described later) in which a difference between a plurality of pieces of held data is associated with held data that should be regular data. The first determination circuit 132c receives the first held data L_DT2h-1, L_DT2h-2,... That are input based on the first data holding signal RDLi input to the holding signal input terminal being switched from the asserted state to the negated state. .., L_DT2h-i is determined with reference to the determination table, the first holding data to be regular data (that is, the first read data L_DT2). The first determination circuit 132c outputs a selection control signal OS including information on the determination result of the first held data to be the first read data L_DT2.

  The first data determination unit 132 receives the hold data determined as normal data (that is, the first read data L_DT2) based on the selection control signal OS input from the first determination circuit 132c. , L_DT2h-i is provided with a first held data selection circuit 132d that selects one of the held data L_DT2h-1, L_DT2h-2,.

  The first holding data selection circuit 132d has the same number of data input terminals (not shown) as the first holding circuit, a selection signal input terminal (not shown) to which the selection control signal OS is inputted, and the selected first holding data. One data output terminal (not shown) from which data is output is provided. The data input terminals are connected so as to satisfy a one-to-one relationship with the output terminals Q of the plurality of first holding circuits 132b-1, 132b-2,..., 132b-n. As a result, the first holding data selection circuit 132d has the first holding data L_DT2h-1, L_DT2h-2 held in each of the first holding circuits 132b-1, 132b-2, ..., 132b-n, ..., L_DT2h-i is input to different input terminals. The first holding data selection circuit 132d connects one data input terminal and a data output terminal among the plurality of data input terminals according to the value of the selection control signal OS input to the selection signal input terminal. Thereby, the first held data selection circuit 132d outputs the selected held data as the first read data L_DT2 from the data output terminal.

  The first data determining unit 132 can output the first read data L_DT2 input from the first held data selection circuit 132d to the first CPU 11, and the first read data L_DT2 input from the first held data selection circuit 132d. A first output buffer circuit 132e that reversibly switches to a high-impedance state that cannot be output.

  The first output buffer circuit 132e includes a data input terminal IN connected to the data output terminal of the first held data selection circuit 132d, and a data output terminal OUT connected to the CPU side first data bus line 22. . The first output buffer circuit 132e includes a control signal input terminal OE that is connected to the first access signal generator 131 and receives the first data read control signal ROE. The first output buffer circuit 132e receives the first read data L_DT2 input from the first held data selection circuit 132d when the first data read control signal ROE input to the control signal input terminal OE is in the asserted state. Is ready to output. On the other hand, when the first data read control signal ROE input to the control signal input terminal OE is in the negated state, the first output buffer circuit 132e sets the data output terminal OUT to the high impedance state and the first read data L_DT2 to the first output data L_DT2. 1 CPU 11 will be unable to output.

  The first CPU 11 synchronizes with the switching from the asserted state to the negated state of the first data read instruction signal L_RD1, and the first CPU 11 receives the first data input from the data output terminal OUT of the first output buffer circuit 132e to the first data bus line 22 on the CPU side. One read data L_DT2 is read.

  The CPU-side first data bus line 22 is directly connected to the write memory-side first data bus line 23 w via the first memory access controller 31. The CPU-side first data bus line 22 is also connected to the data output terminal OUT of the first output buffer circuit 132e. The first access signal generator 131 receives the first address signal L_ADR and asserts the first data read control signal ROE when the first data read instruction signal L_RD1 is asserted. The first CPU 11 does not assert the first data write instruction signal L_WR1 and the first data read instruction signal L_RD1 at the same time. In addition, the first access signal generator 131 generates the first data holding signals RDL1, RDL2,..., RDLi within the assertion period of the first data read instruction signal L_RD.

  Thus, when the first write data L_DT1 input to the CPU side first data bus line 22 is written to the dual port memory 33, the first data read control signal ROE and the first data holding signals RDL1, RDL2,. .. RDLi is negated. For this reason, the data output terminal OUT of the first output buffer circuit 132e is in a high impedance state. Thus, the first write data L_DT1 and the first read data L_DT2 input to the data input terminal of the first output buffer circuit 132e are not input to the CPU-side first data bus line 22 at the same time. . As a result, the first write data L_DT1 output from the first CPU 11 is written into a desired memory cell of the storage unit 333 provided in the desired dual port memory 33 according to the value of the first address signal L_ADR.

  On the other hand, when the first output buffer circuit 132e is in a state capable of outputting the first read data L_DT2, the first data write instruction signal L_WR1 is in a negated state, so the first data write signal L_WR2 is also negated. . Thus, the first read data L_DT2 output from the data output terminal OUT of the first output buffer circuit 132e is input to the memory-side first data bus line 23w but is stored in the storage unit 333 via the first input / output port 331. Will not be written to.

[Configuration of second memory access controller]
The second memory access controller 32 has the same internal configuration as the first memory access controller 31 and exhibits the same function. That is, the second memory access controller 32 has the same configuration as the first access signal generator 131 and the second access signal generator that has the same function as the first access signal generator 131 and the first data determination unit 132. And a second data determining unit that exhibits the same function.

[Operation of multiprocessor system]
Next, the operation of the multiprocessor system 1 according to the present embodiment will be described with reference to FIGS. 3 to 8 with reference to FIGS.

(Write operation)
First, the data write operation of the first memory access controller 31 in the multiprocessor system 1 will be described. FIG. 3 illustrates the operation of the multiprocessor system 1 when the first address signal L_ADR and the second address signal R_ADR having the same value are input to the dual port memory 33 at the same time.

  In the timing chart of the data write operation shown in FIG. 3, “L_ADR” shown in FIG. 3 indicates the first address signal L_ADR, and “L_DT1 (22)” is the first data input to the CPU-side first data bus line 22. Write data L_DT1, “L_WR1” indicates the first data write instruction signal L_WR1, and “L_DT1 (23w)” indicates the first write data L_DT1 input to the write memory side first data bus line 23w. "CLK" indicates the clock signal CLK output from the clock signal transmitter 14, "L_WR2" indicates the first data write signal L_WR2, "R_ADR" indicates the second address signal R_ADR, and "R_DT2" “−k” indicates the second read data read from the dual port memory 33 to be read. In FIG. 3, the passage of time is shown from left to right.

  The dual port memory 13 is mapped in the memory space of the first CPU 11 and the second CPU 12. When the first CPU 11 writes the first write data L_DT1 to the dual port memory 33, the first CPU 11 receives the first address signal L_ADR including the address of the memory cell to be written in the storage unit 333 as a plurality of the dual port memory 33 and the first memory. Output to the access controller 31. In FIG. 3, the first address signal L_ADR having the value “0x020000FE” is output to the dual port memory 33 and the first memory access controller 31 at time t1. The value “0x020000FE” is expressed in the language specification in C language. The notation method of each data value shown in FIG. 4 and FIG. 7 described later is similarly expressed by a language specification in C language. Therefore, the value “0x020000FE” corresponds to the decimal number “335554686”.

  As shown in FIG. 3, at the time t1 when the output of the first address signal L_ADR to the first address bus line 21 is started, the first write data L_DT1 to be written to the dual port memory 33 is transferred from the first CPU 11 to the CPU. Output to the first data bus line 22. FIG. 3 shows a state in which the first write data L_DT1 having the value “0x1234” is output to the first data bus line 22 on the CPU side, for example.

  The write memory side first data bus line 23 w is directly connected to the CPU side first data bus line 22. Therefore, at time t1, the first write data L_DT1 having the same value “0x1234” as that inputted to the CPU side first data bus line 22 is inputted to the write memory side first data bus line 23w. Is done. The timing at which the first write data L_DT1 is input to the write memory side first data bus line 23w is substantially the same as the timing at which the first write data L_DT1 is output from the first CPU to the CPU side first data bus line 22. It is.

  Further, the second address signal R_ADR having the same value as the first address signal L_ADR is output to the second address bus line 41 at time t1. As a result, the dual port memory 33 is chip-selected and can read data.

  As shown in FIG. 3, after the first address signal L_ADR having the value “0x020000FE” and the first write data L_DT1 having the value “0x1234” are output, the switching of the signal level from the high level to the low level is started. The first data write instruction signal L_WR1 that becomes low level at time t2 is output from the first CPU 11 to the first memory access controller 31. First data write instruction signal L_WR1 is negated when the signal level is high, and asserted when the signal level is low. Therefore, first data write instruction signal L_WR1 is asserted at time t2.

  At time t3 after the first data write instruction signal L_WR1 is switched to the asserted state, the clock signal CLK rises. A first data write signal L_WR2 whose signal level is switched from a high level to a low level in synchronization with the rising edge of the clock signal CLK is output from the first access signal generator 131 to the plurality of dual port memories 33. The first data write signal L_WR2 is negated when the signal level is high, and asserted when the signal level is low. As shown in FIG. 3, the first data write signal L_WR2 is changed from the negated state to the asserted state in synchronization with the first rising edge of the clock signal CLK after the first data write instruction signal L_WR1 is asserted. Can be switched. The first data write signal L_WR2 is asserted immediately after time t3.

  As shown in FIG. 3, at time t4 after time t3, the clock signal CLK rises again. In synchronization with this rising edge of the clock signal at time t4, the first data write signal L_WR2 output from the first access signal generator 131 to the dual port memory 33 is switched from the asserted state to the negated state. As a result, the first data write signal L_WR2 is a pulse signal whose signal level is low for a period of one cycle of the clock signal CLK from time t3 to time t4. In FIG. 3, the first data write signal L_WR2 is a pulse signal that becomes low for one cycle of the clock signal CLK, but may be a pulse signal that becomes low for a plurality of cycles of the clock signal CLK. The first data write signal L_WR2 may be a signal synchronized with the falling edge of the clock signal CLK.

  Although illustration is omitted, when the first data write signal L_WR2 is switched from the asserted state to the negated state, the value of the first write data L_DT1 output to the write memory side first data bus line 23w (FIG. 3, “0x1234”) is stored in the memory cell of the storage unit 333 provided in the dual port memory 33 specified by the first address signal L_ADR. For example, the upper several bits of the first address signal L_ADR correspond to the numbers of the plurality of dual port memories 33, and the lower remaining bits correspond to the addresses of the memory cells in the storage unit 333. As a result, the multiprocessor system 1 can write the first data write signal L_WR2 to the designated memory cell of the storage unit 333 of the dual port memory 33 designated by the first CPU 11. At the same time, the multiprocessor system 1 can prevent the first data write signal L_WR2 from being written into the dual port memory 33 not designated by the first CPU 11.

  Further, since the dual port memory 33 is chip-selected, the first data write signal L_WR2 of the value “0x1234” written to the dual port memory 33-k at time t4 is used as the second read data R_DT2-k. The data is output to the read memory side second data bus line 43r-k. Further, the data stored in the storage unit 333 is also output from the remaining dual port memory 33 to the read memory side second data bus line 43r. In the multiprocessor system 1, the difference between the timing at which the first data write signal L_WR2 is written to the dual port memory 33 and the timing at which the second read data R_DT2-k is read is 0 clocks of the clock signal CLK. . However, the multiprocessor system 1 requires several clocks of the clock signal CLK until the second read data R_DT2-k is read after the first data write signal L_WR2 is written in the dual port memory 33. It may be designed to.

  As shown in FIG. 3, thereafter, the first data write instruction signal L_WR1 starts to be switched from the asserted state to the negated state, and enters the negated state at time t5. Thus, the first data write instruction signal L_WR1 is a pulse signal whose signal level becomes low between time t2 and time t5.

Even if the first data write instruction signal L_WR1 is negated, the CPU-side first data bus line 22 and the write memory-side first data bus line 23w remain directly connected. The first write data L_DT1 of the value “0x1234” input to the data bus line 22 continues to be input to the write memory side first data bus line 23w.
Thus, the data write operation of one first write data in the first memory access controller 31 in the multiprocessor system 1 is completed.

  The data write operation of the second memory access controller 32 is the same as that of the operation of the first memory access controller 31 replaced with “second”, and thus description thereof is omitted.

(Data read operation)
Next, the data read operation of the first memory access controller 31 in the multiprocessor system 1 will be described with reference to FIGS. 4 and 6 with reference to FIGS. FIG. 4 shows a case in which the period of time when the first selection data L_DT2s is indefinite (details will be described later) is shorter than one cycle of the clock signal CLK. A timing chart of a data read operation when 1, 132b-2, 132b-3 (i = 3) is provided is shown.

  In the timing chart of the data read operation illustrated in FIG. 4, “CLK” illustrated in FIG. 4 represents the clock signal CLK output from the clock signal transmitter 14, “R_WR2” represents the second data write signal R_WR2, “L_DT2-k” indicates first read data read from the dual-port memory 33-k to be read (an example of read data read from one dual-port memory), and “L_DT2s” indicates the first selection data L_DT2s. Is shown. In FIG. 4, “L_RD1” indicates the first data read instruction signal L_RD1, “RDL1” indicates the first data holding signal RDL1, and “REG1” is the first holding circuit 132b-1. 1 holding data L_DT2h-1, "RDL2" indicates the first data holding signal RDL2, "REG2" indicates the first holding data L_DT2h-2 held in the first holding circuit 132b-2, and "RDL3" Indicates the first data holding signal RDL3, “REG3” indicates the first holding data L_DT2h-3 held in the first holding circuit 132b-3, and “L_DT2 (22)” is sent from the first memory access controller 31 to the CPU. The first read data L_DT2 output to the first data bus line 22 is shown. In FIG. 4, the passage of time is shown from left to right.

  The dual port memory 33 is mapped in the memory space of the first CPU 11 and the second CPU 12. When the first CPU 11 reads the first read data L_DT2 from any of the plurality of dual port memories 33, the first address signal including information on the memory cells of the dual port memory 33 to be read and the storage unit 333 to be read L_ADR is output to the plurality of dual port memories 33 and the first memory access controller 31.

  Further, the dual port memory 33 is chip-selected while the first address signal L_ADR is input. Of the dual-port memory 33, the dual-port memory 33-k (k is 1 to n) to be read, which is chip-selected according to the value of the input first address signal L_ADR (for example, the value of the upper few bits) Is a natural number between them, data is read from the memory cell of the storage unit 333 designated according to the value of the input first address signal L_ADR (for example, the value of the lower few bits). Further, the dual port memory 33-k outputs the read data read from the memory cell to the read memory side first data bus line 23r-k via the first input / output port 331-k. In FIG. 4, the dual port memory 33-k is chip-selected before time t1. Therefore, the first read data L_DT2-k having the value “0x1234” is output to the read memory side first data bus line 23r-k connected to the dual port memory 33-k.

As shown in FIG. 4, the second data write signal R_WR2 is asserted immediately after time t1 in synchronization with the rise of the clock signal CLK.
The first data read instruction signal L_RD1 is negated when the signal level is high and asserted when the signal level is low. An example will be described in which the first data read instruction signal L_RD1 output from the first CPU 11 to the first memory access controller 31 is asserted between time t1 and time t2 when the clock signal CLK rises.

  Second data write output from the second access signal generator to the dual port memory 33 in synchronization with the rising edge of the clock signal CLK at time t2 after the first data read instruction signal L_RD1 is asserted. The signal R_WR2 is switched from the asserted state to the negated state. When the second data write signal R_WR2 is switched from the asserted state to the negated state, the value of the second write data R_DT1 output to the write memory side second data bus line 43w (“0x5678” in FIG. 3). ) Is stored in the designated memory cell of the storage unit 333 of the dual port memory 33-k designated by the second address signal R_ADR.

  Further, since the dual port memory 33-k is chip-selected, the first read data L_DT2-k is read from the memory unit first data bus line 23r- from the storage unit 333 of the dual port memory 33-k at time t2. output to k. As shown in FIG. 4, the value “0x5678” written in the dual port memory 33-k is applied to the read memory side first data bus line 23r-k connected to the dual port memory 33-k to be written. First read data L_DT2-k is output.

  The first line selection circuit 132a has an input terminal connected to the read memory side second data bus line 23r-k to which the first read data L_DT2-k is transmitted according to the value of the first address signal L_ADR, and an output The first read data L_DT2-k is output from the output terminal as the first selection data L_DT2s.

  Here, the delay of the first selection data L_DT2s output from the output terminal of the first read data selection circuit 132a will be described with reference to FIG. Times t2, t3, and t5 in FIGS. 4 and 5 correspond to each other. As shown in FIG. 5, the first read data L_DT2-k is multi-bit data (4 bits in FIG. 5). As shown in the upper part of FIG. 5, at time t2, the first read data L_DT2-k read from the dual port memory 33-k to the read memory side first data bus line 23r-k is before time t2. The output value (hereinafter referred to as “previous value”) is switched to a value (hereinafter referred to as “current value”) stored in the dual port memory 33-k at time t2. The data of each bit of the first read data L_DT2-k is switched from the previous value to the current value at the same timing at time t2. The first line selection circuit 132a includes gate circuits configured in a plurality of stages in order to individually connect the output terminal and the plurality of input terminals. Therefore, as shown in the lower part of FIG. 5, the timing at which the first read data L_DT2-k input to the input terminal of the first read data selection circuit 132a switches from the previous value to the current value depends on the number of stages of this gate circuit. Accordingly, time t3 is delayed with respect to time t2 by a period Tds. Further, due to variations in characteristics of the transistors constituting the dual port memory 33 and the first line selection circuit 132a, the first selection data L_DT2s is output after the first read data L_DT2-k is input to the first line selection circuit 132a. Output delay differs for each bit data. Furthermore, since the length of the wiring of the first data bus line 23r-k for the read memory is different for each bit of the first read data L_DT2-k, the wiring delay is different for each bit data. Therefore, as shown in the lower part of FIG. 5, due to this output delay and wiring delay, a delay variation period Tdb occurs for each bit data of the first read data L_DT2-k. As a result, it takes a total delay time period Tds and delay variation period Tdb before the first selection data L_DT2s of the current value is output from the first line selection circuit 132a. In particular, the first selection data L_DT2s in the delay variation period Tdb is an indefinite value that is neither the previous value nor the current value. If this indeterminate value is read and transmitted to the first CPU 11, industrial equipment to which the multiprocessor system 1 is applied may be unexpectedly controlled and malfunction.

  Therefore, as shown in FIG. 4, the first selection data L_DT2s output from the first line selection circuit 132a becomes an indefinite value during the period from time t3 to time t5.

  At time t2 after the first data read instruction signal L_RD1 is switched to the asserted state, the clock signal CLK rises. A first data holding signal RDL1 whose signal level is switched from a high level to a low level in synchronization with the rising edge of the clock signal CLK is output from the first access signal generator 131 to the first holding circuit 132b-1. The first data holding signal RDL1, the first data holding signals RDL2 and RDL3 (to be described later), and the first data holding signal RDL4 (see FIG. 7) are negated when the signal level is high, and when the signal level is low. Asserted. As shown in FIG. 4, the first data holding signal RDL1 is switched from the negated state to the asserted state in synchronization with the first rising edge of the clock signal CLK after the first data read instruction signal L_RD1 is in the asserted state. . The first data holding signal RDL1 is asserted immediately after time t2.

  At time t3 after time t2, the first selection data L_DT2s output from the first line selection circuit 132a becomes an indefinite value from the previous value.

  At time t4 after time t3, the clock signal CLK rises again. In synchronization with this rising edge of the clock signal at time t4, the first data holding signal RDL1 is switched from the asserted state to the negated state. As a result, the first data holding signal RDL1 becomes a pulse signal whose signal level is low for only one period of the clock signal CLK from time t2 to time t4. When the first data holding signal RDL1 is switched from the asserted state to the negated state, the first holding circuit 132b-1 holds the first selection data L_DT2h-1 as the first holding data L_DT2h-1, and also the first selection data L_DT2s. Output from the output terminal Q. As shown in FIG. 4, since the first selection data L_DT2s at time t4 is an indefinite value, the indeterminate value is held in the first holding circuit 132b-1.

  A first data holding signal RDL2 whose signal level is switched from a high level to a low level in synchronization with the rising edge of the clock signal CLK at time t4 is output from the first access signal generator 131 to the first holding circuit 132b-2. The first data holding signal RDL2 is switched from the negated state to the asserted state in synchronization with the second rising edge of the clock signal CLK after the first data read instruction signal L_RD1 is asserted. The first data holding signal RDL2 is asserted immediately after time t4.

  At time t5 after time t4, all the bit data of the first selection data L_DT2s output from the first line selection circuit 132a has the current value. Thereby, after time t5, the first selection data L_DT2s having the value “0x5678” is output from the output terminal of the first line selection circuit 132a.

  At time t6 after time t5, the clock signal CLK rises again. In synchronization with this rising edge of the clock signal at time t6, the first data holding signal RDL2 is switched from the asserted state to the negated state. As a result, the first data holding signal RDL2 becomes a pulse signal whose signal level is low for only one period of the clock signal CLK from time t4 to time t6. When the first data holding signal RDL2 is switched from the asserted state to the negated state, the first holding circuit 132b-2 holds the first selection data L_DT2s as the first holding data L_DT2h-2 and the first holding data L_DT2h− 2 is output from the output terminal Q. As shown in FIG. 4, since the first selection data L_DT2s at time t6 is the current value “0x5678”, the value “0x5678” is held in the first holding circuit 132b-2.

  A first data holding signal RDL3 whose signal level switches from a high level to a low level in synchronization with the rising edge of the clock signal CLK at time t6 is output from the first access signal generator 131 to the first holding circuit 132b-3. The first data holding signal RDL3 is switched from the negated state to the asserted state in synchronization with the third rising edge of the clock signal CLK after the first data read instruction signal L_RD1 is asserted. The first data holding signal RDL3 is asserted immediately after time t6.

  At time t7 after time t6, the clock signal CLK rises again. In synchronization with this rising edge of the clock signal at time t7, the first data holding signal RDL3 is switched from the asserted state to the negated state. As a result, the first data holding signal RDL3 becomes a pulse signal whose signal level is low only for one period of the clock signal CLK from time t6 to time t7. When the first data holding signal RDL3 is switched from the asserted state to the negated state, the first holding circuit 132b-3 holds the first selection data L_DT2s as the first holding data L_DT2h-3 and the first holding data L_DT2h− 3 is output from the output terminal Q. As shown in FIG. 4, since the first selection data L_DT2s at time t7 is the current value “0x5678”, the value “0x5678” is held in the first holding circuit 132b-3.

  As described above, the first data determination unit 132 sequentially holds the first holding data L_DT2-1, L-DT2-2, and L_DT2-3 at different timings by one clock of the clock signal CLK.

  At time t7, when the last first data holding signal RDL3 generated by the first access signal generating unit 131 is switched from the asserted state to the negated state, the first determination circuit 132c receives the first held data L_DT2h-1 that is input. , L_DT2h-2, L_DT2h-3, the first held data to be the first read data L_DT2 is determined with reference to the determination table.

  Here, the determination table provided in the first determination circuit 132c will be described with reference to FIG. As illustrated in FIG. 6, in the determination table stored in the first determination circuit 132 c, the difference between the plurality of pieces of held data is associated with the held data that should be regular data. The “[REG1 = REG2]?” And “[REG2 = REG3]?” Columns of the determination table are columns indicating the difference between a plurality of retained data, and the “L_DT2” column should be regular data. It is a column indicating retained data. “[REG1 = REG2]?” Indicates that the first holding data L_DT2h-1 held in the first holding circuit 132b-1 and the first holding data L_DT2h-2 held in the first holding circuit 132b-2 are equal. Indicates whether or not you are doing. That is, “[REG1 = REG2]?” Indicates a change between the first holding data L_DT2h-1 and the first holding data L_DT2h-2. “[REG2 = REG3]?” Indicates that the first holding data L_DT2h-2 held in the first holding circuit 132b-2 and the first holding data L_DT2h-3 held in the first holding circuit 132b-3 are obtained. Indicates whether or not they match. That is, “[REG2 = REG3]?” Indicates a change between the first holding data L_DT2h-2 and the first holding data L_DT2h-3. “L_DT2” indicates regular data, that is, retained data to be the first read data L_DT2 in accordance with the difference between the plurality of retained data.

As shown in FIG. 6, when the first holding data L_DT2h-1 and the first holding data L_DT2h-2 match, and the first holding data L_DT2h-2 and the first holding data L_DT2h-3 match The hold data to be the first read data L_DT2 is determined as the first hold data L_DT2h-3.
When the first holding data L_DT2h-1 and the first holding data L_DT2h-2 match and the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are different, the first read data L_DT2 and The hold data to be determined is determined as the first hold data L_DT2h-2.
When the first holding data L_DT2h-1 and the first holding data L_DT2h-2 are different and the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are different, the first reading data L_DT2 and The hold data to be determined is determined as the first hold data L_DT2h-3.
When the first holding data L_DT2h-1 and the first holding data L_DT2h-2 are different and the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are the same, the first reading data L_DT2 The hold data to be determined is determined as the first hold data L_DT2h-3.

  Returning to FIG. 4, the value of the first holding data L_DT2h-1 held in the first holding circuit 132b-1 is an indefinite value, and the first holding data L_DT2h-2 held in the first holding circuit 132b-2. The value of “0x5678” is “0x5678”, and the value of the first holding data L_DT2h-3 held in the first holding circuit 132b-3 is “0x5678”. That is, the first holding data L_DT2h-1 and the first holding circuit 132b-2 are different, and the second holding data L_DT2h-2 and the first holding circuit 132b-3 are the same. For this reason, the first determination circuit 132c performs the determination operation at time t7, and therefore refers to the determination table to determine the retained data to be the first read data L_DT2 as the first retained data L_DT2h-3. The first determination circuit 132c outputs a selection control signal OS for selecting the first holding data L_DT2h-3 to the first holding data selection circuit 132d.

  The first holding data selection circuit 132d selects the first holding data L_DT2h-3 from the first holding data L_DT2h-1, L_DT2h-2, and L_DT2h-3 that are input based on the selection control signal OS. 1 is output to the output buffer circuit 132e. Although illustration is omitted, at time t7, the first address signal L_ADR is input and the first data read control signal ROE is in an asserted state. Therefore, as shown in FIG. 4, the first read data L_DT2 having the same value “0x5678” as the first hold data L_DT2h-3 is output to the first data bus line 22 on the CPU side.

At time t8 after time t7, the first data read instruction signal L_RD1 is switched from the asserted state to the negated state. The first CPU 11 reads the first read data L_DT2 input to the CPU-side first data bus line 22 in synchronization with the switching of the first data read instruction signal L_RD1 from the asserted state to the negated state.
Thus, the data read operation of one data in the first memory access controller 31 in the multiprocessor system 1 is completed.

  The data read operation of the second memory access controller 32 is the same as that of the operation of the first memory access controller 31 replaced with “second”, and thus the description thereof is omitted.

(Other examples of data read operation)
Next, another example of the data read operation of the first memory access controller 31 in the multiprocessor system 1 will be described with reference to FIGS. 1 and 2 and FIGS. FIG. 7 shows a case where the period of the indefinite value of the first selection data L_DT2s is longer than one cycle of the clock signal CLK and shorter than two cycles, and the first data determination unit 132 includes four first holding circuits 132b- The timing chart of the data read operation in the case of having 1, 132b-2, 132b-3, 132b-4 (i = 4) is shown.

  In the timing chart of the data read operation shown in FIG. 7, “CLK”, “L_DT2-k”, “L_DT2s”, “L_RD1”, “RDL1”, “REG1”, “RDL2”, “REG2” shown in FIG. , “RDL3”, “REG3”, and “L_DT2 (22)” are “CLK”, “L_DT2-k”, “L_DT2s”, “L_RD1”, “RDL1”, “REG1”, “RDL2” shown in FIG. , “REG2”, “RDL3”, “REG3”, and “L_DT2 (22)”. “RDL4” shown in FIG. 7 indicates the first data holding signal RDL4, and “REG4” indicates the first holding data L_DT2h-4 held in the first holding circuit 132b-4. In FIG. 7, the passage of time is shown from left to right.

  In the operation from time t1 to time 7 shown in FIG. 7, the period of the indefinite value of the first selection data L_DT2s is from time t3 to time t6 (a period longer than one period of the clock signal CLK and shorter than two periods). Except for certain points and the point that the value of the first holding data L_DT2h-2 held in the first holding circuit 132b-2 is an indefinite value, the operation is similar to the operation from time t1 to time t7 shown in FIG. Therefore, explanation is omitted.

  A first data holding signal RDL4 whose signal level switches from a high level to a low level in synchronization with the rising edge of the clock signal CLK at time t7 is output from the first access signal generator 131 to the first holding circuit 132b-4. The first data holding signal RDL4 is switched from the negated state to the asserted state in synchronization with the fourth rising edge of the clock signal CLK after the first data read instruction signal L_RD1 is asserted. The first data holding signal RDL4 is asserted immediately after time t7.

  At time t8 after time t7, the clock signal CLK rises again. In synchronization with this rising edge of the clock signal at time t8, the first data holding signal RDL4 is switched from the asserted state to the negated state. As a result, the first data holding signal RDL4 becomes a pulse signal whose signal level is low for a period of one cycle of the clock signal CLK from time t7 to time t8. When the first data holding signal RDL4 is switched from the asserted state to the negated state, the first holding circuit 132b-4 holds the first selection data L_DT2s as the first holding data L_DT2h-4 and the first holding data L_DT2h−. 4 is output from the output terminal Q. As illustrated in FIG. 7, the first selection data L_DT2s at time t8 is the current value “0x5678”, and thus the value “0x5678” is retained in the first retention circuit 132b-4.

  As described above, the first data determination unit 132 shifts the timing by one clock of the clock signal CLK in synchronization with the clock signal CLK and shifts the first holding data L_DT2-1, L-DT2-2, L_DT2-3, L_DT2. -4 in order.

  When the first data holding signal RDL4 is switched from the asserted state to the negated state at time t8, the first determination circuit 132c receives the first held data L_DT2h-1, L_DT2h-2, L_DT2h-3, and L_DT2h-4. The first held data to be the normal data, that is, the first read data L_DT2 is determined with reference to the determination table.

  Here, the determination table stored in the first determination circuit 132c will be described with reference to FIG. As shown in FIG. 8, in the determination table stored in the first determination circuit 132c, the difference between the plurality of pieces of held data is associated with the held data that should be regular data. The “[REG1 = REG2]?”, “[REG2 = REG3]?”, And “[REG3 = REG4]?” Columns of the determination table are columns indicating the difference between a plurality of retained data, and are “L_DT2”. The column is a column indicating retained data to be the first data. “[REG1 = REG2]?”, “[REG2 = REG3]?” And “L_DT2” in the determination table shown in FIG. 8 are “[REG1 = REG2]?”, “[REG2 = REG3]? ”And“ L_DT2 ”, the description is omitted. “[REG3 = REG4]?” Indicates that the first holding data L_DT2h-3 held in the first holding circuit 132b-3 and the first holding data L_DT2h-4 held in the first holding circuit 132b-4 are equal. Indicates whether or not you are doing. That is, “[REG3 = REG4]?” Indicates a change between the first holding data L_DT2h-3 and the first holding data L_DT2h-4.

As shown in FIG. 8, the first holding data L_DT2h-1 and the first holding data L_DT2h-2 match, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 match, and the first holding data When L_DT2h-3 and the first hold data L_DT2h-4 match, the hold data to be the first read data L_DT2 is determined as the first hold data L_DT2h-4.
The first holding data L_DT2h-1 and the first holding data L_DT2h-2 match, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 match, and the first holding data L_DT2h-3 and the first holding data When the data L_DT2h-4 is different, the held data to be the first read data L_DT2 is determined as the first held data L_DT2h-3.
The first holding data L_DT2h-1 and the first holding data L_DT2h-2 match, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are different, and the first holding data L_DT2h-3 and the first holding data When the data L_DT2h-4 is different, the retained data to be the first read data L_DT2 is determined as the first retained data L_DT2h-2.
The first holding data L_DT2h-1 and the first holding data L_DT2h-2 are different, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are different, and the first holding data L_DT2h-3 and the first holding data When the data L_DT2h-4 is different, the held data to be the first read data L_DT2 is determined as the first held data L_DT2h-4.
The first holding data L_DT2h-1 and the first holding data L_DT2h-2 are different, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 are different, and the first holding data L_DT2h-3 and the first holding data When the data L_DT2h-4 matches, the held data to be the first read data L_DT2 is determined as the first held data L_DT2h-4.
The first holding data L_DT2h-1 and the first holding data L_DT2h-2 are different, the first holding data L_DT2h-2 and the first holding data L_DT2h-3 match, and the first holding data L_DT2h-3 and the first holding data When the data L_DT2h-4 matches, the held data to be the first read data L_DT2 is determined as the first held data L_DT2h-4.

  Returning to FIG. 7, the value of the first holding data L_DT2h-1 held in the first holding circuit 132b-1 is an indefinite value, and the first holding data L_DT2h-2 held in the first holding circuit 132b-2. Is an indefinite value, the value of the first holding data L_DT2h-3 held in the first holding circuit 132b-3 is “0x5678”, and the first holding data held in the first holding circuit 132b-4 The value of L_DT2h-4 is “0x5678”. That is, the value of the first holding data L_DT2h-1 is different from the value of the first holding data L_DT2h-2, the value of the second holding data L_DT2h-2 is different from the value of the third holding data L_DT2h-3, The value of the first holding data L_DT2h-3 matches the value of the first holding data L_DT2h-4. For this reason, the first determination circuit 132c refers to the determination table and determines the retained data to be the first read data L_DT2 as the first retained data L_DT2h-4. The first determination circuit 132c outputs a selection control signal OS for selecting the first holding data L_DT2h-4 to the first holding data selection circuit 132d.

  Based on the selection control signal OS, the first holding data selection circuit 132d receives the first holding data L_DT2h-4 from the first holding data L_DT2h-1, L_DT2h-2, L_DT2h-3, and L_DT2h-4 that are input. Select and output to the first output buffer circuit 132e. Although illustration is omitted, at time t8, the first data read control signal ROE is in an asserted state. Therefore, as shown in FIG. 7, the first read data L_DT2 having the same value “0x5678” as the first held data L_DT2h-4 is output to the CPU-side first data bus line 22.

At time t9 after time t8, the first data read instruction signal L_RD1 is switched from the asserted state to the negated state. The first CPU 11 reads the first read data L_DT2 input to the CPU-side first data bus line 22 in synchronization with the switching of the first data read instruction signal L_RD1 from the asserted state to the negated state.
Thus, the data read operation of one data in the first memory access controller 31 in the multiprocessor system 1 is completed.

  As described above, the multiprocessor system 1 according to the present embodiment includes the plurality of dual port memories 33, the first CPU 11, the clock signal transmitter 14, the first memory access controller 31, and the first memory access controller 31. The first read data L_DT2-k read from the dual port memory 33-k among the plurality of dual port memories 33 is sequentially synchronized with the clock signal CLK, and the first holding data L_DT2h-1, L_DT2h-2 ,..., L_DT2h-i are stored as a plurality, and data determination is performed to determine regular data to be output to the first CPU 11 from the plurality of first held data L_DT2h-1, L_DT2h-2,. Part 132.

  Thereby, since the multiprocessor system 1 can prevent reading an indefinite value from the dual port memory 13, an unexpected malfunction of the industrial equipment to which the multiprocessor system 1 is applied can be prevented.

  The technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide an effect equivalent to the intended purpose of the present invention. Further, the technical scope of the present invention is not limited to the combinations of features of the invention defined by the claims, but is defined by any desired combination of specific features among all the disclosed features. sell.

1 multiprocessor system 11 first CPU
12 Second CPU
13 Dual port memory 14 Clock signal generator 21 First address bus line 22 CPU side first data bus line 23r Read memory side first data bus line 23w Write memory side first data bus line 31 First memory access controller 32 second memory access controller 33 dual port memory 41 second address bus line 42 CPU side second data bus line 43r read memory side second data bus line 43w write memory side second data bus line 131 access signal generator 132 data determination unit 132a first line selection circuits 132b-1, 132b-2, 132b-i first holding circuit 132c first determination circuit 132d first holding data selection circuit 132e first output buffer circuits 331, 331-1, 331 -2,331- First input / output port 332, 332-1, 332-2, 332-n Second input / output port 333, 333-1, 333-2, 333-n Storage section CLK Clock signal L_ADR First address signal L_DT1 First book Embedded data L_DT2 first read data L_DT2 first hold data L_DT2s first selection data L_DT2h-1, L_DT2h-2, L_DT2h-i first hold data L_RD1 first data read instruction signal L_WR1 first data write instruction signal L_WR2 first Data write signal LT Holding signal input terminal OE Control signal input terminal OS Selection control signal R_ADR Second address signal R_DT1 Second write data R_DT2 Second read data R_RD1 Second data read instruction signal R_WR1 Third data write instruction signal R_WR2 Second data write signal RDL , RDL2, RDL3, RDL4, RDLi first data holding signal ROE first data read control signal Tdb delay variation period Tds period

Claims (4)

A plurality of dual-port memories each having two input / output ports from / to which data is input / output;
A processing device for processing data input / output in the plurality of dual port memories;
A memory access controller that controls access of the processing device to a plurality of the dual port memories;
A clock signal transmitter for transmitting a clock signal input to the memory access controller;
The memory access controller includes a plurality of read data read from one dual-port memory among the plurality of dual-port memories as held data in synchronization with the clock signal, and a plurality of the held data have a data determination unit that determines the data of the normal output to the processing unit from among,
The data determination unit includes a determination unit that determines which of the plurality of retained data is the regular data based on the difference between the plurality of retained data.
A multiprocessor system characterized by The determination unit is a multi-processor system according to claim 1, characterized in that it stores a plurality of difference data held together, the determination table that associates and holding data to be the regular data. The memory access controller selects one data bus line to which the read data is transmitted among data bus lines connected to the plurality of dual port memories based on an address signal input to the plurality of dual port memories. multiprocessor system according to claim 1 or 2, characterized in that it comprises a line selection unit for selecting. The multiprocessor system according to claim 3 , wherein the line selection unit is provided in the data determination unit.

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