JP2009216806A - Drive circuit for electro-optical device, driving method, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent sampling to a data line from being delayed with respect to a supplied data signal. <P>SOLUTION: A reference pulse Ref is supplied to a monitor signal line 173 during a horizontal retrace period and a pulse Ma is supplied to a pulse signal line 143 at the same timing as the reference pulse Ref. A TFT (thin film transistor) 184 in a dummy circuit 180 samples the reference pulse Ref supplied to one end of the input side of the monitor signal line 173 in a panel 100 for a dummy data line 115, on the basis of a signal obtained by logically operating a signal Br and the pulse Ma by an AND circuit 182, to obtain a detection signal Det. The delay amount of the detection signal Det with respect to the reference pulse Ref simulates the delay amount of sampling timing with respect to the supply timing of data signals Vid1 to Vid6, so that a power supply circuit 206 resets power supply voltages (Vdd to Vss) to a value higher than the present set value by one step, when it is judged that the delay amount is greater than a previously set threshold. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for preventing deterioration in display quality and the like.

  In recent years, a projector that forms a reduced image by a display panel such as a liquid crystal and enlarges and projects this reduced image onto a screen, a wall surface, or the like by an optical system is becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with video data (or video signal) from a host device such as a personal computer or a TV tuner. This video data designates the gradation (brightness) of the pixels and is supplied in the form of vertical scanning and horizontal scanning of the pixels arranged in a matrix, so that the panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the panel used for the projector, the scanning lines are sequentially selected, while the data lines are sequentially selected and the data signal is selected over a period in which one scanning line is selected (one horizontal scanning period). A driving method of sampling on the data line is generally used. Here, the data signal is a signal obtained by converting video data so as to be suitable for driving a liquid crystal.

A panel that employs such a driving method is provided with a sampling switch between an image signal line that supplies a data signal and each data line, and the sampling switch is turned on according to the sampling signal, whereby the data signal Are sampled on the data line. In such a configuration, if the pulse widths of the sampling signals corresponding to the adjacent data lines overlap, the data signal different from the original is sampled into the data signal, so that the display quality is deteriorated.
Therefore, in recent years, there is a technique for narrowing the pulse width of the sampling signal with the enable pulse so that the sampling signals output before and after the time do not overlap each other.

By the way, if for some reason the output timing of the sampling signal with respect to the data signal is delayed, the data signal different from the original is sampled on the data line as in the case where the pulse width of the sampling signal is overlapped, so the display quality is lowered. There is a problem that.
In order to solve this problem, a monitor signal synchronized with the enable pulse is supplied to the panel to detect the amount of delay or advance in the panel, and the phase of the enable pulse is adjusted according to the amount of deviation. A technique for correcting the phase shift of the enable pulse has also been proposed (see Patent Document 1).
JP 2003-157063 A

However, this technology selects one signal whose phase has been shifted in multiple stages and supplies it to the panel, which necessitates a multi-stage delay circuit and complicates it, and generates signals that are not actually supplied to the panel. Therefore, it cannot be said that it is preferable in terms of power consumption.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a driving circuit, a driving method, an electro-optical device, and an electronic apparatus for an electro-optical device capable of avoiding a complicated configuration. Is to provide.

  In order to solve the above-described problem, the driving circuit of the electro-optical device according to the present invention is provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines, and the scanning lines and the data lines are selected. A pixel that displays a gradation corresponding to the sampled data signal on the selected data line, a scanning line driving circuit that selects the scanning line, and a period during which the scanning line is selected. A shift register for generating a pulse signal for selecting the data line; a logic circuit for limiting the pulse signal generated by the shift register to a pulse width of an enable pulse; and outputting the sampling signal as a sampling signal; A sampling circuit that samples the data line in accordance with a sampling signal. A delay amount detection circuit for detecting a delay amount when the reference pulse is sampled on the data line or the dummy data line, and when the delay amount detected by the delay amount detection circuit is larger than a predetermined threshold value. And a power supply circuit for increasing a power supply voltage for at least one of the shift register and the logic circuit. According to the present invention, for example, when a constituent element such as a logic circuit is deteriorated and the timing at which a data signal is sampled on the data line is delayed, the power supply voltage is increased and the response characteristic is improved.

In the present invention, the reference pulse is output in a blanking period in which neither the scanning line nor the data line is selected, and the power supply circuit supplies the power supply voltage in an effective display period after the blanking period. A constant configuration is preferable. According to this configuration, the power supply voltage is changed during the blanking period and is constant during the effective display period, so that the display is not adversely affected.
On the other hand, if the increase in the delay amount is due to the deterioration of the constituent elements, the progress of the deterioration is extremely slow. For this reason, the power supply circuit may be configured to increase the power supply voltage stepwise every time the delay amount exceeds a predetermined threshold. According to this configuration, it is possible to appropriately increase the power supply voltage with respect to the progress of gradual deterioration.
The present invention can be conceptualized as a driving method of an electro-optical device, a driving method, an electro-optical device, and an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed circuit board, and is connected to the panel 100 by an FPC (Flexible Printed Circuit) substrate (not shown) and supplies various signals while detecting later described. The signal Det is received.

The processing circuit 50 includes a scanning control circuit 202, a delay amount detection circuit 204, a power supply circuit 206, and a data signal supply circuit 300.
Among these, the data signal supply circuit 300 further includes an S / P conversion circuit 310, a D / A conversion circuit group 320, and an amplification / inversion circuit 330. The S / P conversion circuit 310 is synchronized with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk, distributes digital video data Vid supplied from a host device (not shown) to six channels, and This is expanded six times on the time axis (also referred to as serial-parallel conversion or phase expansion) and output as video data Vd1d to Vd6d.

Here, the video data Vid is data for designating a gradation level (brightness) of a pixel. Specifically, the video data Vid is data that designates the gradation of the pixel that is horizontally scanned in the horizontal effective display period, and designates the gradation of the pixel to the lowest value (black) in the horizontal blanking period.
Note that the reason why the gray level of the pixel is designated as the lowest value in the horizontal blanking period is mainly because the pixel does not contribute to the display even if it is supplied to the pixel due to timing shift or the like. The reason why the video data Vid is converted from serial to parallel is to secure a sample and hold time and a charge / discharge time by increasing the time during which a data signal is applied in a sampling switch described later.

The D / A conversion circuit group 320 is an aggregate of D / A converters provided for each channel, and converts the video data Vd1d to Vd6d into analog signals having voltages corresponding to the gradations of the pixels. It is.
The amplifying / inverting circuit 330 performs polarity inversion or normal rotation on the analog-converted signal, and then amplifies the signal appropriately and supplies it to the panel 100 as data signals Vid1 to Vid6.
Regarding polarity inversion, there are modes such as (a) every scanning line, (b) every data line, (c) every pixel, and (d) every surface (frame). In this embodiment, (a) It is assumed that the polarity is inverted (1H inversion) for each scanning line. However, the present invention is not limited to this.
The voltage Vc is an amplitude center voltage when the polarity of the data signal is inverted, and is substantially equal to the voltage LCcom applied to the counter electrode. In the present embodiment, for convenience, a higher voltage than the amplitude center voltage Vc is referred to as positive polarity, and a lower voltage is referred to as negative polarity.
In this embodiment, the video data Vid is converted to analog after serial-parallel conversion, but it is needless to say that analog conversion may be performed before serial-parallel conversion.

Next, the configuration of the panel 100 will be described. The panel 100 forms a predetermined image by an electro-optical change, and FIG. 2 is a block diagram showing an electrical configuration of the panel 100. FIG. 3 is a diagram illustrating a detailed configuration of the pixels of the panel 100.
As shown in FIG. 2, on the panel 100, a plurality of scanning lines 112 extend in the horizontal direction (X direction), while a plurality of data lines 114 extend in the vertical direction (Y direction) in the drawing. It is installed. Then, the pixels 110 are provided so as to correspond to the intersections of the scanning lines 112 and the data lines 114, respectively, thereby constituting the display area 100a.
In this embodiment, the number of scanning lines 112 (the number of rows) is “m”, the number of data lines (the number of columns) is “6n” (a multiple of 6), and the pixels 110 are m rows × 6n columns. It is assumed that the arrangement is arranged in a matrix.

The six image signal lines 171 are supplied with data signals Vid1 to Vid6 from the amplification / inversion circuit 330, respectively.
One end of each data line 114 is provided with a TFT 150 functioning as a sampling switch for sampling the data signals Vid1 to Vid6 supplied to the image signal line 171 to the data line 114, respectively. Each TFT 150 is an n-channel thin film transistor (hereinafter referred to as TFT) in the present embodiment, and its drain electrode is connected to the data line 114, while its gate electrode has six data lines. 114 is commonly connected as one unit.
Here, the data line 114 to which the gate electrodes of the TFTs 150 are commonly connected is considered as one block. When such a block is considered, in the TFT 150 in which the drain electrode is connected to one end of the data line 114 in the j-th column from the left in FIG. 2, the remainder obtained by dividing j by 6 is “1”. Then, the source electrode is connected to the image signal line 171 to which the data signal Vid1 is supplied. Similarly, each of the TFTs 150 whose drain electrodes are connected to the data lines 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0” Are respectively connected to the image signal lines 171 to which the data signals Vid2 to Vid6 are supplied.
For example, in FIG. 2, the source electrode of the TFT 150 whose drain electrode is connected to the data line 114 in the eleventh column from the left in FIG. 2 has a remainder of “5” obtained by dividing “11” by 6; It is connected to the supplied image signal line 171. Note that “j” here is for generalizing the data line 114 and is a positive integer satisfying 1 ≦ j ≦ 6n.

  The scanning line driving circuit 130 outputs scanning signals G1, G2, G3,..., Gm based on the start pulse Dy and the clock signal Cly generated by the scanning control circuit 202. Specifically, as shown in FIG. 5, the scanning line driving circuit 130 changes the level of the clock signal Cly (rises or falls) from the start pulse Dy supplied at the beginning of the vertical effective display period. The signals are sequentially shifted as they are taken in, and are sequentially output exclusively as scanning signals G1, G2,..., Gm that become H level only during the horizontal scanning period (1H).

  The block selection circuit 140 includes a shift register 142 and an AND circuit 144. Among these, the shift register 142 outputs signals Sa1, Sa2,..., Sa (n−1), San based on the start pulse Dx and the clock signal Clx generated by the scanning control circuit 202. Specifically, as shown in FIG. 6, the scanning line driving circuit 130 captures the start pulse Dx supplied at the beginning of the horizontal effective display period at the timing when the level of the clock signal Clx transitions and sequentially shifts, The signals Sa1, Sa2, Sa3,..., Sa (n−1), San are output. Therefore, the signals Sa1, Sa2,..., Sa (n-1), San each have a pulse width of a half cycle of the clock signal Clx.

The AND circuit 144 is provided at each output stage of the shift register 142, obtains a logical product signal of the signal from the output stage and the signal Enb supplied to the pulse signal line 143, and obtains the logical product signal as a sampling signal. Output as S1, S2, S3,..., Sn.
The AND circuit 144 is a known circuit as shown in FIG. That is, it has a negative logic configuration combining a NAND circuit and a NOT circuit, and uses a higher voltage Vdd and a lower voltage Vss as power supply voltages.

  The signal Enb is supplied to the pulse signal line 143 by the scanning control circuit 20 and has a waveform as shown in FIG. That is, the signal Enb is synchronized with the clock signal Clx in the horizontal blanking period and includes, for example, a pulse Ma corresponding to a half cycle of the clock signal Clx. The signal Enb includes an enable pulse having a pulse width narrower than a half cycle of the clock signal Clx in the normal effective display period. Therefore, in the horizontal effective display period, the signals Sa1, Sa2,..., Sa (n−1), San having a pulse width of a half cycle of the clock signal Clx are narrowed by the enable pulse, and the sampling signal S1 , S2, S3,..., Sn.

  These sampling signals S1, S2, S3,..., Sn are commonly supplied to the gate electrodes of the TFTs 150 corresponding to the data lines 114 that are blocked in FIG. For example, the second block counted from the left corresponds to the data lines 114 in the seventh column to the twelfth column, and therefore the sampling signal S2 is commonly supplied to the gate electrodes of the TFTs 150 corresponding thereto. The TFT 150 is an n-channel type in this embodiment, but may be a p-channel type or a complementary type combining both channels.

  In the present embodiment, the monitor signal line 173 is provided so as to be adjacent to and substantially parallel to the image signal line 171 to which the data signals Vid1 to Vid6 are supplied. Note that the monitor signal line 173 is desirably formed under the same conditions (material, length, width, etc.) as the image signal line 171. A reference pulse Ref is supplied to one end which is an input end of the monitor signal line 173. The reference pulse Ref is output by the scanning control circuit 20 at the same timing and the same pulse width as the pulse Ma in the signal Enb.

On the other hand, the dummy circuit 180 is provided on the opposite side (downstream) of the input side of the monitor signal line 173 and includes an AND circuit 182 and a TFT 184. Among these, the AND circuit 182 has the same configuration as the AND circuit 144, and the TFT 184 has the same characteristics as the TFT 150.
One of the input ends of the AND circuit 182 is connected to the pulse signal line 143, and the other end of the input end is supplied with a signal Br that becomes the voltage Vdd (H level) only in the horizontal blanking period. Further, the TFT 184 is an n-channel type like the TFT 150, and its gate electrode is connected to the output terminal of the AND circuit 182, its source electrode is connected to the other end of the monitor signal line 173, and its drain electrode is dummy data. Connected to line 115.
The signal appearing on the dummy data line 115 is fed back to the processing circuit 50 as the detection signal Det.

Next, the pixel 110 will be described.
As shown in FIG. 3, in the pixel 110, the source electrode of the n-channel TFT 116 is connected to the data line 114 and the drain electrode is connected to the pixel electrode 118, while the gate electrode is connected to the scanning line 112. It is connected.
Further, the counter electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118, and is maintained at a constant voltage LCcom. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the counter electrode 108. Therefore, a liquid crystal capacitor composed of the pixel electrode 118, the counter electrode 108, and the liquid crystal layer 105 is formed for each pixel.

The transmittance of light passing through the liquid crystal capacitor having such a configuration changes according to the effective voltage value held by the pixel electrode 118 and the counter electrode 108. Here, for convenience of explanation, if the effective voltage value held in the liquid crystal capacitor is close to zero, the transmittance is maximized to display white, while the transmittance decreases as the effective voltage value increases. Mode.
In addition, a storage capacitor 109 is formed for each pixel in order to make it difficult for charge to leak in the liquid crystal capacitor. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain electrode of the TFT 116), while the other end is commonly connected across all the pixels and is kept at a constant potential, for example, the same voltage LCcom as the counter electrode 108. ing.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to the constituent elements of the scanning line driving circuit 130, the shift register 142, the AND circuits 144 and 182, and the TFT 150 and TFT 184, thereby reducing the size and cost of the entire device. It contributes to.

The description returns to FIG. 1 again.
The scanning control circuit 202 generates the start pulse Dx and the clock signal Clx based on the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal Dclk, and controls the horizontal scanning by the block selection circuit 140. A start pulse Dy and a clock signal Cly are generated and vertical scanning by the scanning line driving circuit 130 is controlled.
Further, the scanning control circuit 202 outputs a reference pulse Ref in the horizontal blanking period, and outputs a signal Enb including a pulse Ma having the same width as the reference pulse ref and an enable pulse.
In addition, the scanning control circuit 202 controls the phase expansion operation and the polarity inversion operation in the data signal supply circuit 300 in accordance with the control of the vertical scanning and the horizontal scanning.

The delay amount detection circuit 204 detects the delay amount of the detection signal Det with respect to the reference pulse Ref. The power supply circuit 206 outputs the power supplies of the AND circuits 144 and 182 and the voltages Vdd and Vss used for the signal Br based on the delay amount detected by the delay amount detection circuit 204. Specifically, as will be described later, the power supply circuit 206 sets the difference between the voltages Vdd and Vss to be one step higher when the detected delay amount exceeds a predetermined threshold value.
Note that a power source is also required for the scanning line driving circuit 130 and the shift register 142 in the panel 100. However, in this embodiment, a power source separate from the power source circuit 206 is used for convenience of explanation.

Next, the operation of the electro-optical device will be described. First, description will be made without considering the delay amount of the detection signal Det with respect to the reference pulse Ref.
FIG. 5 is a timing chart for explaining vertical scanning in the electro-optical device, FIG. 6 is a timing chart for explaining horizontal scanning, and FIG. 7 shows data supplied over successive horizontal scanning periods. It is a figure which shows the example of the voltage waveform of a signal.

At the beginning of the vertical effective display period, the start pulse Dy is supplied to the scanning line driving circuit 130. By this supply, as shown in FIG. 5, the scanning signals G1, G2, G3,. First, the horizontal scanning period in which the scanning signal G1 is at the H level will be described.
In the present embodiment, since the polarity inversion is performed for each scanning line as described above, positive writing is designated for odd (1, 3, 5,...) Rows in this vertical scanning period. It is assumed that negative polarity writing is designated for the (2, 4, 6,...) Row.

  The horizontal scanning period is divided into a horizontal blanking period and a subsequent horizontal effective display period. In the horizontal effective display period, the video data Vid supplied in synchronization with the horizontal scanning is first distributed to the six channels by the S / P conversion circuit 310 and expanded six times with respect to the time axis, Second, each signal is converted into an analog signal by the D / A conversion circuit group 320. Third, the signal is output by the amplifier / inverter circuit 330 by performing normal rotation with reference to the voltage Vc corresponding to positive polarity writing. The For this reason, the voltages of the data signals Vid1 to Vid6 by the amplifying / inverting circuit 330 become higher than the voltage Vc as the pixel is darkened.

On the other hand, in the horizontal effective display period of the horizontal scanning period in which the scanning signal G1 is at the H level, as shown in FIG. 6, the start pulse Dx is sequentially shifted according to the clock signal Clx by the shift register 142, and the signals Sa1, Sa2 , Sa3,..., San sequentially become H level.
Here, it is assumed that the detection signal Det is not delayed with respect to the reference pulse Ref (as described later, the sampling of the data line 114 is not delayed with respect to the supply of the data signals Vid1 to Vid6). Therefore, as shown in FIG. 6, the signals Sa1, Sa2, Sa3,..., San have their pulse widths that become H level reduced by the signal Enb, and the sampling signals S1, S2, S3,. (N-1), output as Sn.

Now, when the sampling signal S1 becomes H level, the corresponding data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the first block from the left. Since the scanning signal G1 is at the H level, the sampled data signals Vid1 to Vid6 are the first scanning line 112 counted from the top in FIG. 2 and the six scanning lines 112 (1 to 6 counted from the left). It is applied to the pixel electrodes 118 of the pixels intersecting with the data line 114 in the (column).
Thereafter, when the sampling signal S2 becomes H level, the data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the second block, respectively, and these data signals Vid6 to Vid6 are 1 This is applied to the pixel electrode 118 of the pixel that intersects the scanning line 112 in the row and the six data lines 114 (seventh to twelfth columns from the left).

  In the same manner, when the sampling signals S3, S4,..., Sn sequentially become H level, the data signals Vid1 to 6 are applied to the six data lines 114 belonging to the third, fourth,. Corresponding ones of Vid6 are sampled, and the data signals Vid1 to Vid6 are applied to the pixel electrodes 118 of the pixels intersecting with the scanning line 112 of the first row and the six data lines 114, respectively. As a result, the writing of the positive voltage corresponding to the gradation is completed for all the pixels in the first row.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, negative polarity writing is designated in the horizontal scanning period in which the scanning signal G2 is at the H level.
On the other hand, in the horizontal blanking period, the video data Vid designates the black color of the pixel, but in the immediately preceding horizontal effective display period, since the positive writing was performed, the data signals Vid1 to Vid6 are as shown in FIG. At approximately the center timing of the horizontal blanking period, when applied to the pixel electrode 118 in the pixel 110, the pixel is changed to the lowest gradation black from the positive voltage Vb (+) that makes the pixel the black of the lowest gradation. The negative voltage Vb (−) is switched.
Here, the voltages Vb (+) and Vb (−) are symmetrical with each other when the voltage Vc is taken as a reference. In FIG. 7, voltages Vw (+) and Vw (−) are a positive voltage and a negative voltage that, when applied to the pixel electrode 118 in the pixel 110, make the pixel white in the highest gradation. They are symmetrical with each other when Vc is taken as a reference.
As for the voltage relationship between the scanning signals G1, G2, G3, G4,..., Gm, the L level is lower than the voltage Vb (−) and the H level of the scanning signal is higher than the voltage Vb (+).

  The operation in the horizontal effective display period in which the scanning signal G2 becomes H level is the same as that in the horizontal effective display period in which the scanning signal G1 becomes H level, and the sampling signals S1, S2, S3,. Thus, the writing of the voltage corresponding to the gradation is completed for all the pixels in the second row. However, since the negative polarity writing is designated during the period in which the scanning signal G2 is at the H level, the amplifying / inverting circuit 330 distributes the signal which is distributed to 6 channels and is expanded 6 times with respect to the time axis, Corresponding to negative polarity writing, the voltage Vc is inverted and output. Therefore, as shown in FIG. 7, the voltages of the data signals Vid1 to Vid6 become lower than the voltage Vc as the pixel is darkened.

In the same manner, the scanning signals G3, G4,..., Gm become H level, and writing is performed on the pixels in the third row, fourth row,. As a result, positive polarity writing is performed on the pixels in the odd-numbered rows, while negative polarity writing is performed on the pixels in the even-numbered rows. In this one vertical scanning period, the first to m-th rows are performed. Writing is completed over all of the pixels up to the line.
The data signals Vid1 to Vid6 are supplied from the voltage Vb (+) when the horizontal effective display period of the positive polarity writing is shifted to the horizontal effective display period of the negative polarity writing at substantially the center timing of the horizontal blanking period. When shifting from the horizontal effective display period for negative polarity writing to the horizontal effective display period for positive polarity writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal layer 105, and deterioration of the liquid crystal layer 105 is prevented.

By the way, the processing circuit 50 outputs various signals such as the data signals Vid1 to Vid6 and the signal Enb at the same timing. Here, various signals are supplied from the processing circuit 50 to the panel 100 through the FPC board. However, since there are no active elements such as transistors, timing deviation in the FPC board does not become a problem.
However, in the panel 100, the data signals Vid1 to Vid6 are sampled on the respective data lines 114 by the sampling signals S1 to Sn by the logical operation of the signals Sa1 to San and the signal Enb, so that the shift register 142 and the AND circuit 144 When the characteristics of the constituent elements and further the active elements such as the TFT 150 are deteriorated, the sampling timing to the data line 114 is delayed with respect to the supply timing of the data signals Vid1 to Vid6.
Here, even if the sampling timing to the data line 114 is delayed with respect to the supply timing of the data signals Vid1 to Vid6, if the delay amount ΔT is small, as shown in FIG. It is possible to sample a data signal corresponding to the original pixel.
However, when the delay amount ΔT increases, as shown in FIG. 8B, after the data signal corresponding to the original pixel is sampled on each data line 114, the data signal corresponding to a different pixel is received. Since the signal is sampled, the display quality is significantly lowered.
8 (a) and 8 (b), for convenience, the supply timing of the data signals Vid1 to Vid6 is described as the phase development timing to the video data Vd1d to Vd6d before being converted into analog signals. Yes.

In order to prevent such deterioration of display quality, first, it is necessary to detect the delay amount of the sampling timing with respect to the supply timing of the data signals Vid1 to Vid6.
However, the rise and fall timings of the enable pulse do not coincide with those of the clock signal Clx, and it is difficult to directly detect the sampling timing delay with respect to the supply timing of the data signals Vid1 to Vid6 which are analog signals. .

Therefore, in the present embodiment, the scanning control circuit 202 supplies the reference pulse Ref to the monitor signal line 173 in the horizontal blanking period, and supplies the pulse Ma to the pulse signal line 143 at the same timing as the reference pulse Ref. The dummy circuit 180 is included. In this configuration, the TFT 184 receives the reference pulse Ref supplied to one end on the input side of the monitor signal line 173 in the panel 100 based on a signal obtained by logically calculating the signal Br and the pulse Ma by the AND circuit 182, and the dummy data line 115. To sample.
Since the AND circuit 182 and the TFT 184 in the dummy circuit 180 simulate the AND circuit 144 and the TFT 150, respectively, the detection signal Det obtained by sampling the dummy data line 115 is a data signal supplied to the image signal line 171. It is considered that the delay amount is the same as that when the TFT 150 samples the data line 114 based on the sampling signals S1 to Sn obtained by logically calculating the signals Sa1 to San and the signal Enb by the AND circuit 144.
Therefore, in the present embodiment, the delay amount detected by the delay amount detection circuit 204, that is, the delay amount of the detection signal Det with respect to the reference pulse Ref output by the scanning control circuit 202 is relative to the supply timing of the data signals Vid1 to Vid6. This simulates the sampling timing delay.

  When the power supply circuit 206 determines that the delay amount detected by the delay amount detection circuit 204 is larger than a preset threshold value, the power supply voltage (Vdd−Vss) is one step higher than the current set value. Since the value is reset, the response characteristic of the AND circuit 144 using the voltage (Vdd−Vss) as a power source is improved. Further, when the power supply voltage of the AND circuit 144 is increased, the logic amplitude (difference between the H level and the L level) of the output level is also increased. Therefore, the TFT 150 that inputs the sampling signal output from the AND circuit 144 to the gate electrode. The response characteristics are also improved.

For this reason, when the power supply circuit 206 resets the power supply voltage (Vdd−Vss) to a value one step higher, the response characteristics of the AND circuit 144 and the TFT 150 are improved, and the delay amount is reduced. Since the power supply circuit 206 increases the power supply voltage again if the delay amount is larger than the threshold value even if the delay amount is decreased, the delay amount becomes less than the threshold value and the display quality is prevented from being deteriorated due to the delay. It will be.
In addition, since the deterioration of characteristics progresses as time passes, the delay amount becomes larger than the threshold value again. At this time, the delay amount is reduced by the same operation, thereby preventing deterioration of display quality. Is done.

Therefore, according to the present embodiment, it is possible to prevent the display quality from being deteriorated due to the characteristic deterioration of the active element. Further, in this embodiment, it is not necessary to generate an extra signal other than the reference pulse Ref and the pulse Ma, so that the configuration can be simplified correspondingly.
Note that if the power supply voltage is changed during the horizontal effective display period, the sampling delay amount to the data line varies depending on the position of the data line, but in this embodiment, the change of the power supply voltage is changed horizontally. Since it is performed within the line period and is constant in the subsequent horizontal effective display period, it is possible to prevent display unevenness due to variation in the delay amount depending on the position of the data line.
In the present embodiment, the power supply voltage (Vdd−Vss) is set one step higher when it is determined that the detected delay amount is larger than the threshold value. It is desirable to keep the power supply voltage low enough to deal with subsequent deterioration. Since the power supply voltage is low in the initial state, it is possible to suppress power consumption in combination with simplification of the configuration.

By the way, the shift register 142 is configured by a clocked inverter or a NOT circuit that requires a power supply voltage as is well known. When these constituent elements deteriorate, the output of the signals Sa1 to San is delayed, so that it is considered that sampling to the data line 114 is delayed with respect to the supply of the data signals Vid1 to Vid6. Therefore, the power supply circuit 206 may have a configuration in which the power supply voltage of the shift register 142 is increased according to the delay.
From the viewpoint of reducing the sampling delay to the data line with respect to the supply of the data signal, at least when the detected delay amount becomes larger than the threshold value, at least the shift register 142 or the AND circuit 144 A configuration in which either one of the power supply voltages is increased is considered to be sufficient.

In the above embodiment, the power supply voltage is changed step by step. However, the power supply voltage may be increased by the number of stages corresponding to the detected delay amount. Moreover, you may change not continuously but continuously.
In the embodiment, the pulse En is included in the signal Enb. However, the start pulse Dx may be supplied to the monitor signal line 173 as the pulse Ma. However, when substituting with the start pulse Dx, it is necessary to change to a configuration in which a certain amount of time is required until the enable pulse is supplied after the start pulse Dx is supplied.
Further, instead of indirectly detecting the sampling delay amount of the data line with respect to the supply of the data signals Vid1 to Vid6, for example, a dummy signal for detection is inserted into the data signals Vid1 to Vid6 in the blanking period, and the dummy signal The delay of the detection signal obtained by sampling the data line on the data line may be directly detected.

In the above-described embodiment, the video data Vid is expanded into the 6-channel video data Vd1d to Vd6d. However, the number of expanded channels is not limited to “6”. In addition, the configuration is not limited to the phase expansion, and the dot sequential method can be applied as long as the sampling signal is narrowed by the enable pulse.
On the other hand, in the above-described embodiment, the data signal supply circuit 300 processes the digital video signal Vid. However, the data signal supply circuit 300 may be configured to process an analog image signal. Further, in the data signal supply circuit 300, the analog conversion is performed after the S / P expansion. However, if the final output is the same analog signal, the S / P expansion may be performed after the analog conversion. .

Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the counter electrode 108 and the pixel electrode 118 is small. good.
In addition, the present invention is not limited to the liquid crystal display device, and any configuration that supplies video data (video signal) via the image signal line 171 may include, for example, an EL (Electronic Luminescence) element, an electron emission element, an electric peristaltic element, and a digital mirror The present invention can also be applied to devices using elements, plasma displays, and the like.

<Electronic equipment>
Next, a projector using the panel 100 described above as a light valve will be described as an example of an electronic apparatus using the electro-optical device according to the embodiment described above.
FIG. 9 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 is provided with a lamp unit 2102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the panel 100 in the above-described embodiment, and image signals corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 15). Are driven respectively.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

  In addition to the electronic devices described with reference to FIG. 9, direct-view types such as mobile phones, personal computers, televisions, video camera monitors, car navigation devices, pagers, electronic notebooks, calculators, word processors , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a figure which shows the structure of the panel in the same electro-optical apparatus. It is a figure which shows the structure of the pixel in the panel. It is a figure which shows the structure of the AND circuit in the same electro-optical apparatus. It is a figure for demonstrating the vertical scanning of the same electro-optical apparatus. It is a figure for demonstrating the horizontal scanning of the same electro-optical apparatus. FIG. 6 is a diagram for describing voltage writing by horizontal scanning of the electro-optical device. FIG. 10 is a diagram for explaining display unevenness due to delay in the same electro-optical device. It is a figure which shows the structure of the projector to which the same electro-optical apparatus is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Panel, 130 ... Scan line drive circuit, 142 ... Shift register, 143 ... Pulse signal line, 144 ... AND circuit, 150 ... Sampling switch, 171 ... Image signal line, 173 ... Monitor signal line, 202 ... Scan control circuit, 204 ... Delay amount detection circuit, 206 ... Power supply circuit, 2100 ... Projector

Claims (6)

Provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when the scanning lines and the data lines are selected, according to the data signal sampled on the selected data lines A pixel for displaying gradation,
A scanning line driving circuit for selecting the scanning line;
A shift register for generating a pulse signal for selecting the data line over a period in which the scanning line is selected;
A logic circuit that limits the pulse signal generated by the shift register to the pulse width of the enable pulse and outputs it as a sampling signal;
A sampling circuit for sampling the data signal on the data line according to the sampling signal;
A drive circuit for an electro-optical device having:
A delay amount detection circuit for detecting a delay amount when a reference pulse is sampled on the data line or the dummy data line;
A power supply circuit that increases a power supply voltage for at least one of the shift register and the logic circuit when a delay amount detected by the delay amount detection circuit is greater than a predetermined threshold;
A drive circuit for an electro-optical device, comprising: The reference pulse is output in a blanking period in which neither the scanning line nor the data line is selected,
The drive circuit for an electro-optical device according to claim 1, wherein the power supply circuit keeps the power supply voltage constant in an effective display period after the blanking period. The drive circuit for an electro-optical device according to claim 1, wherein the power supply circuit increases the power supply voltage stepwise every time the delay amount exceeds a predetermined threshold. Provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when the scanning lines and the data lines are selected, according to the data signal sampled on the selected data lines A pixel for displaying gradation,
A scanning line driving circuit for selecting the scanning line;
A shift register for generating a pulse signal for selecting the data line over a period in which the scanning line is selected;
A logic circuit that limits the pulse signal generated by the shift register to the pulse width of the enable pulse and outputs it as a sampling signal;
A sampling circuit that samples the data signal on the data line according to the sampling signal, and a driving method of an electro-optical device,
Detect the delay amount when the reference pulse is sampled on the data line or dummy data line,
A driving method of an electro-optical device, wherein a power supply voltage for at least one of the shift register and the logic circuit is increased when the detected delay amount becomes larger than a predetermined threshold value. Provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when the scanning lines and the data lines are selected, according to the data signal sampled on the selected data lines A pixel for displaying gradation,
A scanning line driving circuit for selecting the scanning line;
A shift register for generating a pulse signal for selecting the data line over a period in which the scanning line is selected;
A logic circuit that limits the pulse signal generated by the shift register to the pulse width of the enable pulse and outputs it as a sampling signal;
A sampling circuit that samples the data signal on the data line according to the sampling signal; a delay amount detection circuit that detects a delay amount when a reference pulse is sampled on the data line or a dummy data line;
A power supply circuit that increases a power supply voltage for at least one of the shift register and the logic circuit when a delay amount detected by the delay amount detection circuit is greater than a predetermined threshold;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 5.

Images