JP2006195387A - Electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of longitudinal stripes in a display region. <P>SOLUTION: A constitution is provided to respectively extract shift signals of a shift register by enable signals Enb1 to Enb4 and the signals are outputted as sampling signals. In the above constitution, phase adjusters 541 to 544 are respectively provided to individually adjust the phases of the enable signals Enb1 to Enb4. Rather than limiting the individual adjustment to the phases of the enable signals Enb1 to Enb4, the individual adjustment can also be made for pulse widths, pulse heights and waveforms, if desired. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for preventing deterioration of display quality appearing in an electro-optical device.

  In recent years, projectors that form a small image using an electro-optical panel such as a liquid crystal and enlarge and project the small image using an optical system are becoming widespread. The projector does not have a function of creating an image by itself, and is supplied with image data (or an image signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical and horizontal scanning of the pixels arranged in a matrix, so that the display panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the display panel used in the projector, the scanning lines are selected one by one in a predetermined order, and the data lines are sequentially arranged one by one in a period during which one scanning line is selected (one horizontal scanning period). In general, driving is performed in a dot-sequential manner in which a data signal selected and converted so that image data is suitable for driving a liquid crystal is supplied to a selected data line.

Recently, high definition display images are progressing as in high definition. High definition can be achieved by increasing the number of scanning lines and the number of data lines, but since the frame frequency is fixed, the increase in the number of scanning lines shortens one horizontal scanning period, In the dot sequential method, the data line selection period is shortened by increasing the number of data lines. For this reason, in the dot sequential method, it becomes impossible to secure a sufficient time for supplying the data signal to the data line as the definition becomes higher, and writing to the pixels has started to be insufficient. Therefore, a method called phase expansion drive has been devised for the purpose of eliminating the shortage of writing (see Patent Document 1).
In this phase expansion drive, data lines are blocked every predetermined column, for example, every six columns, and blocks are selected one by one in a predetermined order in one horizontal scanning period, and six columns belonging to the selected block are selected. In this method, a data signal expanded to 6 times the time axis is supplied to each data line. In this phase development driving method, the time for supplying the data signal to the data line can be secured 6 times in this example as compared with the dot sequential method, and thus it is considered suitable for high definition. Yes.

By the way, the sampling of the data signal with respect to the data line is performed by providing a sampling switch between one end of the data line and the image signal line for supplying the data signal, and turning this sampling switch on and off according to the sampling signal. For this reason, the sampling signal is sequentially set to the H level exclusively for each data line in the case of the dot sequential method, and for each block line in the case of the phase expansion method, and when the sampling switch is, for example, an n-channel transistor. And supplied to the gate of the sampling switch.
Here, if a sampling signal pulse (H level) is output for some reason and a pulse of an adjacent sampling signal is overlapped, the data belonging to an adjacent block (if the phase expansion method is used) Since a part of the data signal to be sampled is also sampled on the line), it causes a so-called ghost.
Therefore, in recent years, a technique has also been proposed in which the pulse widths of sampling signals are narrowed by a plurality of control signals called enable signals so that adjacent sampling signal pulses do not overlap each other. ing.
JP 2000-112437 A

However, due to these enable signals, vertical streak-like unevenness, that is, a phenomenon in which the gradation of the pixel is slightly different for each column occurs, and the deterioration of display quality becomes conspicuous.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an electro-optical device and an electronic apparatus capable of suppressing a display quality deterioration phenomenon when the definition is increased.

  In order to achieve the above object, the present invention is provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and the data signal supplied to the data lines when the scanning lines are selected. A pixel having a corresponding gradation, a scanning line driving circuit that selects the scanning lines in a predetermined order, and a shift register that sequentially transfers a predetermined pulse signal according to a predetermined clock signal when the scanning lines are selected. And a circuit for outputting sampling signals whose pulse widths do not overlap each other based on the sequentially transferred pulse signals and a predetermined plurality of series of enable signals, and a data signal supplied to the image signal line in accordance with the sampling signals A sampling switch for sampling the data line; and a processing circuit for supplying the plurality of enable signals in synchronization with the clock signal, And having a processing circuit which individually adjusted response characteristics of several series of enable signals for each sequence. According to the present invention, even when the phases of the plurality of enable signals do not satisfy the predetermined relationship at the time of input of the logical operation circuit, it is possible to adjust the predetermined relationship.

In the present invention, it is preferable that the response characteristic of the enable signal is any one of a phase, a pulse width, a pulse height and a waveform response time of the enable signal, or a combination thereof. Further, it is preferable that the processing circuit supplies a data signal to the image signal line in synchronization with the clock signal.
The present invention can be conceptualized not only as an electro-optical device but also as an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a display panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed board, and is connected to the display panel 100 by an FPC (Flexible Printed Circuit) board or the like.

The processing circuit 50 further includes a data signal supply circuit 300, a scanning control circuit 52, a phase control circuit 54, and phase adjusters 541 to 544. Among these, the data signal supply circuit 300 includes an S / P conversion circuit 320, a D / A conversion circuit group 340, and an amplification / inversion circuit 350.
The S / P conversion circuit 320 distributes digital image data Vd supplied from a host device (not shown) to six channels in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK. The image data is expanded six times on the time axis (phase expansion or serial-parallel conversion) and output as image data Vd1d to Vd6d. Here, the image data Vd is data that designates the gradation (brightness) of the pixel in the horizontal effective display period, and designates the pixel in the lowest gradation (black) in the horizontal blanking period. Note that the reason why a pixel is designated as the lowest gradation in the horizontal blanking period is mainly because the pixel does not contribute to display even if it is supplied to the pixel due to timing shift or the like. For convenience of explanation, the image data Vd1d to Vd6d are referred to as channels 1 to 6, respectively.

The D / A conversion circuit group 340 is an aggregate of D / A converters provided for each channel, and converts the image data Vd1d to Vd6d into analog signals having voltages corresponding to the gradation values. is there.
The amplifying / inverting circuit 350 performs normal rotation or polarity inversion on the analog-converted signal with reference to a voltage Vc described later, and supplies the signal to the display panel 100 as data signals Vid1 to Vid6.
Regarding polarity inversion, there are various modes such as (a) every scanning line, (b) every data signal, (c) every pixel, and (d) every surface (frame). ) It is assumed that the polarity is inverted for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for the sake of convenience, for the data signals Vid1 to Vid6, the higher side than the amplitude center voltage Vc is referred to as positive polarity, and the lower side is referred to as negative polarity.
In this embodiment, the image data Vda is converted from analog to serial after parallel-to-parallel conversion. However, it is needless to say that analog conversion may be performed before serial-to-parallel conversion.

Here, for convenience, the configuration of the display panel 100 will be described. The display panel 100 forms a predetermined image by electro-optic change, FIG. 2 is a block diagram showing an electrical configuration of the display panel 100, and FIG. 3 shows details of pixels of the display panel 100. FIG. The display panel 100 has a configuration in which an element substrate and a counter substrate on which a counter electrode is formed are bonded together with a certain gap, and liquid crystal is sealed in the gap.
As shown in FIG. 2, in the display panel 100, 864 rows of scanning lines 112 extend in the X (horizontal) direction in the figure, while 1152 (= 192 × 6) columns of data lines 114 in the figure Y ( It extends in the (vertical) direction. Pixels 110 are provided so as to correspond to the intersections between the scanning lines 112 and the data lines 114. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 864 rows × 1152 columns. However, the present invention is not limited to this.
In this embodiment, 1152 columns of data lines 114 are divided into blocks every six columns. For convenience of explanation, the first, second, third,..., 192th blocks from the left are denoted as B1, B2, B3,.

As for the detailed configuration of the pixel 110, as shown in FIG. 3, the source of an n-channel TFT (thin film transistor) 116 is connected to the data line 114, the drain is connected to the pixel electrode 118, and the gate Is connected to the scanning line 112.
A common electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118, and is maintained at a constant voltage LCcom in terms of time. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the common electrode 108. Therefore, a liquid crystal capacitor composed of the pixel electrode 118, the common electrode 108, and the liquid crystal layer 105 is formed for each pixel.

Although not shown in particular, the opposing surfaces of both substrates are respectively provided with alignment films that have been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted between the substrates by, for example, about 90 degrees. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the effective voltage applied to the liquid crystal capacitance is zero, the light passing between the pixel electrode 118 and the common electrode 108 is rotated about 90 degrees along the twist of the liquid crystal molecules, while the effective voltage is As it increases, the liquid crystal molecules tilt in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the light transmittance is While the maximum is white display, the amount of transmitted light decreases as the effective voltage value increases, and finally black display with the minimum transmittance is obtained (normally white mode).
Further, in order to reduce the influence of charge leakage from the liquid crystal capacitor via the TFT 116, the storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly grounded to, for example, the lower potential Vss of the power supply over all pixels.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to a scanning line driving circuit 130, a shift register 140, a sampling switch 151, and the like described below, and contributes to downsizing and cost reduction of the entire device. Yes.

  Subsequently, peripheral circuits such as a scanning line driving circuit 130 and a shift register 140 are provided around the pixel region. Among these, as shown in FIG. 4, the scanning line driving circuit 130 outputs scanning signals G1, G2, G3,... The lines are supplied to the scanning lines 112 in the third, third,. The details of the scanning line driver circuit 130 are omitted because they are not directly related to the present invention, but are supplied at the beginning of one vertical scanning period (1F) and have a pulse width (H of about a half cycle of the clock signal CLY. A transfer start pulse DY having a level) is output as scanning signals G1, G2, G3,..., G864 in a form that is sequentially shifted every time the level of the clock signal CLY transitions (rises or falls). It has become.

  Next, as shown in FIG. 5, the shift register 140 supplies a transfer start pulse DX having a pulse width (H level) of about one cycle of the clock signal CLX while being supplied at the start of one horizontal scanning period. Each time the level of the clock signal CLX having a duty ratio of 50% transitions, the signal is sequentially shifted and output as signals F1, F2, F3,. The signals F1, F2, F3,..., F96 are different from the scanning signals G1, G2, G3,..., G864 and are sequentially shifted by a half cycle of the clock signal CLX. Adjacent ones (for example, signals F1 and F2) overlap each other. The first signal F1 is output so as to be at the H level when the clock signal CLX is at the H level and the subsequent L level.

The signal paths of the signals F1, F2,..., F96 by the shift register 140 branch left and right in the drawing, and an AND circuit (logic operation circuit) 142 is provided for each branch path. Here, if m is an integer of 1 to 96 and the number of stages of the signals F1, F2,..., F96 by the shift register 140 is not specified and generally expressed as Fm, m is an odd number (1, 3, 5, ..., 95), the AND circuit 142 corresponding to the left branch path in FIG. 2 of the supply path of the signal Fm uses the AND signal of the signal Fm and the enable signal Enb1 as the sampling signal S ( On the other hand, the AND circuit 142 corresponding to the right branch path outputs a logical product signal of the signal Fm and the enable signal Enb2 as the sampling signal S (2m).
When m is an even number (2, 4, 6,..., 96), the AND circuit 142 corresponding to the left branch path in FIG. 2 among the signal Fm supply paths is enabled with the signal Fm. While the logical product signal with the signal Enb3 is output as the sampling signal S (2m-1), the AND circuit 142 corresponding to the right branch path outputs the logical product signal of the signal Fm and the enable signal Enb4 to the sampling signal S. Output as (2m).
The sampling signals S (2m−1) and S (2m) are output corresponding to the blocks B (2m−1) and B (2m), respectively.

  Here, as shown in FIG. 5, the enable signals Enb1 to Enb4 have substantially the same pulse width period in which they are at the H level, do not overlap each other, and the phases of the pulses are 90 degrees from each other. The signal to be supplied from the processing circuit 50 in a shifted relationship. Further, the pulses of the enable signals Enb4 and Enb1 are output in order during the period when the clock signal CLX is at the H level, and the pulses of the enable signals Enb2 and Enb3 are output in order during the period when the clock signal CLX is at the L level. Is done.

The sampling circuit 150 is an aggregate of sampling switches 151 provided corresponding to each of the data lines 114. Each sampling switch 151 is, for example, an n-channel TFT, and its drain is connected to the data line 114.
Here, the sampling signals corresponding to the blocks are commonly supplied to the gates of the six sampling switches 151 corresponding to the data lines 114 belonging to the same block. For example, the sampling signal S4 corresponding to the block B4 is commonly supplied to the gates of the six sampling switches 151 corresponding to the 19th to 24th data lines 114 belonging to the block B4.

Further, the source of the sampling switch 151 is connected to the image signal line 171 to which the data signals Vid1 to Vid6 are supplied in the following relationship.
That is, in the sampling switch 151 whose drain is connected to one end of the data line 114 in the j-th column from the left in FIG. 2, if the remainder obtained by dividing j by 6 is “1”, the source is the data Similarly, it is connected to the image signal line 171 to which the signal Vid1 is supplied, and similarly to the data line 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0”. The sampling switch 151 to which the drain is connected has its source connected to the image signal line 171 to which the data signals Vid2 to Vid4 are supplied.
For example, in FIG. 2, the source of the sampling switch 151 whose drain is connected to the data line 114 in the 23rd column has a remainder of “5” obtained by dividing “23” by 6; Connected to the signal line 171.

Returning to FIG. 1 again, the scanning control circuit 52 generates and shifts the transfer start pulse DX and the clock signal CLX from the dot clock signal DCLK, the vertical scanning signal Vs, and the horizontal scanning signal Hs supplied from the host device. In addition to controlling horizontal scanning by the register 140, a transfer start pulse DY and a clock signal CLY are generated to control vertical scanning by the scanning line driving circuit 130. Further, the scanning control circuit 52 generates the source signals E1 to E4 of the enable signals Enb1 to Enb4 so as to synchronize with the horizontal scanning, that is, synchronize with the clock signal CLX.
The scanning control circuit 52 controls the phase expansion in the above-described S / P conversion circuit 320 in synchronization with the horizontal scanning and designates the writing polarity in the amplification / inversion circuit 540.

The phase adjuster 541 adjusts the phase of the source signal E1 in accordance with the control of the phase control circuit 54 and outputs it as the enable signal Enb1. Similarly, the phase adjusters 542 to 544 adjust the phases of the source signals E2 to E4 according to the control by the phase control circuit 54 and output them as enable signals Enb2 to Enb4, respectively. It should be noted that the phase adjusters 541 to 544 delay the source signals E1 to E4 in a range from a half cycle to 1.5 cycles, respectively, so that the enable signals Enb1 to Enb4 are apparently ± 180 degrees with respect to the source signal. Adjust the phase within the range.
As will be described later, the phase control circuit 54 adjusts the degree of delay of the source signals E1 to E4 by the phase adjusters 541 to 544, respectively.

  Here, the electro-optical device 10 of the present embodiment has two operation modes: a display mode that is a normal display operation, and an adjustment mode for adjusting the phase of the enable signals Enb1 to Enb4. Among these, the adjustment mode has a property that it is executed, for example, before shipment from the factory, and does not have a property that shifts when designated by the user.

Next, the operation of the electro-optical device 10 of this embodiment will be described.
The present embodiment is characterized by the phase adjustment of the enable signals Enb1 to Enb4 in the adjustment mode. However, in order to understand why the phase adjustment is necessary, it is necessary to know the operation of the display mode. Therefore, in the display mode, the operation when the phase of the enable signals Enb1 to Enb4 is not adjusted and the troubles associated with the operation will be described, and then, by adjusting the phase of the enable signals Enb1 to Enb4 in the adjustment mode, It will be explained in the development of how it can be resolved.

First, the operation of the operation when the phase of the enable signals Enb1 to Enb4 is not adjusted in the display mode will be described.
4 is a timing chart showing vertical scanning of the electro-optical device 10 according to this embodiment, FIG. 5 is a timing chart showing horizontal scanning, FIG. 6 is a timing chart showing sampling, and FIG. These are figures which show the example of the voltage waveform of the data signal supplied over a continuous horizontal scanning period.

As described above, the scanning signals G1, G2, G3,..., G864 are sequentially exclusively exclusively H level for one horizontal effective period by the scanning line driving circuit 130 as shown in FIG.
Here, paying attention to the horizontal scanning period in which the scanning signal G1 is at the H level, the horizontal scanning period is divided into a horizontal blanking period and a subsequent horizontal effective display period. In the horizontal scanning period in which the scanning signal G1 is at the H level, writing is performed with positive polarity.
In the horizontal effective display period, the image data Vid supplied in synchronization with the horizontal scanning is first distributed to the six channels by the S / P conversion circuit 320 and expanded six times with respect to the time axis. Second, each signal is converted into an analog signal by the D / A converter circuit group 340. Third, the signal is output by the amplifier / inverter circuit 350 by rotating forward with reference to the voltage Vc corresponding to the positive polarity writing. The For this reason, the voltages of the data signals Vid1 to Vid6 by the amplifier / inverter circuit 350 become higher than the voltage Vc as the pixels are darkened (see FIG. 8).

On the other hand, in the horizontal scanning period in which the scanning signal G1 is at the H level, the transfer start pulse DX is sequentially shifted by the shift register 140 and output as signals F1, F2, F3,..., F96 as shown in FIG. The
Among these, when m is an odd number, the signal Fm branched to the left side is obtained by ANDing the enable signal Enb1 in the AND circuit 142, the pulse width is narrowed, and the sampling signal S (2m− On the other hand, the signal branched to the right side is output as 1), and the AND circuit 142 obtains the logical product with the enable signal Enb2, so that the pulse width is narrowed and output as the sampling signal S (2m).
Further, when m is an even number, the signal Fm branched to the left side is obtained by ANDing the enable signal Enb3 in the AND circuit 142, the pulse width is narrowed, and the sampling signal S (2m-1 ) Is output to the right side, and the AND circuit 142 obtains the logical product of the enable signal Enb4 and the pulse width is narrowed to be output as the sampling signal S (2m).
Here, the positive pulse widths of the enable signals Enb4 and Enb1 (the period when the clock signal CLX is at the H level) are included in the period when the clock signal CLX is at the H level, and the positive pulse widths of the enable signals Enb2 and Enb3 are the clock signal CLX. Are included in the period when the signal is at the L level, and the positive pulse widths are output so as not to overlap each other. Further, the signal F1 is output during a period in which the clock signal CLX first becomes H level and then L level after the transfer start pulse DX is supplied, and the phases of the enable signals Enb1 to Enb4 are shifted by 90 degrees. is doing. As a result, the sampling signals S1, S2, S3, S4,..., S192 are also sequentially output so that the positive pulse widths do not overlap as shown in FIG.

Here, in the horizontal scanning period in which the scanning signal G1 is at the H level, in the TFT 116 of the pixel 110 located in the scanning line 112 in the first row, the source and the drain are in a conductive (ON) state. On the other hand, when the sampling signal S1 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 in the first to sixth columns belonging to the block B1, respectively. Therefore, the sampled data signals Vid1 to Vid6 are pixels that intersect the first scanning line 112 counted from the top in FIG. 2 and the six (first to sixth columns counted from the left) data lines 114. The pixel electrodes 118 are applied respectively.
Thereafter, when the sampling signal S2 becomes H level, the data signals Vid1 to Vid6 are sampled on the data lines 114 in the seventh to twelfth columns belonging to the block B2, respectively, and these data signals Vid1 to Vid6 are This is applied to the pixel electrode 118 of the pixel that intersects the scanning line 112 in the first row and the data line 114 in the seventh to twelfth columns.

  In the same manner, when the sampling signals S3, S4,..., S192 sequentially become H level exclusively, the data signals Vid1 to Vid6 correspond to the six columns of data lines 114 belonging to the blocks B3, B4,. Are sampled, and these data signals Vid1 to Vid6 are respectively applied to the pixel electrodes 118 of the pixels intersecting the scanning lines 112 in the first row and the data lines 114 in the six columns. As a result, writing to all the pixels in the first row is completed. After that, even if the scanning signal G1 becomes L level and the TFT 116 is turned off, the written voltage is held by the liquid crystal capacitor or the storage capacitor 109.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In the present embodiment, as described above, since polarity inversion is performed in units of scanning lines, negative polarity writing is performed in this horizontal scanning period.
On the other hand, the image data Vid designates the blackening of the pixel in the horizontal blanking period, but since the positive writing was performed in the immediately preceding horizontal effective display period, the data signals Vid1 to Vid6 are as shown in FIG. At a substantially central timing of this horizontal blanking period, a negative electrode that, when applied to the pixel electrode 118, causes the pixel to have the lowest gradation black from the positive voltage Vb (+) that causes the pixel to have the lowest gradation black. Switched to the voltage Vb (-).
Note that the relationship between the voltages in FIG. 8 will be described. When the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118, the pixel is set to the highest gradation white and the intermediate gradation gray, respectively. Negative voltage. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the pixel electrode 118, cause the pixel to have the highest gradation white and the intermediate gradation gray, respectively. It is symmetrical with Vw (−) and Vg (−) when used as a reference.

  The operation in the horizontal scanning period in which the scanning signal G2 is at the H level is the same as the horizontal scanning period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed. However, since the horizontal scanning period in which the scanning signal G2 is at the H level is negative writing, the amplification / inversion circuit 350 applies the signal Vc distributed and expanded to 6 channels to the voltage Vc corresponding to the negative writing. Inverted with reference to output. For this reason, the voltage of the data signals Vid1 to Vid6 becomes lower than the voltage Vc as the pixels are darkened (see FIG. 8).

Similarly, the scanning signals G3, G4,..., G864 become H level, and writing is performed on the pixels in the third row, fourth row,. Thus, positive polarity writing is performed on the pixels in the odd-numbered rows, and negative polarity writing is performed on the pixels in the even-numbered rows. In this one vertical scanning period, the first to 864th rows are performed. Writing will be completed across all of the eye pixels.
Note that the data signals Vid1 to Vid6 are supplied from the voltage Vb (+) when shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing at substantially the center timing of the horizontal blanking period. When shifting from the horizontal effective display period for negative polarity writing to the horizontal effective display period for positive polarity writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal layer 105, and deterioration of the liquid crystal layer 105 is prevented.

By the way, in this embodiment, when expressed as the signal Fm output from the shift register 140, when m is an odd number, the signal Fm is divided by the enable signals Enb1 and Enb2, and when m is an even number, The signal Fm is divided by the enable signals Enb3 and Enb4 and output as sampling signals S (2m-1) and S (2m), respectively.
In such a configuration, if there is a difference in the transfer characteristics of the supply paths of the enable signals Enb1 to Enb4 in the FPC board that connects the processing circuit 50 and the display panel 100 or the display panel 100 itself, the output time point from the processing circuit 50 Then, even if the phase relationship is correct, a phase difference may occur when the input terminal of the AND circuit 142 is reached.
Here, when viewed at the input time of the AND circuit 142, for example, if only the enable signal Enb2 is delayed as compared with the other enable signals Enb1, Enb3, and Enb4, the sampling signals S2, S6, S10,. , Delayed compared to other sampling signals. FIG. 7 shows that the sampling signal S2 is delayed compared to S1 and S3.

  When the sampling signals S2, S6, S10,..., S190 are delayed in this way, for example, when the sampling signal S2 is delayed, as shown in FIG. 7, the seventh to twelfth columns of the block B2 corresponding to the sampling signal S2 In addition to not being able to correctly sample the data signal corresponding to the pixel of, a part of the data signal corresponding to the pixels in the 13th to 18th columns of the adjacent block B3 is sampled redundantly. For this reason, a part of the pixel components in the 13th to 18th columns of the same row appear in the pixels in the 7th to 12th columns in a certain row, and the display quality is deteriorated. In addition, although the block B2 was mentioned here, the same phenomenon appears also about the blocks B6, B10, ..., B190.

  Therefore, in the present embodiment, when the phases of the enable signals Enb1 to Enb4 are individually adjusted by the phase adjusters 541 to 544, and even when there is a difference in the transfer characteristics of the supply path, the time when the input terminal of the AND circuit 142 is reached Thus, the phase is correctly shifted 90 degrees.

Next, the operation in the adjustment mode for adjusting the phases of the enable signals Enb1 to Enb4 in the present embodiment will be described.
In the present embodiment, when the adjustment mode is set, the configuration shown in FIG. 9 is adopted. Specifically, an imaging camera 70 that images the screen of the display panel 100 is disposed, and an imaging signal of the imaging camera 70 is supplied to an adjustment instruction circuit 80 that performs image processing, and data Dm by the adjustment instruction circuit 80 is further processed. 50 phase control circuits 54 are supplied.
On the other hand, image data Vd for providing the following target display contents is supplied from the host device. That is, the pixels 110 in the column belonging to the blocks B1, B5, B9,..., B189 (the block corresponding to the sampling signal extracted by the enable signal Enb1) are set to “light gray”, and the blocks B2, B6, B10,. The pixels 110 in the column belonging to B190 (the block corresponding to the sampling signal extracted by the enable signal Enb2) are set to “slightly light gray”, and the blocks B3, B7, B11,..., B191 (extracted by the enable signal Enb3) The pixels 110 of the column belonging to the block corresponding to the sampling signal are set to “slightly dark gray”, and the column belonging to the block B4, B8, B12,..., B192 (the block corresponding to the sampling signal extracted by the enable signal Enb4). The pixel 110 is “dark gray” Image data Vd are supplied as.

When such image data Vd is supplied and the actual display panel 100 has the target display content, the relationship in which the phases of the enable signals Enb1 to Enb4 are correctly shifted by 90 degrees when the AND circuit 142 is input. It is thought that it is maintained. For this reason, the adjustment instruction circuit 80 does not give any instruction to the phase control circuit 54 as long as it is the display content.
On the other hand, when any of the enable signals Enb1 to Enb4 at the time of input of the AND circuit 142 is out of the above relationship, the brightness of the pixels in the column belonging to the block corresponding to the off enable signal (the sampling signal extracted by the enable signal) Approaches the brightness of the pixels in the column belonging to any of the adjacent blocks.
For example, when only the enable signal Enb2 tends to be delayed as described above, the pixels in the columns belonging to the blocks B2, B6, B10,..., B190 are transferred to the columns belonging to the blocks B3, B7, B11,. Since part of the data signal is sampled, the brightness is close to “slightly dark gray” rather than “slightly light gray”. On the other hand, when only the enable signal Enb2 has a tendency to advance, the pixels in the columns belonging to the blocks B2, B6, B10,..., B190 have the data signals to the columns belonging to the blocks B1, B5, B9,. Since it is sampled partly, the brightness is close to “light gray” rather than “slightly light gray”.
Further, for example, when only the enable signal Enb1 tends to be delayed, the pixels in the columns belonging to the blocks B1, B5, B9,..., B189 have the data signals to the columns belonging to the blocks B2, B6, B10,. Since it is partly sampled, the brightness is close to “slightly light gray” rather than “light gray”. On the other hand, when only the enable signal Enb1 tends to advance, the data signals to the columns belonging to the blocks B4, B8,..., B188 are partially sampled in the pixels belonging to the blocks B5, B9,. Therefore, the brightness is close to “dark gray” instead of “light gray”. In this case, there is no pixel before the block B1, but since the data signal is a voltage corresponding to “black” in the blanking period, the pixels in the column belonging to the block B1 are close to “black”. Become.

In this way, the adjustment instruction circuit 80 can know whether the enable signal Enb2 is in the late phase or the advanced phase by performing image processing on the screen of the display panel 100. If the enable signal Enb2 is late, the adjustment instruction circuit 80 supplies the phase control circuit 54 with data Dm that instructs the phase control circuit 54 to advance the phase of the enable signal Enb2. Thereby, the phase control circuit 54 controls the delay by the phase adjuster 542 and actually advances the phase of the enable signal Enb2. If the target display content is obtained as a result of the phase adjustment, the phase adjustment operation is terminated. It will be easily understood that such phase adjustment is the same even in the case of the enable signals Enb 3 and 4.
When the phase adjustment operation ends, the adjustment mode ends, and thereafter, the display mode is fixed. Such phase adjustment may be performed manually by an operator in addition to image analysis by the adjustment instruction circuit 80.

  Thus, according to the present embodiment, when the shift signal from the shift register 140 is extracted by the plurality of enable signals Enb1 to Enb4 and output as sampling signals, the phase of the enable signals Enb1 to Enb4 at the input time of the AND circuit 142 Can be adjusted to shift 90 degrees correctly. For this reason, it becomes possible to suppress the deterioration of the display quality due to the collapse of the phase relationship between the enable signals Enb1 to Enb4.

  The embodiment has been described by focusing on the phase of the enable signals Enb1 to Enb4. For example, not only the phase but also the pulse height (voltage), the pulse width, and the waveform response time (the pulse is changed from L level to H level or H level). Or the combination thereof may be individually adjusted. That is, in the present invention, it is only necessary that the response characteristics of the plurality of enable signals can be individually adjusted. As a specific example for changing the waveform response time, the output resistance value of the enable signal input to the panel is changed, or a capacitor is added between the wiring for supplying the enable signal and GND, and the capacitance value of the capacitor is changed. A method of changing according to the series of enable signals is suitable.

  In the embodiment, the vertical scanning direction is the downward direction of G1 → G864 and the horizontal scanning direction is the right direction of S1 → S192. However, in the case of a projector or a rotatable display device described later, scanning is performed. It is necessary to reverse the direction.

Further, if the supply method of the image data Vd is changed, the selection order of the scanning lines is not necessarily the order of the first, second, third,..., 864th row, for example, 1, 3, 5,. 2, 4, 6,..., 864, or may be scanned in an interlaced manner, or 1, 433, 2, 434, 3, 435,. The areas may be alternately selected and each area may be scanned sequentially from the top. That is, after a certain scanning line is selected, it is only necessary that another scanning line is selected and all the scanning lines are selected as a result in a certain unit period (vertical scanning period).
In the embodiment, since the positive polarity writing is performed in one vertical scanning period and the negative polarity writing is performed in the next one vertical scanning period, the AC driving cycle is two vertical scanning periods. Of course, the AC drive may be performed periodically.

  In the embodiment described above, the phase expansion drive method is adopted in which the six data lines 114 are blocked and converted into six channels of image data Vd1d to Vd6d. However, the number of channels and the number of data lines applied simultaneously (that is, the number of data lines applied simultaneously) The number of data lines belonging to one block) is not limited to “6”. Further, if it is limited to the first correction process, dot sequential driving may be used.

  On the other hand, in the above-described embodiment, the data signal supply circuit 300 processes the digital image data Vd. However, the data signal supply circuit 300 may be configured to process an analog image signal. Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the common electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good.

In the above-described embodiment, the TN type is used as the liquid crystal. However, a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type or a ferroelectric type, a polymer dispersed type, or a molecular length A dye (guest) having anisotropy in the absorption of visible light in the axial direction and the minor axis direction is dissolved in a liquid crystal (host) having a certain molecular arrangement, and the dye molecule is arranged in parallel with the liquid crystal molecule (GH) A guest-host type liquid crystal may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
Furthermore, the present invention is not limited to a liquid crystal device, and can be applied to all configurations in which the output of a shift register is narrowed by a plurality of enable signals and extracted as a sampling signal.

  Next, as an example of an electronic apparatus using the electro-optical device according to the above-described embodiment, a projector using the above-described display panel 100 as a light valve will be described. FIG. 10 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors. Therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 100 in the above-described embodiment, and images corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 10). Each is driven by a signal. In other words, the projector 2100 has a configuration in which three sets of electro-optical devices including the display panel 100 are provided corresponding to the R, G, and B colors.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmitted image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The image is reversed in the horizontal scanning direction by the light valve 100G and displayed in an inverted image.

  In addition to the electronic device described with reference to FIG. 10, the electronic device includes a television, a viewfinder type / monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel. Needless to say, the display panel according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. 3 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel of the display panel. FIG. 6 is a diagram for explaining a vertical scanning operation of the electro-optical device. It is a figure for demonstrating operation | movement of the horizontal scanning of the same electro-optical apparatus. It is a figure for demonstrating the sampling in the same electro-optical apparatus. It is a figure for demonstrating the malfunction of sampling. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the structure in the case of becoming adjustment mode in the same electro-optical device. FIG. 2 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 50 ... Processing circuit, 52 ... Scanning control circuit,
54 ... Phase control circuit, 100 ... Display panel, 112 ... Scanning line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 130 ... Scanning line drive circuit, 140 ... Shift register, 151 ... Sampling switch, 171 ... Image Signal lines, 300 ... data signal supply circuit, 2100 ... projector

Claims (4)

A pixel that is provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of data lines, and has a gradation corresponding to a data signal supplied to the data lines when the scanning line is selected;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A shift register that sequentially transfers a predetermined pulse signal according to a predetermined clock signal when the scanning line is selected;
A circuit for outputting sampling signals whose pulse widths do not overlap each other based on the sequentially transferred pulse signals and a predetermined plurality of series enable signals;
A sampling switch for sampling the data signal supplied to the image signal line on the data line according to the sampling signal;
A processing circuit that supplies the plurality of enable signals in synchronization with the clock signal, the processing circuit being capable of individually adjusting response characteristics of the plurality of enable signals for each series. Electro-optic device. 2. The electro-optical device according to claim 1, wherein the response characteristic of the enable signal is any one of a phase, a pulse width, a pulse height and a waveform response time of the enable signal, or a combination thereof. The electro-optical device according to claim 1, wherein the processing circuit supplies a data signal to the image signal line in synchronization with the clock signal.   An electronic apparatus comprising the electro-optical device according to claim 1.

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