JP2009186715A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise image display quality by equalizing display luminance without increasing unnaturalness in a display image. <P>SOLUTION: The plasma display device has a loading correction part 70 having a lighting pixel number calculation part 60 which calculates the number of pixels to be lit among pixels formed on a pair of display electrodes for each pair of display electrodes and for each subfield, a load value calculation part 61 which calculates a load value for each pixel based on a calculation result in the lighting pixel number calculation part 60, a correction gain calculation part 62 which calculates a correction gain for each pixel based on a calculation result in the load value calculation part 61, a correction value calculation part 63 which calculates a correction value which changes based on the correction gain, a switching part 67 which selects and outputs either of a value obtained by subtracting the correction value from the correction gain or a value obtained by adding the correction value to the correction gain at random, and a correction part 69 which subtracts a result by multiplying output from the switching part 67 by an input image signal from the input image signal to be output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. During the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent addressing operation are formed on each electrode, and priming particles (excited particles for generating addressing discharge) for stably generating the address discharge. ).

  In the address period, a scan pulse voltage is applied to the scan electrode and an address pulse voltage is selectively applied to the data electrode to selectively generate an address discharge in a discharge cell to be displayed to form a wall charge (hereinafter referred to as a wall charge). This operation is also referred to as “writing”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

  In recent years, further improvement in display quality in a plasma display device has been demanded as the panel has a larger screen and higher definition. However, in the panel, if the driving impedance is different for each scanning electrode even though the image signal having the same luminance is input, a difference in the amount of voltage drop of the driving voltage occurs, and the difference occurs in the emission luminance. There was a problem that the image quality of the image deteriorated.

Therefore, when an image signal having the same luminance is input to an arbitrary pixel on the panel for display, lighting of the subfield within one field is performed when the drive impedance of the display electrode pair including the pixel changes. A technique for changing a pattern is disclosed (for example, see Patent Document 2).
JP 2000-242224 A JP 2006-184843 A

  On the other hand, the driving impedance of the panel tends to increase with the increase in the screen size and the definition of the panel. As drive impedance increases, the difference in drive impedance due to changes in the lighting rate (the proportion of discharge cells to be lit) increases, and the amount of fluctuation in waveform distortion such as ringing generated in the drive waveform generated from the panel drive circuit increases. It becomes easy to become. For this reason, the difference in discharge intensity generated between the discharge cell on the display electrode pair having a large driving impedance and the discharge cell on the display electrode pair having a low driving impedance is enlarged, and occurs regardless of the same gradation value. The difference in emission luminance may be further increased. Such a difference in light emission luminance is one factor that greatly deteriorates the image display quality.

  Further, in the technique disclosed in Patent Document 2, when the correction gain is increased in order to reduce the difference in enlarged light emission luminance, processing generally used for improving the panel image display quality such as error diffusion, for example. When the image signal is applied to the image signal, there is a problem that the noise feeling of the display image appears to increase, which increases the unnaturalness in the display image.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a plasma display device in which display luminance is made uniform and image display quality is improved without increasing unnaturalness in a display image. .

  A plasma display apparatus according to the present invention includes a panel including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period within one field period. A plurality of image signal processing circuits for converting input image signals into image data indicating light emission / non-light emission for each subfield in the discharge cell, and the image signal processing circuit is a pixel formed on the display electrode pair. A lighting pixel number calculating unit for calculating the number of pixels to be lit for each display electrode pair and for each subfield, a load value calculating unit for calculating a load value for each pixel based on a calculation result in the lighting pixel number calculating unit, and a load A correction gain calculation unit that calculates a correction gain for each pixel based on a calculation result in the value calculation unit, and a correction gain calculated in the correction gain calculation unit. A correction value calculating unit that calculates a correction value that changes based on the correction gain, a value obtained by subtracting the correction value calculated by the correction value calculating unit from the correction gain calculated by the correction gain calculating unit, and a value calculated by the correction gain calculating unit A switching unit that randomly selects and outputs one of the correction gain and the value obtained by adding the correction value calculated by the correction value calculation unit, and the result obtained by multiplying the output from the switching unit by the input image signal. And a correction unit that subtracts and outputs the signal.

  As a result, the display luminance can be made uniform without increasing unnaturalness in the display image, the occurrence of the loading phenomenon can be suppressed, and the image display quality in the plasma display device can be improved.

  Further, in this plasma display device, the load value calculation unit and the correction gain calculation unit have the lighting state in each subfield of each pixel set to 1 for lighting and 0 for non-lighting, and the result calculated by the lighting pixel number calculation unit. The luminance weight set for each subfield is multiplied by the lighting state of the pixel for calculating the correction gain, and the sum is calculated as a load value. The number of pixels formed on the display electrode pair is calculated for each subfield. Multiplying the luminance weight set to the lighting state in the pixel for calculating the correction gain and calculating the sum as the maximum load value, subtracting the load value from the maximum load value and dividing the subtraction result by the maximum load value Thus, the correction gain is calculated. As a result, it is possible to accurately calculate the correction gain corresponding to the increase in light emission luminance expected by the loading phenomenon.

  According to the present invention, it is possible to provide a plasma display device in which display luminance is made uniform and image display quality is improved without increasing unnaturalness in a display image.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by barrier ribs 34, and discharge cells are formed at portions where display electrode pairs 24 and data electrodes 32 intersect. These discharge cells discharge and emit light to display an image. One pixel is composed of three discharge cells that emit light of R, G, and B colors.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 81). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance that is the luminance of the black display area that does not generate the sustain discharge is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows a driving voltage waveform of two subfields, that is, a first subfield (first SF) of a subfield performing an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”), A second subfield (second SF) of a subfield (hereinafter referred to as “selective initialization subfield”) for performing a selective initialization operation is shown, but the drive voltage waveforms in the other subfields are substantially the same. is there. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm and sustain electrode SU1 to sustain electrode SUn, respectively, and sustain electrode SU1 to sustain is applied to scan electrode SC1 to scan electrode SCn. A ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gently rises from voltage Vi1 that is equal to or lower than the discharge start voltage to voltage Vi2 that exceeds the discharge start voltage is applied to electrode SUn.

  In the present embodiment, this up-ramp waveform voltage is generated with a slope of about 1.3 V / μsec.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. , A ramp waveform voltage that gradually falls from voltage Vi3 that is equal to or lower than the discharge start voltage to sustain voltage SUn with respect to sustain electrode SU1 to voltage Vi4 that exceeds the discharge start voltage (hereinafter referred to as “down-ramp waveform voltage”). Is applied. During this time, weak initializing discharges are continuously generated between scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm, respectively, and voltage that is equal to or less than the discharge start voltage (for example, 0) is applied to scan electrode SC1 through scan electrode SCn. (V)) is applied to the ramp-down waveform voltage that gradually falls toward the voltage Vi4. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, a scan pulse voltage is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = 1) corresponding to a discharge cell to emit light is applied to data electrode D1 through data electrode Dm. To m), a positive address pulse voltage Vd is applied to selectively generate an address discharge in each discharge cell.

  In the address period, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and the ground potential serving as the base potential, that is, 0 (V), is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are applied alternately to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and a potential difference is given between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, the ramp waveform voltage gradually increases (for example, with a gradient of about 10 V / μsec) from 0 (V), which is the base potential, to voltage Vers at scan electrode SC1 through scan electrode SCn. (Hereinafter referred to as “erasing ramp waveform voltage”). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains. The last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield in the discharge cell.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks.

  Scan electrode drive circuit 43 includes an initialization waveform generation circuit (not shown) for generating an initialization waveform voltage to be applied to scan electrode SC1 through scan electrode SCn in the initialization period, and scan electrode SC1 through scan electrode in the sustain period. A sustain pulse generation circuit (not shown) for generating a sustain pulse to be applied to SCn, a scan pulse having a plurality of scan ICs and generating a scan pulse voltage to be applied to scan electrode SC1 to scan electrode SCn in the address period A generation circuit (not shown) is included. Then, each scan electrode SC1 to scan electrode SCn is driven based on the timing signal.

  The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm based on the timing signal.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit (not shown) and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal. To do.

  Next, a difference in light emission luminance caused by a change in driving load will be described.

  FIG. 5 is a schematic diagram for explaining a difference in light emission luminance caused by a change in driving load. FIG. 5A shows an image generally called a “window pattern”. The region B and the region D shown in the drawing are regions having the same luminance gradation value (for example, 20%), and the region C is an region having a luminance gradation value lower than that of the region B and the region D (for example, 5%). (Hereinafter, the luminance gradation value is also simply referred to as “gradation value”).

  FIG. 5B schematically shows a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10. In FIG. 5B, the display electrode pairs 24 are arranged to extend in the row direction (lateral direction in the drawing) in the same manner as the panel 10 shown in FIG. FIG. 5C shows the gradation value of the luminance of the image signal along the line AA in FIG. 5B, and FIG. 5D shows the A-value in FIG. The light emission luminance of the display image at line A is shown.

  As shown in FIG. 5B, FIG. 5C, and FIG. 5D, when the “window pattern” is displayed on the panel 10, the region B and the region D have the same gradation value. There may be a difference in light emission luminance. This is considered to be due to the following reasons.

  Since the display electrode pairs 24 are arranged extending in the row direction (lateral direction in the drawing), when the “window pattern” as shown in FIG. 24 and the display electrode pair 24 passing through the region C and the region D are generated. In addition, the display electrode pair passing through the region C and the region D has a smaller driving load than the display electrode pair passing through the region B. This is because the gradation value of the region C is low, and accordingly, the discharge current flowing through the display electrode pair passing through the region C and the region D is less than the discharge current flowing through the display electrode pair passing through the region B. Because. Therefore, in the display electrode pair passing through the region C and the region D, the voltage drop of the drive waveform, for example, the sustain pulse voltage is smaller than that in the display electrode pair passing through the region B. That is, the voltage drop of the sustain pulse voltage is smaller in the display electrode pair passing through the region C and the region D than in the display electrode pair passing through the region B, and the region is more than the sustain discharge in the discharge cells included in the region B. It is considered that the sustain discharge in the discharge cells included in D has a higher discharge intensity. As a result, it is considered that the light emission luminance of the region D is higher than that of the region B despite the same gradation value. Hereinafter, such a phenomenon is referred to as “loading”.

  FIG. 6 is a diagram for schematically explaining the loading phenomenon. FIGS. 6A to 6D are diagrams showing the region C having a low gradation value (for example, 5%) in the “window pattern”. It is the figure which showed roughly the display image when changing an area gradually and displaying on the panel. Note that the region D1 in FIG. 6A, the region D2 in FIG. 6B, the region D3 in FIG. 6C, and the region D4 in FIG. 20%).

  Then, as shown in FIGS. 6A to 6D, as the area of the region C1, the region C2, the region C3, the region C4, and the region C increases, the display electrode pair passing through the region C and the region D As a result, the driving load decreases, and as a result, the discharge intensity of the discharge cells included in the region D increases, and the emission luminance of the region D gradually increases to the region D1, the region D2, the region D3, and the region D4. As described above, the increase in light emission luminance due to the loading phenomenon is not uniform, but varies depending on the fluctuation of the driving load. In the present embodiment, this loading phenomenon is reduced, and the image display quality in the plasma display device 1 is improved. Note that processing performed to reduce the loading phenomenon is hereinafter referred to as “loading correction”.

  FIG. 7 is a schematic diagram for explaining the outline of the loading correction in the embodiment of the present invention. FIG. 7A schematically shows a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10 after performing the loading correction in the present embodiment. It is. FIG. 7B shows the luminance gradation value of the image signal along the line AA in FIG. 7A, and FIG. 7C shows the loading correction in this embodiment. FIG. 7 (d) shows the luminance gradation value of the display image on the AA line of FIG. 7 (a), showing the gradation value of the luminance on the AA line of the image signal after application. Is.

  In the present embodiment, for each pixel, a correction value based on the driving load of the display electrode pair passing through that pixel is calculated, the image signal is corrected, and the luminance gradation value is corrected. For example, as shown in FIG. 7B, the region B and the region D have the same gradation value, but since the display electrode pair passing through the region D also passes through the region C, it is determined that the driving load is small. As shown in (c), loading correction is performed by correcting the gradation value. Accordingly, as shown in FIG. 7D, the loading phenomenon is reduced by combining the emission luminances of the region B and the region C in the display image.

  This loading correction in the present embodiment will be described in detail.

  FIG. 8 is a circuit block diagram of the image signal processing circuit 41 according to the embodiment of the present invention. FIG. 8 shows blocks related to loading correction in the present embodiment, and other circuit blocks are omitted.

  The image signal processing circuit 41 includes a lighting pixel number calculation unit 60, a load value calculation unit 61, a correction gain calculation unit 62, a correction value calculation unit 63, a subtractor 64, an adder 65, and a random number generation unit 66. A loading correction unit 70 including a switching unit 67, a multiplier 68, and a correction unit 69.

  The lighting pixel number calculation unit 60 calculates the number of pixels to be lit among the pixels formed on one display electrode pair for each display electrode pair and for each subfield. The load value calculation unit 61 receives a calculation result from the lighting pixel number calculation unit 60 and performs an operation based on the driving load calculation method in the present embodiment (in this embodiment, “load value” and “maximum load value” described later). Calculation). The correction gain calculation unit 62 calculates the correction gain based on the calculation result in the load value calculation unit 61. The correction value calculation unit 63 calculates a correction value to be added to the correction gain based on the calculation result in the correction gain calculation unit 62. In this embodiment, the correction value is changed based on the correction gain. The details of the calculation of the correction gain and the correction value added to the correction gain in the lighting pixel number calculation unit 60, the correction gain calculation unit 62, and the correction value calculation unit 63 will be described later. The subtracter 64 subtracts the correction value calculated by the correction value calculation unit 63 from the correction gain calculated by the correction gain calculation unit 62. The adder 65 adds the correction value calculated by the correction value calculation unit 63 to the correction gain calculated by the correction gain calculation unit 62. The switching unit 67 selects and outputs either the output from the subtractor 64 or the output from the adder 65 based on the output from the random number generation unit 66 that randomly generates “0” or “1”. . The multiplier 68 multiplies the image signal by the correction value output from the switching unit 67 and outputs it as a correction signal. Then, the correction unit 69 subtracts the correction signal output from the multiplier 68 from the image signal and outputs it as a corrected image signal.

  Subsequently, calculation of the correction gain in the present embodiment will be described. In the present embodiment, in order to calculate the correction gain, two parameters called “load value” and “maximum load value” are calculated based on the calculation result in the lighting pixel number calculation unit 60. The “load value” and “maximum load value” are numerical values used to estimate the amount of occurrence of the loading phenomenon in the target pixel. Here, the “load value” in the present embodiment will be described first with reference to FIG. 9, and then the “maximum load value” in the present embodiment will be described with reference to FIG. The calculation of the correction gain based on the “load value” and the “maximum load value” will be described.

  FIG. 9 is a schematic diagram for explaining a “load value” calculation method according to an embodiment of the present invention. FIG. 9A schematically shows a display image when the “window pattern” shown in FIG. 5A is displayed on the panel 10. FIG. 9B is a schematic diagram showing lighting / non-lighting of each pixel in the AA line of FIG. 9A for each subfield, where “1” is lighted and the blank is not lighted. Represents. FIG. 9C is a diagram schematically showing a “load value” calculation method in the present embodiment. Here, in order to simplify the description, it is assumed that the number of pixels in the row direction is 15. Therefore, the following description will be made assuming that 15 pixels are arranged on the AA line in FIG. 9A, but in actuality, the number of pixels of the panel 10 (for example, 1024 or 1920) is adjusted. The following operations are performed.

  The lighting state in each subfield of 15 pixels arranged on the AA line in FIG. 9A is, for example, the state shown in FIG. 9B, that is, the region C in FIG. 9A. In the central five pixels included in the first to third SFs from the first SF to the third SF, the fourth SF to the tenth SF are not lit. In the left and right five pixels not included in the region C, the first SF to the eighth SF The 9th SF and the 10th SF are not lit up.

  When the 15 pixels arranged on the AA line are in such a lighting state, for example, the “load value” in one pixel B is obtained as follows.

  First, the number of lighting pixels for each subfield is calculated. Since all 15 pixels on the line AA are lit from the first SF to the third SF, the number of lit pixels from the first SF to the third SF is “15” as shown in FIG. 9C. Further, since 10 pixels among 15 pixels on the AA line are lit from the 4th SF to the 8th SF, the number of lit pixels from the 4th SF to the 8th SF is as shown in FIG. 9C. Becomes “10”. In the ninth SF and the tenth SF, since all 15 pixels on the line AA are not lit, the number of lit pixels in the ninth SF and the tenth SF is “0” as shown in FIG. 9C. Next, the luminance weight of each subfield (for example, 1, 2, 3, 6, 11, 18, 30, 44, 60, in order from the first SF) is added to the number of lighting pixels of each subfield thus obtained. 81) and the lighting state of each subfield in the pixel B (here, lighting is 1 and non-lighting is 0. Therefore, the lighting state in the pixel B is 1, 1, 1, 1, 1 in order from the first SF). 1, 1, 1, 0, 0). The calculated value of the result is (15, 30, 45, 60, 110, 180, 300, 440, 0, 0) in order from the first SF. Then, the sum of the calculated values is obtained (here, 1180). This sum is a “load value” in the pixel B. In this embodiment, the “load value” is obtained for each pixel in this way.

  FIG. 10 is a schematic diagram for explaining a “maximum load value” calculation method according to the embodiment of the present invention. FIG. 10A is the same drawing as FIG. FIG. 10B schematically shows lighting / non-lighting for each subfield when the lighting state of the pixel B is applied to all the pixels on the line AA in order to calculate the “maximum load value”. FIG. FIG. 10C is a diagram schematically showing a “maximum load value” calculation method in the present embodiment.

  In the present embodiment, the “maximum load value” is calculated as follows. For example, when calculating the “maximum load value” in the pixel B, it is assumed that all the pixels on the line AA are lit in the same state as the pixel B as shown in FIG. The number of lighting pixels for each subfield is calculated. Since the lighting state of each subfield in the pixel B is (1, 1, 1, 1, 1, 1, 1, 1, 0, 0) in order from the first SF, the number of lighting pixels is shown in FIG. (15, 15, 15, 15, 15, 15, 15, 15, 0, 0) in order from the first SF. Next, the luminance weight of each subfield (for example, 1, 2, 3, 6, 11, 18, 30, 44, 60, in order from the first SF) is added to the number of lighting pixels of each subfield thus obtained. 81) and the lighting state of each subfield in pixel B (here, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0) in order from the first SF. The calculated value of the result is (15, 30, 45, 90, 165, 270, 450, 660, 0, 0) in order from the first SF. Then, the sum of the calculated values is obtained (here, 1725), and this sum becomes the “maximum load value” in the pixel B. In this embodiment, the “maximum load value” is obtained for each pixel in this way.

  Note that the “maximum load value” in the pixel B is the number of pixels formed on the display electrode pair 24 (here, 15) by the luminance weight of each subfield (for example, 1, 2, 3 in order from the first SF). , 6, 11, 18, 30, 44, 60, 81), and the multiplication result and the lighting state of each subfield in pixel B (here, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0) and the calculated values (here, 15, 30, 45, 90, 165, 270, 450, 660, 0, 0 in order from the first SF) The sum may be calculated and calculated. Even with such a calculation method, a calculation result similar to that described above (here, 1725) can be obtained.

In this embodiment, the correction gain is calculated by substituting the calculated “load value” and “maximum load value” into the following equation (maximum load value−load value) / maximum load value. For example, (1725-1180) /1725=0.315 is calculated from “load value” = 1180 and “maximum load value” = 1725 in the pixel B described above. The above is the calculation method of the correction gain in the present embodiment. Then, a correction gain is calculated for each pixel.

  FIG. 11 is a schematic diagram illustrating another calculation result of the “load value” according to the embodiment of the present invention. FIG. 11A displays on the panel 10 a “window pattern” in which the area of the region C having a low gradation value (for example, 5%) is larger than the “window pattern” shown in FIG. The display image at the time is schematically shown.

  For example, when the “load value” of the pixel B shown in FIG. 11A is calculated based on the above-described calculation method, it becomes “853” as shown in FIG. That is, the correction gain of the pixel B shown in FIG. 11 is (1725−853) /1725=0.506, which is larger than the correction gain 0.315 of the pixel B shown in FIG.

  In the case of no correction, as shown in FIG. 6, the emission luminance of the pixel B in the display image is larger in the “window pattern” shown in FIG. 11 than in the “window pattern” shown in FIG. Expected. In the correction gain calculation method according to the present embodiment, as described above, the “load value” and the “maximum load value” are calculated, and the correction gain is calculated based on the calculation result. It is possible to accurately calculate a correction gain corresponding to the increase in.

In the present embodiment, loading correction is performed by applying correction based on the correction gain thus obtained to the input image signal. At this time,
Even if the output image signal is calculated only by the calculation formula of output image signal = input image signal−input image signal × correction gain, the effect of reducing the loading phenomenon can be obtained.

  However, if the loading correction is performed based only on this calculation formula, the gradation value change point (the pattern of the display image) is applied when image processing called error diffusion, which is generally used to improve image display quality, is performed. It has been confirmed that there is a problem that the amount of error diffused at the boundary) increases, and the boundary is emphasized at the boundary portion where the luminance change is large and looks unnatural.

  Therefore, in this embodiment, in order to reduce such unnaturalness at the boundary between symbols, the correction gain is randomly added to or subtracted from the calculated correction gain to randomly change the correction gain. And Specifically, as shown in FIG. 8, the subtractor 64 subtracts the correction value from the correction gain, and the adder 65 adds the correction value to the correction gain. Then, the switching unit 67 selects either the output from the subtractor 64 or the output from the adder 65 based on the output from the random number generation unit 66 that randomly generates “0” or “1”. Output. By performing such processing, it is possible to alleviate the problem that, when error diffusion is performed, the boundary between symbols is emphasized and looks unnatural.

  On the other hand, when the correction value to be added to the correction gain is set to a constant value, it is confirmed that the amount of noise in the display image increases (hereinafter, such apparent noise amount is referred to as “noise feeling”). It was. The present inventor has found that such a feeling of noise can be reduced by changing the magnitude of the correction value in accordance with the magnitude of the correction gain. Therefore, in the present embodiment, the correction value is generated while changing the magnitude of the correction value in accordance with the magnitude of the correction gain, thereby reducing the sense of noise in the display image.

  FIG. 12 is a characteristic diagram showing the relationship between the correction gain and the correction value in one embodiment of the present invention. In FIG. 12, the horizontal axis represents the correction gain, and the vertical axis represents the correction value.

  In the present embodiment, as shown in FIG. 12, when the correction gain is 0, the correction value is 0, when the correction gain is 0.75, the correction value is 0.2, and from the correction gain 0 to the correction gain. The correction value is linearly changed until 0.75, and the correction value is generated by fixing the correction value to 0.2 when the correction gain is 0.75 or more.

  Then, by changing the magnitude of the correction value according to the magnitude of the correction gain as shown in FIG. 12, the noise feeling of the display image is reduced compared to the case where the correction value is set to a constant value, and more natural. It was confirmed that image display is possible. Note that the numerical values shown in FIG. 12 are merely examples, and the present embodiment is not limited to these numerical values. The change of the correction value according to the magnitude of the correction gain may be optimally set according to the panel characteristics, subfield configuration, error diffusion setting, target image quality, and the like.

  As described above, according to the present embodiment, the “load value” and the “maximum load value” are calculated for each pixel to calculate the correction gain, and the correction value is set according to the magnitude of the correction gain. Even if the image processing such as error diffusion is performed, the boundary of the symbol is emphasized by generating and correcting the input image signal by randomly adding or subtracting the correction value to or from the correction gain. It is possible to make the display brightness uniform and reduce the loading phenomenon without increasing unnaturalness in the display image such as an increase in noise and a sense of noise, and it is possible to improve the image display quality in the plasma display device 1.

  In addition, although FIG. 12 demonstrated the structure which changes a correction value linearly according to a correction gain, this invention is not limited to this structure at all. FIG. 13 is a characteristic diagram showing another example of the relationship between the correction gain and the correction value according to the embodiment of the present invention. For example, as shown in FIG. 13, the correction value may change stepwise according to the correction gain. Even with such a configuration, it was confirmed that the same effects as those described above can be obtained.

  In FIGS. 6A to 6D, the example in which the light emission luminance is changed due to the fluctuation of the driving load has been described. However, depending on the panel characteristics, the light emission luminance is not necessarily linearly changed when the loading phenomenon occurs. Some do not. FIG. 14 is a diagram showing an example of the relationship between the area C of the region C and the light emission luminance of the region D in the “window pattern” shown in FIG. 6. When the area C of the region C increases depending on the panel, FIG. When the driving load of the display electrode pair is reduced (for example, C4 in the drawing), the loading phenomenon may be extremely deteriorated, and the emission luminance in the region D may be greatly increased (for example, D4 in the drawing). A configuration may be adopted in which the correction gain is weighted according to the characteristics of the panel and the correction gain is changed nonlinearly. FIG. 15 is a characteristic diagram showing an example of nonlinear processing of correction gain according to an embodiment of the present invention. For example, a plurality of correction gains set in accordance with the characteristics of the panel 10 are stored in a lookup table in advance. If the correction gain is read from the lookup table based on the calculation result of the correction gain, the correction gain can be set nonlinearly as shown in FIG.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of a panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method, and the same effect as described above can be obtained.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other. , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,... ”Is also effective in a panel having an electrode structure (hereinafter referred to as“ ABBA electrode structure ”).

  It should be noted that the specific numerical values shown in the present embodiment are set based on the characteristics of a 42-inch panel having 1080 display electrode pairs, and are merely examples of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma display device because the display luminance can be made uniform and the image display quality can be improved without increasing unnaturalness in the display image.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention Schematic for explaining the difference in light emission luminance caused by changes in driving load Diagram for schematically explaining the loading phenomenon Schematic for explaining the outline of loading correction in one embodiment of the present invention 1 is a circuit block diagram of an image signal processing circuit according to an embodiment of the present invention. Schematic for explaining a method of calculating “load value” in an embodiment of the present invention Schematic for explaining a method of calculating a “maximum load value” in an embodiment of the present invention Schematic explaining another calculation result of “load value” in one embodiment of the present invention The characteristic view which shows the relationship between the correction gain and correction value in one embodiment of this invention The characteristic view which shows another example of the relationship between the correction gain and correction value in one embodiment of this invention The figure which showed an example of the relationship between the area of the area | region C in a window pattern, and the light emission luminance of the area | region D The characteristic view which shows an example of the nonlinear process of the correction | amendment gain in one embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 60 lighting pixel number calculation unit 61 load value calculation unit 62 correction gain calculation unit 63 correction value calculation unit 64 subtractor 65 adder 66 random number generation unit 67 Switching unit 68 Multiplier 69 Correction unit 70 Loading correction unit

Claims (2)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
An image signal processing circuit in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field period, and an input image signal is converted into image data indicating light emission / non-light emission for each subfield in the discharge cell. And
The image signal processing circuit includes:
A lighting pixel number calculation unit that calculates the number of pixels to be lit among the pixels formed on the display electrode pair for each display electrode pair and for each subfield;
A load value calculation unit that calculates a load value for each pixel based on a calculation result in the lighting pixel number calculation unit;
A correction gain calculation unit that calculates a correction gain for each pixel based on a calculation result in the load value calculation unit;
A correction value calculation unit that calculates a correction value that changes based on the correction gain calculated in the correction gain calculation unit;
In the correction value calculation unit, a value obtained by subtracting the correction value calculated in the correction value calculation unit from the correction gain calculated in the correction gain calculation unit and the correction gain calculated in the correction gain calculation unit. A switching unit that randomly selects and outputs one of the calculated correction values and a value added thereto;
A plasma display device, comprising: a correction unit that subtracts a result obtained by multiplying the output from the switching unit and the input image signal from the input image signal and outputs the result. The load value calculator and the correction gain calculator are
The lighting state in each subfield of each pixel is 1 for lighting and 0 for non-lighting.
Multiplying the result calculated in the lighting pixel number calculation unit, the luminance weight set for each subfield, and the lighting state in the pixel for calculating the correction gain, and calculating the sum as a load value; and Multiplying the number of pixels formed on the display electrode pair, the luminance weight set for each subfield and the lighting state in the pixel for calculating the correction gain, and calculating the sum as a maximum load value, The plasma display apparatus according to claim 1, wherein the correction gain is calculated by subtracting the load value from a maximum load value and dividing the subtraction result by the maximum load value.

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