JP2009151752A - Bus switch, electronic equipment and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus switch, electronic equipment and a data transfer method, capable of easily improving data transfer performance of a serial transfer interface. <P>SOLUTION: This bus switch 107 of the serial transfer interface is provided between a memory control means 103 and a plurality of processing control means 104 and 106, and has first data transmitting-receiving means 202 and 203 for controlling data transmitting-receiving with the processing control means 104 and 106, a second data transmitting-receiving means 201 for controlling data transmitting-receiving with the memory control means 103, and a switching means for switching the connection between the first data transmitting-receiving means 202 and 203 and the second data transmitting-receiving means 201. The first data transmitting-receiving means 202 and 203 have buffers 204 and 205 of capacity not less than an amount of data transferrable with a memory 102 in one instruction from the processing control means 104 and 106. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bus switch, an electronic device, and a data transfer method, and more particularly, to a bus switch of a serial transfer interface, an electronic device having the bus switch, and a data transfer method in the bus switch.

  For example, some copiers, printers, personal computers (PCs), and the like as examples of electronic devices use a serial transfer interface instead of the PCI bus. For example, an example of a serial transfer interface is PCIe (PCI Express). In an electronic device using PCIe, the data transfer performance of PCIe may become a bottleneck when trying to improve the device performance.

Japanese Patent Laid-Open No. 2004-228561 describes content that distributes the load of data transfer by preventing a memory bus bandwidth from becoming insufficient by connecting a plurality of memories to a PCIe bus switch to distribute memory access. Yes.
JP 2005-332372 A

  Conventionally, in order to improve the data transfer performance of PCIe, a method of increasing the number of bus lanes, a method of increasing the operating frequency, and the like can be considered. However, the method of increasing the number of bus lanes and the method of increasing the operating frequency have greatly changed the device, and had the following effects on development costs, personnel, man-hours, and risks.

  As an influence on the development cost, there is a problem that it is necessary to newly develop or procure a logical layer IP and a physical layer IP. As an influence on personnel, there is a problem that it is necessary to secure human resources for device development. As an influence on the man-hours, there was a problem that the man-hours for developing the device were several months. In addition, as an impact on risk, there is a problem that the operation results of the old device cannot be applied to develop the device.

  Although Cited Document 1 can prevent the memory bus bandwidth from becoming insufficient, it cannot prevent the PCIe bus bandwidth from becoming insufficient. Thus, conventionally, there has been a problem that the data transfer performance of PCIe cannot be easily improved.

  SUMMARY An advantage of some aspects of the invention is that it provides a bus switch, an electronic device, and a data transfer method capable of easily improving data transfer performance of a serial transfer interface.

  In order to solve the above problems, the present invention is provided between a memory control unit that controls reading of data from a memory and writing of data to the memory, and a plurality of processing control units that process the data. A bus switch of a serial transfer interface, provided for each of the processing control means, between a first data transmission / reception means for controlling data transmission / reception performed with the processing control means, and the memory control means Second data transmission / reception means for controlling data transmission / reception to be performed, and switching means for switching connection between the first data transmission / reception means and the second data transmission / reception means, the first data transmission / reception means, A buffer having a capacity larger than the amount of data that can be transferred to and from the memory by a single command from the processing control means is provided.

  The present invention is also an electronic apparatus comprising memory control means for controlling reading of data from a memory and writing of data to the memory, and a plurality of processing control means for processing the data, wherein the memory control And a bus switch of a serial transfer interface between the plurality of processing control means, and the bus switch is provided for each of the processing control means and controls data transmission / reception performed with the processing control means A first data transmission / reception means, a second data transmission / reception means for controlling data transmission / reception performed between the memory control means, and a connection between the first data transmission / reception means and the second data transmission / reception means. Switching means for switching, wherein the first data transmitting / receiving means can transfer data to and from the memory by a single command from the processing control means. Characterized in that it has a buffer of a data amount greater capacity.

  The present invention also provides a serial transfer interface bus provided between memory control means for controlling reading of data from the memory and writing of data to the memory and a plurality of processing control means for processing the data. A data transfer method in a switch, wherein a first data transmission / reception unit provided for each of the processing control units and controlling data transmission / reception to / from the processing control unit is provided between the processing control unit and the memory. A step of receiving a read command performed in step S2, a second data transmitting / receiving unit controlling data transmission / reception performed with the memory control unit transmitting the read command to the memory control unit, and the second data The transmission / reception means receives the data read from the memory in response to the read command from the memory control means. And the first data transmission / reception unit that transmits the read command to the data received from the memory control unit by the switching unit that switches the connection between the first data transmission / reception unit and the second data transmission / reception unit. And transmitting the data using a buffer having a capacity larger than the amount of data that can be transferred to and from the memory by a single command from the processing control means. And transmitting to the control means.

  In addition, what applied the component, expression, or arbitrary combination of the component of this invention to a method, an apparatus, a system, a computer program, a recording medium, a data structure, etc. is also effective as an aspect of this invention.

  According to the present invention, it is possible to provide a bus switch, an electronic device, and a data transfer method capable of easily improving the data transfer performance of the serial transfer interface.

  Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings. In this embodiment, a printer which is an image processing apparatus will be described as an example of an electronic apparatus. However, any electronic apparatus may be used. First, in order to facilitate understanding of the present invention, a configuration example of a conventional printer will be described.

  FIG. 1 is a configuration diagram of an example of a conventional printer. In the configuration diagram of FIG. 1, a part unnecessary for the description of the present invention is partially omitted. The printer shown in FIG. 1 includes a CPU 101, a system memory 102, an MCH (Memory Controller Hub) 103, an image processing controller 104, and an image output device (plotter unit) 105.

  The MCH 103 is a chip set for a memory interface (I / F). In the MCH 103 of this embodiment, the PCIe I / F port can be connected in a maximum of 8 lanes. A lane is a transmission path with a minimum configuration used in PCIe. A port is a configuration in which a plurality of lanes are bundled. The image processing controller 104 is a device that performs image compression, scaling, color conversion, gradation processing, and the like. The image output apparatus 105 is an apparatus that forms an image on a medium such as paper based on data (image data).

  The CPU 101, the system memory 102, and the image processing controller 104 are connected via the MCH 103. The image processing controller 104 is connected to the image output device 105. The image processing controller 104 performs various image processing using the system memory 102. The image processing controller 104 also has a function of outputting data in the system memory 102 to the image output device 105. In the image processing controller 104 of this embodiment, the PCIe I / F port can be connected in a maximum of four lanes.

  As described above, in the conventional printer shown in FIG. 1, the MCH 103 and the image processing controller 104 are connected via PCIe four-lane “PCIe × 4” in terms of system performance. However, when a higher performance system is constructed in order to improve the printer performance, the conventional printer shown in FIG. 1 has insufficient PCIe bus bandwidth, and there are four PCIe lanes between the MCH 103 and the image processing controller 104. It can be a bottleneck.

  In the conventional printer shown in FIG. 1, even if it is found that the bus bandwidth is insufficient unless the number of PCIe lanes of the image processing controller 104 is 8, the maximum number of PCIe I / F ports is 8 lanes as described above. There is a problem in that the image processing controller 104 cannot be easily changed so that the connection can be made.

  FIG. 2 is a configuration diagram of an embodiment of the printer of the present invention. In the configuration diagram of FIG. 2, a part unnecessary for the description of the present invention is partially omitted. The printer shown in FIG. 2 includes a CPU 101, a system memory 102, an MCH 103, an image processing controller 104, an image output device 105, an image processing controller 106, and a PCIe bus switch 107.

  The printer shown in FIG. 2 has a configuration in which an image processing controller 106 and a PCIe bus switch 107 are added to the printer shown in FIG. Similar to the image processing controller 104, the image processing controller 106 is a device that performs image compression, scaling, color conversion, gradation processing, and the like. The PCIe bus switch 107 combines two or more ports and performs packet routing between the ports.

  The bus switch 107 of the present embodiment has three ports, one port on the upstream (upstream) side can be connected with a maximum of 8 lanes, and two ports on the downstream (downstream) side can be connected with a maximum of 4 lanes. To do.

  In the printer shown in FIG. 2, a PCIe bus switch 107 is interposed between the MCH 103 and the image processing controllers 104 and 106. The image processing controller 106 may be any device that can distribute the load on the image processing controller 104, and may be the same device as the image processing controller 104 or a different device.

  The image processing controllers 104 and 106 are both connected to the bus switch 107 and four lanes of PCIe. Further, the MCH 103 and the bus switch 107 are connected by eight lanes of PCIe. In the printer shown in FIG. 2, the number of lanes connecting the MCH 103 and the bus switch 107 is larger than the number of lanes connecting the image processing controller 104 and the bus switch 107 respectively.

  In the printer shown in FIG. 2, the number of lanes connecting the MCH 103 and the bus switch 107 is more than twice the number of lanes connecting the image processing controller 104 and the bus switch 107, in other words, the transfer rate is more than twice. It is desirable that Note that in a printer in which N (hereinafter, N is a plurality) image processing controllers 104 are connected to the bus switch 107, the number of lanes connecting the MCH 103 and the bus switch 107 is the number of lanes connecting the image processing controller 104 and the bus. It is desirable that the number of lanes connected to the switch 107 is N times or more, in other words, the transfer rate is N times or more.

  In the printer according to the present invention, a plurality of devices (image processing controllers 104 and 106) that access the system memory 102 as a master are connected to the PCIe bus switch 107, and the number of lanes connecting each device and the bus switch 107 is “ By increasing the number of lanes “8” connecting the MCH 103 and the bus switch 107 to 4 ”, a bottleneck in the PCIe bus band is eliminated by providing a transfer rate difference.

  The original use of the PCIe bus switch 107 is to connect a plurality of modules (functions) to one bus. However, in the printer shown in FIG. 2, a plurality of identical modules are connected to enhance data transfer performance. As in the printer shown in FIG. 1, the printer shown in FIG. 2 can use the existing image processing controllers 104 and 106 having four lanes of PCIe, thereby minimizing development costs, personnel, man-hours, and risks. Thus, the data transfer performance of PCIe can be improved. Therefore, in the printer shown in FIG. 2, the device performance can be easily improved.

  FIG. 3 is a timing chart of data transfer performed by a conventional printer. In FIG. 3, the PCIe bus between the MCH 103 and the image processing controller 104 is “bus 1”. The timing chart of FIG. 3 shows the operation of “bus 1” when the image processing controller 104 reads the output image data from the system memory 102 in response to the activation request from the CPU 101.

  First, the CPU 101 accesses a register (not shown) in the image processing controller 104 and activates the image processing controller 104. The image processing controller 104 issues a read command (C 1) for the system memory 102 to the MCH 103. The MCH 103 that has received the read command (C 1) reads the data at the designated address from the system memory 102.

  The MCH 103 returns the data (D1) read from the system memory 102 to the image processing controller 104 as a PCIe response to the read command (C1). The image processing controller 104 performs image processing on the data (D 1) received from the MCH 103 and sends it to the image output device 105. The image output device 105 prints the received data on paper.

  The image processing controller 104 issues the next read command (C2) for the system memory 102 to the MCH 103 in parallel with the process of processing the data (D1) received from the MCH 103 and sending it to the image output device 105. Hereinafter, in the conventional printer, the processing is continued in the same manner as the read command (C1).

  FIG. 4 is a timing chart of data transfer performed by the printer according to the present invention. In FIG. 4, the PCIe bus between the MCH 103 and the bus switch 107 is “bus 1”, the PCIe bus between the image processing controller 104 and the bus switch 107 is “bus 2”, and the image processing controller 106 and the bus switch 107. The PCIe bus between and is called “bus 3”.

  The timing chart of FIG. 4 shows operations of “bus 1” to “bus 3” when the image processing controllers 104 and 106 read the output image data from the system memory 102 in response to the activation request from the CPU 101. Yes. In the timing chart of FIG. 4, the image processing controllers 104 and 106 share different output images. For example, when the printer handles CMYK 4 plane data, the image processing controller 104 shares the C and M planes, and the image processing controller 106 shares the Y and K planes. In addition, when the printer performs double-sided simultaneous printing, the image processing controller 104 may share the front surface and the image processing controller 106 may share the back surface.

  First, the CPU 101 accesses a register (not shown) in the image processing controllers 104 and 106 and activates the image processing controllers 104 and 106. The image processing controller 104 issues a read command (C1) for the system memory 102 to the MCH 103 via the “bus 2”. The image processing controller 106 issues a read command (C B) for the system memory 102 to the MCH 103 via the “bus 3”.

  The bus switch 107 sends the received two read commands (C1, Ca) to the MCH 103 via the “bus 1” in order without processing. The MCH 103 that has received the read command (C1, CA) reads the data at the designated address from the system memory 102, respectively.

  The MCH 103 returns the data (D1, DA) read from the system memory 102 to the bus switch 107 via the “bus 1” as a PCIe response to the read command (C1, CA).

  The bus switch 107 returns the received data (D1) via the “bus 2” to the image processing controller 104 that requested the read command (C1). In addition, the bus switch 107 returns the received data (D B) to the image processing controller 106 that requested the read command (C B) via the “bus 3”.

  The image processing controller 104 issues the next read command (C2) while performing image processing on the data (D1) received from the bus switch 107 and passing it to the image output device 105. The image processing controller 106 issues the next read command (C) while processing the data (D) received from the bus switch 107 and passing it to the image output device 105.

  When the image output device 105 receives the data after image processing by the image processing controller 104 or 106, the image output device 105 prints the received data on paper. The read command (C2, C b) is transmitted to the MCH 103 in the same manner as the read command (C1, C b). Hereinafter, in the printer according to the present invention, the processing is continued as in the case of the read command (C1, C b).

  In the timing chart shown in FIG. 4, the data (D2) of “bus 1” and the read command (C) overlap. However, since the PCIe bus is a full-duplex transfer in which a transmission bus and a reception bus are separated, simultaneous transfer is possible.

  Since the “bus 1” has more lanes than the “bus 2” and “bus 3”, in other words, the bus bandwidth is wide, the timing chart of the printer according to the present invention shown in FIG. 4 is the conventional timing chart shown in FIG. Data transfer efficiency is better than the printer timing chart.

  FIG. 5 is a schematic diagram showing the configuration of the PCIe bus switch and the flow of data. The PCIe bus switch 107 in FIG. 5 has three ports 201 to 203. The upstream side (ENDP) port 201 is connected to the MCH 103 which is an upstream device in 8 lanes “PCIe × 8”. The downstream side (ROOT) ports 202 and 203 are connected to the image processing controllers 104 and 106 which are downstream devices in 4 lanes “PCIe × 4”.

  The ports 202 and 203 on the downstream side have buffers 204 and 205 used for data transmission / reception. When the capacity of the buffers 204 and 205 is only one transfer size (the amount of data that can be transferred by one command: 4 kbytes, for example), read commands are alternately issued from the image processing controllers 104 and 106 that are downstream devices. Then, the best performance comes out.

  However, when the read commands from the image processing controllers 104 and 106 that are downstream devices are not issued alternately (the same downstream device issues read commands successively), the buffer 204 or 205 corresponding to the issuer of the read command is stored in the buffer 204 or 205. Until the buffer 204 or 205 corresponding to the issuer of the read command becomes empty, the next data transfer is in a wait state.

  When the capacity of the buffers 204 and 205 is more than a plurality (N) of transfer sizes (data amount that can be transferred by N commands), read commands are alternately issued from the image processing controllers 104 and 106 as downstream devices. Even without this, it is possible to prevent the data transfer performance from deteriorating. Specifically, if the capacity of the buffers 204 and 205 is N transfer size, even if the same downstream device issues a read command N times consecutively, if the buffer 204 or 205 corresponding to the read command issue source is full. Therefore, the next data transfer is not in a waiting state.

  Next, the operation of the PCIe bus switch 107 will be described. Each port 201 to 203 of the bus switch 107 is mapped to a memory space, for example, as shown in FIG. FIG. 6 is a schematic diagram showing an example of how each port of the bus switch is mapped in the memory space. The mapping to the memory space is performed by the configuration for each of the ports 201 to 203 at the time of activation (general PCI configuration).

  For example, assuming that a bus switch having ports 201 to 203 is mapped to a memory space as shown in FIG. 6, when an upstream device connected to the port 201 accesses the address space of the port 202 (for example, 0x3000 0000), the port Connected to downstream devices connected to 202. That is, the upstream device connected to the port 201 can access the downstream device connected to the port 202.

  Note that the PCIe bus switch 107 is not based on the memory map method described above, but has an individual access window, and maps the entire address space for each port 201 to 203 by setting an offset of the window. May be. The bus switch 107 according to the present invention does not depend on the switching method, and it is sufficient that the connection (path) between the ports 201 to 203 can be appropriately switched.

  Next, for reference, a timing chart of data transfer when the bus switch 107 has the buffers 204 and 205 and does not have the buffers 204 and 205 will be described. FIG. 7 shows a timing chart of data transfer when there is no buffer inside the bus switch. A timing chart of data transfer when the buffers 204 and 205 are provided inside the bus switch 107 is as shown in FIG.

  A data transfer timing chart when the bus switch 107 does not have the buffers 204 and 205 will be described with reference to FIG. Since the buffers 204 and 205 are not included inside, the timing chart of FIG. 7 shows that although the read command (C1, C B) is issued in succession by “Bus 1”, the received data (D1, D B) is one. One by one.

  In the timing chart of FIG. 7, the bus switch 107 receives data (D1) on “bus 1” and transmits the data (D1) on “bus 1” until the data (D1) is sent to the image processing controller 104 on “bus 2”. D) I can't receive it.

  That is, the bus switch 107 that does not have the buffers 204 and 205 inside reduces the performance of the data transfer performance due to its own latency, and improves the performance of the data transfer performance even if a plurality of read commands are continuously transferred. I can not connect it. The latency referred to here is the time from when a read command is issued until data is returned to the read command issuer.

  On the other hand, as shown in FIG. 4, the bus switch 107 having the buffers 204 and 205 internally degrades the data transfer performance due to its own latency, but the data can be prefetched by having the buffers 204 and 205. By continuously transferring a plurality of read commands, its own latency can be offset and the data transfer performance can be improved.

  Next, a timing chart when the bus switch 107 has the buffers 204 and 205 and the read command is first thrown from the image processing controllers 104 and 106 will be described. FIG. 8 shows a timing chart of data transfer when the bus switch has a buffer and a read command is thrown first. Note that read command first throwing means that the downstream device that is the issuer of the read command issues the next read command before receiving data for the previous read command.

  The timing chart of FIG. 8 represents operations of “bus 1” to “bus 3” when the image processing controllers 104 and 106 read the output image data from the system memory 102 in response to the activation request from the CPU 101. Yes. In the timing chart of FIG. 8, upon receiving a start request from the CPU 101, the image processing controllers 104 and 106 continuously issue a plurality (two in FIG. 8) of read commands to the data (responses) of the previously issued read commands. By issuing it before receiving (data), the read command is thrown first.

  First, the CPU 101 accesses a register (not shown) in the image processing controllers 104 and 106 and activates the image processing controllers 104 and 106. The image processing controller 104 continuously issues read commands (C1, C2) to the system memory 102 to the MCH 103 via the “bus 2”. The image processing controller 106 issues a read command (C B, C B) for the system memory 102 to the MCH 103 via the “bus 3”. The bus switch 107 sends the received four read commands (C1, C, C2, C) to the MCH 103 via the “bus 1” in order without processing.

  The MCH 103 that has received the read command (C1, C B, C2, C B) reads the data (D1, D B, D2, D B) at the specified address from the system memory 102, respectively. The MCH 103 returns the data (D1, DA) read from the system memory 102 to the bus switch 107 via “Bus 1” as a PCIe response to the read command (C1, CA).

  FIG. 8 shows an example in which the capacity of the buffers 204 and 205 is one transfer size. Therefore, at this time, the data (D2, D) read from the system memory 102 is not returned to the bus switch 107.

  The bus switch 107 returns the received data (D1) via the “bus 2” to the image processing controller 104 that requested the read command (C1). The bus switch 107 returns the received data (D B) to the image processing controller 106 that has requested the read command (C B) via “Bus 3”.

  The image processing controller 104 issues the next read command (C3) while image-processing the data (D1) received from the bus switch 107 and passing it to the image output device 105. The image processing controller 106 issues the next read command (C) while image-processing the data (D) received from the bus switch 107 and passing it to the image output device 105. The read command (C3, C) is transmitted to the MCH 103 in the same way as the read command (C1, C, etc.).

  Note that, since the buffer 204 becomes empty when the transfer of the data (D1) is completed on the “bus 2”, the bus switch 107 starts the transfer of the data (D2) on the “bus 1”. Immediately after issuing the read command (C3), the image processing controller 104 starts receiving data (D2).

  In addition, since the buffer 205 becomes empty when the transfer of data (D B) is completed in “Bus 3”, the bus switch 107 starts transferring data (D B) in “Bus 1”. Immediately after issuing the read command (C c), the image processing controller 106 starts receiving data (D).

  When the image output device 105 receives the data after the image processing by the image processing controller 104 or 106, the image output device 105 prints the received data on paper. Hereinafter, in the printer according to the present invention, the processing is continued as in the case of the read command (C1, C b).

  As described above, the timing chart of the printer according to the present invention shown in FIG. 8 can effectively use the bus bandwidth of “bus 1” when the image processing controllers 104 and 106 first throw the read command, so that the data transfer efficiency Can be further improved.

  To further improve the data transfer efficiency, increase the number of downstream image processing controllers 104 and 106, increase the capacity of buffers 204 and 205, and downstream image processing controllers 104 and 106 This can be handled by increasing the number of read commands to be executed. When the number of image processing controllers 104 and 106 that are downstream devices is increased, the effect is reduced when the bus band of “bus 1” is narrow.

  By the way, if the data transfer unit (packet) is small, the bus switch 107 according to the present invention cannot effectively use the bus band of “Bus 1”, and the data transfer efficiency deteriorates. Next, a timing chart of data transfer when the data transfer unit (packet) in the bus switch 107 according to the present invention is large and small will be described.

  FIG. 9 shows a timing chart of data transfer when the data transfer unit (packet) is large and small. FIG. 9A is a timing chart of data transfer when there is no first throw of the read command and the packet is small. FIG. 9B is a timing chart of data transfer when there is no read command first throw and the packet is large.

  As shown in FIG. 9A, if one packet is small (short) in the bus switch 107, the occurrence frequency of the blank time waiting for the read command issuance on the “bus 1” increases, and the data transfer efficiency deteriorates. On the other hand, as shown in FIG. 9B, when one packet is large (long) in the bus switch 107, the occurrence frequency of the blank time waiting for the read command issuance in “bus 1” is reduced, and the data transfer efficiency is improved. Become.

  As described above, the bus switch 107 according to the present invention causes the occurrence of the read command issue wait time in the “bus 1” to be less when the packet is longer than when the packet is short. Can be ignored, and the data transfer efficiency is improved by effectively using the bus band of “bus 1”.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims. For example, the bus switch 107 has three ports. However, the bus switch 107 is not limited to three ports, and may have a configuration having four or more ports. The number of lanes (4, 8) of the bus is also an example, and other lane numbers may be used.

  FIG. 10 is a configuration diagram of another embodiment of the printer of the present invention. In the configuration diagram of FIG. 10, parts unnecessary for the description of the present invention are partially omitted. The printer shown in FIG. 10 includes a CPU 101, a system memory 102, an MCH 103, an image processing controller 104, an image output device 105, an image processing controller 106, and a PCIe bus switch 107.

  The printer shown in FIG. 10 has the same configuration as the printer shown in FIG. In the printer shown in FIG. 10, the image processing controller 106 is connected to the bus switch 107 in one lane of PCIe, the image processing controller 104 shares the C, M, and Y planes, and the image processing controller 106 It differs from the printer of FIG. 2 in that the K plane is shared.

  That is, in the printer shown in FIG. 10, the number of lanes connecting the image processing controller 104 and the bus switch 107 is different from the number of lanes connecting the image processing controller 106 and the bus switch 107. In other words, the transfer rate between the image processing controller 104 and the bus switch 107 is different from the transfer rate between the image processing controller 106 and the bus switch 107 in the printer shown in FIG.

  10 is similar to the printer of FIG. 2 in that the lanes connecting the MCH 103 and the bus switch 107 are more than the number of lanes connecting the image processing controller 104 or 106 and the bus switch 107, respectively. The number is higher.

  The printer shown in FIG. 10 enhances data transfer performance by connecting a plurality of modules (image processing controllers 104 and 106) that can distribute the load. The printer shown in FIG. 10 can use the existing image processing controllers 104 and 106 having 4 or 1 lanes of PCIe as in the printer shown in FIG. 2, thereby minimizing development costs, personnel, man-hours, and risks. The data transfer performance of PCIe can be improved. Therefore, the device performance can be easily improved in the printer shown in FIG.

  In the printer shown in FIG. 2, the transfer rate between the image processing controller 104 and the bus switch 107 is equal to the transfer rate between the image processing controller 106 and the bus switch 107, and the timing chart shown in FIG. As described above, the bus 2 and the bus 3 use the bandwidth of the bus 1 equally.

  On the other hand, the transfer rate between the image processing controller 104 and the bus switch 107 differs from the transfer rate between the image processing controller 106 and the bus switch 107 in the printer shown in FIG. The timing chart is as shown.

  FIG. 11 is a timing chart in the case where there is a difference in transfer rate among the data transfers performed by the printer according to the present invention. In FIG. 11, as in FIG. 8, the PCIe bus between the MCH 103 and the bus switch 107 is “bus 1”, and the PCIe bus between the image processing controller 104 and the bus switch 107 is “bus 2”. The PCIe bus between the bus 106 and the bus switch 107 is referred to as “bus 3”.

  The timing chart of FIG. 11 is similar to the timing chart of FIG. 8 when “bus 1” to “bus 1” to “image 1” when the image processing controllers 104 and 106 read the output image data from the system memory 102 in response to the activation request from the CPU 101. The operation of the “bus 3” is shown.

  In the timing chart of FIG. 11, when an activation request is received from the CPU 101, the image processing controllers 104 and 106 first throw the read command first, as in the timing chart of FIG.

  First, the CPU 101 accesses a register (not shown) in the image processing controllers 104 and 106 and activates the image processing controllers 104 and 106. The image processing controller 104 continuously issues read commands (C1, C2) to the system memory 102 to the MCH 103 via the “bus 2”. The image processing controller 106 issues a read command (C B, C B) for the system memory 102 to the MCH 103 via the “bus 3”. The bus switch 107 sends the received four read commands (C1, C, C2, C) to the MCH 103 via the “bus 1” in order without processing.

  The MCH 103 that has received the read command (C1, C B, C2, C B) reads the data (D1, D B, D2, D B) at the specified address from the system memory 102, respectively. The MCH 103 returns the data (D1, DA) read from the system memory 102 to the bus switch 107 via “Bus 1” as a PCIe response to the read command (C1, CA).

  FIG. 8 shows an example in which the capacity of the buffers 204 and 205 is one transfer size. Therefore, at this time, the data (D2, D) read from the system memory 102 is not returned to the bus switch 107.

  The bus switch 107 returns the received data (D1) via the “bus 2” to the image processing controller 104 that requested the read command (C1). The bus switch 107 returns the received data (D B) to the image processing controller 106 that has requested the read command (C B) via “Bus 3”.

  However, since the transfer rate of “bus 3” between the image processing controller 106 and the bus switch 107 is slower than the transfer rate of “bus 2” between the image processing controller 104 and the bus switch 107, “bus” Even if the transfer of the data (D1) is completed in “2”, the transfer of the data (D b) in “bus 3” is not completed for a while.

  The image processing controller 104 issues the next read command (C3) while image-processing the data (D1) received from the bus switch 107 and passing it to the image output device 105. As described above, when the transfer of one data from the bus switch 107 is completed, the image processing controller 104 issues the next read command.

On the other hand, the image processing controller 106 issues the next read command (C) after receiving data (D, D) from the bus switch 107. The image processing controller 106 does not issue the next read command (C) for a while after the first two read commands (C B, C B) are issued. During this time, “bus 2” can intermittently use “bus 1” to transfer data.

  The printer shown in FIG. 10 has a different transfer rate between the image processing controller 104 and the bus switch 107 and a transfer rate between the image processing controller 106 and the bus switch 107, and the timing chart shown in FIG. Thus, the bus 2 uses more bandwidth of the bus 1 than the bus 3.

  FIG. 12 is a configuration diagram of another embodiment of the printer of the present invention. In the configuration diagram of FIG. 12, a part unnecessary for explanation of the invention is partially omitted. The printer shown in FIG. 12 includes a CPU 101, a system memory 102, an MCH 103, an image processing controller 104, an image output device 105, an image processing controller 106, a PCIe bus switch 107, and an image output device 108.

  The printer shown in FIG. 12 has the same configuration as the printer shown in FIG. In the printer shown in FIG. 12, the image processing controllers 104 and 106 share the C, M, Y, and K planes, and the image processing controller 106 is connected to the image output device 108 instead of the image output device 105. Is different from the printer of FIG.

  The printer shown in FIG. 12 can perform double-sided simultaneous printing, with the image processing controller 104 sharing the front side and the image processing controller 106 sharing the back side. The printer shown in FIG. 12 enhances data transfer performance by connecting a plurality of modules (image processing controllers 104 and 106) that can distribute the load to the bus switch 107, and the image processing controller 104 shares the surface in simultaneous duplex printing. In addition, since the image processing controller 106 shares the back surface in the simultaneous duplex printing, the printing function can be enhanced.

  The memory control means described in the claims corresponds to the MCH 103, the processing control means corresponds to the image processing controllers 104 and 106, the first data transmission / reception means corresponds to the ports 202 and 203, and the second Data transmission / reception means corresponds to the port 201.

It is a block diagram of an example of the conventional printer. It is a block diagram of one Example of the printer of this invention. It is a timing chart of the data transfer performed with the conventional printer. 4 is a timing chart of data transfer performed by the printer according to the present invention. It is the schematic diagram showing the structure of the bus switch of PCIe, and the flow of data. It is the schematic diagram of an example showing a mode that each port of the bus switch was mapped to the memory space. 6 is a timing chart of data transfer when a buffer is not provided in the bus switch. It is a timing chart of data transfer when there is a buffer in the bus switch and there is a read command first throw. It is a timing chart of data transfer when the data transfer unit (packet) is large and small. It is a block diagram of the other Example of the printer of this invention. 4 is a timing chart in the case where there is a difference in transfer rate among data transfer performed by the printer according to the present invention. It is a block diagram of the other Example of the printer of this invention.

Explanation of symbols

101 CPU
102 System memory 103 MCH (Memory Controller Hub)
104, 106 Image processing controller 105, 108 Image output device (plotter unit)
107 PCIe bus switch 201-203 port 204, 205 buffer

Claims (16)

A bus switch of a serial transfer interface provided between a memory control unit that controls reading of data from a memory and writing of data to the memory, and a plurality of processing control units that process the data,
A first data transmitting / receiving unit that is provided for each of the processing control units and controls data transmission / reception performed with the processing control unit;
Second data transmission / reception means for controlling data transmission / reception performed with the memory control means;
Switching means for switching the connection between the first data transmission / reception means and the second data transmission / reception means;
The bus switch according to claim 1, wherein the first data transmitting / receiving means includes a buffer having a capacity larger than the amount of data that can be transferred to and from the memory by a single command from the processing control means.   The first data transmitting / receiving unit receives a next read command from the processing control unit before transmitting data read from the memory by the one read command from the processing control unit to the processing control unit. The bus switch according to claim 1.   The transfer rate of the second data transmission / reception means connected to the memory control means is N times or more the transfer rate of the first data transmission / reception means connected to the N processing control means. The bus switch according to claim 1.   The transfer rate of the second data transmission / reception means connected to the memory control means is equal to or higher than the transfer rate obtained by summing the transfer rates of the N first data transmission / reception means connected to the N processing control means. The bus switch according to claim 1, wherein:   2. The bus switch according to claim 1, wherein the plurality of processing control means have the same function and share and process the data. An electronic device having memory control means for controlling reading of data from a memory and writing of data to the memory, and a plurality of processing control means for processing the data,
A serial transfer interface bus switch is provided between the memory control means and the plurality of process control means,
The bus switch is
A first data transmitting / receiving unit that is provided for each of the processing control units and controls data transmission / reception performed with the processing control unit;
Second data transmission / reception means for controlling data transmission / reception performed with the memory control means;
Switching means for switching the connection between the first data transmission / reception means and the second data transmission / reception means;
The electronic device according to claim 1, wherein the first data transmission / reception means includes a buffer having a capacity larger than an amount of data that can be transferred to and from the memory by a single command from the processing control means.   The first data transmitting / receiving unit receives a next read command from the processing control unit before transmitting data read from the memory by the one read command from the processing control unit to the processing control unit. The electronic device according to claim 6.   The transfer rate of the second data transmission / reception means connected to the memory control means is N times or more the transfer rate of the first data transmission / reception means connected to the N processing control means. The electronic device according to claim 6.   The transfer rate of the second data transmission / reception means connected to the memory control means is equal to or higher than the transfer rate obtained by summing the transfer rates of the N first data transmission / reception means connected to the N processing control means. The electronic apparatus according to claim 6, wherein:   7. The electronic apparatus according to claim 6, wherein the plurality of processing control means have the same function and share and process the data.   The electronic device according to claim 6, wherein the electronic device is an image processing apparatus including a plotter unit. A data transfer method in a bus switch of a serial transfer interface provided between a memory control means for controlling reading of data from a memory and writing of data to the memory and a plurality of processing control means for processing the data. There,
A first data transmitting / receiving unit that is provided for each of the processing control units and controls data transmission / reception performed with the processing control unit, receives a read command performed with the memory from the processing control unit; ,
A second data transmission / reception unit for controlling data transmission / reception performed with the memory control unit transmits the read command to the memory control unit;
The second data transmission / reception means receiving data read from the memory in response to the read command from the memory control means;
The switching means for switching the connection between the first data transmission / reception means and the second data transmission / reception means transmits the data received from the memory control means to the first data transmission / reception means that has transmitted the read command. Steps,
The first data transmitting / receiving means transmitting the data to the processing control means using a buffer having a capacity equal to or larger than the amount of data that can be transferred to and from the memory by a single command from the processing control means; A data transfer method characterized by comprising: The first data transmitting / receiving unit receives a next read command from the processing control unit before transmitting the data read from the memory by the one read command from the processing control unit to the processing control unit. The data transfer method according to claim 12, further comprising a step.   The transfer rate of the second data transmission / reception means connected to the memory control means is N times or more the transfer rate of the first data transmission / reception means connected to the N processing control means. The data transfer method according to claim 12.   The transfer rate of the second data transmission / reception means connected to the memory control means is equal to or higher than the transfer rate obtained by summing the transfer rates of the N first data transmission / reception means connected to the N processing control means. The data transfer method according to claim 12, wherein:   13. The data transfer method according to claim 12, wherein the plurality of processing control means have the same function, and share and process the data.

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