JP2009146497A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the higher reliability of a semiconductor device provided with a nonvolatile memory cell. <P>SOLUTION: By an electronic circuit electrically connected to a memory array which is composed of a plurality of memory cells, voltages are applied to a selection gate for constituting the memory cell, a memory gate, a well, a source and a drain to control operation such as the writing, erasing, application of an alleviation pulse, and verification. In the application of the alleviation pulse, a positive voltage is applied to the selection gate in a state that holes are distributed at the selection gate side of a charge accumulating film, and 0V is applied to the memory gate to connect the hole and the electron, and thereby electric charges in the charge accumulating film are stabilized. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to an operation method of a semiconductor device including a nonvolatile memory cell.

  One type of integrated semiconductor memory incorporated in an LSI is a nonvolatile memory. The nonvolatile memory is an element in which stored information remains even when the power of the LSI is turned off, and is an extremely important element for using the LSI for various applications.

  Non-volatile memories of semiconductor elements include so-called floating gate type memories and memories using insulating films. Normally, these memory cells are arranged in a matrix and used by forming an array (memory array) composed of a plurality of bit lines and word lines.

  Japanese Patent Laid-Open No. 2003-46002 (Patent Document 1) uses a stacked structure of a silicon oxide film / a silicon nitride film / a silicon oxide film as an insulating film charge storage film, and a selection transistor is provided on the side surface of the memory transistor. A so-called split gate type MONOS (Metal Oxide Nitride Oxide Semiconductor) memory is disclosed. As the operation method of this memory cell, a source side hot electron injection (hereinafter referred to as SSI-HE injection) at the time of writing and an interband induced hot hole injection (hereinafter referred to as BTBT-HH injection) at the time of erasing are adopted.

  In the SSI-HE injection at the time of writing and the BTBT-HH injection at the time of erasing, the electron injection by the writing operation and the hole injection position by the erasing operation are different, so that mismatch easily occurs, and the electron / hole charge distribution in the charge storage film It will be in the state. In this state, if the memory cell is left unattended, charge diffusion occurs, and charge pair annihilation may occur, thereby changing the threshold value of the memory cell.

In view of this, as a technique for reducing the mismatch of the charge distribution and causing the memory cell to operate stably, Japanese Patent Application Laid-Open No. 2006-12382 (Patent Document 2) describes that a plurality of pulse voltages or multi-step voltages are stored in a memory during a write / erase operation. A method of applying to a gate or the like is disclosed.
JP 2003-46002 A JP 2006-12382 A

  The present inventors have studied a split gate type MONOS memory as disclosed in Patent Documents 1 and 2, and the following problems arise when the gate length of a memory transistor is shortened due to scaling. I found it.

  FIG. 1 is a schematic diagram for explaining a mismatch in charge distribution of memory cells when the memory gate length is long (a) to (c) and when the memory gate length is short (d) to (f). Reference numerals 50 and 60 are silicon substrates, reference numerals 51 and 61 are memory gates, reference numerals 52 and 62 are selection gates, reference numerals 53, 54, 63, and 64 are silicon oxide films, and reference numerals 55 and 65 are charge storage films. Reference numerals 56, 57, 66 and 67 denote n-type semiconductor regions (diffusion layers), reference numerals 58 and 68 denote p-type wells, and reference numerals 59 and 69 denote silicon oxide films.

  When the memory gate length is long, the multi-step step voltage is set to the memory gate 52 and the n-type during the write (FIG. 1 (a)) / erase (FIG. 1 (b)) operation as described in Patent Document 2. It is effective to relax the mismatch of the charge distribution by applying it to the semiconductor region 56 (FIG. 1C). Here, when the memory gate length is sufficiently long, the injection position of the BTBT-HH injection at the time of erasure is sufficiently separated from the SSI-HE injection position at the time of writing. As shown in FIG. 1C, the hole distribution mismatch is caused by holes in the silicon nitride film 55 (charge storage film) on the n-type semiconductor region 56 side and silicon nitride film 55 (charge) on the select gate 52 side. In the storage film), electrons are localized and distributed.

  On the other hand, when the memory gate length is about 40 nm or less, a multi-step voltage is applied to the memory gate 62 and the n-type semiconductor region 66 during the write (FIG. 1 (d)) / erase (FIG. 1 (e)) operation. Even when the distribution mismatch is relaxed, the BTBT-HH implantation position is shifted to the selection gate 52 side by the amount of the shortened gate length, and the region where the selection gate 52 and the memory gate 51 are insulated from each other. The hole will reach. That is, as shown in FIG. 1 (f), the mismatch between electrons and holes associated with the rewriting of the memory cell is caused by electrons being transferred to the silicon nitride film 65 (charge storage film) on the n-type semiconductor region 66 side. Holes are localized and distributed in the silicon nitride film 65 (charge storage film), and the distribution is reversed as compared with the case where the memory gate length is long.

  For this reason, when the memory cell is left, in addition to the movement of electrons / holes in the silicon nitride film 65 (charge storage film) on the channel, holes reaching the region where the selection gate 62 and the memory gate 61 are insulated are diffused. As a result, the present inventors have found that the problem of greatly impairing the reliability occurs.

  An object of the present invention is to provide a technique capable of increasing the reliability of a semiconductor device including a nonvolatile memory cell.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In one embodiment of the present invention, a positive voltage is applied to the selection gate and 0 V (reference voltage) is applied to the memory gate in a state where holes are distributed more than electrons on the selection gate side of the charge storage film. , It combines holes and electrons.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to this embodiment, the reliability of the semiconductor device including the nonvolatile memory cell can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof may be omitted. In addition, in order to make the drawing easy to see, hatching may be applied even in a plan view, and hatching may not be applied even in a cross-sectional view.

(Embodiment 1)
FIG. 2 is a block diagram of a semiconductor device (semiconductor integrated circuit device) including a memory array 9 composed of a plurality of nonvolatile memory cells (hereinafter simply referred to as memory cells) in the present embodiment. FIG. 3 is a block diagram of the memory array 9 of FIG. FIG. 4 is an equivalent circuit diagram of the memory array 9 of FIG. 5 is a schematic diagram showing a plane of the memory array 9 of FIG. 2, and FIG. 6 is a cross-sectional view taken along lines AA ′, BB ′, CC ′, and DD ′ of FIG. It is a schematic diagram shown. FIG. 7 is a schematic diagram showing a cross section of the memory cell MC in the present embodiment, in which the cross section taken along the line AA ′ of FIG. 6 is enlarged.

  As shown in FIG. 2, the semiconductor device according to the present embodiment includes a control circuit 1, an input / output circuit 2, an address buffer 3, a row decoder 4, a column decoder 5, a verify sense amplifier circuit 6, a high-speed read sense amplifier circuit 7, The rewriting circuit 8, the memory array 9, and the power supply circuit 10 are comprised. An electronic circuit such as the control circuit 1 is electrically connected to the memory array 9 that stores information as a memory by wiring, and signals are transferred. Although not shown, a power supply line for supplying a reference voltage to an electronic circuit such as the memory array 9 and the control circuit 1 and a power supply line for supplying a power supply voltage are also electrically connected.

  The control circuit 1 temporarily stores a control signal input from a host such as a connected microcomputer, and controls operation logic. Although details will be described later, the control circuit 1 controls the potential of the gate electrode of the memory cell in the memory array 9.

  Various data such as data read from or written to the memory array 9 and program data are input to and output from the input / output circuit 2. The address buffer 3 temporarily stores an address input from the outside. A row decoder 4 and a column decoder 5 are connected to the address buffer 3, respectively.

  The row decoder 4 performs decoding based on the row address output from the address buffer 3, and the column decoder 5 performs decoding based on the column address output from the address buffer 3.

  The verify sense amplifier circuit 6 is a sense amplifier for erase / write verify, and the high-speed read sense amplifier circuit 7 is a read sense amplifier used at the time of data reading. The rewrite circuit 8 includes a memory gate control circuit, a selection gate control circuit, a source control circuit, a drain control circuit, and the like for operating the memory cell MC, and latches write data input via the input / output circuit 2. Control data writing. The power supply circuit 10 includes a voltage generating circuit that generates various voltages used for data writing, erasing, verifying, and the like, and a current trimming circuit 11 that generates an arbitrary voltage value and supplies it to the rewriting circuit.

  The memory array 9 is divided into a plurality of blocks, and FIG. 3 shows an example in which the memory array 9 is divided into 8 blocks A0 to A7. Since signals are transferred for each of a plurality of blocks, efficiency can be improved and high-speed operation can be achieved.

  As shown in FIG. 4, the memory array 9 is composed of a plurality of memory cells MC provided in a matrix. The memory cell MC is composed of a field effect transistor, and includes a memory transistor Qm for storing information and a selection transistor Qc for selecting a predetermined memory cell MC. Note that in this embodiment mode, a memory cell MC formed of an n-channel field effect transistor is described for the sake of explanation, but a p-channel field effect transistor can be formed in the same manner in principle. .

  The memory cell MC and the above-described rewrite circuit 8 are electrically connected. The memory gate (MG) of the memory cell has a memory gate control circuit, the selection gate (CG) has a selection gate control circuit, and the source has a memory gate (MG). An electronic circuit such as a drain control circuit is electrically connected to the source control circuit and the drain.

  The planar layout of the memory array 9 is such that a plurality of memory cells MC are provided in a matrix along the X direction of the main surface of the semiconductor substrate and the Y direction intersecting therewith, as shown in FIG. Yes. The memory gate 101 and select gate 102 extending in the X direction are configured as word lines, and the n-type semiconductor region 106 (diffusion layer, source of the memory cell MC) extending in the X direction is configured as a source line. A wiring 111 extending in the Y direction electrically connected to the n-type semiconductor region 107 (diffusion layer, drain of the memory cell MC) extending in the direction via the contact 110 is configured as a bit line, It is electrically connected to an electronic circuit such as the rewrite circuit 8 described above.

  As shown in FIGS. 6 and 7, the memory cells MC constituting the memory array 9 are formed on a well 108 that is a p-type semiconductor region provided on the main surface of a silicon substrate 100 that is a semiconductor substrate, and on the well 108. And a selection gate 102 which is a gate electrode of the selection transistor Qc provided through a silicon oxide film 109 which is a gate insulating film.

  In addition, the memory cell MC is provided adjacent to the selection gate 102 on the well 108 with the stacked insulating film including the charge storage film provided along the side wall and the well 108 of the select gate 102 and the stacked insulating film interposed therebetween. And a memory gate 101 which is a gate electrode of the memory transistor Qm. In the present embodiment, the memory transistor Qm is configured so that the memory gate length is 40 nm.

  The stacked insulating film between the well 108 and the select gate 102 has a silicon nitride film 105 which is a charge storage film in which charges of electrons and holes having different polarities are stored under the memory gate 101, and the silicon oxide film 103. The silicon nitride film 105 is laminated between the silicon oxide film 104 and the silicon oxide film 104.

  Further, the memory cell MC is provided in the well 108 so as to sandwich a region (channel region) where a channel is formed under the selection gate 102 and the memory gate 101, and an n-type semiconductor region 106 (source) and a semiconductor region 107 ( Drain).

  As described above, in the memory cell MC in the present embodiment, the memory gate 101 that performs memory operation and the selection gate 102 that performs cell selection are separately formed on the silicon substrate 100. The gate insulating film (laminated insulating film) of the memory gate 101 has a structure in which the silicon nitride film 105 is sandwiched between two silicon oxide films 103 and 104, and has a so-called MONOS structure. The silicon nitride film 105 has a charge (electron, hole). Can be operated as a memory. In this operation, an electronic circuit such as the control circuit 1 applies a voltage to the selection gate 102, the memory gate 101, the p-type well 108, the n-type semiconductor region 106 (source), and the n-type semiconductor region 107 (drain). Then, control is performed to inject holes or electrons into the silicon nitride film 105 which is a charge storage film.

  Next, an example of three operations of reading, writing, and erasing will be described as basic operations of the memory cell MC in the present embodiment. In this specification, an operation for increasing the charge in the charge storage film is described as a writing operation, and an operation for decreasing the charge is described as an erasing operation.

  For these read, write, and erase operations of the memory cell MC, a voltage is applied to the select gate 102, the memory gate 101, the well 108, the semiconductor region 106 (source), and the semiconductor region 107 (drain). This control is performed from an electronic circuit such as the control circuit 1 electrically connected to the memory cell MC (memory array 9). Note that in the semiconductor device in this embodiment, the reference voltage is 0 V and the power supply voltage Vdd is 1.5 V.

  During a read operation, the selection gate 102 has a positive power supply voltage Vdd, the well 108 has 0 V, the semiconductor region 106 (source) has 0 V, the semiconductor region 107 (drain) has a positive potential, the power supply voltage Vdd, and the selection gate 102 has a positive potential. The channel under the selection gate 102 is turned on by applying the power supply voltage Vdd. In this state, by applying an appropriate memory gate potential (for example, 0 V) that can determine the threshold difference of the memory gate 101 given by the write / erase state to the memory gate 101, the channel of the memory gate 101 is written in the write state. In the erase state, almost no current flows in the channel of the memory gate 101. Therefore, the write / erase state of the memory cell MC can be determined based on the amount of current flowing through the channel of the memory gate 101.

  Further, all the voltages necessary for reading are the power supply voltage Vdd, which can be driven only by the low-voltage power supply circuit, so that the memory cell can be read at high speed.

  During a write operation, a gate overdrive voltage higher than the power supply voltage Vdd is applied to the memory gate 101 while a positive potential higher than the power supply voltage Vdd is applied to the well 108 and the semiconductor region 106 (source). The channel under the memory gate 101 is turned on. Note that the voltage applied to the semiconductor region 107 (drain) is controlled so that a desired current flows through the channel.

  Here, the potential is applied to the selection gate 102 as a value higher by 0.1 to 0.2 V, for example, than the threshold value, so that the ON state is obtained. Under this voltage condition, a strong electric field is generated in the channel region between the memory gate 101 and the selection gate 102, and many hot electrons are generated. Writing is performed by injecting part of the generated hot electrons into the silicon nitride film 105 which is a charge storage film on the memory gate 101 side. Generally, this phenomenon is known as source-side hot electron injection (SSI-HE injection).

  Here, in the present embodiment, the write operation of the memory cell MC uses multi-stage write performed by setting the write voltage and pulse time as shown in the table of FIG. 8, and is applied to the memory gate 101 at every step. Increase the voltage to be applied. As a result, electrons can be widely distributed in the silicon nitride film 105 under the memory gate 101, and the write characteristics can be improved and the electron retention characteristics after writing can be improved.

  In the erase operation, 0V is applied to the selection gate 102, a negative potential is applied to the memory gate 101, 0V is applied to the well 108, a positive potential higher than the power supply voltage is applied to the semiconductor region 106 (source), and a power supply voltage Vdd is applied to the semiconductor region 107 (drain). As a result, by causing strong inversion in a region where the memory gate 101 and the semiconductor region 106 (source) overlap with each other, a band-to-band tunneling phenomenon can occur and holes can be generated. In this memory cell MC, the generated holes are accelerated in the channel direction, attracted by the electric field from the memory gate 101, and injected into the silicon nitride film 105, thereby performing an erase operation. That is, erasing is performed by lowering the threshold value of the memory gate 101 that has been raised by hot electron injection by hole injection. Generally, this phenomenon is known as interband induced hot hole injection (BTBT-HH injection).

  FIG. 9 is a flow chart of a sequence showing the erase operation of the memory cell MC in the present embodiment. The feature of this sequence is to solve the problem found by the present inventors, that is, electrons are transferred to the silicon nitride film 105 (charge storage film) on the semiconductor region 106 (source) side and silicon nitride on the select gate 102 side. In order to alleviate the mismatch in which holes are localized and distributed in the film 105 (charge storage film), a pulse for applying a positive potential only to the selection gate 102 after the erase pulse application and before the erase verify (hereinafter referred to as relaxation). (Referred to as a pulse).

  FIG. 10 shows a difference between before and after applying a positive voltage relaxation pulse to the selection gate 102 with respect to a mismatch in electron and hole distribution accompanying rewriting of the memory cell MC. FIG. 10A shows the charge distribution before the relaxation pulse is applied, and FIG. 10B shows the charge distribution after the relaxation pulse is applied. In FIG. 10, hatching is not added to make the drawing easy to see.

  Before the positive voltage pulse is applied to the selection gate 102, as shown in FIG. 10A, the holes are on the side of the selection gate 102 in the silicon nitride film 105, which is a charge storage film, and the selection gate 102 and the memory. The electrons are distributed in the stacked insulating film region that insulates the gate 101, and the electrons are distributed on the semiconductor region 106 (source) side in the silicon nitride film 105. That is, holes are distributed more than electrons on the selection gate 102 side of the silicon nitride film 105 as a charge storage film.

  In this state, as shown in FIG. 10B, after the erase pulse is applied and before the erase verify, the selection gate 102 has a positive voltage relaxation pulse, and the memory gate 101 has a voltage lower than the positive voltage of the relaxation pulse (for example, 0 V). Is applied, the holes distributed in the region on the selection gate 102 side are moved to the semiconductor region 106 (source) side to combine electrons and holes. Thereby, the mismatch of electron and hole distribution can be relieved. In particular, when the memory gate length is 40 nm as in the present embodiment due to scaling or the memory cell MC with a memory gate length shorter than that is left, the electrons / electrons in the silicon nitride film 105 (charge storage film) are left untreated. The movement of holes can be reduced, and the diffusion of holes into the region where the selection gate 102 and the memory gate 101 are insulated can be suppressed.

  Thus, in a state where holes (positive charges) are distributed more than electrons (negative charges) on the selection gate 102 side of the silicon nitride film 105 which is a charge storage film, the electronic circuit such as the control circuit 1 is selected. A positive voltage is applied to the gate 102 and a voltage lower than the positive voltage is applied to the memory gate 101 to control the coupling between holes and electrons.

  Specifically, in the erase operation of the memory cell MC controlled by the electronic circuit such as the control circuit 1 in the present embodiment, FIG. 11 shows an example of the multi-stage erase voltage condition and the pulse time setting.

  In this erase operation, first, the voltage applied to the memory gate 101 and the semiconductor region 106 (source) is increased every time the erase step is performed (Steps 1 to 7). By this multi-stage erase pulse, when a large negative voltage is applied to the memory gate 101 and a large positive voltage is applied to the semiconductor region 106 (source) in the initial stage of erasure (a situation where electrons exist in the charge storage film), the multi-stage erase pulse is effective due to the presence of electrons. By increasing the negative voltage of the typical memory gate 101, a large amount of holes are generated and injected, and the charge storage film is deteriorated. In addition, since a large current necessary for generating a large amount of holes flows between the semiconductor region 106 (source) and the well 108, a large power supply is required according to the large current. Can be generated. Further, when erasing progresses and holes are accumulated in the charge storage film, the negative voltage to the memory gate 101 is suppressed due to the presence of holes, so that generation / injection of holes is suppressed and the erasing speed is reduced. With the erase pulse, holes can be generated and injected efficiently.

  Subsequently, Step 8 is performed. The pulse condition for applying a positive voltage only to the selection gate 102 is the above-described relaxation pulse for moving the hole distribution. As a result of investigations by the inventors, it has been clarified that the effect of the relaxation pulse can be expected by increasing the applied voltage and setting the application time to 10 μs or more. In this embodiment, since the selection gate 102 is connected to a low-voltage power supply circuit, the applied voltage is preferably set to the power supply voltage Vdd (= + 1.5 V) for the convenience of circuit control.

  Subsequently, as shown in FIG. 9, the erase verify operation is performed. However, when the threshold value of the memory cell MC is not lowered to a desired erase verify level (verify Fail), Step 7, Step 8, and erase verify are performed. Is repeated until the verify is passed.

  FIG. 12 shows a timing chart of a pulse sequence from application of the erase pulse (Step 7) and relaxation pulse (Step 8) in FIG. 11 to the erase verify. The number of target cells is one cell. In the figure, time t0 to t7 are erase pulse application operations, time t7 to t10 are relaxation pulse application operations, and time t10 to t13 are erase verify operations, which are shown as Step 7, Step 8, and Step 9, respectively. The select gate 102, the memory gate 101, the well 108, the semiconductor region 106 (source), and the semiconductor region 107 (drain) are used for the erase pulse application operation, relaxation pulse application operation, and erase verify operation to the memory cell MC. Although voltages are applied, their control is performed from an electronic circuit such as the control circuit 1 electrically connected to the memory cell MC (memory array 9). Note that in the semiconductor device in this embodiment, the reference voltage is set to 0 V, and the power supply voltage Vdd is set to +1.5 V.

  First, the erase pulse application operation will be described. Note that 0 V is applied to the well 108 during the erase pulse application operation (time t0 to t7).

  At time t0, among the voltages applied to the erase pulse (Step 7), the voltages of the semiconductor region 106 (source) and the memory gate 101 are both started to rise from the reference voltage of 0V. At this time, 0 V is applied to the selection gate 102 and Vdd is applied to the semiconductor region 107 (drain). At time t1, the semiconductor region 106 (source) voltage becomes Vdd. At time t2, the voltage of the memory gate 101 becomes -7V, and at the same time, the semiconductor region 106 (source) starts to be further boosted. At time t3, the semiconductor region 106 (source) is boosted to a desired 6.5V.

  The time between time t3 and time t4 is a state in which the erase voltage is applied to both the semiconductor region 106 (source) and the memory gate 101, and the threshold value of the memory cell can be lowered by generating and injecting hot holes. it can. For example, in FIG. 11, it is 50 μs.

  The semiconductor region 106 (source) starts to fall at time t4 and is set to Vdd at time t5. At the same time, the memory gate 101 starts to fall at time t5. At time t6, the semiconductor region 106 (source) starts to fall to 0V, and at time t7, both the memory gate 101 and the semiconductor region 106 (source) become 0V.

  Subsequently, the relaxation pulse application operation will be described. During the relaxation pulse application operation (time t7 to t10), 0 V is applied to the well 108.

  At time t7, the voltage of the semiconductor region 107 (drain) starts to fall from Vdd, and is set to 0 V at time t8. At the same time, at t8, the voltage of the selection gate 102 starts to rise from 0V and is set to Vdd at time t9. The time between time t9 and t10 is the relaxation pulse application time, and 0 V is applied to each of the select gates 102 so that no current flows between the semiconductor region 106 (source) and the semiconductor region 107 (drain). A positive voltage of 0 V is applied to the memory gate 101. As a result, the holes distributed in the region on the select gate 102 side of the charge storage film (silicon nitride film 108) are moved to the semiconductor region 106 (source) side, and the effect of combining electrons and holes can be obtained (FIG. 10 (FIG. 10). b)). According to the study by the inventors, when the voltage applied to the selection gate 102 is +1.5 V of the power supply voltage and the voltage applied to the memory gate 101 is 0 V, the effect can be obtained in 10 μs or more.

  Next, the erase verify operation will be described. Note that 0 V is applied to the well 108 during the erase verify operation (time t10 to t13).

  The semiconductor region 107 (drain) starts to rise at time t10, and is set to Vdd at time t12. At time t12, the semiconductor region 107 (drain) starts to fall, and at time t13, the voltage is set to 0 V, and the erase verify operation is finished.

  A channel current is passed during a time between time t11 and t12, and the threshold value of the memory cell is determined based on the measured current amount. At this time, an electronic circuit such as the control circuit 1 applies a voltage to the select gate 102, the memory gate 101, the p-type well 108, the semiconductor region 106 (source), and the semiconductor region 107 (drain). Control is performed to measure the current flowing between the (source) and the semiconductor region 107 (drain). The control of the verify operation is an erase verify operation performed after the control of the erase operation.

  Normally, when the erase verify operation is performed on all tens of thousands of memory cells MC, the operation time is 1 μs or less. For this reason, even when the rising timing of the semiconductor region 107 (drain) is shifted and there is a time during which the positive voltage is applied to the selection gate 102 and 0 V is applied to the memory gate 101, as in the case of the relaxation pulse application before the erase verify operation. The relaxation pulse application time is extremely shorter than 10 μs or more. That is, by applying the relaxation pulse, the holes distributed in the region on the selection gate 102 side are sufficiently coupled with the electrons on the semiconductor region 106 (source) side, and the rising timing of the semiconductor region 107 (drain) is shifted. In a short time, it is considered that the effect of electron-hole combination is difficult to see. For example, it is considered that the improvement of the retention characteristic described with reference to FIG.

  In the present embodiment, the same voltage Vdd is continuously applied to the selection gate 102 by the relaxation pulse and the erase verify operation. This eliminates the time required to increase / decrease the selection gate voltage during the same operation, and allows the memory cell operation to be performed at high speed. For example, as shown in FIG. 13, even when a voltage that increases the relaxation pulse from 0 V to Vdd and applies it for 10 μs and then reduces the voltage to 0 V is applied to the selection gate 102, The above-described mismatch of charge distribution in the charge storage film can be alleviated. However, the memory cell operation can be performed at high speed by continuously applying the same Vdd to the selection gate 102 by the relaxation pulse and the erase verify operation.

  FIG. 14 shows the retention characteristics on the erase side after performing the rewrite operation according to the sequence in the present embodiment as compared with the case where no relaxation pulse is applied. FIG. 14 shows retention characteristics when rewriting is performed 30000 times at room temperature and then left at room temperature. It can be seen that the retention characteristic is improved by about 0.1 V when left for about 10 hours when the relaxation pulse shown in (b) is present, compared to the case without the relaxation pulse shown in (a) in the figure. . As described above, after the erase pulse is applied and before the erase verify, Vdd is applied to the select gate 102 and 0 V is applied to the memory gate 101 to apply the holes distributed in the region on the select gate 102 side to the semiconductor. This is because the mismatch between the electrons and the hole distribution is mitigated by moving to the region 106 (source) side to combine the electrons and holes. Thus, the reliability of the semiconductor device can be improved by improving the retention characteristics.

(Embodiment 2)
In the second embodiment, a case where a selective gate positive voltage pulse is applied collectively in a plurality of blocks will be described. The configuration of the memory module, the block configuration of the memory array, and the memory cell structure are the same as those in the first embodiment.

  FIG. 15 shows the multistage erase voltage conditions according to the second embodiment. Here, as shown in FIG. 3, the memory array 9 is assumed to be divided into 8 blocks, and it is assumed that four blocks are erased simultaneously. In FIG. 15, Step 1 and Step 2 apply the erase pulse only to the block: A0. As described above, this is because, in the initial stage of erasing, a large current flows between the semiconductor region 106 (source) and the well 108 (silicon substrate 100) due to the influence of electrons in the silicon nitride film 105, and the power supply capability deteriorates. This is to suppress this. As erasure progresses as in Steps 9 to 11, since the current between the semiconductor region 106 (source) and the well 108 (silicon substrate 100) at the time of erasing pulse application decreases, the same erasing pulse is applied across a plurality of blocks. However, the power supply capacity is not deteriorated.

  Step 12 is the voltage condition of the relaxation pulse. Since the voltage applied to the electrodes other than the selection gate 102 is 0 V, no current flows through the channel. Therefore, the power consumed by the relaxation pulse is small, and the relaxation pulse can be applied to the selection gates 102 of a plurality of blocks. Furthermore, since the relaxation pulses can be applied to the selection gates 102 at a time, the erase speed seen by the module should be the same as the multi-stage erase condition of the first embodiment even if the applied pulse width is increased. Is possible.

  FIG. 16 shows the dependency of the relaxation characteristics on the erase side after the rewrite operation on the applied pulse width of the relaxation pulse. (A) No relaxation pulse, (b) Relaxation pulse (1.5 V, 10 us) applied, (c) Relaxation pulse (1.5 V, 30 us) applied, (d) Relaxation pulse (1.5 V, 100 us) Applied. As is apparent from the figure, by increasing the pulse width, the effect of relaxing the mismatch of the charge distribution is increased, and the retention characteristics are improved.

(Embodiment 3)
In the third embodiment, a case where a voltage higher than the power supply voltage Vdd is applied to the selection gate 102 when the relaxation pulse is applied will be described. The configuration of the memory module, the block configuration of the memory array 9 and the structure of the memory cell MC are the same as those of the first embodiment. However, as the circuit of the selection gate 102, for example, as shown in FIG. A selector of voltage (V1> Vdd) is provided, and a circuit for driving the driver of the selection gate 102 is added via the selector, so that a voltage higher than Vdd can be applied. A similar circuit is also added to the circuit for supplying power to the semiconductor region 107 (drain) in FIG. 7, and a voltage of Vdd or higher can be applied to the semiconductor region 107 (drain).

  However, when a high voltage is applied to the select gate 102, the same voltage is also applied to the semiconductor regions 106 (source) and 107 in the structure of the memory cell MC shown in FIG. Thus, it is necessary to reduce the electric field (difference between the voltage applied to the selection gate 102 and the channel potential) applied to the gate insulating film (silicon oxide film 109).

  FIG. 18 shows a timing chart of a pulse sequence from the application of the erase pulse and the relaxation pulse to the erase verify in the third embodiment. However, the multi-stage erase condition is the same as in FIG. 11 and the number of target cells is 1 cell. Further, in FIG. 18, the time t0 to t7 in FIG. 18 is the erase pulse application operation, the time t7 to t11 is the relaxation pulse application operation, and the time t11 to t15 is the erase verify operation.

  First, the erase pulse application operation is controlled by an electronic circuit such as the control circuit 1. At time t 0, among the voltages applied to the erase pulse (Step 7 in FIG. 11), the voltages of the semiconductor region 106 (source) and the memory gate 101 start to rise from 0 V, which is the base voltage. At this time, the selection gate 102 voltage is 0V, and the semiconductor region 107 (drain) voltage is 1.5V. At time t1, the semiconductor region 106 (source) voltage becomes 1.5V. At time t2, the voltage of the memory gate 101 becomes -7V, and at the same time, the semiconductor region 106 (source) starts to be further boosted. At time t3, the semiconductor region 106 (source) is boosted to a desired 6.5V.

  The time between time t3 and time t4 is a state in which the erase voltage is applied to both the semiconductor region 106 (source) and the memory gate 101, and the threshold value of the memory cell can be lowered by generating and injecting hot holes. it can. For example, in FIG. 11, it is 50 μs.

  The semiconductor region 106 (source) starts to fall at time t4 and is set to 1.5 V at time t5. At the same time, the memory gate 101 starts to fall at time t5. At time t6, the semiconductor regions 106 (source) and 107 start to fall to 0V, and at time t7, both the memory gate 101 and the semiconductor regions 106 (source) and 107 become 0V.

  Subsequently, the relaxation pulse application operation is controlled by an electronic circuit such as the control circuit 1. At time t8, the voltage of the selection gate 102 and the semiconductor regions 106 (source) and 107 starts to fall from 0V, and is set to V1 (V1> Vdd) at time t9. The time between time t9 and t10 is the time during which the relaxation pulse is applied, and according to the study by the inventors, the effect can be obtained at 10 μs or more. Thus, if no current flows between the semiconductor region 106 (source) and the semiconductor region 107 (drain), 0 V is applied to the p-type well 108 and a positive voltage V1 is applied to the semiconductor region 106 (source). The operation of relaxing pulse application may be controlled by applying V1 having the same positive voltage as that of the semiconductor region 106 (source) to the semiconductor region 107 (drain).

  Subsequently, the erase verify operation is controlled by an electronic circuit such as the control circuit 1. At time t10, the selection gate 102 and the semiconductor regions 106 (source) and 107 start to be depressurized. At time t11, the selection gate 102 is set to Vdd, and the semiconductor regions 106 (source) and 107 are set to 0V. The semiconductor region 107 (drain) starts to rise at time t12, and is set to Vdd at time t13.

  A channel current is passed during a time between time t13 and t14, and the threshold value of the memory cell is determined based on the amount of current. Usually, the time is 1 microsecond or less. At time t14, the semiconductor region 107 (drain) starts to fall, and at time t15, the voltage is set to 0 V, and the erase verify operation is finished.

  FIG. 19 shows the dependency of the relaxation characteristics on the erase side after the rewrite operation on the selection gate applied voltage of the relaxation pulse. In the figure, (a) no relaxation pulse, (b) relaxation pulse (1.5 V, 10 us) applied, (c) relaxation pulse (2.5 V, 10 us) applied. As is apparent from the figure, by increasing the applied voltage, the effect of reducing the mismatch of the charge distribution is increased, and the retention characteristics are improved.

  Further, as described in the second embodiment, it is possible to apply a relaxation pulse to a plurality of blocks of CG at the same time, and it goes without saying that the same effect as the effect disclosed in the second embodiment can be obtained. Yes.

(Embodiment 4)
In the fourth embodiment, a case will be described in which the present invention is applied to a memory cell that is operated by injecting and releasing charges into nano-sized fine particles formed of silicon or the like instead of a charge storage film. FIG. 20 shows a cross-sectional view of the memory cell in the fourth embodiment. In the figure, the nano-sized fine particles 405 are formed as a single layer, but by forming the nano-sized fine particles multiple times to increase the density of the fine particles, accumulating more charges and expanding the memory operation margin. Is also possible.

  In the memory cell operation of the fourth embodiment, if the source side injection method of hot electrons is used for writing and the hot hole injection method induced by band-to-band tunneling is used for erasing, the electron / hole injection positions are different, and thus the charge distribution. The mismatch will occur. As a result, if the memory cell is left in the erased state, the threshold value of the memory cell increases due to the tunnel diffusion of charges between the nano-sized fine particles.

  However, by applying the present invention described in the first to third embodiments, it is possible to alleviate the mismatch of the charge distribution, suppress an increase in memory cell threshold value, and improve reliability. Become.

(Embodiment 5)
In the fifth embodiment, a case where the present invention is applied to a so-called twin MONOS type memory cell in which memory gates exist on both sides of a selection gate will be described. FIG. 21 shows a cross-sectional view of a memory cell of the nonvolatile semiconductor memory device according to the fifth embodiment. The memory operation will be described for the case where the memory gate 101A (101) in FIG. In the first to fourth embodiments, the semiconductor region 106 is described as a source and the semiconductor region 107 is a drain. However, in the fifth embodiment, the semiconductor region 106 is a source or a drain and the semiconductor region 107 is a drain depending on the operation. Or become a source.

  The memory cell operation method and applied voltage conditions of the fifth embodiment are the same as those of the first to fourth embodiments, hot electron source side injection method for writing, and hot hole injection method induced by band-to-band tunneling for erasing. Is used. However, it is necessary to pass the voltage of the semiconductor region 107 by applying a pass voltage (Vpass) of about 5 V, for example, to the memory gate 101B (101), which is a non-selected bit during the read operation and the write operation. In the erase operation, 0 V is applied to the gate.

  Therefore, also in the memory cell of the fifth embodiment, electron / hole distribution mismatch occurs in the write / erase operation. Therefore, by applying a positive voltage mismatch relaxation pulse to the select gate 102 after the erase pulse and before the erase verify operation, the reliability of the memory cell can be improved as in the first to fourth embodiments. Is possible.

(Embodiment 6)
FIG. 22 is a schematic diagram showing a plane of the memory array 9 in the sixth embodiment, and FIG. 23 is a schematic diagram showing a cross section of a plurality of memory cells MC constituting the memory array 9.

  The semiconductor device according to the sixth embodiment includes a memory array 9 and an electronic circuit such as the control circuit 1 electrically connected to the memory array 9 as shown in FIG. Although not shown, a power supply line for supplying a reference voltage to an electronic circuit such as the memory array 9 and the control circuit 1 and a power supply line for supplying a power supply voltage are also electrically connected. Note that in the semiconductor device in this embodiment, the reference voltage is 0 V and the power supply voltage Vdd is 1.5 V.

  The planar layout of the memory array 9 is such that a plurality of memory cells MC are provided in a matrix along the X direction of the main surface of the semiconductor substrate and the Y direction intersecting therewith, as shown in FIG. Yes. A memory gate 601 extending in the X direction is configured as a word line, and an n-type semiconductor region 606 (diffusion layer, source of the memory cell MC) extending in the X direction is configured as a source line, extending in the X direction. A wiring 611 extending in the Y direction and electrically connected to the n-type semiconductor region 607 (diffusion layer, drain of the memory cell MC) via the contact 610 is configured as a bit line.

  Memory cell MC in the sixth embodiment is a so-called NROM as shown in FIG. This NROM has a well 608 which is a p-type semiconductor region provided on the main surface of a silicon substrate 600 which is a semiconductor substrate, and a gate electrode which is provided on the well 608 via a laminated insulating film including a charge storage film. A memory gate 601.

  The stacked insulating film between the well 608 and the memory gate 601 has a silicon nitride film 605 that is a charge storage film in which charges of electrons and holes having different polarities are stored under the memory gate 601, and a silicon oxide film 603. The silicon nitride film 605 is sandwiched between the silicon oxide film 604 and the silicon oxide film 604.

  Further, the memory cell MC is provided in the well 608 so as to sandwich a region (channel region) where a channel is formed under the memory gate 601, and an n-type semiconductor region 606 (source) and an n-type semiconductor region 607 (drain) are provided. Have.

  The n-type semiconductor regions 606 and 607 (source / drain) are provided between the silicon nitride films 605 that are charge storage films. In other words, the silicon nitride film 605 that is a charge storage film is provided between the n-type semiconductor region 606 (source) and the n-type semiconductor region 607 (drain). The sixth embodiment is characterized in that the n-type semiconductor regions 606 and 607 are stacked up to a position higher than the charge storage film 605. The stacked n-type semiconductor regions 606 and 607 can be formed by, for example, processing the memory gate 601 and then ion-implanting it after stacking silicon by vapor phase epitaxial growth or the like. In the sixth embodiment, the silicon nitride film 605 that is a charge storage film is formed from the silicon substrate 600 so as to be between the n-type semiconductor region 606 (source) and the n-type semiconductor region 607 (drain). Although the case where the source / drain is configured by stacking has been described, a groove may be formed in the silicon substrate 600, and the memory gate 601 may be provided in the groove via a stacked film including a charge storage film.

  Next, an example of three operations of reading, writing, and erasing will be described as the basic operation of the memory cell MC.

  In a read operation, a positive potential (Vdd) is applied to the n-type semiconductor region 607, and in this state, an appropriate memory gate potential (for example, 3.5 V) that can determine the threshold difference of the memory gate 601 provided by the write / erase state is applied. By applying the voltage, a current flows through the channel of the memory gate 601 in the write state, and a current hardly flows through the channel of the memory gate 601 in the erased state. Therefore, the write / erase state of the memory cell can be determined based on the amount of current flowing through the channel of the memory gate 601.

  At the time of writing operation, a positive potential is applied to the n-type semiconductor region 606 that becomes a source at the time of reading. By applying a high gate overdrive voltage to the memory gate 601, the channel below the memory gate 601 is turned on. The voltage applied to the n-type semiconductor region 607 is controlled so that a current of about 30 μA flows through the channel. Under this voltage condition, the energy of electrons in the current flowing through the channel increases, and a part of the energy is injected into the silicon nitride film 605 that is a charge storage film on the n-type semiconductor region 606 side (channel hot electron writing method). The threshold value of the memory cell MC increases.

  In the cell operation, multi-stage writing is used as shown in FIG. 24, and the voltage applied to the memory gate 601 is increased every step. This is because as the writing progresses, the voltage applied to the write memory gate 601 is weakened due to the influence of electrons injected into the silicon nitride film 605, so that the write speed deteriorates when the same voltage is applied.

  During the erase operation, a negative potential is applied to the memory gate 601 and a positive potential is applied to the n-type semiconductor region 606. As a result, by causing strong inversion in a region where the memory gate 601 and the n-type semiconductor region 606 overlap with each other, a band-to-band tunneling phenomenon can occur and holes can be generated. In this memory cell MC, the generated holes are accelerated in the channel direction, attracted by the electric field from the memory gate 601 and injected into the silicon nitride film 605, thereby performing an erase operation. That is, erasing is performed by lowering the threshold value of the memory gate 601 that has been raised by hot electron injection by hole injection.

  FIG. 25 shows an example of multi-stage erase voltage conditions and pulse time settings according to the sixth embodiment. In the sixth embodiment, similarly to the first to fifth embodiments, the multi-stage erase pulse is used during the erase operation. Further, Vdd is applied to the diffusion layer 607 during the erase operation.

  FIG. 26 shows a timing chart of a pulse sequence from application of the erase pulse (Step 7) and mismatch relaxation pulse (Step 8) in FIG. 25 to erasure verification (Step 9). The number of target cells is one cell. In the figure, time t0 to t7 are erase pulse application operations, time t7 to t11 are relaxation pulse application operations, and time t10 to t15 are erase verify operations.

  The erase pulse operation will be described. At time t0, among the voltages applied to the erase pulse (Step 7), the voltages of the n-type semiconductor region 606 and the memory gate 601 start to rise from 0 V which is the base voltage. At this time, the voltage of the n-type semiconductor region 607 is Vdd. At time t1, the voltage of the n-type semiconductor region 606 becomes 1.5V. At time t2, the voltage of the memory gate 601 becomes -7V, and at the same time, the n-type semiconductor region 606 starts to be further boosted. At time t3, the n-type semiconductor region 606 is boosted to a desired 6.5V.

  The time between time t3 and time t4 is a state in which the erase voltage is applied to both the n-type semiconductor region 606 and the memory gate 601, and the threshold value of the memory cell can be lowered by generating and injecting hot holes. . For example, in FIG. 25, it is 50 μs.

  The n-type semiconductor region 606 starts to fall at time t4 and is set to Vdd at time t5. At the same time, the memory gate 601 starts to fall at time t5. At time t6, the n-type semiconductor regions 606 and 607 start to fall to 0V, and at time t7, both the memory gate 601 and the n-type semiconductor regions 606 and 607 become 0V.

  Subsequently, the relaxation pulse operation will be described. At time t8, the voltage of the n-type semiconductor regions 606 and 607 starts to rise and is set to Vdd at time t9. The time between time t9 and t10 is the relaxation pulse application time, and according to the study by the inventors, the effect is obtained in 10 μs or more.

  Next, the erase verify operation will be described. The n-type semiconductor regions 606 and 607 are lowered at time t10, and are set to 0 V at time t11.

  At time t11, the memory gate 601 starts to rise, and at time t12, the read voltage is set to about 3.5V. At the same time, the voltage applied to the diffusion layer 607 starts to rise at time t12, and is set to Vdd at time t13.

  A channel current is passed during a time between time t13 and t14, and the threshold value of the memory cell MC is determined based on the amount of current. Usually, the time is 1 μs or less. At time t14, the n-type semiconductor region 607 starts to fall, and at time t15, the voltage is set to 0 V, and the erase verify operation is finished.

  By performing the rewriting operation according to such a sequence, the same effect as in the first embodiment can be obtained for the improvement of the retention characteristics.

  In the memory cell of the sixth embodiment, it is needless to say that the effect of improving the retention characteristics can be increased by increasing the relaxation pulse time and increasing the relaxation pulse applied voltage by the method disclosed in the second and third embodiments. There is no.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the case where the memory gate length is 40 nm has been described. However, even in the case of a memory cell having a memory gate length longer than 40 nm (FIGS. 1A to 1C), after the erase pulse is applied, By applying a relaxation pulse before erasure verification, the mismatch between electron and hole distribution can be relaxed. In that case (see FIG. 1C), electrons are distributed more than holes on the side of the selection gate 52 of the charge storage film 55. Therefore, a negative voltage relaxation pulse is applied to the selection gate 52 and a relaxation pulse is applied to the memory gate 51. This is because by applying a voltage (for example, 0 V) higher than the voltage, electrons distributed in the region on the selection gate 52 side can be moved to the source 56 side to combine the electrons and holes.

  The present invention is suitable for use in a semiconductor device, in particular, a memory device for an embedded microcomputer for consumer use, OA, in-vehicle use, industrial use, and the like.

FIG. 6 is a schematic diagram for explaining a mismatch in charge distribution in memory cells when the memory gate length is long (a) to (c) and when the memory gate length is short (d) to (f). 1 is a block diagram of a semiconductor device including a memory array according to an embodiment of the present invention. FIG. 3 is a block diagram of the memory array of FIG. 2. FIG. 3 is an equivalent circuit diagram of the memory array of FIG. 2. FIG. 3 is a schematic diagram showing a plane of the memory array of FIG. 2. FIG. 6 is a schematic diagram illustrating a cross section taken along lines A-A ′, B-B ′, C-C ′, and D-D ′ in FIG. 5. It is a schematic diagram which shows the cross section of the memory cell in one embodiment of this invention. 8 is a table showing write operation conditions of the memory cell of FIG. FIG. 8 is a sequence flowchart showing an erase operation of the memory cell of FIG. 7. It is a schematic diagram for demonstrating the electric charge distribution of the memory cell before and behind a relaxation pulse application, (a) Before application, (b) After application is shown. 8 is a table showing erase operation conditions in the memory cell of FIG. 7. FIG. 8 is a timing chart of a pulse sequence in the order of erase pulse, relaxation pulse, and erase verify in the memory cell of FIG. 7. It is a timing chart which shows the modification of the pulse sequence shown in FIG. It is explanatory drawing of the retention characteristic which made the parameter the presence or absence of the relaxation pulse. It is a table | surface which shows the erase operation conditions in other embodiment of this invention. It is explanatory drawing of the retention characteristic which made the application time of the relaxation pulse a parameter. It is a block diagram of the principal part of the semiconductor device in other embodiment of this invention. 18 is a timing chart of an erase pulse, a relaxation pulse, and a pulse sequence in the erase verify order in a memory cell using the selector of FIG. It is explanatory drawing of the retention characteristic which used the applied voltage of the relaxation pulse as a parameter. It is a schematic diagram which shows the cross section of the memory cell in other embodiment of this invention. It is a schematic diagram which shows the cross section of the memory cell in other embodiment of this invention. It is a schematic diagram which shows the plane of the memory array in other embodiment of this invention. FIG. 23 is a schematic diagram showing a cross section of the memory cell of FIG. 22; 24 is a table showing write operation conditions in the memory cell of FIG. 24 is a table showing erase operation conditions in the memory cell of FIG. FIG. 24 is a timing chart of an erase pulse, a relaxation pulse, and a pulse sequence in the erase verify order in the memory cell of FIG. 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control circuit 2 Input / output circuit 3 Address buffer 4 Row decoder 5 Column decoder 6 Verify sense amplifier circuit 7 High-speed read sense amplifier circuit 8 Rewrite circuit 9 Memory array 10 Power supply circuit 11 Current trimming circuit 12 Block 100 Silicon substrate (semiconductor substrate)
101, 101A, 101B Memory gate 102 Select gate 103, 104 Silicon oxide film 105 Silicon nitride film (charge storage film)
106 n-type semiconductor region 107 n-type semiconductor region 108 p-type well (p-type semiconductor region)
109 Silicon oxide film (gate insulating film)
110 Contact 111 Wiring 405 Nano-sized fine particle 600 Silicon substrate (semiconductor substrate)
601 Memory gate 603 Silicon oxide film 604 Silicon oxide film 605 Silicon nitride film 606 n-type semiconductor region 607 n-type semiconductor region 608 p-type well 610 contact 611 wiring MC memory cell Qc selection transistor Qm memory transistor

Claims (13)

A memory array composed of a plurality of nonvolatile memory cells provided in a matrix along the first direction of the main surface of the semiconductor substrate and the second direction intersecting therewith,
An electronic circuit electrically connected to the memory array;
A semiconductor device comprising:
The nonvolatile memory cell is
A first semiconductor region of a first conductivity type provided on the main surface of the semiconductor substrate;
A first gate provided on the first semiconductor region via a first insulating film;
A second insulating film provided along a side wall of the first gate and the first semiconductor region;
A second gate provided adjacent to the first gate on the first semiconductor region via the second insulating film;
A second conductivity type second semiconductor region and a third semiconductor region provided in the first semiconductor region so as to sandwich the channel region under the first gate and the second gate, and opposite to the first conductivity type; ,
A field effect transistor having
The second insulating film is
A charge storage film for storing a first charge of a first polarity and a second charge opposite to the first polarity under the second gate;
The electronic circuit is
A voltage is applied to the first gate, the second gate, the first semiconductor region, the second semiconductor region, and the third semiconductor region, and the first charge or the second charge is applied to the charge storage film. Having a first control to inject, and
In a state where the first charge is distributed more than the second charge on the first gate side of the charge storage film, the first voltage having the first polarity is applied to the first gate, and the second gate is applied. And a second control that applies a second voltage lower than the first voltage to combine the first charge and the second charge. The semiconductor device according to claim 1,
The electronic circuit applies a voltage to the first gate, the second gate, the first semiconductor region, the second semiconductor region, and the third semiconductor region, so that the second semiconductor region and the third semiconductor are applied. A semiconductor device, further comprising a third control for measuring a current flowing between the regions, wherein the third control is performed after the second control is performed. The semiconductor device according to claim 1,
A reference voltage is applied to the first semiconductor region, a third voltage different from the reference voltage is applied to the second semiconductor region, a fourth voltage that is the same as the third voltage is applied to the third semiconductor region, and A semiconductor device characterized in that second control is performed. The semiconductor device according to claim 1,
A semiconductor device characterized in that the time for performing the second control is 10 μs or more. The semiconductor device according to claim 1,
The plurality of nonvolatile memory cells are divided into a plurality of blocks,
The electronic circuit performs the second control collectively on the plurality of blocks. The semiconductor device according to claim 1,
A semiconductor device characterized in that the gate length of the second gate is 40 nm or less. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first voltage is higher than a power supply voltage. The semiconductor device according to claim 1,
The electronic circuit includes a selector that selects one of a plurality of different voltage sources when the first voltage is applied to the first gate. The semiconductor device according to claim 1,
The semiconductor device, wherein the charge storage film is a silicon nitride film. The semiconductor device according to claim 1,
The semiconductor device, wherein the charge storage film is nano-sized fine particles. The semiconductor device according to claim 1,
The first gate is provided extending in the first direction,
The semiconductor device according to claim 1, wherein the second gate is provided on both side walls of the first gate so as to extend in the first direction. A memory array composed of a plurality of nonvolatile memory cells provided in a matrix along the first direction of the main surface of the semiconductor substrate and the second direction intersecting therewith,
An electronic circuit electrically connected to the memory array;
A first power supply line for supplying a reference voltage to the memory array and the electronic circuit;
A second power supply line for supplying a power supply voltage to the memory array and the electronic circuit;
A semiconductor device comprising:
The nonvolatile memory cell is
A p-type first semiconductor region provided on the main surface of the semiconductor substrate;
A first gate provided on the first semiconductor region via a first insulating film;
A second insulating film provided along a sidewall of the first gate and the first semiconductor region and including a charge storage film;
A second gate provided adjacent to the first gate on the first semiconductor region via the second insulating film;
An n-type second semiconductor region and a third semiconductor region provided in the first semiconductor region so as to sandwich a channel region under the first gate and the second gate;
A field effect transistor having
The electronic circuit is
The reference voltage is applied to the first semiconductor region, the reference voltage is applied to the first gate, a negative voltage with respect to the reference voltage is applied to the second gate, and the reference is applied to the second semiconductor region. A first control for applying a positive voltage to the voltage and applying a power supply voltage to the third semiconductor region;
The reference voltage is applied to the first semiconductor region, a positive voltage is applied to the first gate with respect to the reference voltage, the reference voltage is applied to the second gate, and the reference is applied to the second semiconductor region. A second control for applying a voltage and applying a reference voltage to the third semiconductor region;
Applying the reference voltage to the first semiconductor region; applying the power supply voltage to the first gate; applying the reference voltage to the second gate; applying the reference voltage to the second semiconductor region; A third control for applying a positive voltage to a reference voltage to the third semiconductor region;
Have
A voltage is applied to each of the first gate, the second gate, the first semiconductor region, the second semiconductor region, and the third semiconductor region in the order of the first control, the second control, and the third control. Is applied to the semiconductor device. A memory array composed of a plurality of nonvolatile memory cells provided in a matrix along the first direction of the main surface of the semiconductor substrate and the second direction intersecting therewith,
An electronic circuit electrically connected to the memory array;
A semiconductor device comprising:
The nonvolatile memory cell is
A first semiconductor region of a first conductivity type provided on the main surface of the semiconductor substrate;
A gate provided on the first semiconductor region via an insulating film;
A second semiconductor region and a third semiconductor region which are provided in the first semiconductor region so as to sandwich the channel region under the gate and which are opposite to the first conductivity type;
A field effect transistor having
The insulating film is
Under the gate, there is a charge storage film in which a first charge having a first polarity and a second charge opposite to the first polarity are stored,
Provided between the second semiconductor region and the third semiconductor region;
The electronic circuit is
First control for injecting the first charge or the second charge into the charge storage film by applying a voltage to the first gate, the first semiconductor region, the second semiconductor region, and the third semiconductor region. In addition,
In a state where the first charge is distributed more than the second charge on the second semiconductor region side of the charge storage film, the first voltage having the first polarity is applied to the second semiconductor region, and the gate And a second control that applies a second voltage lower than the first voltage to combine the first charge and the second charge.

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