JP2009116962A - Ddr memory system provided with odt control function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize a signal reflection in a simple configuration in a DDR memory system configured with chip selects having different data bus widths. <P>SOLUTION: The DDR (Double Data Rate) memory system is equipped with a function to control ODT (On Die Termination) for each chip select and is further equipped with: a memory controller; a first chip select to be selected by a first chip select signal from the memory controller; a second chip select which is selected by a second chip select signal from the memory controller and has data bus width larger than that of the first chip select; a first data bus for connecting the memory controller with the second chip select and the first chip select; and a second data bus for connecting the memory controller with the second chip select and further with a terminating resistor which is mounted on a substrate in advance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination).

  In the DDR2 system defined by JEDEC (Joint Electron Device Engineering Council), DRAM has a termination resistor that can be turned on / off for each terminal (DQ: data input / output, DQS, / DQS: differential data strobe, DM: write data mask). By holding it inside and controlling it with an ODT signal, signal reflection is reduced to ensure signal quality, and high-speed data transfer of DDR2 is realized. The impedance value of the termination resistor can be selected from one of ODT non-selected (off: infinity), ODT selected (50Ω), ODT selected (75Ω), and ODT selected (150Ω).

  However, the control method standardized by JEDEC is defined only by a system having the same data bus width for each chip select (each data area). On the other hand, the ODT signal is a signal interlocked with the chip select signal, and is one for each chip select. Therefore, in a system in which the data bus width varies depending on the chip select, ON / OFF of the termination resistance in the DRAM by ODT control is not successful, and a signal quality problem occurs due to the influence of signal reflection. A high-speed data transfer system requires a high-quality signal, and even a small amount of noise is a big problem for the system.

  An object of the present invention is to minimize signal reflection with a simple configuration in a DDR memory system configured by chip select having different data bus widths.

A first aspect of the present invention is a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select,
A memory controller;
A first chip select selected by a first chip select signal from the memory controller;
A second chip select selected by a second chip select signal from the memory controller and having a data bus width larger than the first chip select;
A first data bus connecting the memory controller, the second chip select, and the first chip select;
A second data bus connecting the memory controller and the second chip select and connecting to a termination resistor mounted in advance on the substrate;
Is provided.

  The first chip select may be composed of a DDR chip mounted in advance on the substrate, and the second chip select may be composed of a detachable DDR chip mounted in a slot on the substrate.

A second aspect of the present invention is a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select,
A memory controller;
Multiple chip select with different data bus widths,
A plurality of data buses connecting the memory controller and the chip select;
A termination resistor mounted in advance on the substrate, connected to a data bus not connected to at least one of the plurality of chip select.

  According to the present invention, in a DDR memory system configured by chip select having different data bus widths, signal reflection can be minimized with a simple configuration.

  Prior to describing embodiments of the present invention, for the sake of easy understanding, first, conventional problems will be described with specific examples.

  FIG. 2 (Table 1) shows an ODT control matrix at the time of read / write data transmission defined by JEDEC. Table 1 shows the standard value (specified value) of the ODT resistor for each configuration of the DDR memory system.

  “SR (single rank)” means a configuration in which a memory chip is mounted on the front side. “DR (dual rank)” means a configuration in which memory chips are mounted on the front side and the back side.

  FIG. 3 is a diagram illustrating an example of the configuration of the memory system.

  The memory system in FIG. 3A includes a DDR controller (“ASIC” in Table 2) 30, slot 1, slot 2, and data bus 31.

  DDR chips 11 and 12 having an ODT function are mounted in the slot 1 and the slot 2, respectively.

  The slot 1 corresponds to a chip select selected by a chip select signal CS_1 from the DDR controller 30. The slot 2 corresponds to a chip select selected by a chip select signal CS_2 from the DDR controller 30.

  The data bus 31 is a data transmission / reception transmission path, and connects the DDR controller 30, the slot 2, and the slot 1.

  In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. When the ODT control as defined in the table of FIG. 2 is performed (see thick line frame F1), the ODT resistance (impedance value of the termination resistor) of the DDR chip 11 in the slot 1 becomes “75Ω”, and the ODT of the DDR chip 21 in the slot 2 The resistance is “off (non-selected)”.

  The memory system in FIG. 3B has a configuration similar to that in FIG. 3A, but there is no DDR chip in slot 1. In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 2. When the ODT control as defined in the table of FIG. 2 is performed (see the thick frame F2), the ODT resistance of the DDR chip 21 in the slot 2 becomes “off”.

  Next, as shown in FIG. 4, a memory system composed of chip select having different data bus widths is considered.

  The memory system in FIG. 4 includes a DDR controller 30, a slot 1, a slot 2, and a data bus 31, as in FIG. However, in addition to the DDR chip 21, the DDR chip 22 is mounted in the slot 2.

  That is, slot 1 and slot 2 have different data bus widths, and slot 2 has a larger data bus width.

  The data bus 31 is divided into a data bus group A and a data bus group B. The data bus group A connects the DDR controller 30, the DDR chip 21 in the slot 2, and the DDR chip 11 in the slot 1. On the other hand, the data bus group B connects the DDR controller 30 and the DDR chip 21 in the slot 2 and is not connected to the slot 1.

  The memory system in FIG. 4 can be considered as a configuration in which the DDR memory system in FIG. 3A and the DDR memory system in FIG. 3B are combined.

  In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. However, since the ODT signal is a signal linked to the chip select signal, it is sent for each slot. That is, DDR chips mounted in the same slot are subjected to the same ODT control.

  The table in FIG. 2 assumes a system with the same data bus width for each chip select (each data area), and does not assume systems with different data bus widths. Therefore, ODT control to be applied is considered for each data bus group.

  When attention is paid to the data bus group A, the configuration is the same as that of FIG. Therefore, it is assumed that the ODT control as defined for the configuration of FIG.

  When the ODT control as specified in the table of FIG. 2 is performed (see thick line frame F1), the ODT resistance of the DDR chip 11 in the slot 1 becomes “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 becomes “off”. . At this time, since the ODT control is performed for each slot, the ODT resistance of the DDR chip 22 in the slot 2 is also “off”.

  On the other hand, focusing on the data bus group B, the configuration is the same as that in FIG. 3B, and the DDR chip 22 should be subjected to ODT control similar to the configuration in FIG.

  In this regard, in the ODT control having the configuration shown in FIG. 3B, the ODT resistance of the DDR chip 22 should be “off”.

  That is, the ODT resistance of the DDR chip 22 is the same as when the control to be applied to the configuration of FIG. 3B is performed even if the ODT control to be applied to the configuration of FIG.

  As described above, in the case of data reading, it is understood that the ODT control as prescribed may be performed by paying attention to the data bus group connected to the slot having a small data bus width.

  Next, the case of data writing will be considered with reference to FIGS.

  The DDR memory systems of FIGS. 5A and 5B correspond to the DDR memory systems of FIGS. 3A and 3B, respectively. The DDR memory system of FIG. 6 corresponds to the DDR memory system of FIG.

  Consider the ODT control at the time of data writing to the slot 2 in the configuration of FIG.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. When the ODT control as specified in the table of FIG. 2 is performed (see thick line frame F3), the ODT resistance of the DDR chip 11 in the slot 1 becomes “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 becomes “off”. .

  When the ODT control as defined in the table of FIG. 2 is performed in the configuration of FIG. 5B (see the thick line frame F3), the ODT resistance of the DDR chip 21 in the slot 2 becomes “150Ω”.

  Next, as shown in FIG. 6, a memory system composed of chip select having different data bus widths is considered. Focusing on the data bus group A, the configuration is the same as that shown in FIG. Therefore, it is assumed that ODT control is performed as prescribed to be applied to the configuration of FIG.

  When the ODT control as specified in the table of FIG. 2 is performed (see thick line frame F3), the ODT resistance of the DDR chip 11 in the slot 1 becomes “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 becomes “off”. . At this time, since the ODT control is performed for each slot, the ODT resistance of the DDR chip 22 in the slot 2 is also “off”.

  On the other hand, focusing on the data bus group B, the configuration is the same as that in FIG. 5B, and the DDR chip 22 should be subjected to ODT control similar to the configuration in FIG. 5B.

  However, when the ODT control to be applied to the configuration of FIG. 5A is performed, the ODT resistance of the DDR chip 22 is the ODT resistance (150Ω) when the control to be applied to the configuration of FIG. Don't be. This cannot sufficiently suppress signal reflection.

  As described above, in the case of data writing, even if ODT control focusing on the data bus group A is performed, the signal reflection of the data bus group B cannot be suppressed.

  The present invention has been made to solve such problems.

FIG. 1 is a diagram showing a configuration of a DDR memory system to which an embodiment of the present invention is applied.
The DDR memory system according to the present embodiment includes a DDR controller 30, a slot 1, a slot 2, and a data bus 31 (data bus group A, data bus group B).

  The slot 1 corresponds to a chip select selected by a chip select signal CS_1 from the DDR controller 30. The slot 2 corresponds to a chip select selected by a chip select signal CS_2 from the DDR controller 30.

  In the slot 1, a DDR chip (DDR SDRAM) 11 having an ODT function is mounted. In the slot 2, in addition to the DDR chip 21 having an ODT function, a DDR chip 22 having an ODT function is mounted. All the DDR chips 11, 21, and 22 have a data bus width of 16 bits. That is, slot 1 and slot 2 have different data bus widths, and slot 2 has a larger data bus width.

  The data bus 31 is divided into a data bus group A and a data bus group B. The data bus group A connects the DDR controller 30, the DDR chip 21 in the slot 2, and the DDR chip 11 in the slot 1. On the other hand, the data bus group B connects the DDR controller 30 and the DDR chip 21 in the slot 2 and is not connected to the slot 1.

  The DDR controller 30 performs data writing and data reading with respect to the DDR chips 11, 21, and 22 in accordance with instructions from a control device (not shown) such as a CPU. Therefore, chip select signals CS_1 and CS_2 are sent to slots 1 and 2. The ODT signal for ODT control is linked to the chip select signals CS_1 and CS_2. Therefore, the DDR controller 30 performs ODT control in slot units. That is, DDR chips belonging to the same slot are subjected to the same ODT control.

  The data bus group B is connected to a terminating resistor (motherboard termination) 40 mounted in advance on a mother board (board). Thereby, signal reflection is suppressed. There is no restriction | limiting in the aspect of termination resistance. Any device that can suppress signal reflection may be used. The resistance value of the termination resistor is, for example, 150Ω. The terminal resistor may be disposed between the slot 2 and the slot 1, or the data bus group B may be extended to the position of the slot 1 and disposed below the slot 1.

  The DDR chips 11, 21, and 22 are detachable from the slot 1 and the slot 2, respectively, and can be exchanged.

  However, the present invention is not limited to this, and the DDR chips 11, 21, and 22 may be directly mounted on the substrate without opening the slot.

  For example, the DDR chip 11 may be mounted on the motherboard in advance without going through the slot 1.

  For example, it is assumed that a chip select (DDR chip 11) having a small data bus width is already mounted on the motherboard. On the other hand, for the chip select (DDR chips 21 and 22) having a large data bus width, the slot 2 is provided so that it can be mounted later.

  In this way, it is possible to provide a product in which the user can freely expand the memory capacity while mounting a memory with a minimum necessary capacity in advance. As described above, according to the present embodiment, signal reflection can be suppressed even when the data bus width of the mounted memory chip is different from the data bus width of the commercially available memory chip for expansion.

  The above embodiment can be variously modified within the scope of the present invention.

  For example, the number of chip select, the number of DDR chips belonging to one chip select, and the data bus width are not limited.

  The memory system of the present invention can be applied to a printing apparatus such as an ink jet printer or a laser printer, a scanner apparatus, a facsimile apparatus, and a complex machine thereof.

1 is a schematic configuration diagram of a DDR memory system according to an embodiment of the present invention. Table of ODT control matrix. The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC.

Explanation of symbols

11, 21, 22 ... DDR memory chip,
30 ... DDR controller 31 ... Data bus CS_1, CS_2 ... Chip select signal 40 ... Terminating resistor (motherboard termination)

Claims (3)

A DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select,
A memory controller;
A first chip select selected by a first chip select signal from the memory controller;
A second chip select selected by a second chip select signal from the memory controller and having a data bus width larger than the first chip select;
A first data bus connecting the memory controller, the second chip select, and the first chip select;
A second data bus connecting the memory controller and the second chip select and connecting to a termination resistor mounted in advance on the substrate;
A DDR memory system comprising: The DDR memory system according to claim 1,
The first chip select is
Consisting of a DDR chip pre-mounted on the substrate,
The second chip select is
A DDR memory system comprising a detachable DDR chip mounted in a slot on the substrate. A DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select,
A memory controller;
Multiple chip select with different data bus widths,
A plurality of data buses connecting the memory controller and the chip select;
A termination resistor pre-mounted on a substrate connected to a data bus not connected to at least one of the plurality of chip select;
A DDR memory system comprising:

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