JP5145880B2 - DDR memory system with ODT control function - Google Patents

Description

  The present invention relates to a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination).

  In the DDR2 system defined by JEDEC (Joint Electron Device Engineering Council), DRAM has a termination resistor that can be turned on / off for each terminal (DQ: data input / output, DQS, / DQS: differential data strobe, DM: write data mask). By holding it inside and controlling it with an ODT signal, signal reflection is reduced to ensure signal quality, and high-speed data transfer of DDR2 is realized. The impedance value of the termination resistor can be selected from one of ODT non-selection (off: infinity), ODT selection (50Ω), ODT selection (75Ω), and ODT selection (150Ω).

  However, the control method standardized by JEDEC is defined only by a system having the same data bus width for each chip select (each data area). On the other hand, the ODT signal is a signal interlocked with the chip select signal, and is one for each chip select. Therefore, in a system in which the data bus width varies depending on the chip select, ON / OFF of the termination resistance in the DRAM by ODT control is not successful, and a signal quality problem occurs due to the influence of signal reflection. A high-speed data transfer system requires a high-quality signal, and even a small amount of noise is a big problem for the system.

  An object of the present invention is to minimize signal reflection by a simple method in a DDR memory system configured by chip select having different data bus widths.

A first aspect of the present invention is, for example, a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select, and is connected to the memory controller and the memory controller. The first data bus and the second data bus, the first chip select connected to the first data bus, and the second data bus connected to the first data bus and the second data bus. Chip select. The ODT resistance of the first chip select is controlled in accordance with the ODT resistance (standard value) of the second chip select.
A second aspect of the present invention is a DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select, and is connected to the memory controller and the memory controller. The first data bus and the second data bus, the first chip select connected to the first data bus, and the second data bus connected to the first data bus and the second data bus. Chip select. An ODT resistor of the DDR chip connected to the first data bus belonging to the first chip select and an ODT resistor of the ODT chip connected to the first data bus belonging to the second chip select. ODT control of each chip select is performed so that the combined resistance (pseudo termination resistance) is equal to the ODT resistance determined as a standard value.

  According to the present invention, in a DDR memory system configured by chip select having different data bus widths, signal reflection can be minimized by a simple method.

  An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing a configuration of a DDR memory system to which an embodiment of the present invention is applied.
FIG. 2 (Table 1) is a table showing an ODT control matrix at the time of data writing.

  As shown in FIG. 1, the DDR memory system of the present embodiment includes a DDR controller 30, a slot 1, a slot 2, and a data bus 31 (data bus group A, data bus group B).

  The slot 1 corresponds to a chip select selected by a chip select signal CS_1 from the DDR controller 30. The slot 2 corresponds to a chip select selected by a chip select signal CS_2 from the DDR controller 30.

  In the slot 1, a DDR chip (DDR SDRAM) 11 having an ODT function is mounted. In the slot 2, in addition to the DDR chip 21 having an ODT function, a DDR chip 22 having an ODT function is mounted. All the DDR chips 11, 21, and 22 have a data bus width of 16 bits. That is, slot 1 and slot 2 have different data bus widths, and slot 2 has a larger data bus width.

  The data bus 31 includes a data bus group A and a data bus group B. The data bus group A connects the DDR controller 30, the DDR chip 21 in the slot 2, and the DDR chip 11 in the slot 1. On the other hand, the data bus group B connects the DDR controller 30 and the DDR chip 21 in the slot 2 and is not connected to the slot 1.

  The DDR controller 30 performs data writing and data reading with respect to the DDR chips 11, 21, and 22 in accordance with instructions from a control device (not shown) such as a CPU. Therefore, chip select signals CS_1 and CS_2 are sent to slots 1 and 2. The ODT signal for ODT control is linked to the chip select signals CS_1 and CS_2. Therefore, the DDR controller 30 performs ODT control in slot units. That is, DDR chips belonging to the same slot are subjected to the same ODT control.

  The DDR chips 11, 21, and 22 are detachable from the slot 1 and the slot 2, respectively, and can be exchanged.

  In this configuration, in this embodiment, the memory controller 30 performs ODT control for each chip select.

  Here, before explaining the control method of the present embodiment, for the sake of easy understanding, first, conventional problems will be described with specific examples.

  FIG. 3 (Table 2) shows an ODT control matrix at the time of read / write data transmission defined by JEDEC. Table 2 shows the standard value (specified value) of the ODT resistor for each configuration of the DDR memory system.

  “SR (single rank)” means a configuration in which a memory chip is mounted on the front side. “DR (dual rank)” means a configuration in which memory chips are mounted on the front side and the back side.

  FIG. 4 is a diagram illustrating an example of the configuration of the memory system.

  The memory system shown in FIG. 4A includes a DDR controller (“ASIC” in Table 2) 30, slot 1, slot 2, and data bus 31.

  DDR chips 11 and 12 having an ODT function are mounted in the slot 1 and the slot 2, respectively.

  The slot 1 corresponds to a chip select selected by a chip select signal CS_1 from the DDR controller 30. The slot 2 corresponds to a chip select selected by a chip select signal CS_2 from the DDR controller 30.

  The data bus 31 is a data transmission / reception transmission path, and connects the DDR controller 30, the slot 2, and the slot 1.

  In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. When the ODT control stipulated in JEDEC of Table 2 is performed (see thick line frame F1), the ODT resistance (impedance value of the termination resistance) of the DDR chip 11 in the slot 1 becomes “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 “Off (non-selection)”.

  The memory system in FIG. 4B has a configuration similar to that in FIG. 4A, but there is no DDR chip in slot 1. In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 2. When the ODT control stipulated in JEDEC of Table 2 is performed (see the thick frame F2), the ODT resistance of the DDR chip 21 in the slot 2 is “off”.

  Next, as shown in FIG. 5, a memory system composed of chip select having different data bus widths is considered. The configuration of FIG. 5 is the same as the configuration of FIG.

  The memory system in FIG. 5 can be considered as a configuration in which the DDR memory system in FIG. 4A and the DDR memory system in FIG. 4B are combined.

  In this configuration, consider ODT control when reading data from slot 2.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. However, since the ODT signal is a signal linked to the chip select signal, it is sent for each slot. That is, DDR chips mounted in the same slot are subjected to the same ODT control.

  The specification of JEDEC in Table 2 assumes a system with the same data bus width for each chip select (each data area), and does not assume systems with different data bus widths. Therefore, ODT control to be applied is considered for each data bus group.

  When attention is paid to the data bus group A, the configuration is the same as that of FIG. Therefore, it is assumed that the ODT control as defined for the configuration of FIG.

  When the ODT control stipulated in JEDEC of Table 2 is performed (see thick line frame F1), the ODT resistance of the DDR chip 11 in the slot 1 is “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 is “off”. At this time, since the ODT control is performed for each slot, the ODT resistance of the DDR chip 22 in the slot 2 is also “off”.

  On the other hand, focusing on the data bus group B, the configuration is the same as that in FIG. 4B, and the DDR chip 22 should be subjected to ODT control similar to the configuration in FIG. 4B.

  In this regard, in the ODT control having the configuration shown in FIG. 4B, the ODT resistance of the DDR chip 22 should be “off”.

  That is, the ODT resistance of the DDR chip 22 is the same as when the control to be applied to the configuration of FIG. 4B is performed even if the ODT control to be applied to the configuration of FIG.

  As described above, in the case of data reading, it is understood that the ODT control stipulated by JEDEC may be performed by paying attention to a data bus group connected to a slot having a small data bus width.

  Next, the case of data writing will be considered with reference to FIGS.

  The DDR memory systems shown in FIGS. 6A and 6B correspond to the DDR memory systems shown in FIGS. 4A and 4B, respectively. The DDR memory system of FIG. 7 corresponds to the DDR memory system of FIG.

  Consider the ODT control at the time of data writing to slot 2 in the configuration of FIG.

  The DDR controller 30 performs ODT control by sending an ODT signal to the slot 1 and the slot 2. When the ODT control stipulated in JEDEC of Table 2 is performed (see the thick frame F3), the ODT resistance of the DDR chip 11 in the slot 1 is “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 is “off”.

  In the configuration of FIG. 6B, when the ODT control stipulated in JEDEC of Table 2 is performed (see the thick line frame F3), the ODT resistance of the DDR chip 21 in the slot 2 becomes “150Ω”.

  Next, as shown in FIG. 7, a memory system including chip select having different data bus widths is considered. Focusing on the data bus group A, the configuration is the same as that of FIG. Therefore, it is assumed that ODT control is performed as prescribed to be applied to the configuration of FIG.

  When the ODT control stipulated in JEDEC of Table 2 is performed (see the thick frame F3), the ODT resistance of the DDR chip 11 in the slot 1 is “75Ω”, and the ODT resistance of the DDR chip 21 in the slot 2 is “off”. At this time, since the ODT control is performed for each slot, the ODT resistance of the DDR chip 22 in the slot 2 is also “off”.

  On the other hand, focusing on the data bus group B, the configuration is the same as that in FIG. 6B, and the DDR chip 22 should be subjected to ODT control similar to the configuration in FIG. 6B.

  However, when the ODT control to be applied to the configuration of FIG. 6A is performed, the ODT resistance of the DDR chip 22 is the ODT resistance (150Ω) when the control to be applied to the configuration of FIG. Don't be. This cannot sufficiently suppress signal reflection.

  As described above, in the case of data writing, even if ODT control focusing on the data bus group A is performed, the signal reflection of the data bus group B cannot be suppressed.

  The present embodiment has been made to solve such problems.

  In this embodiment, ODT control at the time of data writing is performed according to the ODT control matrix of FIG. 2 (Table 1).

  In Table 1, parts different from Table 2 are indicated by “*”.

  The reason why the JEDEC standard values are changed as shown in Table 1 will be described below.

  Consider the ODT control at the time of writing to the slot 2 in the configuration of FIG.

  Focusing on the data bus group B, the configuration is “Slot 1: Empty, Slot 2: SR”. Therefore, referring to Table 2 of JEDEC, the slot 2 is controlled so that the ODT resistance is “150Ω”. It should be.

  Therefore, the ODT resistance (R1) of the DDR chip 22 connected to the data bus group B of the slot 2 in Table 1 is set to “150Ω” as defined by JEDEC.

  In order to perform such control, when an ODT signal is sent to the slot 2, the ODT resistance (R2) of the DDR chip 21 connected to the data bus group A of the slot 2 is also controlled to “150Ω”.

  Here, focusing on the data bus group A, according to the JEDEC regulations (Table 2), “75Ω” should be ensured as the termination resistance.

  Since “150Ω” is already set in the DDR chip 21 in the slot 2, if the ODT resistance of the DDR chip 11 in the slot 1 is controlled to “150Ω”, the total combined resistance by the parallel connection becomes “75Ω”. Meet JEDEC regulations.

  Therefore, the memory controller 30 sends an ODT signal to the slot 1 to control the ODT resistance (R3) of the DDR chip 11 to “150Ω”. Then, by using the internal termination resistors of the two DDR chips 11 and 21, a pseudo “75Ω” termination resistor is created.

  As described above, the ODT resistances (R1 to R3) at the time of data writing to the slot 2 are as shown in Table 1.

  Next, consider the case of writing data to slot 1.

  It is not practical to change the ODT control each time when writing data to the slot 1 and when writing data to the slot 2. Therefore, the ODT control for writing data to data 1 is matched with the ODT control for writing data to data 2.

  That is, since the ODT resistance (R3) of the slot 1 at the time of data writing to the slot 2 is “150Ω”, the ODT resistance (R4) of the slot 1 at the time of data writing to the slot 1 is also controlled to “150Ω”. .

  Further, since the ODT resistance (R2) of the slot 2 when writing data to the slot 2 is “150Ω”, the ODT resistance (R5) of the slot 2 when writing data to the slot 1 is also controlled to “150Ω”. Is done.

As described above, the ODT control at the time of data writing to the slot 2 is as follows.
(1) The ODT resistor (R2) of the DDR chip 21 connected to the data bus group A in slot 2 is equal to the ODT resistor (R1) defined in JEDEC of the DDR chip 22 connected to the data bus group B in slot 2. Controlled.
(2) The ODT resistor (R3) of the DDR chip 11 connected to the data bus group A in slot 1 is the ODT resistor (R3) and the ODT resistor (R2) of the DDR chip 21 connected to the data bus group A in slot 2 ) And the combined resistance of the DDR chip 22 connected to the data bus group B of the slot 2 is controlled to be equal to the ODT resistance (R1) defined by JEDEC.

The ODT control at the time of data writing to the slot 1 is as follows.
(1) The ODT resistor (R4) of the DDR chip 21 connected to the data bus group A of the slot 1 is the ODT resistor (R3) at the time of writing to the slot 2 of the DDR chip 11 connected to the data bus group A of the slot 1 Is controlled to be equal to
(2) The ODT resistor (R4) of the DDR chip 21 connected to the data bus group A of the slot 2 is the ODT resistor (R2) at the time of writing to the slot 2 of the DDR chip 21 connected to the data bus group A of the slot 2 Is controlled to be equal to

  That is, the ODT resistors R2 to R5 are controlled based on the JEDEC-specified ODT resistor (R1).

  Note that, when the memory configuration includes dual rank (DR), ODT control is performed based on the same concept. Table 1 shows the ODT control when writing data.

  The memory controller 30 sends an ODT signal to the DDR chip belonging to each slot (chip select) so that the ODT control shown in Table 1 is performed according to the configuration of the memory system. It is assumed that the control values in Table 1 are stored in advance in a register or the like.

  The embodiment of the present invention has been described above.

  According to the above-described embodiment, signal reflection can be reduced by ODT control using a software method even in a memory system configured by chip select having different data bus widths.

  The above embodiment can be variously modified within the scope of the present invention.

  For example, the DDR chips 11, 21, and 22 may be mounted on the motherboard without using a slot. For example, the DDR chip 11 may be mounted on the motherboard in advance without going through the slot 1.

  For example, it is assumed that a chip select (DDR chip 11) having a small data bus width is already mounted on the motherboard. On the other hand, for the chip select (DDR chips 21 and 22) having a large data bus width, the slot 2 is provided so that it can be mounted later.

  In this way, it is possible to provide a product in which the user can freely expand the memory capacity while mounting a memory with a minimum necessary capacity in advance. As described above, according to the present embodiment, signal reflection can be suppressed even when the data bus width of the mounted memory chip is different from the data bus width of the commercially available memory chip for expansion.

  The number of chip select, the number of DDR chips belonging to one chip select, and the data bus width are not limited.

  The memory system of the present invention can be applied to a printing apparatus such as an ink jet printer or a laser printer, a scanner apparatus, a facsimile apparatus, and a complex machine thereof.

1 is a schematic configuration diagram of a DDR memory system according to an embodiment of the present invention. The ODT control matrix in this embodiment (Table 1). ODT control matrix defined in JEDEC (Table 2). The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC. The figure which shows ODT control as prescribed in JEDEC.

Explanation of symbols

11, 21, 22 ... DDR memory chip,
30 ... DDR controller 31 ... Data bus CS_1, CS_2 ... Chip select signal

Claims (6)

A DDR (Double Data Rate) memory system having a function of controlling ODT (On Die Termination) for each chip select,
A memory controller;
A first data bus and a second data bus connected to the memory controller;
A first chip select connected to the first data bus;
A second chip select connected to the first data bus and the second data bus;
With
The ODT resistances of the first chip select and the second chip select at the time of writing are set when only one of the first chip select or the second chip select is connected. The DDR memory system is controlled so as to be equal to the ODT resistance . The DDR memory system according to claim 1,
The ODT resistance of the first chip select is
A DDR memory system, characterized in that the DDR memory system is controlled to be equal to an ODT resistor predetermined as a standard value for a DDR chip connected to the second data bus of the second chip select. The DDR memory system according to claim 2,
The ODT resistance of the DDR chip connected to the first data bus of the second chip select is equal to the ODT resistance of the DDR chip connected to the second data bus of the second chip select,
The ODT resistance of the first chip select is
Combining the ODT resistor of the DDR chip connected to the first data bus of the first chip select and the ODT resistor of the DDR chip connected to the first data bus of the second chip select Resistance,
The DDR memory system, wherein the DDR chip connected to the first data bus of the first chip select is controlled to be equal to an ODT resistor predetermined as a standard value. The DDR memory system according to any one of claims 1 to 3,
The ODT resistance at the time of data writing to the first chip select is
A DDR memory system, wherein the DDR memory system is controlled to be equal to an ODT resistance when data is written to the second chip select. A DDR memory system according to any one of claims 1 to 4,
The control value of each ODT resistor is stored in a register provided in the memory system.
A DDR memory system. A DDR memory system according to any one of claims 1 to 5,
The first chip select is
It consists of a DDR chip pre-mounted on the board,
The second chip select is
Consists of a removable DDR chip mounted in a slot on the board
DDR memory system comprising a call.

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