JP2009033631A - Parallel decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decode even a signal of which the transmission rate is high and which is encoded by a code with a long code length, by correlating the signal with a low-speed clock signal. <P>SOLUTION: A parallel decoder 12 is constituted by comprising a control signal generating section 16 and a decoding section 14. An optical signal 9 encoded and transmitted is converted into an input electric signal 11 by an O/E converter 10 and inputted to the parallel decoder. The input electric signal is branched into a first electric signal 21-1 and a second electric signal 21-2 by a 2-branch switch 20, inputted to a first speed changer 22 and a second speed changer 26, respectively, converted into a first MF input signal 23 and a second MF input signal 27 by reducing the bit rate into 1/2 to be output. The first and second MF input signals are correlation-processed by a first MF 24 and a second MF 28, respectively, and output as a first correlation signal 25-1 and a second correlation signal 29. By performing addition processing and threshold processing on the first and second correlation signals in a determination section 30, a decoded signal 35 is produced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a decoder for an optical access system, particularly a parallel decoder, which communicates using code division multiplexing (CDM).

  COF (CDM on Fiber), which is a communication method using CDM between business operators and users, has attracted attention in the field of optical access networks. The optical access method based on COF has a feature that long-distance transmission is possible, compared with the optical access method based on time division multiplexing (TDM). In addition, since the optical access method using COF is a method in which two-way communication using the same wavelength is performed, there is a feature that it can be easily applied to an optical access system using a wavelength division multiplexing (WDM) method. is there. Therefore, recently, a WDM-CDM-PON system, which is a PON (Passive Optical Network) system realized by coexistence of WDM and CDM, has been proposed (see Non-Patent Document 1).

  In the field of optical access networks, in recent years, further increase in transmission rate and increase in the number of multiplexing have been demanded.

  First, in order to increase the transmission rate, a matched filter that operates with a clock signal synchronized with a high code spread rate is required. Currently, matched filters are used in COF decoding circuits (see, for example, Non-Patent Documents 1 to 3 and Patent Document 1). This is because the analog matched filter is superior to the digital matched filter in terms of operation speed, power consumption, chip size, and the like. Therefore, at present, an analog type matched filter is used when high speed operation is particularly required. However, a high speed digital type matched filter in which the above-mentioned problems are solved will be realized in the future. For example, it is expected to be actively used from the standpoint of mass productivity or cost.

  An analog matched filter uses a flip-flop circuit to latch a code-spread signal with a clock signal synchronized with a code spread rate, and performs decoding by adding these signals with an analog adder. (For example, see Non-Patent Document 4 and Patent Document 1).

  On the other hand, in order to increase the number of multiplexing, it is necessary to increase the length of the code pattern, that is, the code length. When an analog matched filter is used as a decoder, it is necessary to increase the number of shift registers in the matched filter in order to cope with a code having a long code length. When the number of stages of the shift register is increased, there is a problem that the residual charge in the shift register increases, that is, the transfer efficiency decreases.

Whichever analog matched filter or digital matched filter is adopted as a decoding circuit, a decoding circuit that can respond to the recent demands for higher transmission rates and increased multiplexing is required. Yes.
Tamai, et al., “Research and Development of Next Generation Optical Access System COF-PON -Long-Distance Hybrid WDM-CDM-PON-” Oki Electric Research and Development No. 210, Vol.74, No.2, April 2007 Kashima, et al., “Research and Development of High QoS Multimedia Optical Distribution System-COF Transceiver-” Oki Electric R & D No.200, Vol.71, No.4, October 2004 Hirose, "Optical Code Division Multiple Access Technology in Optical Communication Systems" Technical Information Magazine TELECOMFRONTIER, November 2004 T. Sugiyama el al., "HEMT CCD MF for Spread Spectrum Communication", 6 Topical Workshop on Heterostructure Microelectronics, TuB4, Aug. 2005. JP 2003-317026 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder capable of correlating and decoding with a low-speed clock signal even for a signal encoded with a code having a high transmission rate and a long code length. It is to provide.

  The present invention has a configuration in which a decoder is configured using a plurality of matched filters, and the encoded signal is correlated and decoded with a low-speed clock signal by dividing the correlation processing into each matched filter. A decoder is provided. That is, the correlation processing required for decoding is divided and distributed equally to the number of matched filters, and the correlation processing divided into each matched filter is executed in parallel in time. As a result, each matched filter can execute the distributed correlation processing with a low-speed clock signal corresponding to the number of matched filters. As a result, it is possible to realize a decoder that can meet the demands for higher transmission rate and increased number of multiplexing without increasing the operation speed of the matched filter constituting the decoder.

  Therefore, according to the gist of the present invention, a parallel decoder having the following configuration is provided.

  The parallel decoder according to the first invention includes a control signal generation unit and a decoding unit that receives an input electric signal, decodes it, and outputs it.

  The control signal generation unit extracts a clock signal from an encoded input electrical signal input from the outside, ½ frequency clock signal of 1/2 frequency of this clock signal, and this 1/2 frequency division A delay 1/2 divided clock signal in which a delay is given to the clock signal is generated and output.

  The decoding unit includes a two-branch switch, a first speed converter, a second speed converter, a first matched filter, a second matched filter, and a determination unit.

  The two-branch switch, in synchronization with the 1/2 frequency-divided clock signal, alternately branches the chip pulses of the input electrical signal arranged on the time axis one by one in sequence, and one branch chip pulse train is used as the first electrical signal. And the other branched chip pulse train is output as the second electric signal.

  The first speed converter generates and outputs a first matched filter input signal by reducing the bit rate frequency of the first electric signal to ½ in synchronization with the delay ½ frequency-divided clock signal. The second speed converter generates and outputs a second matched filter input signal by reducing the bit rate frequency of the second electric signal to ½ in synchronization with the delay ½ frequency-divided clock signal.

  The first matched filter receives the first matched filter input signal, correlates the first matched filter input signal, and generates and outputs a first correlation signal. The second matched filter receives the second matched filter input signal, correlates the second matched filter input signal, and generates and outputs a second correlation signal.

  The determination unit generates a combined signal of the first correlation signal and the second correlation signal, performs a threshold determination process on the combined signal, and outputs the result as a decoded signal.

  In the parallel decoder according to the first aspect of the invention, the first correlation signal is further input after the first matched filter, and the first correlation signal is delayed by adding a phase delay of one chip pulse to the first correlation signal. A first correlation signal delay unit that generates and outputs the first correlation signal delay unit, and in a synthesis circuit provided with the determination unit, a synthesized signal of the delayed first correlation signal and the second correlation signal is generated, and threshold determination processing of the synthesized signal is performed. Thus, it may be configured to output as a decoded signal.

  In the parallel decoder according to the first aspect of the present invention, the control signal generation unit may include a clock signal extraction unit, a 1/2 frequency divider, and a timing adjuster. The clock signal extraction unit extracts a clock signal from the input electric signal and outputs the clock signal. The 1/2 frequency divider receives this clock signal, and generates and outputs a 1/2 frequency-divided clock signal having a 1/2 frequency of the clock signal. The timing adjuster adjusts the timing of the 1/2 frequency-divided clock signal by delaying the 1/2 frequency-divided clock signal, the first and second speed converters, the first and second matched filters, And a clock signal synchronized with the first and second electric signals and the first and second matched filter input signals, respectively.

  The parallel decoder according to the second invention comprises a control signal generation unit and a decoding unit that receives an input electric signal, decodes it, and outputs it.

Control signal generation unit extracts a clock signal from the input electrical signal encoded is input from the outside, 1/2 ^N divided clock signal of 1/2 ^N the frequency of the clock signal, and the 1/2 It generates a delay 1/2 ^N divided clock signal delayed ^N divided clock signal is applied to the output. Here, N is an integer of 2 or more.

The decoding unit includes a ^2N branch switch, a kth speed converter, a kth matched filter, and a determination unit.

The 2 ^N branch switch is synchronized with the 1/2 ^N frequency-divided clock signal to branch the input electrical signal chip pulses lined up on the time axis one by one and 2 ^N chip pulses as one cycle. The 1st to 2nd ^Nth branch chip pulse trains obtained in this way are output as 1st to 2nd ^N electrical signals, respectively.

That is, the operation of sequentially branching the first chip pulse as the chip pulse of the first branch chip pulse train and branching the second chip pulse as the chip pulse of the second branch chip pulse train is performed sequentially, and the second ^N th The operation until this chip pulse is branched as the chip pulse of the second ^N- branch chip pulse train is the operation for one cycle. The operation in the second period is to branch the (2 ^N +1) -th chip pulse as the chip pulse of the (2 ^N +1) -branch chip pulse train, and to the (2 ^N +2) -th chip pulse ( 2 ^N +2) Branched chip pulse trains are sequentially executed as a chip pulse, and the (2 ^N +2 ^N ) th chip pulse, that is, the (2 ^{N + 1} ) th chip pulse is ^{N + 1} ) Operation until branching as a chip pulse of a branched chip pulse train. The ^2N branch switch has a function of continuing such an operation after the third cycle.

The k-th speed converter generates and outputs the k-th matched filter input signal by reducing the bit rate frequency of the k-th electrical signal to 1/2 ^N in synchronization with the delay 1/2 ^N divided clock signal. .

  The kth matched filter receives the kth matched filter input signal, correlates the kth matched filter input signal, generates a kth correlation signal, and outputs it.

The determination unit generates a composite signal of the second ^N correlation signal from the first correlation signal, performs a threshold determination process on the composite signal, and outputs it as a decoded signal. Here, k is an integer of 1 to ^2N .

In the parallel decoder according to the second aspect of the present invention, the j-th correlation signal is further input after the j-th matched filter, and a phase delay corresponding to j times one chip pulse is added to the j-th correlation signal to obtain a delay j A j-th correlation signal delay unit for generating and outputting a correlation signal is provided. In this j-th correlation signal delay unit, a delayed (2 ^N -1) correlation signal and a second ^N correlation signal are synthesized from the delayed first correlation signal. It is preferable that the signal is generated, and the determination unit performs threshold determination processing of the combined signal and outputs the result as a decoded signal. Here, j is all integers from 1 to (2 ^N -1).

In the parallel decoder according to the second aspect of the present invention, the control signal generation unit may include a clock signal extraction unit, a 1/2 ^N frequency divider, and a timing adjuster. The clock signal extraction unit extracts a clock signal from the input electric signal and outputs the clock signal. 1/2 ^N divider input the clock signal, and generates and outputs a 1/2 ^N divided clock signal of 1/2 ^N the frequency of the clock signal. The timing adjuster supplies a clock signal synchronized with both the kth electrical signal and the kth matched filter input signal.

  According to the parallel decoder of the first aspect of the invention, the encoded input electric signal input from the outside is branched into the first electric signal and the second electric signal by the two-branch switch. The bit rate frequency of the first electric signal and the second electric signal is reduced to 1/2 by the first speed converter and the second speed changing unit, respectively.

  Here, the bit rate frequency is generally defined as the reciprocal of the time slot assigned to one bit of an uncoded electric signal. Here, one chip pulse of the encoded electric signal is used. Means the reciprocal of the time slot assigned to. Similarly, in the following description, unless otherwise specified, the bit rate frequency means the reciprocal of the time slot allocated to one chip pulse.

  Thus, the first electric signal and the second electric signal are reduced in bit rate frequency to ½ and input to the first and second matched filters, respectively. In the first and second matched filters, the first and second matched filters need only be correlated with the first and second matched filter input signals generated by reducing the bit rate frequency to 1/2, respectively. The correlation processing may be performed at a speed defined by the bit rate frequency of the first electric signal and the second electric signal, that is, half the bit rate frequency of the encoded input electric signal input from the outside. become.

  That is, the input electrical signal is correlated and decoded by a matched filter that operates at a frequency that is half the bit rate frequency of the input electrical signal. As a result, the transmission rate of the input electrical signal is high, and a signal encoded by a code having a long code length is also a low speed that is half the frequency corresponding to the bit rate frequency of the input electrical signal. A decoder is realized that can be correlated and decoded with a clock signal.

  In the parallel decoder according to the first aspect of the present invention, the first correlation signal and the second correlation signal are further provided in the synthesis circuit including the determination unit by including the first correlation signal delay unit after the first matched filter. It is possible to completely match the phases of the two. As a result, the reliability of the synthesized signal generation operation in the synthesis circuit is increased, and errors in the received signal generated by decoding can be reduced.

According to the parallel decoder of the second aspect of the invention, the encoded input electrical signal input from the outside is branched into the first to second ^N electrical signals by the ^2N branch switch. The bit rate frequency of the first to second ^N electrical signals is reduced to 1/2 ^N by the kth speed converter, respectively.

In this way, the first to second ^N electrical signals are reduced in bit rate frequency to 1/2 ^N and input to the kth matched filter, respectively. In the k-th matched filter, since the k-th matched filter input signal generated by reducing the bit rate frequency to 1/2 ^N may be correlated, the k-th matched filter includes the first to second ^N That is, the correlation processing may be performed at a speed defined by a bit rate frequency of 1/2 ^N of the bit rate frequency of the coded input electrical signal input from the outside. That is, by setting the value of N to 2 or more, correlation processing can be performed by a matched filter that operates at a lower speed than the parallel decoder of the first invention described above, and therefore decoding is possible. It becomes.

Further, in the parallel decoder according to the second aspect of the invention, the j-th correlation signal delay unit is further provided at the subsequent stage of the j-th matched filter, so that the delay is delayed from the delayed first correlation signal in the synthesis circuit including the determination unit. It is possible to completely match the phases of the combined signal of the (2 ^N -1) th correlation signal and the second ^N correlation signal. As a result, the reliability of the synthesized signal generation operation in the synthesis circuit is increased, and errors in the received signal generated by decoding can be reduced as in the parallel decoder of the first invention described above.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each figure shows an example of the configuration according to the present invention, and only schematically shows the arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is limited to the illustrated example. is not. In the following description, specific electric circuits and conditions may be used. However, these electric circuits and conditions are only one preferred example, and are not limited to these. In each figure, the same component is shown with the same number, and redundant description thereof may be omitted.

  First, the principle of the encoding process and the decoding process, which are the premise of the description of the configuration and operation of the parallel decoders of the first and second embodiments, will be described, and the specific decoding process by the analog matched filter will be described To do. Based on this description, the configuration and operation of the parallel decoders of the first and second embodiments will be described by taking the case of using an analog matched filter as an example.

  Note that the parallel decoders of the first and second embodiments can be realized in the same manner even when a digital matched filter is used. However, if an example of using an analog matched filter with a high operating speed is known, a person skilled in the art can realize the parallel decoder of the first and second embodiments using a digital matched filter. Is easy. Therefore, the parallel decoders of the first and second embodiments configured using a digital matched filter are supplemented as necessary in the description of an example of the case of using an analog matched filter. An accompanying explanation will be given.

<Encoding process>
A process of encoding a transmission signal will be described with reference to FIGS. 1 (A1) to (C), assuming that code division multiplexing transmission is performed by assigning different codes to the first and second channels. . In FIGS. 1A1 to 1C, the horizontal axis and the vertical axis are omitted, but the direction of the horizontal axis indicates the direction of the time axis, and the direction of the vertical axis indicates the signal strength. 1 (A1) and (A2) show the transmission signal and the encoded transmission signal of the first channel, respectively, and FIGS. 1 (B1) and (B2) show the transmission signal and the encoded transmission signal of the second channel, respectively. Show. FIG. 1 (C) shows a time waveform of a code division multiplexed signal in which the encoded transmission signal of the first channel and the encoded transmission signal of the second channel are combined. In FIG. 1 (A1) to (C), the 0 level of the signal is indicated by a one-dot broken line. The level 0 or higher is represented as “1”, and the level 0 or lower is represented as “−1”.

  The transmission signal of the first channel shown in FIG. 1 (A1) assumes the case of (1, 0, 1,...) And shows its time waveform. FIG. 1 (A2) assumes the code given by (1, 0, 0, 1) having a code length of 4, and the time of the encoded transmission signal of the first channel generated by encoding with this code The waveform is shown. Further, the transmission signal of the second channel shown in FIG. 2 (B1) assumes the case of (1, 1, 0,...) And shows its time waveform. FIG. 2 (B2) assumes the code given by (1, 0, 1, 0) having a code length of 4, and the time of the encoded transmission signal of the second channel generated by encoding with this code The waveform is shown.

  Here, the code length refers to the number of terms in a sequence of “0” and “1” that define the code. In this example, the number sequence that defines the code is (1, 0, 0, 1) or (1, 0, 1, 0), and since the number of terms in this number sequence is 4, the code length is 4. Become. In addition, a sequence that gives a code is called a code sequence, and each term “0” and “1” of the code sequence is called a chip. When this chip is expressed by an electric pulse or an optical pulse, the electric or optical pulse is Sometimes called a pulse. In addition, 0 and 1 themselves may be referred to as code values.

  The code value “0” is associated with the absence of an electrical or optical pulse, and the code value “1” is associated with the presence of an electrical or optical pulse. Alternatively, the code value “1” may correspond to the absence of an electrical or optical pulse, and the code value “0” may correspond to the presence of an electrical or optical pulse.

  In encoding, 4 chips constituting a code are allocated to a time slot allocated to 1 bit of a transmission signal before encoding. That is, a code signal corresponding to a number sequence (1, 0, 0, 1) or (1, 0, 1, 0) that defines a code within one bit of the transmission signal before encoding on the time axis Are arranged on the time axis so that the That is, in this case, the bit rate of the code signal is four times the bit rate before the transmission signal is encoded.

The meaning of encoding a transmission signal with a code having a code length of 4 is the product of the transmission signal (hereinafter also referred to as “D”) and the encoded transmission signal (hereinafter also referred to as “C”). This corresponds to obtaining D × C. In the following description, when it is necessary to distinguish which channel corresponds to D or C, the number of channels is added. For example, D and C of the first channel are denoted as D ₁ and C ₁ , respectively. The same applies to the second channel and the like.

  Specifically, the encoding processing circuit for obtaining the product D × C includes EXNOR (exclusive) which is a gate circuit in which an inverter is connected to the output of an exclusive OR operation EXOR (exclusive or OR) gate.・ Noah) circuit is used. In this case, a transmission signal, an encoded transmission signal, and the like expressed as binary signals of 1 and 0 are converted into binary signals of 1 and -1. Specifically, the bias voltage of the transmission signal and the encoded transmission signal may be adjusted to change the center of the amplitude of these signals to the 0 V level.

  Since the transmission signal of the first channel shown in FIG. 1 (A1) is (1, 0, 1,...), If this is converted into a binary signal of 1 and -1, (1, -1, 1 , ...). Since the code used to encode the transmission signal of the first channel is (1, 0, 0, 1), when this is converted into a binary signal of 1 and -1, (1, -1,- 1, 1).

  The first bit of the transmission signal of the first channel is “1”, the second bit is “0”, and the third bit is “1”. Here, if the transmission signal of the first channel is encoded with the code given by (1, -1, -1, 1), the first bit "1" is (1, -1 , -1, 1), the second bit "-1" is encoded with the code given by (1, -1, -1, 1), and the third This means that the bit “1” is encoded with the code given by (1, −1, −1, 1). Although not shown, it is the same for the fourth and subsequent bits to be encoded.

  Since encoding the transmission signal D with the code C is equivalent to obtaining the product D × C, the first bit “1” of the transmission signal is (the first bit of D ( 1)) × C (1, -1, -1, 1) = (1 × 1, 1 × (-1), 1 × (-1), 1 × 1) = (1, -1, -1, 1) is encoded. The second bit “−1” of the transmission signal is (the second bit of D (−1)) × C (1, −1, −1, 1) = ((− 1) × 1 , (-1) x (-1), (-1) x (-1), (-1) x 1) = (-1, 1, 1, -1). The same applies to the third bit. Therefore, the encoded transmission signal obtained by encoding the transmission signal of the first channel shown in FIG. 1 (A1) is ((1, -1, -1, 1), (-1 , 1, 1, -1), (1, -1, -1, 1)) = (1, -1, -1, 1, -1, 1, 1, -1, 1, -1, -1 , 1, ...).

  In addition, the transmission signal of the second channel shown in FIG. 1 (B1) is obtained by converting the code (1, 0, 1, 0) into a binary signal of 1 and -1, (1, -1, 1, -1) The encoding is the same as in the case of the first channel. The first bit “1” of the transmission signal is (D 1st bit (1)) × C (1, −1, 1, −1) = (1 × 1, 1 × (− 1), 1 × 1, 1 × (-1) = (1, -1, 1, -1) Since the second bit of the transmission signal is also “1”, the second of D The th bit is also encoded as (1, -1, 1, -1).

  Since the third bit is “−1” (the third bit of D (−1)) × C (1, −1, 1, −1) = ((− 1) × 1, (− 1) × (-1), (-1) × 1, (-1) × (-1) = (-1, 1, -1, 1). The encoded transmission signal obtained by encoding the transmission signal of the second channel shown is ((1, -1, 1, -1), (1, -1, 1, -1) as described above. , (-1, 1, -1, 1)) = (1, -1, 1, -1, 1, -1, 1, -1, -1, 1, -1, 1, ...) Become.

  1st channel coded transmission signal (1, -1, -1, 1, -1, 1, 1, -1, 1, -1, -1, 1, ...) and 2nd channel coding The code division multiplexed signal given as the sum of the transmission signals (1, -1, 1, -1, 1, -1, 1, -1, -1, 1, -1, 1, ...) is ( 1 + 1, -1-1, -1 + 1, 1-1, -1 + 1, 1-1, 1 + 1, -1-1, 1-1, -1 + 1, -1-1, 1 + 1) = (+2, -2, 0, 0, 0, 0, 2, -2, 0, 0, -2, 2). Figure 1 (C) shows the time waveform of this code division multiplexed signal. Indicates.

  The code division multiplexed signal shown in FIG. 1C is converted into, for example, an optical signal and transmitted through an optical fiber transmission line. When the transmitted code division multiplexed signal is received, it is converted again into an electric signal and decoded to extract the received signal. Therefore, the absolute value of the amplitude of the time waveform of the code division multiplexed signal shown in FIG. 1C does not have an essential meaning because it does not take into account the attenuation received during optical fiber transmission. Therefore, the code division multiplexed signal shown in FIG. 1 (C) sets the center of the maximum value and the minimum value of the amplitude to 0 level and normalizes the amplitude value to 1 (+1, -1, 0, Even if expressed as 0, 0, 0, 1, -1, 0, 0, -1, 1), there is no inconvenience in the description of the decoding process.

<Decryption process>
A process of decoding a code division multiplexed signal will be described with reference to FIGS. 2A to 2D, taking the first channel as an example. In FIGS. 2A and 2B, the horizontal axis indicates the direction of the time axis, while the vertical axis is omitted, but the direction of the vertical axis indicates the signal strength. FIG. 2A shows a time waveform of a code division multiplexed signal input to the analog matched filter. The center of the maximum value and the minimum value of the amplitude of the code division multiplexed signal shown in FIG. 1 (C) is set to 0 level, and the amplitude value is normalized to 1. FIG. 2 (B) shows a time waveform of a signal output after being decoded by an analog matched filter. The signal output from the analog matched filter is the sum of the autocorrelation wave component that is the received signal component of the optical terminal device of the received channel and the cross-correlation wave component that is the other component. That is, the cross-correlation wave component is a noise component.

  FIG. 2 (C1) shows a time waveform of a signal output after the threshold value is determined by the determination circuit. FIG. 2 (C2) shows a time waveform of a clock signal for latching the signal shown in FIG. 2 (C1). FIG. 2D shows a time waveform of a signal obtained by latching the signal output after the threshold determination shown in FIG. 2C1 is performed with the clock signal shown in FIG. The signal shown in FIG. 2D is a received signal. In FIG. 2 (C1), (C2) and (D), the horizontal and vertical axes are omitted, but the horizontal axis indicates the time axis and the vertical axis indicates the signal strength. . Also, the 0 level of the signal is indicated by a one-dot broken line.

  The meaning of encoding the transmission signal corresponds to obtaining the product D × C of the transmission signal D and the code signal C as described above. On the other hand, receiving a code division multiplexed signal that has been encoded and transmitted and decoding the code division multiplexed signal corresponds to re-encoding the code division multiplexed signal with the same code.

The code division multiplexed signal includes a first channel encoded transmission signal (D ₁ × C ₁ ), a second channel encoded transmission signal (D ₂ × C ₂ ), and a third channel encoded transmission signal (D ₃ × C ₁ ). C ₃ ), etc., which is the sum of all encoded transmission signals to be multiplexed. Therefore, the code division multiplexed signal is represented by (D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) +. Decoding this code division multiplexed signal with code C ₁ assigned to the first channel means {(D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) + ... .} × C ₁ , that is, encoding the code division multiplexed signal with the code C ₁ .

That is, the time waveform of the decoded and output signal is {(D ₁ × C ₁ ) + (D ₂ × C ₂ ) + (D ₃ × C ₃ ) + ....} × C ₁ = ( D ₁ × C ₁ ) × C ₁ + (D ₂ × C ₂ ) × C ₁ + (D ₃ × C ₃ ) × C ₁ + .... = D ₁ × C ₁ ² + (D ₂ × C ₂ × C ₁ ) + (D ₃ × C ₃ × C ₁ ) + .... Here, C ₁ ² = 1. This is because they are products of the same code, and all the chips constituting both codes have the same value, that is, “1” or “−1”. That is, when the calculation of C ₁ ² is seen for each chip of the code, 1 × 1 = 1 or (−1) × (−1) = 1 is always “1”. Accordingly, the first term D ₁ × C ₁ ² representing the time waveform of the decoded and output signal becomes D ₁ , and the pulse D _{1 of} each bit constituting the transmission signal of the first channel is reproduced. That is, this component corresponds to an autocorrelation wave component for the transmission signal of the first channel of the signal output after being decoded by the analog matched filter.

On the other hand, the second and subsequent terms representing the time waveform of the decoded and output signal are C ₁ × C _i ≠ 1 (where i = 2, 3,...). From the terms (D ₂ × C ₂ ) × C ₁ and (D ₃ × C ₃ ) × C ₁ , the pulses D ₂ and D ₃ of each bit constituting the transmission signals of the second and third channels are reproduced. Not. That is, it corresponds to the cross-correlation wave component of the signal output by decoding these components with respect to the transmission signal of the first channel.

  In FIG. 2B, the pulse components shown on the time axis (indicated by P and Q in FIG. 2B) are autocorrelation wave components. Further, the cross-correlation wave component is a noise component that falls within a broken line shown above and below across the time axis. In FIG. 2 (B), the shape of the cross-correlation wave component is extremely complicated, so the maximum and minimum levels are indicated by broken lines that are shown above and below the time axis, and the detailed shape is omitted. It is.

  The time waveform of the signal decoded and output by the analog matched filter shown in FIG. 2 (B) is processed by the decision circuit, and only the autocorrelation wave component is extracted and the output signal is shown in FIG. 2 (C1). It is shown. The signal shown in FIG. 2 (C1) is latched by the clock signal shown in FIG. 2 (C2), and the received signal shown in FIG. 2 (D) is obtained.

  Next, the contents of the latch process in the determination circuit will be described with reference to FIGS. 2 (C1), (C2), and (D). Since a known D flip-flop circuit or the like can be used as the latch circuit for performing the latch processing, description of the latch circuit itself is omitted. The latch circuit can be realized by using a D flip-flop circuit. For example, MC100LVEL31 (manufactured by ON semiconductor) or the like can be used as appropriate.

  The time waveform shown in FIG. 2 (C1) is generated by processing the decoded and output signal shown in FIG. 2 (B) by a threshold processing circuit as will be described later. That is, the threshold processing circuit plays a role of converting the analog decoded signal shown in FIG. 2 (B) into a digital decoded signal shown in FIG. 2 (C1). Therefore, the time waveform shown in FIG. 2 (C1) is characterized in that a rectangular wave (rectangular pulse) appears corresponding to the autocorrelation wave component of the decoded and output signal shown in FIG. 2 (B). . The amplitude of the rectangular pulse is defined by the threshold processing circuit, and the amplitudes of all the rectangular pulses appearing in FIG. 2 (C1) are constant. In FIG. 2 (C1), an example of this rectangular pulse is shown sandwiched between two downward arrows with a and b, respectively. As the threshold processing circuit, a suitable one from known comparators can be appropriately selected and used, for example, MAX9600 (manufactured by MAXIM Integrated Products) can be used as appropriate.

  When the digital decoded signal shown in FIG. 2 (C1) and the clock signal shown in FIG. 2 (C2) are input to the D flip-flop circuit functioning as a latch circuit, the following processing is performed, and FIG. The received signal shown in (D) is obtained.

  The rising edge of the clock signal shown in FIG. 2 (C2) (for example, the moment indicated by X in FIG. 2 (C2)) corresponds to the peak of the autocorrelation waveform of the digital decoded signal (for example, FIG. 2). (C2) is sandwiched between two downward arrows with a and b attached to each other.) If there is an intensity corresponding to “1” from the output terminal of the D flip-flop circuit A signal begins to be output. Then, until the next rising edge of the clock signal again (the moment indicated by Y in FIG. 2 (C2)), a signal having an intensity corresponding to “1” continues to be output from the output terminal of the D flip-flop circuit. At the moment, the signal changes from the output terminal of the D flip-flop circuit to a signal having the intensity equivalent to “-1”.

  Similarly, the next time the signal having the intensity corresponding to “1” starts to be output from the output terminal of the D flip-flop circuit is the rising edge of the clock signal indicated by Z in FIG. 2 (C2). The output signal from the output terminal of the D flip-flop circuit changes to a signal having a strength corresponding to “-1” at the moment when the clock signal rises again (this moment deviates from FIG. 2 (C2)). ing.).

  As described above, when the rising edge of the clock signal is input to the D flip-flop circuit within the existence time of the rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal, the reception shown in FIG. A rectangular pulse having an intensity corresponding to “1” of the signal is generated. On the other hand, when the rising signal of the clock signal is input to the D flip-flop circuit outside the existence time of the rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal, the output terminal of the D flip-flop circuit “ The signal corresponding to “−1” is still output.

  In this way, it corresponds to “1” from the output terminal of the D flip-flop circuit, corresponding to whether or not there is a rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal at the rising edge of the clock signal. Or a signal corresponding to “−1” is output. As a result, the received signal is reproduced. The received signal shown in FIG. 2 (D) is a part of the transmission signal (1, -1, 1, ...) shown in FIG. 1 (A1). The part has been reproduced. In FIG. 2D, signal values “1” and “−1” are shown in parentheses in order to clearly indicate the portion corresponding to (1, −1, 1,...).

  As is clear from the above description, if there is no rectangular pulse corresponding to the peak of the autocorrelation waveform of the digital decoded signal at the moment of the rising edge of the clock signal, the reception signal shown in FIG. I can't. Therefore, it is necessary to adjust the relative positional relationship on the time axis between the digital decoded signal shown in FIG. 2 (C1) and the clock signal shown in FIG. 2 (C2). This adjustment can be realized by adjusting the delay time with respect to the clock signal for latching the signal shown in FIG.

<Analog matched filter>
With reference to FIGS. 3A and 3B, the configuration and operation of the analog matched filter will be described. 3A and 3B are schematic block configuration diagrams of the analog matched filter. 3A is an analog matched filter circuit for decoding the first channel signal, and FIG. 3B is an analog matched filter circuit for decoding the second channel signal. Here, a conventional decoding method will be described in which decoding is performed using one analog matched filter for one channel.

  The analog matched filter outputs the output signals output from the analog shift register 140, the plus signal adder 142, the minus signal adder 144, the plus signal adder 142, and the minus signal adder 144, respectively. An analog adder 146 for adding and a low-pass filter 148 are provided. The plus signal adder 142 and the minus signal adder 144 include an amplifier 150 and an inverting amplifier 152, respectively. The amplifier 150 and the inverting amplifier 152 are shown with their peripheral circuits omitted.

  A code division multiplexed signal is input to an input terminal indicated as data input. A clock signal having a transmission rate frequency of the transmission signal is input to an input terminal indicated as clock input.

  The analog matched filter shown in FIG. 3A is designed on the assumption that decoding is performed using a code given by a sequence of numbers (1, 0, 0, 1). That is, the code given by the sequence (1, 0, 0, 1) is called the code given by the sequence (1, -1, -1, 1) when the binary representation of "1" and "-1" is displayed. Also good.

  Here, for simplicity, first, only the component of the first channel in the code division multiplexed signal will be taken up and described. The code division multiplexed signal also contains the transmission signal encoded in the second channel, but is not reproduced because it is encoded with a code different from the code assigned to the first channel. .

  The encoded transmission signal of the first channel shown in FIG. 1 (A2) has the same time waveform as the transmission signal of the first channel having the time waveform shown in FIG. 1 (A1) by the analog matched filter. The reproduction as a received signal will be described.

  The analog shift register 140 is a shift register (hereinafter referred to as “CCD shift register”) formed by a charge coupled device CCD (Charge Coupled Device) having four stages (shown in order from the input side as 1, 2, 3, 4). Register ")). That is, the analog shift register 140 is a 4-bit CCD shift register. Here, since it is assumed that encoding is performed with a code having 4 chips (a code having a code length of 4), a 4-stage CCD shift register is used. Actually, since a code with a long code length such as a code with 16 or 32 chips is used, a CCD shift register with a large number of stages such as a 16 or 32 stage CCD shift register is used, but the principle described below is It is the same.

A clock signal having a transmission rate frequency is input to the clock input terminal of the CCD shift register 140. Further, a code division multiplexed signal (the encoded transmission signal shown in FIG. 1 (A2)) is input to the data input terminal of the CCD shift register 140. The first stage input terminal of the CCD shift register 140 shown in FIGS. 3 (A) and 3 (B) is indicated as D ₁ , and the output terminal is indicated as Q ₁ . In addition, the second, third, and fourth stage input terminals are denoted as D ₂ , D ₃ , and D ₄ , respectively, and the output terminals are denoted as Q ₂ , Q ₃ , and Q ₄ , respectively. Data input terminal of the CCD shift register 140 is connected to the input terminal D ₁ of the first stage.

  With reference to FIG. 3 (A), the principle of decoding the code division multiplexed signal of the first channel encoded with the code (1, -1, -1, 1) will be described.

First, the first stage data input terminal D ₁ of the CCD shift register 140 is connected to the code division multiplexed signal, that is, “1” (1) of the encoded transmission signal of the first channel shown in FIG. Figure 1 (A2) CS1 and indicated time slot is set to 1.) is input in synchronization with the clock signal, from the output terminal to Q ₁ first stage output is "1" The Then, "-1" in the first channel of encoded transmission signal to the data input terminal D ₁ of the first stage (CS2 and indicated time slot of FIG. 1 (A2) is -1.) Of Once entered, "1" is output from the output terminal Q ₂ of the second stage is output "-1" from the output terminal to Q ₁ first stage in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to the data input terminal D ₁ of the first stage, in synchronization with a clock signal, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

At the stage where all the chips of the encoded transmission signal existing in the time slot from CS1 to CS4 are all input from the data input terminal of the analog shift register 140, the output terminals of the first to fourth stages, Q ₁ , Q ₂ , Q _3, and Q ₄ output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (1, -1, -1, 1). In other words, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first to fourth stages are the voltage values at the positions indicated by F, G, H, and I in the CCD shift register 140. appear.

  The voltage value at position F and the voltage value at position I are input to the plus signal adder 142, combined by the electrical signal combiner 154, and input to the amplifier 150. The voltage value at position F and the position I Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position G and the voltage value at position H are input to the negative signal adder 144, combined by the electrical signal combiner 156, and input to the inverting amplifier 152, and the voltage value of the position G And a voltage value corresponding to the sum of the voltage value at position H (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the low-pass filter 148.

  The low-pass filter 148 filters the base rate frequency signal out of the signal output from the analog adder 146 and serves to block high frequency noise components.

The encoded transmission signal, just steps chips that are time slots from CS1 to CS4 is all inputted from the data input terminal of the analog shift register 140 Q _1, Q _2, Q from ₃ and the output terminal of Q ₄ Since the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (1, -1, -1, 1), the electric signal multiplexer 154 has a potential that is the potential at the positions F and I. 1 and the potential 1 are input, and the potential 2 is input to the amplifier 150. Further, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are the electric potentials at the G and H positions, and inputs the electric potential −2 to the inverting amplifier 152.

  Therefore, the amplifier 150 outputs a signal having a potential proportional to the potential 2 (here, the amplification factor is 1 for simplicity), and the inverting amplifier 152 inverts the potential −2 (here, the simple Therefore, the amplified signal of potential 2 is output, and both are combined by the analog adder 146 and output from the data output terminal of the low-pass filter 148 as a signal of potential 4. .

The next time the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 becomes (1, -1, -1, 1) is the chip that exists in the time slots from CS9 to CS12 Are all input from the data input terminal of the CCD shift register 140. Similarly, at this time, a signal having a potential of 4 is output from the data output terminal of the low-pass filter 148.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), the data output of the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4. This is because the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), for example, (-1, -1, 1, 1 ) Etc., it is clear if the same explanation as above is considered.

  Next, with reference to FIG. 3B, the principle of decoding the second channel code division multiplexed signal encoded with the code (1, -1, 1, -1) will be described. The difference between the analog matched filter shown in FIG. 3 (A) and the analog matched filter shown in FIG. 3 (B) is that the signal input to the amplifier 150 and the inverting amplifier 152 is in any position of F, G, H, and I. The difference between taking out from. In the analog matched filter shown in FIG. 3A, the input signal to the amplifier 150 is taken out from the positions F and I, and the input signal to the inverting amplifier 152 is taken out from the positions G and H. On the other hand, in the analog matched filter shown in FIG. 3B, the input signal to the amplifier 150 is extracted from the G and I positions, and the input signal to the inverting amplifier 152 is extracted from the F and H positions. . As described above, an arbitrary code having a code length of 4 can be set depending on whether the signal input to the amplifier 150 and the inverting amplifier 152 is extracted from F, G, H, or I.

  Code-division multiplexed signals also contain encoded transmission signals of channels other than the second channel, but these are encoded with a code different from the code assigned to the second channel. Does not play.

  The encoded transmission signal of the second channel shown in FIG. 1 (B2) has the same time waveform as the transmission signal of the second channel having the time waveform shown in FIG. 1 (B1) by the analog matched filter. The reproduction as a received signal will be described. Also in the analog matched filter shown in FIG. 3B, the decoding operation is basically the same as that of the analog matched filter shown in FIG.

First, the data input terminal D ₁ of the first stage of the CCD shift register 140, code division multiplex signal, i.e., here, "1" of the second channel of the encoded transmission signal shown in FIG. 1 (B2) ( Figure 1 (B2) CS1 and indicated time slot is set to 1.) is input in synchronization with the clock signal, from the output terminal to Q ₁ first stage output is "1" The Then, "-1" of the second channel of the encoded transmission signal to the data input terminal D ₁ of the first stage (CS2 and indicated time slot of FIG. 1 (B2) is set to -1.) Of When input, “−1” is output from the first stage output terminal Q ₁ and “1” is output from the second stage output terminal Q ₂ in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to the data input terminal D ₁ of the first stage, in synchronization with a clock signal, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

At the stage where all the chips of the encoded transmission signal existing in the time slot from CS1 to CS4 are all input from the data input terminal of the analog shift register 140, the output terminals of the first to fourth stages, Q ₁ , Q ₂ , Q ₃ and Q ₄ output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (−1, 1, −1, 1). That is, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first stage to the fourth stage are the voltage values at the positions indicated by F, G, H, I in the analog shift register 140. appear.

  The voltage value at position G and the voltage value at position I are input to the plus signal adder 142, combined by the electrical signal combiner 154, and input to the amplifier 150. Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position F and the voltage value at position H are input to the negative signal adder 144, combined by the electrical signal combiner 156, and input to the inverting amplifier 152, and the voltage value of the position F And a voltage value corresponding to the sum of the voltage value at position H (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the low-pass filter 148.

The encoded transmission signals, from Q _1, Q _2, Q ₃ and the output terminal of Q ₄ just step chips that are time slots from CS1 to CS4 are input all the data input terminal of the CCD shift register 140 Since the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are (-1, 1, -1, 1), the electric signal multiplexer 154 has a potential that is a potential at the positions of G and I. 1 and the potential 1 are input, and the potential 2 is input to the amplifier 150. In addition, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are the electric potentials at the positions F and H, and inputs the electric potential −2 to the inverting amplifier 152.

  Therefore, a signal having a potential proportional to the potential 2 is output from the amplifier 150, and a signal having a potential 2 in which the potential -2 is inverted is output from the inverting amplifier 152. Both signals are combined by the analog adder 146. The signal having the potential 4 is output from the data output terminal of the CCD shift register 140 through the low-pass filter 148.

The next value of the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is (-1, 1, -1, 1) is the chip in the time slot from CS5 to CS8 Are all input from the data input terminal of the analog shift register 140. At this time as well, a signal having a potential of 4 is output from the data output terminal of the CCD shift register 140.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (-1, 1, -1, 1), the data output from the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4.

As described above, only when the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 matches the set sign, the potential 4 from the data output terminal of the CCD shift register 140 Is output. This is a signal corresponding to the autocorrelation waveform. For example, in the time waveform of the signal obtained by decoding the encoded transmission signal of the first channel shown in FIG. 2 (B), the peaks indicated as P and Q are the data of the CCD shift register 140. This is a peak that appears at the moment when a signal having a potential of 4 is output from the output terminal.

<Determination circuit>
A determination circuit that performs determination processing on the signal output from the analog matched filter corresponds to a determination circuit described later.

  With reference to FIGS. 4A to 4C, the configuration and operation of the determination circuit will be described. FIG. 4 (A) is a schematic block configuration diagram of the determination circuit, and FIG. 4 (B) shows a time waveform of a decoded signal output from the analog matched filter. FIG. 4C shows a time waveform of a signal output after threshold determination. 4 (B) and 4 (C), the direction of the horizontal axis indicates time on an arbitrary scale, while the vertical axis is omitted, but the signal intensity is indicated on the vertical axis direction on an arbitrary scale.

  The time waveform shown in FIG. 4 (B) corresponds to the time waveform of the signal decoded and output by the analog matched filter shown in FIG. 2 (B). Although FIG. 4 (B) and FIG. 2 (B) are apparently different, each figure is shown abstracted for convenience of explanation, and the time waveform of the actual signal is shown in FIG. 4 (B). close.

  The determination circuit includes a comparator 86 and a D flip-flop circuit 88. The decoded signal output from the analog matched filter shown in FIG. 4B is input from the analog data input terminal of the determination circuit to the input terminal (IN) of the comparator 86. On the other hand, a signal having a potential set as a threshold value is input from the threshold level input terminal (REF). This potential corresponds to the potential described as the threshold value in FIG.

  A signal having a potential corresponding to 1 is output from the output terminal (OUT) of the comparator 86 when the level of the signal input from the input terminal (IN) exceeds the threshold value. On the other hand, when the level of the signal input from the input terminal (IN) is below the threshold, a signal having a potential corresponding to 0 is output. Therefore, the time waveform of the signal output from the output terminal (OUT) of the comparator 86 is the time waveform shown in FIG. The time waveform shown in FIG. 4 (C) corresponds to the time waveform shown in FIG. 2 (C1) described above.

  A signal having a time waveform shown in FIG. 4C is input to the input terminal (D) of the D flip-flop circuit 88. On the other hand, a clock signal is input to the clock signal input terminal (CLK) of the D flip-flop circuit 88. The clock signal input to the clock signal input terminal (CLK) is the clock signal shown in FIG. 2 (C2). That is, a threshold value input to the input terminal (D) is determined by this clock signal, and the output signal is latched. Since the principle of the latch operation has already been described, it will not be repeated here.

In FIG. 2 (C1), the widths of the rectangular pulses are shown to be equal, but actually the widths of the rectangular pulses are not equal as in the time waveform shown in FIG. 4 (C). However, since it is sufficient that the rising edge of the clock signal is included in the range of the width of the rectangular pulse, the widths of the rectangular pulses are not necessarily equal. However, a delay circuit or the like so that the rising edge of the clock signal input to the clock signal input terminal (CLK) falls within the rectangular pulse width (W ₁ and W ₂ ) shown in FIG. Therefore, it is necessary to adjust the position of the clock signal on the time axis.

  As described above, the threshold value determination process is performed by the determination circuit, and the time zone in which the intensity of the signal input to the determination circuit exceeds the threshold level is set to level 1, and the intensity of the combined signal is lower than the threshold level. It is output as a signal whose level is level 0. This determination circuit is provided in the determination unit of the parallel decoder according to the first and second embodiments described later, and is used for generating a decoded signal.

<Parallel decoder according to the first embodiment>
The configuration and operation of the parallel decoder according to the first embodiment will be described with reference to FIG. FIG. 5 is a schematic block diagram of the parallel decoder according to the first embodiment.

[Constitution]
The parallel decoder 12 according to the first embodiment includes a control signal generation unit 16 and a decoding unit 14 that receives an input electric signal 11 and decodes and outputs it.

  An optical signal 9 input from the outside and encoded and transmitted is received by a photoelectric converter (O / E converter) 10 and is generated as an input electrical signal 11, which is a parallel type of the first embodiment. Input to the decoder 12. The input electrical signal 11 is bifurcated into the input electrical signal 11-1 and the input electrical signal 11-2 by the branching device 18, the input electrical signal 11-1 is controlled by the decoding unit 14, and the input electrical signal 11-2 is controlled. The signal is input to the signal generator 16.

  The control signal generation unit 16 includes a clock signal extraction unit 40, a 1/2 frequency divider 42, and a timing adjuster 44. The clock signal extraction unit 40 extracts the clock signal 41 from the input electric signal 11-2 and outputs it. For the clock signal extraction unit 40, for example, a well-known clock signal extraction device disclosed in JP-A-2005-252942, JP-A-2006-49967, or the like can be appropriately selected and used.

  The 1/2 divider 42 receives the clock signal 41, generates a 1/2 divided clock signal 43 having a 1/2 frequency of the clock signal, and outputs it. The timing adjuster 44 gives the first speed converter 22 and the second speed converter 26, the first analog matched filter 24 and the second analog matched filter 28 by delaying the 1/2 frequency-divided clock signal 43. The timing of the 1/2 frequency-divided clock signal to be supplied is adjusted, and a clock signal synchronized with the first and second electric signals is supplied to the first analog matched filter 24 and the second analog matched filter 28, respectively.

  In FIG. 5, for the sake of simplification and visibility, the delay ½ frequency division clock signal 45 output from the timing adjuster 44 is simply branched by the branching units 38-1 and 38-2 to be the first speed. It is shown to be supplied to the converter 22, the second speed converter 26, the first matched filter 24 and the second matched filter 28. However, the actual configuration of this part is a configuration in which the timing amount is individually adjusted and supplied to the first speed converter 22, the second speed converter 26, the first matched filter 24, and the second matched filter 28. I want you to understand that

  That is, the control signal generation unit 16 extracts the clock signal 41 from the input electrical signal 11-2, ½ frequency clock signal 43 of 1/2 frequency of this clock signal 41, and this 1/2 frequency division. It has a function of generating and outputting a delay ½ frequency divided clock signal 45 in which a delay is given to the clock signal.

  The 1/2 frequency-divided clock signal 43 is supplied to the 2-branch switch 20. Further, the delayed 1/2 divided clock signal 45 is branched into delayed 1/2 divided clock signals 45-1, 45-2, 45-3, and 45-4 by branching units 38-1 and 38-2. Then, the signals are supplied to the first speed converter 22, the second speed converter 26, the first matched filter 24, and the second matched filter 28, respectively, included in the decoding unit 14.

  The decoding unit 14 includes a two-branch switch 20, a first speed converter 22, a second speed converter 26, a first matched filter (first MF) 24, and a second matched filter (second MF) 28. And a determination unit 30.

  The two-branch switch 20 alternately branches the chip pulses of the input electric signal 11-1 aligned on the time axis one by one in synchronization with the 1/2 frequency-divided clock signal 43, The first electric signal 21-1 is output, and the other branched chip pulse train is output as the second electric signal 21-2.

  The 2-branch switch 20 has a function of outputting the input electrical signal 11-1 in parallel with the first electrical signal 21-1 and the second electrical signal 21-2 using the 1/2 frequency-divided clock signal 43 as a trigger. Have. As a switch having such a function, for example, a product name “Serial Controlled 8-Channel SPST Switch MAX335” (Maxim Japan Co., Ltd.) can be used as appropriate.

  Further, the two-branch switch 20 controls the input electric signal 11-1 by controlling the output gate provided by the two-branch switch 20 with the 1/2 frequency-divided clock signal 43, and the first electric signal 21 -1 and the second electric signal 21-2 may be generated and output. For this configuration, for example, a trade name “multiplexer / switch MAX4524 or MAX4525” (Maxim Japan Co., Ltd.) can be used as appropriate.

  The first speed converter 22 is input to the first MF 24 by reducing the bit rate frequency of the first electric signal 21-1 to 1/2 in synchronization with the delay 1/2 frequency-divided clock signal 45-1. A first MF input signal 23 that is a signal is generated and output. The second speed converter 26 reduces the bit rate frequency of the second electric signal 21-2 to 1/2 in synchronization with the delay 1/2 frequency divided clock signal 45-2 and inputs it to the second MF 28. A second MF input signal 27, which is a signal, is generated and output. The first speed converter 22 and the second speed converter 26 can appropriately use a 1/2 frequency divider, and can be configured by a known method using, for example, a D flip-flop.

  The first MF 24 receives the first MF input signal 23, performs correlation processing on the first MF input signal 23, and generates and outputs a first correlation signal 25-1. The second MF 28 receives the second MF input signal 27, performs correlation processing on the second MF input signal 27, and generates and outputs a second correlation signal 29.

  In FIG. 5, the first correlation signal delay device 36 is provided at the output stage of the first MF 24. However, the first correlation signal delay device 36 is not necessarily a component that must be provided. The first correlation signal delay unit 36 adds a phase delay of one chip pulse of the first correlation signal 25-1 to the first correlation signal 25-1 to generate and output a delayed first correlation signal 25-2 have. Although details will be described later, by providing the first correlation signal delay unit 36, in the synthesis circuit 32 provided in the determination unit 30, the first correlation signal (that is, the delayed first correlation signal 25-2), the second It is possible to completely match the phases of both of the correlation signals 29.

  In the following description, the description will be given on the assumption that the first correlation signal delay unit 36 is not provided, and then the case where the first correlation signal delay unit 36 is provided will be described. Therefore, in the following description, it should be understood that the first correlation signal delay unit 36 is not provided until the first correlation signal delay unit 36 is specifically referred to.

  The determination unit 30 includes a synthesis circuit 32 and a determination circuit 34. The combining circuit 32 generates and outputs a combined signal 33 of the first correlation signal 25-1 and the second correlation signal 29. The synthesized signal 33 is input to the determination circuit 34, subjected to threshold determination processing, and a decoded signal 35 is generated and output.

[Operation]
With reference to FIGS. 6A to 6G, the operation of the parallel decoder according to the first embodiment will be described. FIGS. 6A to 6G are timing charts for explaining the operation of the parallel decoder according to the first embodiment. For convenience of explanation, in FIGS. 6A to 6G, it is assumed that the transmission signal is (1, 1, 0,...). Therefore, when this transmission signal is converted into a binary signal of 1 and -1, (1, 1, -1,...) Is obtained. Also, the transmission signal (1, 1, 0, ...) is encoded and transmitted by the code given by (1, 0, 0, 1, 0, 1, 1, 0) with a code length of 8. It is assumed that

  Therefore, the optical signal 9 input from the outside to the O / E converter 10 provided in the preceding stage of the input of the parallel decoder of the first embodiment is a transmission signal (1, 1, 0,...) Is an optical signal encoded by a code (1, 0, 0, 1, 0, 1, 1, 0). That is, it is received as an optical chip pulse train in which the presence of the optical pulse corresponds to the chip given by “1” and the absence of the optical pulse corresponds to the chip given by “0”.

  The above transmission signal and code are assumed for the sake of convenience of explanation, and it is clear that the following explanation is not limited to these conditions.

  6A to 6G, the time waveforms shown from (A) shown at the top to (G) shown at the bottom are as follows. Here, each time waveform is represented by binary signals of 1 and -1.

  The time waveform (A) is a time waveform of the transmission signal (1, 1, 0,...) Before being encoded. The bit indicating “1” of the transmission signal is associated with the presence of a pulse, and the bit indicating “−1” of the transmission signal is associated with the absence of a pulse.

  The time waveform (B) is a time waveform indicating a code used for encoding on the transmission side. Therefore, in the time waveform (B), a rectangular pulse sequence indicating a code sequence given by (1, 0, 0, 1, 0, 1, 1, 0) repeatedly appears as one cycle. This one period corresponds to one bit of the transmission signal (1, 1, 0,...) Before encoding. That is, eight chip pulses corresponding to a code length of 8 are contained in a 1-bit time slot of a transmission signal before encoding. Here, the chip indicating the code value “1” is associated with the presence of a chip pulse, and the chip indicating the code value “0” is associated with the absence of the chip pulse.

  The time waveform (C-1) shows the time waveform of the first electric signal 21-1, and the time waveform (C-2) shows the time waveform of the second electric signal 21-2.

  The first electric signal 21-1 and the second electric signal 21-2 are generated by the two-branch switch 20 that alternately splits the chip pulses of the input electric signal 11-1 arranged on the time axis one by one sequentially. Signal. Therefore, in the time waveforms (B), (C-1), and (C-2), the sign values “1” and “-1” are parenthesized for the chip pulses constituting the second electric signal 21-2. By distinguishing them from the chip pulses constituting the first electric signal 21-1, they are shown.

  Since the chip pulses arranged on the time waveform (C-1) are configured by switching the code values without parentheses in the time waveform (B), the code pulses (1, -1, -1, Code sequence (1, -1, -1, 1, -1, 1, 1, -1, 1, -1, -1, 1, 1, -1, 1, -1) -1, 1, 1, -1, ...) every other chip and arranges the code sequence (1, -1, -1, 1) as one cycle (1, -1) , -1, 1, 1, -1, -1, 1, ...). On the other hand, since the chip pulses arranged on the time waveform (C-2) are configured by switching the code values in parentheses in the time waveform (B), the code pulses (-1, 1, 1, -1) is a code sequence (-1, 1, 1, -1, -1, 1, 1, -1, ...).

  In the time waveforms (C-1) and (C-2), the width on the time axis occupied by one chip pulse is the time axis occupied by one chip pulse in the time waveform (B). The feature is that it is twice the width of. In other words, for example, the first chip in the time waveform (C-1) has a code value of “1”, which is twice the width occupied by the first chip on the time axis in the time waveform (B). You can see that it exists. In the time waveform (B), the time width for one bit of the chip pulse is one width of the parallel line indicated by the vertical broken line, whereas in the time waveform (C-1), the chip pulse 1 The time width for bits is two widths of parallel lines indicated by vertical broken lines. This means that the bit rates in the time waveforms (C-1) and (C-2) are half of the bit rate in the time waveform (B).

  Thus, in the time waveforms (C-1) and (C-2), the width on the time axis occupied by one chip pulse is the time axis occupied by one chip pulse in the time waveform (B). The reason why it is twice as wide as the above is as follows. That is, one chip pulse after branching can be attributed to being able to occupy twice the width of the time slot occupied on the time axis by the chip pulse before branching. That is, the first electric signal 21-1 and the second electric signal 21-2 represented by the time waveforms (C-1) and (C-2) are input electric signals arranged on the time axis by the two-branch switch 20. 11-1 is a signal generated by alternately branching one chip pulse at a time, so each of the chip pulses constituting the first electric signal 21-1 and the second electric signal 21-2 is Thus, each chip pulse of the input electric signal 11-1 before branching can occupy twice the width of the time slot occupied on the time axis.

  The time waveform (D) shows the time waveform of the 1/2 frequency-divided clock signal 43 that is input to the 2-branch switch 20 as a synchronization signal.

  The time waveforms (E-1) and (E-2) show the time waveforms of the first MF input signal 23 and the second MF input signal 29, respectively. The time waveforms (E-1) and (E-2) are the first electric signal 21-1 and the second electric signal 21-2, respectively, by the first speed converter 22 and the second speed converter 26. The bit rates of the time waveforms (E-1) and (E-2) are 1/2 compared to the first electric signal 21-1 and the second electric signal 21-2. It has become.

  The time waveform (F-1) and the time waveform (F-2) show the time waveforms of the first correlation signal 25-1 and the second correlation signal 29, respectively. The first correlation signal 25-1 and the second correlation signal 29 are output from the first MF 24 and the second MF 28, respectively, and input to the determination unit 30.

  Further, the time waveform (G) indicates the time waveform of the decoded signal 35 output from the determination unit 30. The signal represented by the time waveform (A) is a signal in the NRZ (Non-Return to Zero) format, whereas the signal represented by the time waveform (G) is a signal in the RZ (Return to Zero) format. However, this time waveform (G) is obtained by decoding the transmission signal (1, 1, -1, ...) that is a binary digital signal shown in the time waveform (A). It turns out that it is.

  The contents described above with reference to the timing charts shown in FIGS. 6A to 6G are summarized as follows.

  The optical signal 9 is input to the O / E converter 10, converted into an input electrical signal 11, and output. The input electric signal 11 is branched into an input electric signal 11-1 and an input electric signal 11-2 by a branching unit 18, the input electric signal 11-1 is sent to the first speed converter 22, and the input electric signal 11-2 is Input to the second speed converter 26. The bit rate of the first MF input signal 23 and the second MF input signal 27 output from the first speed converter 22 and the second speed converter 26, respectively, is half of the bit rate of the input electrical signal 11. Thus, it can be seen that the first speed converter 22 and the second speed converter 26 can be configured using a 1/2 frequency divider.

  The first MF input signal 23 and the second MF input signal 27 are input to the first MF 24 and the second MF 28, respectively, and are generated as the first correlation signal 25-1 and the second correlation signal 29 to be combined. The signal is input to the circuit 32 and is generated and output as a synthesized signal 33.

  Here, when a digital matched filter is used as the first MF 24 and the second MF 28, the synthesis circuit 32 can be formed by a logical product circuit (AND circuit). When an analog matched filter is used as the first MF 24 and the second MF 28, the synthesis circuit 32 can be formed by an analog adder. In the following description of the decoding process using the first and second analog matched filters, it is assumed that analog matched filters are used as the first MF 24 and the second MF 28. Therefore, description will be made assuming that the synthesis circuit 32 uses an analog adder.

<Decoding processing by the first and second analog matched filters>
A specific configuration of the first MF 24, the second MF 28, and the determination unit 30, and a decoding process by the first and second analog matched filters will be described with reference to FIG. Here, as described above, analog matched filters are used as the first MF 24 and the second MF 28. FIG. 7 is a schematic block configuration diagram of the first MF, the second MF, and the determination unit of the parallel decoder according to the first embodiment.

  The first MF 24 and the second MF 28 shown in FIG. 7 decode the analog matched filter and the second channel signal for decoding the first channel signal shown in FIGS. 3 (A) and 3 (B), respectively. It corresponds to the analog matched filter to make it. That is, conventionally, one analog matched filter is used to decode a signal for one channel, whereas the parallel decoder of the first embodiment decodes a signal for one channel. However, two analog matched filters are used.

  As described above, the parallel decoder of the first embodiment divides the signal for one channel into two and divides the decoding process into two analog matched filters, so that the operation speed is half the bit rate of the input signal. Thus, it is possible to decode the input signal. That is, by using two analog matched filters, the parallel decoder of the first embodiment performs correlation processing in synchronization with a low-speed clock signal having a period that is half the bit rate of the input signal, thereby allowing the input signal to be processed. It is possible to decrypt.

In general, by using 2 ^N analog matched filters, it is possible to decode the input signal by performing a correlation process synchronized with a low-speed clock signal of 1/2 ^N period of the input signal bit rate. is there. A parallel decoder configured by using 2 ^N (N is an integer of 2 or more) analog matched filters is a parallel decoder according to a second embodiment, which will be described later. Also in the parallel decoder of the second embodiment, the decoding operation described below is in principle the same as the parallel decoder of the first embodiment configured by two analog matched filters. Therefore, here, the decoding operation of the parallel decoder of the first embodiment will be described, and the detailed operation description of the decoding by the parallel decoder of the second embodiment will be omitted.

  The first MF 24 is a circuit similar to the matched filter circuit for decoding the signal of the first channel shown in FIG. 3 (A) in order to explain the conventional decoder. However, the decoding code set in the first MF 24 is the code (1, 0, 0, 1, 0, 1, 1, 0) obtained by encoding the input signal shown in FIG. Is a code (1, -1, -1, 1) for decoding the first MF input signal 21-1 shown in FIG. 6 (E-1). In the decoder described with reference to FIG. 3 (A), the code used to encode the input signal of the first channel has a code length of 4 (1, -1, -1, 1) Therefore, it coincides with the code (1, -1, -1, 1) for decoding the first MF input signal 21-1 shown in FIG. 6 (E-1). The meaning of is completely different.

  On the other hand, the second MF 28 is a circuit similar to the matched filter circuit for decoding the signal of the second channel shown in FIG. 3 (B) in order to explain the conventional decoder. However, the decoding code set in the second MF 28 is different from the code (1, -1, 1, -1) obtained by encoding the input signal shown in FIG. 6 is a code (-1, 1, 1, -1) for decoding the second MF input signal 23 shown in (E-2). In the decoder described with reference to FIG. 3B, the code used to encode the input signal of the second channel has a code length of 4 (-1, 1, -1, 1) Therefore, it is different from the code (-1, 1, 1, -1) for decoding the second MF input signal 21-2.

In general, an input electrical signal 11 encoded with a code having a code length of 8 (c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , c ₆ , c ₇ , c ₈ ) The codes set in the first MF 24 and the second MF 28 for decoding by the parallel decoder are the code (c ₁ , c ₃ , c ₅ , c ₇ ) and the code (c ₂ , c ₄ , c ₆ , c ₈ ). In other words, the code set in the first MF 24 is configured by sequentially arranging only the code values of the odd-numbered chips of the code used for encoding the input electrical signal 11. On the other hand, the code set in the second MF 28 is configured by sequentially arranging only the code values of even-numbered chips of the codes used for encoding the input electrical signal 11. The same is true even if the code length of the code used to encode the input electrical signal 11 is 16 or the like.

  The first MF input signal 23 is input to an input terminal indicated by Q of the first MF 24. Further, a delay 1/2 frequency-divided clock signal 45-3 is input to an input terminal indicated by R.

  The first MF input signal 23 shown in FIG. 6 (E-1) is correlated with the code (1, -1, -1, 1) by the first MF 24, and the first correlation signal 25-1 is obtained. The process to be generated will be described.

  As described above, the delay ½ frequency divided clock signal 45-1 (shown in FIG. 6B) is input to the clock input terminal R of the CCD shift register 140. The first MF input signal 23 (shown in FIG. 6E-1) is input to the data input terminal Q of the CCD shift register 140.

First, the data input terminal D ₁ of the first stage of the CCD shift register 140 has “1” of the first MF input signal 23 (the time slot indicated as CS 1 in FIG. 6 (E-1) is 1). If.) is inputted in synchronization with the clock signal, "1" is output from the output terminal to Q ₁ first stage. Then, "-1" in the first MF input signal 23 to the data input terminal D ₁ of the first stage (time indicated as CS2 in FIG. 6 (E-1) slot is -1.) Of When input, “−1” is output from the first stage output terminal Q ₁ and “1” is output from the second stage output terminal Q ₂ in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to the data input terminal D ₁ of the first stage, in synchronization with a clock signal, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

The first MF input signal 23, just in all chips that are time slots from CS1 to CS4 stage input from the data input terminal D ₁ of the CCD shift register 140, each of the outputs of the fourth stage from the first stage The output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) from the output terminals of the terminals, Q ₁ , Q ₂ , Q ₃ and Q ₄ are (1, -1, -1, 1). In other words, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first to fourth stages are the voltage values at the positions indicated by F, G, H, and I in the CCD shift register 140. appear.

  The voltage value at position F and the voltage value at position I are input to the plus signal adder 142, combined by the electrical signal combiner 154, and input to the amplifier 150. The voltage value at position F and the position I Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position G and the voltage value at position H are input to the negative signal adder 144, combined by the electrical signal combiner 156, and input to the inverting amplifier 152, and the voltage value of the position G And a voltage value corresponding to the sum of the voltage value at position H (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the synthesis circuit 32.

Q ₁ , Q ₂ , Q _3, and Q ₄ output terminals when all the chips of the first MF input signal 23 that are present in the time slot from CS1 to CS4 are all input from the data input terminal of the CCD shift register 140 Output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) becomes (1, -1, -1, 1), so that the electric signal multiplexer 154 uses the potentials at the F and I positions. A certain potential 1 and potential 1 are input, and the potential 2 is input to the amplifier 150. In addition, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are the electric potentials at the positions G and H, and inputs the electric potentials −2 to the inverting amplifier 152.

  Therefore, the amplifier 150 outputs a signal having a potential proportional to the potential 2 (here, the amplification factor is 1 for simplicity), and the inverting amplifier 152 inverts the potential −2 (here, the simple Therefore, the amplified signal of potential 2 is output, and both signals are combined by the analog adder 146 and input to the synthesis circuit 32.

The next time the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 becomes (1, -1, -1, 1) is the chip that exists in the time slots from CS9 to CS12 Are all input from the data input terminal of the CCD shift register 140. Also at this time, the first correlation signal 25-1 having the potential 4 is generated from the data output terminal of the CCD shift register 140 and input to the synthesis circuit 32.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), the data output of the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4. This is because the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (1, -1, -1, 1), for example, (-1, -1, 1, 1 ) Etc., it is clear if the same explanation as above is considered.

The signal output from the data output terminal of the CCD shift register 140 of the first MF 24 is the first correlation signal 25-1. FIG. 6 (F-1) shows the time waveform of the first correlation signal 25-1 with the potential normalized to 1. In FIG. 6 (F-1), the pulse indicated by “1” is the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 next to (1, −1, −1 , 1). In FIG. 6 (F-1), the pulse indicated by “−1” is the next output value (−1, 1) of the CCD shift register 140 (Q ₁ , Q ₂ , Q ₃ , Q ₄ ). , 1, -1).

  Next, the second MF input signal 27 shown in FIG. 6 (E-2) is correlated with the code (-1, 1, 1, -1) by the second MF 28 to obtain the second correlation signal 25. Explain the process of generating -2.

  As described above, the delay ½ frequency division clock signal 45-4 (shown in FIG. 6B) is input to the clock input terminal T of the CCD shift register 140. Further, the second MF input signal 27 (shown in FIG. 6E-2) is input to the data input terminal S of the CCD shift register 140.

  The difference between the first MF 24 and the second MF 28 is a difference in which signal input to the amplifier 150 and the inverting amplifier 152 is extracted from any of F, G, H, and I positions. In the first MF 24, an input signal to the amplifier 150 is taken out from positions F and I, and an input signal to the inverting amplifier 152 is taken out from positions G and H. On the other hand, in the second MF 28, the input signal to the amplifier 150 is taken out from the positions G and H, and the input signal to the inverting amplifier 152 is taken out from the positions F and I.

First, the data input terminal D ₁ of the first stage of the CCD shift register 140, "-1" (Fig. 6 (E-2) CS1 and indicated time slots of the 2 MF input signal 27 becomes -1 When it has.) is inputted in synchronization with the clock signal, "-1" is output from the output terminal to Q ₁ first stage. Then, "1" of the 2 MF input signal 27 (FIG. 6 (E-2) of CS2 and the indicated time slot is set to 1.) Is input to the data input terminal D ₁ of the first stage Then, “1” is output from the first stage output terminal Q ₁ and “−1” is output from the second stage output terminal Q ₂ in synchronization with the clock signal. Thus successively CS3 and indicated time slot, when a signal CS4 and the indicated time slot is inputted to data input terminal D ₁ of the first stage, in synchronism with clock signals, first from the first stage From the four-stage output terminals, the previously output signals are shifted one by one and output.

At the stage where all the chips present in the time slot from CS1 to CS4 of the second MF input signal 27 are all input from the data input terminal of the CCD shift register 140, the output terminals of the first stage to the fourth stage, Q _1, Q _2, Q ₃ and an output value from the output terminal of Q ₄ (Q _1, Q _2, Q _3, Q ₄₎ is (- 1, 1, 1, -1) becomes. In other words, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the first to fourth stages are the voltage values at the positions indicated by F, G, H, and I in the CCD shift register 140. appear.

  The voltage value at position G and the voltage value at position H are input to the plus signal adder 142, combined by the electric signal combiner 154, and input to the amplifier 150. Is output as a signal corresponding to the sum of the voltage values of On the other hand, the voltage value at position F and the voltage value at position I are input to the negative signal adder 144, combined by the electric signal combiner 156, input to the inverting amplifier 152, and the voltage value of the position F. And a voltage value corresponding to the sum of the voltage value at position I (a negative value) is converted into a positive voltage value and output.

  The output signal from the amplifier 150 and the output signal from the inverting amplifier 152 are combined by the analog adder 146 and input to the synthesis circuit 32.

Q ₁ , Q ₂ , Q _3, and Q ₄ output terminals when all the chips of the second MF input signal 27 that are present in the time slot from CS1 to CS4 are all input from the data input terminal of the CCD shift register 140 Since the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) from (1) are (-1, 1, 1, -1), the electric signal multiplexer 154 uses the potentials at the G and H positions. A certain potential 1 and potential 1 are input, and the potential 2 is input to the amplifier 150. Further, the electric signal multiplexer 156 receives the electric potentials −1 and −1 which are electric potentials at the positions F and I, and inputs the electric potential −2 to the inverting amplifier 152.

  Therefore, a signal having a potential proportional to the potential 2 is output from the amplifier 150, and a signal having a potential 2 in which the potential -2 is inverted is output from the inverting amplifier 152. Both signals are combined by the analog adder 146. The second correlation signal 29 having the potential 4 is generated and input to the synthesis circuit 32.

The output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is (-1, 1, 1, -1) next in the chip in the time slot from CS5 to CS8 Are all input from the data input terminal of the analog shift register 140. Similarly, at this time, the second correlation signal 29 having the potential 4 is input to the synthesis circuit 32.

When the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is different from (-1, 1, 1, -1), the data output of the CCD shift register 140 A signal having a potential of 4 or higher is never output from the terminal, and the potential is always less than 4.

As described above, only when the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 matches the set sign, the potential 4 from the data output terminal of the CCD shift register 140 Is output as the second correlation signal 29 and is input to the synthesis circuit 32.

FIG. 6 (F-2) shows the time waveform of the second correlation signal 29 with the potential normalized to 1. In the pulse shown as “1” in FIG. 6 (F-2), the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 is the next (-1, 1, 1, -1) This is the moment. In FIG. 6 (F-2), the pulse indicated by “-1” is the output value (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) of the CCD shift register 140 next to (1, −1). , -1, 1).

In the CCD shift register 140 of the second MF 28, the output values (Q ₁ , Q ₂ , Q ₃ , Q ₄ ) are set as in the CCD shift register 140 of the first MF input signal 23. Only when it matches the sign, it is output from the data output terminal of the CCD shift register 140 as the second correlation signal 29 having the potential 4, and is input to the synthesis circuit 32.

  The first correlation signal 25-1 having the time waveform shown in FIG. 6 (F-1) and the second correlation signal 29 having the time waveform shown in FIG. 6 (F-2) are input to the synthesis circuit 32. Then, a composite signal 33 given as the sum of the intensities of the two is generated. The synthesized signal 33 is input to the determination circuit 34, subjected to threshold processing, and a decoded signal 35 shown in FIG. 6 (G) is generated and output. That is, the combined signal 33 is input to the determination circuit 34, threshold determination processing is performed, and the time zone in which the intensity of the combined signal 33 exceeds the threshold level is set to level 1, and the intensity of the combined signal 33 is set to the threshold level. It is generated and output as a decoded signal with level 0 as the lower time zone.

  Here, since the parallel decoder of the first embodiment has been described on the assumption that it is configured using an analog matched filter, the first correlation signal 25-1 and the second correlation signal 29 are analog signals. Is output. Therefore, the time waveform to be shown in FIGS. 6 (F-1) and (F-2) is not a rectangular wave but a pulse waveform having a complicated shape originally. However, for ease of explanation, the time waveforms shown in FIGS. 6 (F-1) and (F-2) are obtained by simplifying actual waveforms with rectangular waves.

  The first correlation signal 25-1 and the second correlation signal 29 are output as analog signals, but are decoded by the parallel decoder of the first embodiment by performing threshold processing by the determination circuit 34. The signal 35 is a binary digital signal composed of rectangular pulses.

  If the parallel decoder of the first embodiment is configured using an analog matched filter, the first correlation signal 25-1 and the second correlation signal 29 are output as binary digital signals, so that the determination circuit 34 Even if the threshold processing is not performed, the determination unit 30 can easily generate the decoded signal 35 by using only an AND circuit that generates and outputs a logical product by omitting the threshold processing. However, at present, the analog matched filter is superior in high-speed operation compared to the digital matched filter, so that there is an advantage of configuring a parallel decoder using the analog matched filter.

It can be seen that the time waveform of the first correlation signal 25-1 shown in FIG. 6 (F-1) and the second correlation signal 29 shown in FIG. 6 (F-2) are out of phase by one chip pulse. . That is, the phase of the second correlation signal 29 is advanced by one chip pulse with respect to the first correlation signal 25-1.
This is because the first electric signal 21-1 and the second electric signal 21-2 are alternately branched by the two-branch switch 20 one by one in sequence of the chip pulses of the input electric signal 11-1 arranged on the time axis. Since it is a generated signal, the first chip pulse of the second electric signal 21-2 is advanced by one chip pulse on the time axis with respect to the first chip pulse of the first electric signal 21-1. by. The same applies to the second and subsequent chip pulses of the first electric signal 21-1 and the second electric signal 21-2, so the phase of the second correlation signal 29 with respect to the first correlation signal 25-1 Will advance by one chip pulse.

  Therefore, the first correlation signal 25-1 is input after the first MF 24, and the delayed first correlation signal 25-2 is added to the first correlation signal 25-1 by adding a phase delay of one chip pulse. It can be seen that it is preferable to provide a first correlation signal delay 36 that is generated and output so that the phases of the first correlation signal and the second correlation signal are aligned.

In FIG. 6 (F-1), the delayed first correlation signal 25-2 output from the first correlation signal delay unit 36.
Is represented by a broken line. Further, in FIG. 6 (G), the time waveform of the synthesized signal 33 generated by synthesizing the delayed first correlation signal 25-2 and the second correlation signal 29 by the synthesis circuit 32 included in the determination unit 30, It is indicated by a broken line. Thus, by providing the first correlation signal delay device 36 that is a means for matching the phases of the first correlation signal and the second correlation signal, the parallel decoder of the first embodiment for some reason causes the first It can be seen that even if fluctuations occur in the phase of the correlation signal or the second correlation signal, it becomes difficult to generate a combined signal of the first correlation signal and the second correlation signal.

  After the phases of the first correlation signal and the second correlation signal are matched, the synthesis circuit 32 provided in the determination unit 30 generates the synthesized signal 33 of the delayed first correlation signal 25-2 and the second correlation signal 29. In addition, by performing a threshold determination process on the combined signal 33 and outputting it as the decoded signal 35, the decoding process is performed more reliably. That is, by providing the first correlation signal delay device 36 at the subsequent stage of the first MF 24, the reliability of the operation of generating the synthesized signal 33 in the synthesis circuit 32 is increased, and the received signal generated by decoding is generated. It is possible to reduce the error.

<Parallel Decoder of Second Embodiment>
With reference to FIG. 8, the configuration and operation of the parallel decoder according to the second embodiment will be described. FIG. 8 is a schematic block diagram of the parallel decoder according to the second embodiment. In the following description, overlapping description of the components that can obtain the same effects as those of the parallel decoder of the first embodiment, including the contents of the effects, is omitted.

[Constitution]
The parallel decoder 52 according to the second embodiment includes a control signal generation unit 56 and a decoding unit 54 that receives the input electric signal 51, decodes it, and outputs it.

  An optical signal 49 that is input from the outside and is transmitted after being encoded is received by the O / E converter 50, generated as an input electrical signal 51, and input to the parallel decoder 52 of the second embodiment. Is done. The input electric signal 51 is branched into two by the branching device 58 into an input electric signal 51-1 and an input electric signal 51-2. The signal is input to the signal generator 56.

The control signal generator 56 includes a clock signal extractor 80, a 1/2 ^N frequency divider 82, and a timing adjuster 84. The clock signal extraction unit 80 extracts the clock signal 81 from the input electric signal 51-2 and outputs it.

The 1/2 ^N frequency divider 82 receives the clock signal 81 and generates and outputs a 1/2 ^N frequency-divided clock signal 83 having a frequency of 1/2 ^{N of the} clock signal. The timing adjuster 84 adjusts the timing of the 1/2 ^N frequency-divided clock signal by giving a delay to the 1/2 ^N frequency-divided clock signal 83, so that the first speed converter 62-1 to the second ^N speed A clock signal synchronized with the first to second ^N electrical signals is supplied to the converter 62-2 ^N and the first MF 64-1 to the second ^N MF 64-2 ^N , respectively.

The 1/2 ^N divided clock signal 83 is also supplied to the 2 ^N branch switch 60. The delay 1/2 ^N divided clock signals 85, the splitter 78 is branched to the delay 1/2 ^N divided clock signal 85-1～85-2 ^N and 87-1～87-2 ^N, The first speed converter 62-1, the second speed converter 62-2,..., The second ^N speed converter 62-2 ^N and the first MF 64-1 respectively included in the decoding unit 54. , Second MF 64-2,..., Second ^N MF 64-2 ^N.

In FIG. 8, for the sake of simplification and ease of viewing, the delay 1/2 ^N frequency-divided clock signal 85 output from the timing adjuster 84 is simply branched by the branching device 78 to be converted into the first speed converter 62-1. - a first 2 ^N rate converter 62-2 ^N, is shown to be supplied to the 1 MF 64-1~ first 2 ^N MF 64-2 ^N. However, the actual configuration of this part is different for the first speed converter 62-1 to the second ^N speed converter 62-2 ^N and the first MF 64-1 to the second ^N MF 64-2 ^N. It should be understood that the timing amount is adjusted and supplied.

Control signal generating unit 56, as described above, to extract a clock signal 81 from the input electrical signal 51-2, 1/2 ^N divided clock signals 83 of 1/2 ^N the frequency of the clock signal 81, and this 1/2 ^N divided clock signals has a function of generating a delay 1/2 ^N divided clock signal 85 to which the delay is given which are required for synchronization can take output.

Decoding unit 54, a 2 ^N-branch switch 60, the first speed converter 62-1, second speed converter 62-2, ..., a 2 ^N rate converter 62-2 ^N, and the first MF 64-1, second MF 64-2,..., Second ^N MF 64-2 ^N , and determination unit 70.

The 2 ^N branch switch 60 synchronizes with the 1/2 ^N frequency-divided clock signal 83, one by one for the chip pulses of the input electrical signal 51-1 arranged on the time axis, and 1 for 2 ^N chip pulses. as a cycle, the first to 2 ^N -th branch chip pulse train obtained by branching, as first to 2 ^N electrical signals 61-1 and 61-2 ^N, and outputs, respectively.

For example, when N = 2 and the code length is 16, the codes (c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , c ₆ , c ₇ , c ₈ , c ₉ , c ₁₀ , c ₁₁ , c ₁₂ , c ₁₃ , c ₁₄ , c ₁₅ , c ₁₆ ) Input electrical signal 51-1 encoded with 2 ^2- branch switch (4-branch switch) is explained as follows. become. That is, the first electric signal 61-1 becomes (c ₁ , c ₅ , c ₉ , c ₁₃ ), and the second electric signal 61-2 becomes (c ₂ , c ₆ , c ₁₀ , c ₁₄ ), The third electric signal 61-3 becomes (c ₃ , c ₇ , c ₁₁ , c ₁₅ ), and the fourth electric signal 61-4 becomes (c ₄ , c ₈ , c ₁₂ , c ₁₆ ).

2 ^N-branch switch 60, like the two-branch switch 20, and a 1/2 ^N divided clock signals 83 to trigger an input electrical signal 51-1, and parallelism to the first to 2 ^N electrical signal output It has a function to do. As a switch having such a function, for example, a trade name “Serial Controlled 8-Channel SPST Switch MAX335” (Maxim Japan Co., Ltd.) can be used in appropriate combination.

Further, 2 ^N-branch switch 60 is a 1/2 ^N divided clock signals 83, by controlling the output gate 2 ^N-branch switch 60 is equipped, by controlling the input electrical signal 51-1, the first It is also possible to generate and output the second ^N electrical signal. For example, the product name “multiplexer / switch MAX4524 or MAX4525” (Maxim Japan Co., Ltd.) can be used in appropriate combination.

The first speed converter 62-1 reduces the bit rate frequency of the first electric signal 61-1 to 1/2 ^N in synchronization with the delay 1/2 ^N divided clock signal 85-1, and reduces the first MF A first MF input signal 63-1 that is an input signal to 64-1 is generated and output. Similarly, the 2 ^N rate converter 62-2 ^N, in synchronization with the delayed 1/2 ^N divided clock signals 85-2 ^N, the bit rate frequency of the 2 ^N electrical signals 61-2 ^N 1 / an input signal is reduced to a 2 ^N MF 64-2 ^N to 2 ^N and generates a first 2 ^N MF input signal 63-2 ^N outputs.

The first MF 64-1 receives the first MF input signal 63-1 and performs correlation processing on the first MF input signal 63-1 to generate and output a first correlation signal 65-1. Similarly, the 2 ^N MF 64-2 ^N inputs the first 2 ^N MF input signal 63-2 ^N, the 2 ^N correlation signal 65 the first 2 ^N MF input signal 63-2 ^N Correlates -2 Generate and output ^N.

8, except for the subsequent second ^N MF 64-2 ^N, the first MF 64-1～ the second second-stage of the ^{N-1 MF 64-2 N-1} , the first correlation signal delayer 76, respectively -1 to 2nd ^N-1 correlation signal delay device 76-2 ^N-1 (the 2nd ^N-1 correlation signal delay device 76-2 ^N-1 is not shown). That is, the j-th correlation signal is input to the subsequent stage of the j-th MF, and a delayed j-th correlation signal is generated and output by adding a phase delay corresponding to j times one chip pulse to the j-th correlation signal. Includes a signal delay. Next, the determination unit 70 generates a composite signal of the delayed first correlation signal to the delayed second (2 ^N -1) correlation signal and the second ^N correlation signal, performs threshold determination processing of the composite signal, and generates a decoded signal It is the composition to output. Here, j is an all integers 1~ (2 ^N -1).

In other words, the first correlation signal delay unit 76-1 to the second ^N-1 correlation signal delay unit 76-2 ^N-1 are respectively connected from the first correlation signal 65-1 to the second ^N-1 correlation signal 65-2. ^N-1 to 1 chip pulses to 2 ^N-1 generates and outputs a chip pulses in addition to phase delay delays the first correlation signal 77-1～ delay the 2 ^N-1 correlation signal 77-2 ^N-1 It has a function to do. Although details will be described later, the first correlation signal delay unit 76-1 to the second ^N-1 correlation signal delay unit 76-2 ^N-1 are provided in the synthesis circuit 72 including the determination unit 70 in the ^first correlation signal delay unit 76-2 ^N- 1. Thus, it is possible to completely match all phases of the second ^N correlation signal.

However, the above-described correlation signal delay units (the first correlation signal delay unit 76-1 to the second ^N-1 correlation signal delay unit 76-2 ^N-1 ) are not necessarily included.

Therefore, in the following description, first, it is assumed that the first correlation signal delay device 76-1 to the second ^N-1 correlation signal delay device 76-2 ^N-1 is not provided, and then, The case where the first correlation signal delay unit 76-1 to the second ^N-1 correlation signal delay unit 76-2 ^N-1 are provided will be described. Therefore, in the following description, in particular, until refer first correlation signal delayer 76-1～ first 2 ^N-1 correlation signal delayer 76-2 ^N-1, the first correlation signal delayer 76-1～ It should be understood that the second ^N-1 correlated signal delay unit 76-2 ^N-1 is not provided.

The determination unit 70 includes a synthesis circuit 72 and a determination circuit 74. Combining circuit 72 generates and outputs a composite signal 73 of the first correlation signal 65-1～ first 2 ^N correlation signal 65-2 ^N. The synthesized signal 73 is input to the determination circuit 74, subjected to threshold determination processing, and a decoded signal 75 is generated and output. That is, the combined signal 73 is input to the determination circuit 74, threshold determination processing is performed, and the time zone in which the intensity of the combined signal 73 exceeds the threshold level is set to level 1, and the intensity of the combined signal 73 is set to the threshold level. It is generated and output as a decoded signal with level 0 as the lower time zone.

[Operation]
In the following description of the operation of the parallel decoder of the second embodiment, the case of N = 2 is assumed. That is, the parallel decoder according to the second embodiment is characterized in that 2 ² (= 4) analog matched filters are used to decode a signal for one channel. As described above, the parallel decoder of the second embodiment shown below divides the signal for one channel into four parts and divides the decoding process into four analog matched filters, thereby reducing the bit rate of the input signal by half. It is possible to decode the input signal at the operation speed. That is, the parallel decoder of the second embodiment shown below performs correlation processing synchronized with a low-speed clock signal having a cycle of 1/4 of the bit rate of the input signal by using four analog matched filters. This makes it possible to decode the input signal. Compared with the parallel decoder of the first embodiment, correlation processing synchronized with a slower clock signal is possible.

  Of course, the following description holds true for the case where N ≧ 3.

  With reference to FIGS. 9 (A) to (D) and FIGS. 10 (D) to (G), the operation of the parallel decoder of the second embodiment will be described. FIGS. 9 (A) to (D) and FIGS. 10 (D) to (G) are timing charts for explaining the operation of the parallel decoder according to the second embodiment. It is divided into However, in order to make the timing chart easier to see, the time waveform of the 1/4 frequency-divided clock signal input as the synchronization signal to the 4-branch switch, which is the reference for the operation, is shown in FIG. 9 (D) and FIG. 10 (D ) Are shown in duplicate.

  Similar to the description of the operation of the parallel decoder of the first embodiment, in the description of the operation of the parallel decoder of the second embodiment, the transmission signal is (1, 1, 0,...) Assuming it is (1, 1, -1, ...) when converted to a binary signal. The transmission signal (1, 1, 0, ...) has a code length of 16 (1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0) is assumed to be encoded and transmitted.

  The optical signal 49 inputted from the outside to the O / E converter 50 provided in the preceding stage of the input of the parallel decoder 52 of the second embodiment is a transmission signal (1, 1, 0,...). It is an optical signal encoded by a code (1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0).

  In FIGS. 9A to 9D and FIGS. 10D to 10G, the time waveforms shown in FIGS. 9A to 10G are as follows. Here, each time waveform is represented by binary signals of 1 and -1. The horizontal axis indicates the direction of the time axis and the vertical axis is omitted, but the direction of the vertical axis indicates the signal strength.

  The time waveform (A) is a time waveform of the transmission signal (1, 1, 0,...) Before being encoded.

  The time waveform (B) is a time waveform indicating a code used for encoding on the transmission side. Therefore, the time waveform (B) is a rectangle indicating a code string given by (1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0). The pulse train appears repeatedly as one period. This one period corresponds to one bit of the transmission signal (1, 1, 0,...) Before encoding. That is, 16 chip pulses corresponding to the code length 16 are accommodated in a 1-bit time slot of the transmission signal before being encoded.

  The time waveforms (C-1) to (C-4) show the time waveforms of the first electric signal 61-1 to the fourth electric signal 61-4, respectively. The first electric signal 61-1 to the fourth electric signal 61-4 are sequentially supplied to the chip pulses of the input electric signal 51-1 arranged on the time axis one by one by the 4-branch switch 60. As one cycle, the first to fourth branch chip pulse trains obtained by branching are output as first to fourth electric signals, respectively.

  That is, an input electric signal encoded with a code having a code length of 16 (1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0) 51-1 is branched into four by a four-branch switch, and the first electric signal 61-1 to the fourth electric signal 61-4 are generated. That is, the first electric signal 61-1 becomes (1, 0, 0, 1, ...), the second electric signal 61-2 becomes (0, 1, 1, 0, ...), The third electric signal 61-3 becomes (0, 1, 0, 1,...), And the fourth electric signal 61-4 becomes (1, 0, 1, 0,...). When the first electric signal 61-1 to the fourth electric signal 61-4 are displayed as binary digital signals “1” and “−1”, the first electric signal 61-1 is (1, −1, −1). , 1, ...), the second electric signal 61-2 becomes (-1, 1, 1, -1, ...), and the third electric signal 61-3 becomes (-1, 1, -1, 1, ...) and the fourth electric signal 61-4 becomes (1, -1, 1, -1, ...).

  The chip pulses arranged on the time waveform (C-1) are represented by code sequences (1, -1, -1, 1, 1, -1, -1, 1, ...). The chip pulses arranged on the time waveform (C-2) are code sequences (-1, 1, 1, -1, -1, 1, 1) with the code sequence (-1, 1, 1, -1) as one cycle. 1, -1, ...). The chip pulses arranged on the time waveform (C-3) are code sequences (-1, 1, -1, 1, -1, 1, 1) with the code sequence (-1, 1, -1, 1) as one cycle. -1, 1, ...). The chip pulses arranged on the time waveform (C-4) are code sequences (1, -1, 1, -1, 1, -1, 1, -1, ...).

  In the time waveforms (C-1) to (C-4), the width on the time axis occupied by one chip pulse is the same as the width on the time axis occupied by one chip pulse in the time waveform (B). The feature is that it is 4 times the width of. In other words, for example, the first chip in the time waveform (C-1) has a code value of `` 1 '', which is four times the width occupied by the first chip on the time axis in the time waveform (B). You can see that it exists. In the time waveform (B), the time width for one bit of the chip pulse is one width of the parallel line indicated by the vertical broken line, whereas in the time waveform (C-1), the chip pulse 1 The time width for bits is four widths of parallel lines indicated by vertical broken lines. This means that the bit rate in the time waveforms (C-1) to (C-4) is 1/4 of the bit rate in the time waveform (B).

  A time waveform (D) shows a time waveform of the 1/4 frequency-divided clock signal 83 input to the 4-branch switch 60 as a synchronization signal.

  Time waveforms (E-1) to (E-4) show time waveforms of the first MF input signal 63-1 to the fourth MF input signal 63-4, respectively. The time waveforms (F-1) to (F-4) show the time waveforms of the first correlation signal 65-1 to the fourth correlation signal 65-4, respectively. The first correlation signal 65-1 to the fourth correlation signal 65-4 are output from the first MF 64-1 to the fourth MF 64-4, respectively, and input to the determination unit 70.

  The codes for decoding set in the first MF 64-1 to the fourth MF 64-4 are as follows when represented by code strings. That is, the code set for the first MF 64-1 is (1, 0, 0, 1), and the code set for the second MF 64-2 is (0, 1, 1, 0). Yes, the code set for the third MF 64-3 is (0, 1, 0, 1), and the code set for the fourth MF 64-4 is (1, 0, 1, 0). is there. The decoding operations performed by the first MF 64-1 to the fourth MF 64-4 are different only in the decoding codes set for the first MF 64-1 to the fourth MF 64-4. Since it is the same as the decoding operation by the 1 MF 24 and the second MF 26, a duplicate description is omitted. 6 (E-1) and (E-2) and FIGS. 10 (E-1) to (E-4), CS1 to CS4 shown in FIGS. 1 (A2) and (B2) are shown. The same symbols CS1 to CS4 are attached to the time slots corresponding to these time slots to indicate the corresponding relationship.

  The time waveform (G) shows the time waveform of the decoded signal 75 output from the determination unit 70. The signal represented by the time waveform (A) is a signal in the NRZ format, whereas the signal represented by the time waveform (G) is different from the signal in the RZ format, but this time waveform (G) It can be seen that the transmission signal (1, 1, -1,...) That is a binary digital signal shown in the time waveform (A) is decoded.

  The contents described above with reference to the timing charts shown in FIGS. 9 (A) to 9 (D) and FIGS. 10 (D) to (G) are summarized as follows.

  The optical signal 49 is input to the O / E converter 50, converted into an input electrical signal 51, and output. The input electrical signal 51 is branched into four by the branching device 58 from the input electrical signal 51-1 to the input electrical signal 51-4. The input electrical signal 51-1 to the input electrical signal 51-4 are respectively the first speed converter Input to 62-1 to fourth speed converter 62-4. The bit rate of the first MF input signal 63-1 to the fourth MF input signal 63-4 respectively output from the first speed converter 62-1 to the fourth speed converter 62-4 is the bit of the input electric signal 51. Since the rate is 1/4, it can be seen that the first speed converter 62-1 to the fourth speed converter 62-4 can be configured using a 1/4 frequency divider. For example, the 1/4 frequency divider can be configured by a known method using a combination of two D flip-flops.

  The first MF input signal 63-1 to the fourth MF input signal 63-4 are input to the first MF 64-1 to the fourth MF 64-4, respectively, and the first correlation signal 65-1 to the fourth correlation signal are input. 65-4 is input to the combining circuit 72, and is generated and output as a combined signal 73. Here, when a digital matched filter is used as the first MF 64-1 to the fourth MF 64-4, the synthesis circuit 72 can be formed by a logical product circuit (AND circuit). Further, when an analog matched filter is used as the first MF 64-1 to the fourth MF 64-4, the synthesis circuit 72 can be formed by an analog adder. In the above-described embodiment, analog matched filters are used as the first MF 64-1 to the fourth MF 64-4, so an analog adder is used for the synthesis circuit 72.

It is a diagram for explaining the process in which the transmission signal is encoded, (A1) and (A2) shows the transmission signal and the encoded transmission signal of the first channel, respectively (B1) and (B2), respectively (C) shows the time waveform of the code division multiplexed signal in which the encoded transmission signal of the first channel and the encoded transmission signal of the second channel are combined. Show. It is a diagram for explaining the process of decoding a received signal, (A) shows the time waveform of the code division multiplexed signal input to the matched filter, (B) is decoded by the matched filter and output (C1) shows the time waveform of the signal that was output after the threshold judgment in the decision circuit, and (C2) shows the clock signal for latching the signal shown in (C1) (D) shows the time waveform of the received signal obtained by latching the signal that has been subjected to the threshold determination shown in (C1) and output with the clock signal shown in (C2). FIG. 2 is a schematic block configuration diagram of a matched filter, where (A) is a circuit for decoding a first channel signal and (B) is a circuit for decoding a second channel signal. . FIG. 2 is a schematic block configuration diagram of a determination circuit and a diagram for explaining an operation principle thereof, (A) is a schematic block configuration diagram of a determination circuit, and (B) is a decoding output from a matched filter. (C) shows the time waveform of the signal output after the threshold judgment. FIG. 2 is a schematic block configuration diagram of a parallel decoder according to the first embodiment. FIG. 6 is a timing chart for explaining the operation of the parallel decoder of the first embodiment, (A) shows a time waveform of a transmission signal (1, 1, 0,...) Before being encoded; (B) shows a time waveform indicating the code used for encoding on the transmission side, and (C-1) and (C-2) show the time waveforms of the first electric signal and the second electric signal, respectively. (D) shows the time waveform of the 1/2 frequency-divided clock signal input as a synchronization signal to the 2-branch switch, (E-1) and (E-2) are the first MF input signal and The time waveform of the second MF input signal is shown, (F-1) and (F-2) show the time waveforms of the first correlation signal and the second correlation signal, respectively, and (G) is output from the determination unit. The time waveform of the decoded signal is shown. FIG. 3 is a schematic block configuration diagram of a first MF, a second MF, and a determination unit of the parallel decoder according to the first embodiment. FIG. 5 is a schematic block configuration diagram of a parallel decoder according to a second embodiment. FIG. 7 is a timing chart for explaining the operation of the parallel decoder of the second embodiment, (A) shows a time waveform of a transmission signal (1, 1, 0,...) Before being encoded; (B) shows the time waveform indicating the code used for encoding on the transmission side, (C-1) ~ (C-4) shows the time waveform of the first to fourth electrical signals, respectively, (D) shows a time waveform of a 1/4 frequency-divided clock signal input as a synchronization signal to the 4-branch switch. FIG. 9 is a timing chart for explaining the operation of the parallel decoder according to the second embodiment, and (D) shows a time waveform of a 1/4 frequency-divided clock signal input as a synchronization signal to the 4-branch switch; -1) to (E-4) show the time waveforms of the first to fourth MF input signals, respectively, and (F-1) to (F-4) show the time waveforms of the first to fourth correlation signals, respectively. (G) shows the time waveform of the decoded signal output from the determination unit.

Explanation of symbols

10, 50: O / E converter
12: Parallel decoder of the first embodiment
14, 54: Decoding part
16, 56: Control signal generator
18, 38-1, 38-2, 58, 78: Branch
20: 2-branch switch
22, 62-1: 1st speed converter
24, 64-1: First matched filter (first MF)
26, 62-2: Second speed converter
28, 64-2: 2nd matched filter (2nd MF)
30, 70: Judgment part
32, 72: Synthesis circuit
34, 74: Judgment circuit
36, 76-1: First correlation signal delay unit
40, 80: Clock signal extractor
42: 1/2 divider
44, 84: Timing adjuster
52: Parallel decoder of the second embodiment
60: 2 ^N branch switch
62-2 ^N : 2nd ^N speed converter
64-2 ^N : 2nd ^N matched filter (2nd ^N MF)
76-2: Second correlation signal delay unit
82: 1/2 ^N frequency divider
86: Comparator
88: D flip-flop circuit
140: Analog shift register
142: Adder for positive signal
144: Adder for negative signal
146: Analog adder
148: Low-pass filter
150: Amplifier
152: Inverting amplifier

Claims (6)

A clock signal is extracted from an encoded input electrical signal input from the outside, and a delay is given to the 1/2 frequency-divided clock signal of 1/2 frequency of the clock signal and the 1/2 frequency-divided clock signal. A control signal generator for generating and outputting the delayed 1/2 frequency divided clock signal;
A decoding unit that inputs the input electrical signal, decodes and outputs the input electrical signal, and
The decoding unit
In synchronization with the 1/2 frequency-divided clock signal, the chip pulses of the input electric signal arranged on the time axis are alternately branched one by one, one branch chip pulse train as the first electric signal, and the other A two-branch switch that outputs a branch chip pulse train of
A first speed converter that generates and outputs a first matched filter input signal by reducing the bit rate frequency of the first electric signal to ½ in synchronization with the delayed 1/2 frequency-divided clock signal;
A second speed converter that generates and outputs a second matched filter input signal by reducing the bit rate frequency of the second electric signal to ½ in synchronization with the delayed 1/2 frequency-divided clock signal;
A first matched filter that receives the first matched filter input signal, correlates the first matched filter input signal to generate and output a first correlation signal;
A second matched filter that receives the second matched filter input signal, correlates the second matched filter input signal to generate and output a second correlated signal; and
A composite signal of the first correlation signal and the second correlation signal is generated, a threshold determination process is performed, and a time zone in which the strength of the composite signal exceeds a threshold level is set to level 1, and the strength of the composite signal is A parallel decoder comprising: a determination unit that outputs a decoded signal with a time zone that is below a threshold level as level 0. A clock signal is extracted from an encoded input electrical signal input from the outside, and a delay is given to the 1/2 frequency-divided clock signal of 1/2 frequency of the clock signal and the 1/2 frequency-divided clock signal. A control signal generator for generating and outputting the delayed 1/2 frequency divided clock signal;
A decoding unit that inputs the input electrical signal, decodes and outputs the input electrical signal, and
The decoding unit
In synchronization with the 1/2 frequency-divided clock signal, the chip pulses of the input electric signal arranged on the time axis are alternately branched one by one, one branch chip pulse train as the first electric signal, and the other A two-branch switch that outputs a branch chip pulse train of
A first speed converter that generates and outputs a first matched filter input signal by reducing the bit rate frequency of the first electric signal to ½ in synchronization with the delayed 1/2 frequency-divided clock signal;
A second speed converter that generates and outputs a second matched filter input signal by reducing the bit rate frequency of the second electric signal to ½ in synchronization with the delayed 1/2 frequency-divided clock signal;
A first matched filter that receives the first matched filter input signal, correlates the first matched filter input signal to generate and output a first correlation signal;
A second matched filter that receives the second matched filter input signal, correlates the second matched filter input signal to generate and output a second correlated signal; and
A first correlation signal delay unit that inputs the first correlation signal, adds a phase delay of one chip pulse to the first correlation signal, and generates and outputs a delayed first correlation signal;
A composite signal of the delayed first correlation signal and the second correlation signal is generated, a threshold determination process is performed, and a time zone in which the strength of the composite signal exceeds a threshold level is set to level 1, and the strength of the composite signal A parallel type decoder comprising: a determination unit that outputs a time zone in which the signal is below the threshold level as a decoded signal having a level 0. The control signal generator is
A clock signal extraction unit for extracting and outputting the clock signal from the input electrical signal;
A 1/2 divider that inputs the clock signal, generates and outputs a 1/2 divided clock signal of 1/2 frequency of the clock signal,
A delay is applied to the 1/2 divided clock signal to generate a delayed 1/2 divided clock signal, which is synchronized with the first and second electric signals and the first and second matched filter input signals, respectively. A timing adjuster that outputs as a clock signal,
3. The parallel decoder according to claim 1, further comprising an output delay unit. From the encoded input electric signal input from the outside to extract the clock signal, 1/2 ^N divided clock signal of 1/2 ^N the frequency of the clock signal, and said 1/2 ^N divided clock signal A control signal generator for generating and outputting a delay 1/2 ^N divided clock signal to which a delay is given;
A decoding unit that inputs the input electrical signal, decodes and outputs the input electrical signal, and
The decoding unit
In synchronization with the 1/2 ^N frequency-divided clock signal, the chip pulses of the input electric signal arranged on the time axis are sequentially one by one, and the 2 ^N chip pulses are divided into one cycle to obtain a first cycle. 1 the first 2 ^N-th branch chip pulse train, as first to 2 ^N electrical signals, and 2 ^N-branch switch for outputting respectively,
The kth speed converter for generating and outputting the kth matched filter input signal by reducing the bit rate frequency of the kth electrical signal to 1 / ^2N in synchronization with the delayed 1 / ^2N frequency-divided clock signal When,
Inputting the k-th matched filter input signal, correlating the k-th matched filter input signal to generate a k-th correlation signal and outputting the k-th matched filter;
A composite signal of the second ^N correlation signal is generated from the first correlation signal, a threshold determination process is performed, and a time zone in which the strength of the composite signal exceeds a threshold level is set to level 1, and the strength of the composite signal is A parallel decoder comprising: a determination unit that outputs a decoded signal with a time zone that is below a threshold level as level 0.
Here, N is an integer of 2 or more, and k is an integer of 1 to ^2N . From the encoded input electric signal input from the outside to extract the clock signal, 1/2 ^N divided clock signal of 1/2 ^N the frequency of the clock signal, and said 1/2 ^N divided clock signal A control signal generator for generating and outputting a delay 1/2 ^N divided clock signal to which a delay is given;
A decoding unit that inputs the input electrical signal, decodes and outputs the input electrical signal, and
The decoding unit
In synchronization with the 1/2 ^N frequency-divided clock signal, the chip pulses of the input electric signal arranged on the time axis are sequentially one by one, and the 2 ^N chip pulses are divided into one cycle to obtain a first cycle. 1 the first 2 ^N-th branch chip pulse train, as first to 2 ^N electrical signals, and 2 ^N-branch switch for outputting respectively,
The kth speed converter for generating and outputting the kth matched filter input signal by reducing the bit rate frequency of the kth electrical signal to 1 / ^2N in synchronization with the delayed 1 / ^2N frequency-divided clock signal When,
Inputting the k-th matched filter input signal, correlating the k-th matched filter input signal to generate a k-th correlation signal and outputting the k-th matched filter;
A j-th correlation signal delay unit that inputs a j-th correlation signal, adds a phase delay corresponding to j times one chip pulse to the j-th correlation signal, and generates and outputs a delayed j-th correlation signal;
A combined signal of the delayed (2 ^N -1) correlation signal and the second ^N correlation signal is generated from the delayed first correlation signal, and a threshold determination process is performed to determine a time period during which the intensity of the combined signal exceeds the threshold level A parallel type decoder comprising: a determination unit configured to output a decoded signal having a level 1 and a level 0 in a time zone in which the intensity of the combined signal is below a threshold level.
Here, N is an integer of 2 or more, j is all integers of 1 to (2 ^N −1), and k is all integers of 1 to 2 ^N. The control signal generator is
A clock signal extraction unit that extracts and outputs a clock signal from the input electrical signal;
Enter the clock signal, a 1/2 ^N divider which generates and outputs a 1/2 ^N divided clock signal of 1/2 ^N the frequency of the clock signal,
The 1/2 ^N divided clock signal is delayed to generate a delayed 1/2 ^N divided clock signal, which is output as a clock signal synchronized with both the kth electrical signal and the kth matched filter input signal. A timing adjuster,
6. The parallel decoder according to claim 4, further comprising:

Images