JP2001094474A - Synchronization detection circuit employing matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make reduction in power consumption by decreasing mis-detection of a peak position due to thinning of samples compatible with maintenance of a synchronization detection characteristic. SOLUTION: After thinning samples of a digital received signal outputted from an A/D conversion circuit 22 into half, the resulting sample is given to a matched filter 43, the digital received signal is divided into groups 1 and 2 for each summing period in the case of thinning processing and different thinning timing is set to the respective groups.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple access (CDMA) as a radio access system.
The present invention relates to a synchronization detection circuit using a matched filter used for detecting a synchronization code coming from a base station in a mobile communication device adopting a Multiple Access (Multiple Access) system.

[0002]

2. Description of the Related Art In recent years, a mobile communication system employing a CDMA system has attracted attention. The CDMA mobile communication system uses a spread spectrum communication system, and performs communication as follows, for example.

[0003] That is, a communication device on the transmitting side firstly primary-modulates digitized voice data and image data by a digital modulation method such as a PSK modulation method. next,
This modulated data is spread into a wideband transmission signal by spread spectrum using a spreading code, and the wideband transmission signal is converted into a radio frequency signal and transmitted. On the other hand, the communication device on the receiving side first performs spectrum despreading on the received radio frequency signal using the same spreading code as that used in the communication device on the transmitting side. Then, PSK (Ph
Primary demodulation is performed by a digital demodulation method such as an ase shift keying (demodulation) method to reproduce received data.

The CDMA system (1) uses a spread spectrum technique to easily maintain a high communication quality with respect to a change in the communication environment such as fading. (2) By using the RAKE reception method, a soft handover is possible, and a stable handover without instantaneous interruption of communication can be realized. (3) High frequency use efficiency can be realized by sharing one radio frequency by many users. Etc., a frequency division multiple access system (FDMA: Frequency)
Division Multiple Access) and time division multiple access (T
It has an advantage that DMA (Time Division Multiple Access) does not have.

By the way, a CDMA communication apparatus used as a mobile station in this type of system executes a procedure for detecting a synchronization code transmitted by a base station and establishing synchronization before communication. For example, W-CDMA (Wideband-Code Division Multipl) proposed by ARIB
e Access) system, the base station generates a synchronization code by spreading a known symbol with a known spreading code,
This synchronization code is inserted into each slot as the 1st Search Code and transmitted. On the other hand, the mobile station is provided with a synchronization detection circuit, and after receiving the above-mentioned known synchronization code arriving from the base station, the mobile station adds the same in the slot length cycle and detects symbol synchronization to establish synchronization. I do.

In general, a matched filter is used for the synchronization detection circuit. FIG. 7 shows an example of the configuration of a matched filter. The matched filter includes a tap unit 1 in which a plurality of taps are connected in series, a multiplying unit 2, and an adding unit 3. Each time the received signal is shifted into the tap unit 1 by one sample, the received signal is extracted from each tap, multiplied by the spreading code by the multiplying unit 2, the multiplied output is added by the adding unit 3, and the output of the filter is added. Get output. That is, the matched filter detects a correlation value between the synchronization code and the spreading code included in the received signal, and outputs a signal corresponding to the correlation value. Therefore, by detecting the timing when the correlation output value becomes maximum, it is possible to establish symbol synchronization with the synchronization code.

[0007] Although a matched filter is useful for synchronization, it has a drawback of large power consumption. Therefore, as one of the measures for reducing the power consumption, a method of lowering the sampling frequency of the received signal is considered.
However, it is generally difficult for the mobile station to reduce the sampling frequency because it is necessary to sample the received signal at a sampling frequency about four times the spread code chip rate for the sake of signal processing.

On the other hand, as another measure for reducing power consumption, a method of reducing only the operating frequency of the matched filter without decreasing the sampling frequency of the received signal has been considered. This technique is realized, for example, by thinning out samples of the received signal input to the matched filter at regular intervals.

However, when this method is used for a CDMA synchronization detection circuit, the following problem occurs. That is, since the signal waveform of the received signal input to the matched filter has passed through the roll filter for waveform shaping,
For example, the waveform is dull as shown in FIG. In the mobile station, the peak position of the waveform is unknown at least until time synchronization is detected.

For this reason, a sample having the maximum amplitude in the output of the matched filter is generally recognized as a peak position. However, in this case, depending on the positional relationship between the thinned sample timing and the peak of the waveform, a value lower than the original peak may be detected as the peak.

For example, when the positional relationship between the sample timing and the peak of the waveform is as shown in FIG. 9A, even if any of the samples of the sample timings .quadrature. The peak values are almost the same, and there is no significant difference in synchronization detection characteristics. However, if the positional relationship between the sample timing and the peak of the waveform is as shown in FIG. 9 (b), the original peak value of the waveform must be detected when △ is thinned and □ is used as the sample timing. Conversely, if □ is thinned out and △ is used as the sample timing, the detected value of the peak will be significantly smaller than the original peak value.

In addition, in the synchronization detection circuit, an adder is provided after the matched filter in order to improve the synchronization detection characteristic, and the adder periodically adds the correlation output of the matched filter. However, the addition cycle is equal to the interval between known symbols for synchronization detection, and is set to a natural number times the chip cycle of the spread code. Therefore, when a peak smaller than the original peak is detected, a smaller peak is always detected and added during the period of periodic addition, and as a result, the synchronization detection characteristic is deteriorated.

[0013]

As described above, in a conventional synchronous detection circuit using a matched filter, depending on the positional relationship between the thinned sample timing and the peak of the waveform, a value smaller than the original peak may be obtained. There is a problem of detection as a peak, and as a result, the synchronization detection characteristic is deteriorated.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the occurrence of erroneous detection of a peak position due to the process of reducing the number of samples, thereby reducing power consumption and synchronizing. It is an object of the present invention to provide a synchronous detection circuit using a matched filter that is compatible with maintaining detection characteristics.

[0015]

According to a first aspect of the present invention, a reception signal converted into a digital signal at a predetermined sampling period is input to a digital matched filter, and the correlation output is also obtained. And a synchronization detection circuit for detecting a synchronization code included in the digital reception signal and establishing synchronization, wherein thinning processing means is provided in a stage preceding the matched filter, and the thinning processing means converts the digital reception signal in the time direction. In this case, samples at relatively different time positions are thinned out for each of these groups and input to the matched filter, and a period adding means is provided at a subsequent stage of the matched filter. , The correlation outputs of the respective groups output from the matched filter are added to each other, and the added outputs are synchronized. It is obtained by configured to provide to the detection processing of the item.

According to a second aspect of the present invention, digital reduction signals are divided into a plurality of groups in the time direction by a sample reduction processing means provided at a preceding stage of the matte filter. The processing of generating a digital received signal with a reduced number of samples by adding a plurality of samples adjacent to each other and inputting the signal to the matched filter is performed in the time direction by combining the samples to be added for each of the plurality of groups. Periodic adding means is provided downstream of the matched filter, the correlation outputs of the respective groups output from the matched filter are added to each other, and the added output is subjected to a synchronous code detection process. It is configured so as to be provided.

Therefore, according to these inventions, the matched filter receives a digital reception signal whose number of samples is reduced by thinning out samples or adding and synthesizing samples. For this reason, the number of taps of the matched filter is reduced, whereby the size of the circuit can be reduced, and the operating clock frequency can be reduced, thereby reducing the power consumption of the matched filter.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a CDMA according to the present invention.
FIG. 2 is a circuit block diagram illustrating a first embodiment of the mobile communication device.

In FIG. 1, a transmitted voice signal of a speaker output from a microphone 10a is converted to a digital signal by an analog-to-digital converter (AD) 11a, and then is converted to a voice coded-decoded ( Voice coder −decoder
, Hereinafter referred to as Vocoder) 12. The vocoder 12 encodes the input digital audio signal at a coding rate of, for example, 64 Kbps.

The control circuit 13 adds a control signal and the like to the coded digital audio signal output from the vocoder 12, and thereby creates transmission data. The transmission data is encoded by a convolutional encoder 15 after an error detection code and an error correction code are added by a data generation circuit 14. Then, the encoded transmission data is subjected to an interleaving process in an interleaving circuit 16. The transmission data output from the interleave circuit 16 is primary-modulated by a modulation circuit (not shown) and then spectrum-spread by a spectrum spreader 17 by a spreading code corresponding to a channel specified by the control circuit 13 to be converted into a wideband signal. Is done. As the primary modulation method, for example, a QPSK method is used.

This spread spectrum transmission signal is:
After unnecessary frequency components are removed by the digital filter 18, a digital-analog converter (DA) 19
Is converted into an analog transmission signal. Then, the analog transmission signal is up-converted to a predetermined radio frequency by the analog front end 20, controlled to a predetermined transmission power level, and then transmitted from the antenna 21 to a base station (not shown).

On the other hand, the spread spectrum radio signal received by the antenna 21 is amplified by the low noise amplifier in the analog front end 20, and then down-converted into a signal of an intermediate frequency or a baseband frequency. The received signal output from the analog front end 20 is converted into an analog-digital converter (A
-D) After being converted into a digital signal at a predetermined sampling period in 22, the digital signal is input to the RAKE receiver 25.

The RAKE receiver 25 has n (n = 1, 2, 2)
3,...) Finger circuits 31 to 3n and a symbol combiner 30. Each of the finger circuits 31 to 3n has a function as a CDMA demodulation circuit, and generates a spreading code corresponding to the wireless communication channel specified by the control circuit 13. Then, by performing spectrum despreading processing on the reception signal of a desired path having a high reception level using the spreading code, the reception signals of a maximum of n paths are separated from the multipath radio signal and reproduced. The symbol synthesizer 30 includes the finger circuits 31 to 3
n, and selectively synthesizes the symbols after synchronizing the timing with the despread signal output from n and outputs the resultant.

The demodulated symbols output from the RAKE receiver 25 are input together with timing information to a primary demodulation circuit (not shown), where they are primarily demodulated, and then input to a deinterleave circuit 26. Then, the deinterleave circuit 26 performs a deinterleave process. The demodulated symbols after the deinterleaving are Viterbi-decoded in the Viterbi decoder 27, and the demodulated symbols after the Viterbi decoding are error-correction-decoded by the error correction circuit 28 to become reception data, which are input to the control circuit 13. .

In the control circuit 13, the input received data is separated into audio data and control data. The voice data is decoded by the vocoder 12 and then converted into an analog signal by a digital-to-analog converter (DA) 11b, and then output from the speaker 10b.

Even when other element data such as image data and computer data are multiplexed with the transmission data, these element data are separated by the control circuit 13 and reproduced by the respective decoders. After that, it is displayed on a display, for example.

The keypad / display 29 is provided for the user to input and set dial data and control data, and to display various information relating to the operation state of the communication device. The operation of the keypad / display 29 is controlled by the control circuit 13.

The finger circuits 31 to 3n
Among them, a specific finger circuit 31 is provided with a synchronization detecting circuit. Note that the synchronization detection circuit may be provided for a plurality of fingers.

As shown in FIG. 2, for example, the synchronization detection circuit includes a timing generation circuit 40, an AD clock generation circuit 41, a latch circuit 42, a matched filter 43,
A frequency dividing circuit 44 and a period adding circuit 45 are provided.

The timing generation circuit 40 generates a reference operation clock and supplies it to the AD clock generation circuit 41.
The AD clock generation circuit 41 generates a sampling clock required for A / D conversion of the received signal based on the reference operation clock and supplies the sampling clock to the A / D converter 22. The A / D converter 22 samples the received signal in synchronization with the sampling clock, and converts the amplitude value into a digital signal.

The timing generation circuit 40 generates a thinning clock required for thinning the received signal sample based on the reference operation clock, and supplies the thinning clock to the latch circuit 42. The latch circuit 42 thins out the sample by latching the digital reception signal output from the AD converter 22 in synchronization with the thinning clock supplied from the timing generation circuit 40, and after thinning out the sample. Is input to the matched filter 43.

The matched filter 43 operates in synchronism with the operation clock supplied from the frequency dividing circuit 44, and outputs the digital received signal after the above-mentioned thinning processing and a spread code generated from a spread code generating circuit (not shown). Find the correlation. Then, the correlation signal is input to the cycle addition circuit 45. The frequency dividing circuit 44 generates the operation clock by dividing the frequency of the sampling clock generated from the AD clock generating circuit 41 by a frequency dividing ratio corresponding to the thinning rate of the received signal sample.

The period addition circuit 45 adds the correlation signal output from the matched filter 43 at a predetermined addition period, that is, one symbol period, and outputs the result.

Next, the operation of the CDMA synchronization detection circuit configured as described above will be described. The received signal output from the analog front end 20 is supplied to an A / D conversion circuit 22.
In step (1), sampling is performed in synchronization with a sampling clock generated from the AD clock generation circuit 41, and converted into a digital signal. At this time, the frequency of the sampling clock is set to four times the chip rate of the spread code. Therefore, the received signal is sampled by the A / D conversion circuit 22 at four samples per chip.

The digital reception signal output from the A / D conversion circuit 22 is input to the matched filter 43 after the sampling circuit is thinned out in the finger circuit 31. That is, the timing generation circuit 4
At 0, the frequency is の of the sampling clock
Is generated, and the latch circuit 42 performs a latch output operation of the digital reception signal in synchronization with the thinned clock. For this reason, the digital reception signal is supplied to
As shown in (a), four samples per chip are reduced to two samples.

Moreover, in this thinning-out process, the digital reception signals are alternately divided into groups 1 and 2 for each addition cycle, and thinned out at different timings for each of the groups 1 and 2.

That is, the phase of the thinned clock output from the timing generation circuit 40 is shifted by one sampling period for each addition period as shown in FIGS. Accordingly, the digital reception signal output from the A / D conversion circuit 22 is latched at the timing shown by ○ as shown in FIG. 3A in one addition cycle, and is shown in FIG. 3B in the next addition cycle. As shown above in Figure 3
It is latched at a timing shifted by one sample period with respect to the latch timing of (a). Thereafter, the latch operation at the timing shown in FIG. 3A and the latch operation at the timing shown in FIG. 3B are alternately performed for each addition cycle.

The digital received signal subjected to the decimation process is input to the matched filter 43, where it is multiplied by a spreading code for each sample in synchronization with the operation clock supplied from the frequency dividing circuit 44 and A correlation is determined. At this time, the frequency of the operation clock is set to の of the sampling clock corresponding to the sampling period of the digital reception signal after the thinning process. Therefore, power consumption by the matched filter 43 is reduced. In addition, the number of samples in one addition cycle of the digital reception signal after the above-described thinning processing is 比 べ of that before the thinning. Therefore, the matched filter 43
, The number of taps can be reduced to で, whereby the circuit size of the matched filter 43 can be reduced.

The correlation signal output from the matched filter 43 is added for a predetermined number of slot periods by the addition cycle after the phase information is removed by the cycle addition circuit 45. That is, group 1 and group 2
Are added to each other for a plurality of cycles, and the added signal is used for synchronization detection. Therefore, the added correlation signal output from the periodic addition circuit 45 includes both the group 1 correlation signal component and the group 2 correlation signal component. Therefore, by performing synchronization detection using the added correlation signal, it is possible to detect a peak value equivalent to the case where a digital reception signal before thinning is used.

As described above, in the first embodiment, A
The samples of the digital reception signal output from the -D conversion circuit 22 are decimated to 1/2 and then input to the matched filter 43. In this decimating process, the digital reception signals are grouped into groups 1 and Group 2 is used, and the thinning-out timing is made different for each of these groups.

Therefore, the operating frequency of the matched filter 43 can be reduced to one-half that of the case where no thinning processing is performed, and the power consumption of the matched filter can be reduced. In addition, the number of samples in one addition cycle of the digital reception signal after the thinning processing is １ ／ of that before the thinning, and as a result, the number of taps of the matched filter 43 is reduced by half.
Circuit size can be reduced. In addition, since the thinning-out timing is made different between Group 1 and Group 2, it is possible to detect a peak value equivalent to that in the case where synchronization detection is performed using a digital reception signal before thinning-out, thereby improving synchronization detection performance. Can be held.

(Second Embodiment) A second embodiment according to the present invention
In this embodiment, two adjacent samples of the digital reception signal are added to each other so that the digital reception signal is decimated from four samples to two samples. In the decimating process, the digital reception signal is grouped for each addition cycle. The positions of the two samples to be added are different for each of the groups 1 and 2.

FIG. 4 is a circuit block diagram showing a configuration of a synchronization detection circuit according to the second embodiment of the present invention. 2, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.

The synchronization detection circuit of this embodiment includes a timing generation circuit 50, a buffer circuit 51, and a buffer control circuit 52. Timing generation circuit 50
Generates a reference operation clock and supplies it to the AD clock generation circuit 41, and also supplies a timing signal indicating an addition cycle to the buffer control circuit 52.

The buffer circuit 51 includes the A / D converter 2
After the digital received signal output from 2 is once written, a process of adding two adjacent samples is performed, and then the digital received signal after the addition process is read and input to the matched filter 43. The buffer control circuit 52 synchronizes with a timing signal indicating an addition cycle generated from the timing generation circuit 50 and a sampling clock generated from the AD clock generation circuit 41 to generate a clock necessary for the operation of the buffer circuit 51. And a control signal, which is supplied to the buffer circuit 51.

Next, the operation of the CDMA synchronization detecting circuit thus configured will be described. The digital reception signal output from the A / D conversion circuit 22 is synchronized with the sampling timing of the A / D conversion circuit 22 by the buffer circuit 51.
Is written to. Then, the two adjacent samples are added to each other on the memory as shown in FIG. 5A, for example, and reduced to one sample. Then, the sample after this addition is read and input to the matched filter 43. You.

In the sample reduction process, the buffer circuit 51 divides the digital reception signals into groups 1 and 2 alternately for each addition cycle in accordance with the timing signal indicating the addition cycle output from the buffer control circuit 52. Is done. Then, for each of these groups 1 and 2, the combination position of the two samples to be added is shifted by one sample.

For example, in a certain addition cycle, FIG.
As shown in (a), two samples from the first sample are combined and added sequentially, and the added sample is output to the matched filter 43. On the other hand, in the next addition cycle, as shown in FIG. 5B, two samples from the second sample from the top are combined and sequentially added, and the added sample is output to the matched filter 43. Is done.

In the matched filter 43, as in the first embodiment, the digital reception signal supplied from the buffer circuit 51 is synchronized with the operation clock supplied from the frequency dividing circuit 44 for each sample. The correlation is obtained by multiplying by the spreading code. At this time, the frequency of the operation clock is set to の of the sampling clock corresponding to the sampling period of the digital reception signal after the thinning processing. Therefore, power consumption by the matched filter 43 is reduced. In addition, the number of samples in one addition cycle of the digital reception signal after the above-described thinning processing is 比 べ of that before the thinning. For this reason, the number of taps of the matched filter 43 can be reduced to １ ／, whereby the circuit size of the matched filter 43 is reduced.

After the phase information is removed from the correlation signal output from the matched filter 43 in the cycle addition circuit 45, the correlation signal is added for each of the addition cycles over a prescribed number of slot periods. That is, group 1 and group 2
Are added to each other for a plurality of cycles, and the added signal is used for synchronization detection. Therefore, the added correlation signal output from the periodic addition circuit 45 includes both the group 1 correlation signal component and the group 2 correlation signal component. Therefore, by performing synchronization detection using the added correlation signal, it is possible to detect a peak value equivalent to that when using a digital reception signal before sample reduction.

As described above, in the second embodiment, A
The sample of the digital reception signal output from the -D conversion circuit 22 is reduced to 1/2 by the buffer circuit 51 and then input to the matched filter 43. In the sample reduction processing, the digital reception signal is added. Each cycle is divided into groups 1 and 2, and the combination position of the two samples to be added is shifted by one sample for each of these groups 1 and 2.

Therefore, also in the second embodiment, the operating frequency of the matched filter 43 can be reduced to half compared with the case where no thinning processing is performed.
Thus, power consumption by the matched filter can be reduced. In addition, the number of samples in one addition cycle of the digital reception signal after the thinning processing is 1 compared to that before the thinning.
As a result, the number of taps of the matched filter 43 can be reduced by half, and the circuit size of the matched filter 43 can be reduced.

Further, since the combination position of the two samples to be added is shifted by one sample between groups 1 and 2, it is equivalent to the case where synchronization detection is performed using a digital reception signal before the number of samples is reduced. , And the synchronization detection performance can be kept high.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the number of samples of the digital reception signal input to the matched filter 43 is reduced to １ ／, but may be reduced to １ ／ or less. The higher the decimation ratio, the lower the power consumption of the matched filter 43, and the smaller the number of taps of the matched filter, thereby downsizing the circuit. However, on the other hand, the higher the thinning rate, the longer the addition period in the cycle addition circuit 45 needs to be set.

In the above embodiment, the case where the synchronization detection circuit is incorporated in one or a plurality of finger circuits has been described as an example. However, the synchronization detection circuit is, for example, 3z in FIG.
May be provided independently of the finger circuits 31 to 3n. With this configuration, the finger circuits 31 to
Since it is not necessary to use one or more of 3n for synchronization detection, all the finger circuits 31 to 3n can be used for data reception.

In addition, not only the type and configuration of the CDMA mobile communication device, but also the configurations of the thinning processing circuit and the sample reduction processing circuit, the processing procedure and its contents, etc.
Various modifications can be made without departing from the scope of the present invention.

[0057]

As described above in detail, according to the present invention, thinning-out processing means is provided before the matched filter, and the digital reception signals are divided into a plurality of groups in the time direction by the thinning-out processing means. The samples at relatively different time positions are thinned out and input to the matched filter, or a sample reduction processing means is provided in the preceding stage of the matte filter. Processing of generating a digital reception signal having a reduced number of samples by adding a plurality of adjacent samples of the grouped digital reception signals and inputting the digital reception signal to the matched filter. The sample combinations to be added for each group are made different in the time direction. And a period adding means provided at a stage subsequent to the matched filter. The period adding means adds the correlation outputs of the respective groups outputted from the matched filter to each other, and detects the added output as a synchronous code detection process. It is configured to be provided for.

Therefore, according to the present invention, erroneous detection of the peak position can be prevented by the process of reducing the number of samples, thereby achieving a match that achieves both reduction in power consumption and maintenance of the synchronization detection characteristic. And a synchronization detection circuit using the same filter.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a CDMA mobile communication device according to the present invention.

FIG. 2 is a circuit block diagram showing a first embodiment of a CDMA synchronization detection circuit according to the present invention.

FIG. 3 is a diagram used to explain the operation of the circuit shown in FIG. 2;

FIG. 4 is a circuit block diagram showing a CDMA synchronization detection circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram used to explain the operation of the circuit shown in FIG. 4;

FIG. 6 is a circuit block diagram showing another embodiment of the CDMA synchronization detection circuit according to the present invention.

FIG. 7 is a diagram showing an example of the configuration of a matched filter.

FIG. 8 is a diagram showing a received signal waveform that has passed through a roll-off filter for waveform shaping.

FIG. 9 is a diagram used to explain the operation of a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Tap part 2 ... Multiplication part 3 ... Addition part 11a, 22 ... Analog-digital converter (AD) 11b, 19 ... Digital-analog converter (DA) 12 ... Voice coding-decoding device ( Vocoder) 13 Control circuit 14 Data generation circuit 15 Convolutional encoder 16 Interleave circuit 17 Spectrum spreader 18 Digital filter 20 Analog front end 21 Antenna 25 RAKE receiver 26 Deinterleave circuit 27 Viterbi decoder 28 Error correction circuit 29 Keypad / display 30 Symbol synthesizer 31-3n Finger circuit 3z Synchronization detection circuit 40, 50 Timing generation circuit 41 AD clock generation circuit 42 Latch circuit 43: matched filter 44: frequency dividing circuit 45: period adding circuit 51: Buffer circuit 52 ... Buffer control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Narito Saito 3-1-1 Asahigaoka, Hino-shi, Tokyo Inside the Toshiba Hino Plant Co., Ltd. (72) Miyuki Ogura 3-1-1 Asahigaoka, Hino-shi, Tokyo 1 Toshiba Hino Plant, Ltd. (72) Inventor Hiroshi Ogura 3-1, 1-1 Asahigaoka, Hino-shi, Tokyo 1- Within Toshiba Hino Plant, Ltd. No. 1 F-term in Toshiba R & D Center (reference) 5K022 EE02 EE33 EE36 5K047 AA03 AA04 BB01 CC01 GG34 GG37 HH01 HH03 HH15 HH21 MM33 5K072 AA20 BB13 CC20 FF08 FF11

Claims (2)

[Claims] 1. A received signal converted into a digital signal at a predetermined sampling period is input to a digital matched filter, and a synchronization code included in the digital received signal is detected based on the correlation output to synchronize the digital signal. In the synchronization detection circuit to be established, the digital reception signal is divided into a plurality of groups in the time direction, and a sampling processing means for thinning out samples at relatively different time positions for each of these groups and inputting the samples to the matched filter, Periodic addition means for mutually adding the correlation outputs of the respective groups output from the matched filter and providing the added output to the synchronous code detection processing. Detection circuit. 2. A received signal converted into a digital signal at a predetermined sampling period is input to a digital matched filter, and a synchronization code included in the digital received signal is detected based on the correlation output to synchronize the digital signal. In the synchronization detection circuit to be established, the digital reception signal is divided into a plurality of groups in the time direction, and a plurality of adjacent samples of the grouped digital reception signals are added to each other to reduce the number of samples. Sample reduction processing means for performing a process of generating and inputting to the matched filter by changing a combination of samples to be added for each of the plurality of groups in a time direction; and each of the groups output from the matched filter. Are added to each other, and the added output is used for the synchronous code detection process. Synchronization detection circuit using a matched filter, characterized by comprising a period adding means.