JP2009032761A - Manufacturing method of light-emitting device, and light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a light emitting device for simplifying a manufacturing process of the light emitting device. <P>SOLUTION: In the manufacturing method of the light emitting device 1, the light emitting device 1 having a first conduction-type first semiconductor layer and a second conduction-type second semiconductor layer different from the first conduction-type and emitting light by applying voltage in a forward direction to the first semiconductor layer and the second semiconductor layer is manufactured. The manufacturing method comprises an electrode forming process for forming a first electrode and a second electrode detached from the first electrode on the first semiconductor layer and a voltage applying process for applying voltage between the first electrode and the second electrode, which are formed in the electrode forming process, and making the second electrode and the second semiconductor layer in an electrically conductive state in both directions. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a light emitting device including a partial conduction part and the light emitting device.

  Conventionally, as a method for manufacturing a light emitting diode (LED) formed of a nitride compound semiconductor, an n-type GaN layer, a light emitting layer, and a p-type GaN layer are arranged in this order on a sapphire substrate. After the compound semiconductor layer is formed by growth, etching is performed from the p-type GaN layer to a part of the n-type GaN layer to expose the n-type GaN layer, and a p-type electrode is formed on the p-type GaN layer. On the other hand, a manufacturing method is known in which an n-type electrode is formed separately from a p-type electrode on an exposed n-type GaN layer.

  In the light emitting device described in Patent Document 1, after a buffer layer, an n layer, and a semi-insulating layer (I layer) are formed in this order on a sapphire substrate, n is formed on the surface of the I layer. A light-emitting element is described in which a low resistance region is formed immediately below an n-side electrode by forming a side electrode and subjected to heat treatment, and then an I-side electrode is formed.

According to the light emitting device described in Patent Document 1, since a low resistance region can be formed in the region of the I layer immediately below the n-side electrode, a current is generated between the I-side electrode and the n-side electrode without forming a contact hole. It can flow.
JP-A-4-273175

  However, in a conventional manufacturing method for manufacturing an LED from a nitride-based compound semiconductor, a step of removing the compound semiconductor layer using a photolithography technique and an etching technique is required when forming an n-type electrode. Further, since the p-type electrode is in contact with the p-type GaN layer and the n-type electrode is in contact with the n-type GaN layer, the p-type electrode and the n-type electrode are required from the viewpoint that an ohmic junction is required between the electrode and the semiconductor. Since it is difficult to form the electrodes for use with the same material, it is necessary to form the p-type electrode and the n-type electrode in separate steps. Therefore, it is difficult to simplify the LED manufacturing process in the conventional nitride compound semiconductor LED manufacturing method.

  In manufacturing the light-emitting element described in Patent Document 1, a heat treatment step is required after the n-side electrode is provided, and an I-side electrode is required after the heat treatment step. That is, in the light emitting element described in Patent Document 1, the n-side electrode and the I-side electrode cannot be formed simultaneously. Therefore, in the method for manufacturing a light emitting element described in Patent Document 1, it is difficult to simplify the manufacturing process of the light emitting element.

  Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to simplify the manufacturing process of the light emitting device.

  In order to achieve the above object, the present invention includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type, A method for manufacturing a light emitting device that emits light by applying a forward voltage to a second semiconductor layer, wherein a first electrode and a second electrode spaced apart from the first electrode are formed on the first semiconductor layer. An electrode forming step, and a voltage is applied between the first electrode and the second electrode formed in the electrode forming step, respectively, so that the second electrode and the second semiconductor layer can be electrically connected in both directions. There is provided a method of manufacturing a light emitting device including a voltage applying step for setting the state.

  In the method for manufacturing a light emitting device, the first conductivity type is p-type, the second conductivity type is n-type, and the voltage application step applies a voltage between the first electrode and the second electrode. Then, by destroying a part of the pn junction between the first semiconductor layer and the second semiconductor layer, the second electrode and the second semiconductor layer may be electrically connected in both directions. .

  In the method for manufacturing a light emitting device, in the electrode formation step, the first electrode and the second electrode may be formed so that the area of the second electrode is smaller than the area of the first electrode. Further, in the electrode forming step, the first electrode and the second electrode may be formed simultaneously. And in the manufacturing method of the said light-emitting device, an electrode formation process may form a 1st electrode and a 2nd electrode with the same material.

  In order to achieve the above object, in the present invention, a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type are provided on the first semiconductor layer. A semiconductor layer; a first electrode provided on the first semiconductor layer; a second electrode provided separately from the first electrode on the first semiconductor layer; and a second electrode formed below the second electrode, There is provided a light emitting device including a partial conduction part that electrically conducts an electrode and a second semiconductor layer bidirectionally.

  In the light emitting device, the partial conduction portion may be formed by applying a predetermined voltage between the first electrode and the second electrode. In the light emitting device, the area of the second electrode may be smaller than the area of the first electrode. Furthermore, in the above light emitting device, the material forming the first electrode and the material forming the second electrode may be the same.

  According to the present invention, the manufacturing process of the light emitting device can be simplified.

[First Embodiment]
FIG. 1 is a schematic perspective view of a light emitting device according to a first embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view of the light emitting device according to the first embodiment.

(Configuration of light-emitting device 1)
As shown in FIG. 1, the light emitting device 1 according to the first embodiment includes a sapphire substrate 10 having a (0001) plane and a second conductivity type second semiconductor layer provided on the sapphire substrate 10. n-type GaN layer 20, light-emitting layer 22 provided on n-type GaN layer 20, and p-type as a first semiconductor layer of a first conductivity type different from the second conductivity type provided on light-emitting layer 22 A semiconductor multilayer structure having a GaN layer 24 is provided.

  The light emitting device 1 is separated from the p-type electrode 40 as a first electrode provided in a predetermined region on the p-type GaN layer 24 and the p-type electrode 40 on the p-type GaN layer 24. And an n-type electrode 42 as a second electrode provided. Further, as shown in FIG. 2, the light emitting device 1 penetrates the p-type GaN layer 24 and the light emitting layer 22 below the n-type electrode 42 and reaches a predetermined region reaching the partial region of the n-type GaN layer 20. In the region, a partial conduction portion 26 capable of electrically conducting the n-type electrode 42 and the n-type GaN layer 20 in both directions is provided.

  Here, the n-type GaN layer 20, the light-emitting layer 22, and the p-type GaN layer 24 are each a group III nitride formed by, for example, metal organic chemical vapor deposition (MOCVD). It is a layer made of a compound semiconductor.

For example, the n-type GaN layer 20 is formed of n-GaN doped with a predetermined amount of Si as an n-type dopant. The light emitting layer 22 has a quantum well structure formed of In _x Ga _1-x N / GaN. Further, the p-type GaN layer 24 is formed of p-GaN doped with a predetermined amount of Mg as a p-type dopant.

  Further, the n-type electrode 42 provided on the p-type GaN layer 24 according to the present embodiment is provided at a position separated from the p-type electrode 40, that is, electrically disconnected from each other. For example, the n-type electrode 42 is provided in a predetermined region including the vicinity of one corner on the upper surface of the p-type GaN layer 24 of the light emitting device 1 having a substantially square shape when viewed from above. The p-type electrode 40 is separated from the n-type electrode 42, that is, a predetermined region including at least one diagonal of the upper surface of the p-type GaN layer 24 separately from the n-type electrode 42. Is provided.

  Here, the p-type electrode 40 and the n-type electrode 42 are each formed of the same material. For example, the p-type electrode 40 and the n-type electrode 42 are each made of ITO (Indium Tin Oxide). Further, in the present embodiment, the n-type electrode 42 is formed so that the area of the n-type electrode 42 is smaller than the area of the p-type electrode 40.

  The partial conducting portion 26 is a region formed below the n-type electrode 42 and electrically conducting the n-type electrode 42 and the n-type GaN layer 20 in both directions. Due to the presence of the partial conducting portion 26, the p-type GaN layer 24 and the n-type GaN layer 20 are electrically conducted in both directions. Specifically, the partial conduction portion 26 is a region that electrically conducts at least a part of the p-type GaN layer 24 and the light emitting layer 22 below the n-type electrode 42 to a part of the n-type GaN layer 20. . That is, in the partial conduction part 26, no rectification characteristic is generated between the p-type GaN layer 24 and the n-type GaN layer 20.

  For example, when the p-type GaN layer 24 and the n-type GaN layer 20 are pn-junctioned, the partial conduction portion 26 applies a voltage that breaks the pn junction between the p-type electrode 40 and the n-type electrode 42. Is applied to the n-type electrode 42 to destroy a part of the pn junction between the p-type GaN layer 24 and the n-type GaN layer 20 below the n-type electrode 42. This is a region where the n-type electrode 42 and the n-type GaN layer 20 can be electrically connected in both directions.

Before forming the n-type GaN layer 20, a buffer layer made of AlN or GaN can be formed on the sapphire substrate 10 by MOCVD. The quantum well structure of the light emitting layer 22 can be either a single quantum well structure or a multiple quantum well structure, or can be a light emitting layer that does not have a quantum well structure. Further, a p-type contact layer (p ⁺ -type GaN layer) doped with Mg at a doping concentration higher than the doping amount of Mg with respect to the p-type GaN layer 24 can be formed on the p-type GaN layer 24 by MOCVD. .

  Further, the buffer layer, the n-type GaN layer 20, the light emitting layer 22, the p-type GaN layer 24, the p-type GaN layer 24, and the p-type contact layer provided on the sapphire substrate 10 are formed by molecular beam epitaxy (Molecular Beam Epitaxy). : MBE) or a compound semiconductor layer formed by halide vapor phase epitaxy (HVPE) or the like.

  The p-type electrode 40 and the n-type electrode 42 can also be formed from zinc oxide (ZnO). Alternatively, the p-type electrode 40 and the n-type electrode 42 may be formed of a metal material mainly composed of Ag, Al, Ni, Au, Pd, Cr, or the like. Furthermore, a pad electrode can be formed in a partial region on the p-type electrode 40. Similarly, a pad electrode can be formed in a predetermined region on the n-type electrode 42. In this case, the material for forming the pad electrode provided on the p-type electrode 40 and the pad electrode provided on the n-type electrode 42 can be formed from the same material. For example, the pad electrode can be mainly formed from a metal material such as Ti, Ni, and Au.

  The light emitting device 1 of the present embodiment configured as described above is an LED that emits light having a wavelength in the blue region. For example, the light emitting device 1 is a face-up blue LED that emits light having a peak wavelength of 470 nm when the forward voltage is 3.5 V and the forward current is 20 mA. The planar dimension of the light emitting device 1 is approximately 350 μm in vertical and horizontal dimensions.

  The light emitting device 1 may be an LED that emits light having a peak wavelength in the ultraviolet region, the near ultraviolet region, or the green region, but the peak wavelength region of the light emitted from the LED is not limited to these wavelengths. In other modified examples, the planar dimensions of the light emitting device 1 are not limited to this. For example, the planar dimension of the light emitting device 1 can be designed so that the vertical dimension and the horizontal dimension are each approximately 1 mm.

(Method for manufacturing light-emitting device 1)
FIG. 3A shows a longitudinal sectional view of the epitaxial growth substrate. FIG. 3B shows a longitudinal sectional view after electrodes are formed on the epitaxial growth substrate. FIG. 3C shows a longitudinal sectional view after forming the p-type electrode and the n-type electrode. Furthermore, FIG.3 (d) shows the longitudinal cross-sectional view after forming a partial conduction | electrical_connection part.

  First, the group III nitride compound semiconductor is epitaxially grown on the surface of the sapphire substrate 10 using MOCVD, whereby the epitaxial growth substrate 2 is formed. That is, the n-type GaN layer 20, the light emitting layer 22, and the p-type GaN layer 24 are epitaxially grown in this order on the sapphire substrate 10 to form the epitaxial growth substrate 2 (FIG. 3A).

  Next, an electrode 46 is formed on the p-type GaN layer 24 by vacuum evaporation, and the p-type GaN layer 24 is covered with the electrode 46 (FIG. 3B). In the present embodiment, transparent electrode ITO is used as the electrode 46. Note that the electrode 46 can also be formed from a metal material such as Ag, Al, Ni, Au, Pd, or Cr by sputtering.

  Then, a mask made of a photoresist is formed in a predetermined region on the electrode 46 by using a photolithography technique. Here, the mask is formed so that the area of the n-type electrode 42 is smaller than the area of the p-type electrode 40. Next, the p-type electrode 40 and the n-type electrode 42 are formed by removing the electrode 46 other than the region covered with the mask using an etching technique. Therefore, the p-type electrode 40 and the n-type electrode 42 are simultaneously formed from the same material. As a result, the electrode-attached substrate 3 in which the p-type electrode 40 and the n-type electrode 42 are provided on the epitaxial growth substrate 2 is formed (FIG. 3C).

  Before forming the electrode 46 shown in FIG. 3B, a predetermined mask pattern is provided using a photolithography technique. After the electrode 46 is formed on the formed mask pattern, the p-type is formed by a lift-off method. The electrode 40 and the n-type electrode 42 can also be formed.

  Subsequently, for the purpose of applying a predetermined voltage between the p-type electrode 40 and the n-type electrode 42, the voltage application probe 50 is brought into contact with the p-type electrode 40, and the n-type electrode A probe 50 for applying a voltage is brought into contact with 42. Then, a predetermined voltage is applied between the p-type electrode 40 and the n-type electrode 42 via the probe 50 and the probe 52. The probe 50 and the probe 52 are made of, for example, a metal such as tungsten or an electrically conductive material.

  That is, first, the p-type electrode 40 is set on the positive side, and the n-type electrode 42 is set on the negative side. Then, an excessive voltage is applied between the p-type electrode 40 and the n-type electrode 42 to make the n-type electrode 42 and the n-type GaN layer 20 electrically conductive in both directions. . By passing through such a process, the n-type electrode 42 and the n-type GaN layer 20 can be electrically connected to each other in both directions. That is, by applying an excessive voltage between the p-type electrode 40 and the n-type electrode 42, at least between the p-type GaN layer 24 and the n-type GaN layer 20 below the n-type electrode 42. A part is electrically conducted in both directions.

  Specifically, one of both the semiconductor junction between the p-type GaN layer 24 and the light emitting layer 22 located below the n-type electrode 42 and the semiconductor junction formed from the light emitting layer 22 and the n-type GaN layer 20. The p-type electrode 40 and the n-type electrode have a sufficient reverse voltage so that the p-type GaN layer 24 is electrically connected to the n-type GaN layer 20 via the light emitting layer 22 in both directions. 42 is applied.

  As a result, a part of the n-type GaN layer 20 from the p-type GaN layer 24 below the n-type electrode 42, that is, a part of the n-type GaN layer 20 that penetrates the light-emitting layer 22 from the p-type GaN layer 24. A partial conducting portion 26 is formed, which reaches the portion and electrically conducts the p-type GaN layer 24 and the n-type GaN layer 20 in both directions (FIG. 3D). Thereby, the light emitting device 1 is formed.

  Note that the magnitude of the reverse voltage is such that the semiconductor junction formed between the p-type GaN layer 24 and the n-type GaN layer 20 is broken, and the electrical connection between the p-type GaN layer 24 and the n-type GaN layer 20 occurs. The size is such that it conducts bidirectionally. For example, when the p-type GaN layer 24 and the n-type GaN layer 20 form a pn junction, a voltage for breaking the pn junction is applied between the p-type electrode 40 and the n-type electrode 42. By applying, the partial conduction part 26 is formed.

  Further, when the light emitting layer 22 is formed between the p-type GaN layer 24 and the n-type GaN layer 20, the junction formed between the p-type GaN layer 24 and the light emitting layer 22, and the light emitting layer By applying a voltage between the p-type electrode 40 and the n-type electrode 42 such that the junction formed between the n-type GaN layer 20 and the junction formed between the p-type electrode 40 and the n-type GaN layer 20 is broken. It is formed.

  Further, when the light emitting layer 22 has a quantum well structure, a junction formed between the p-type GaN layer 24 and the quantum well structure, and a plurality of well layers and a plurality of barrier layers included in the quantum well structure. A voltage having such a magnitude that a plurality of junctions to be formed and a junction formed between the quantum well structure and the n-type GaN layer 20 are destroyed is applied between the p-type electrode 40 and the n-type electrode 42. By applying, the partial conduction part 26 is formed.

(Operation of the light emitting device 1)
First, when predetermined power is supplied to the p-type electrode 40 and the n-type electrode 42, the current passes from the n-type electrode 42 through the partial conduction part 26 and from the partial conduction part 26 through the n-type GaN layer 20. Supplied to the light emitting layer 22. The light emitting layer 22 emits light in a predetermined wavelength range according to the supplied current. The light emitted from the light emitting layer 22 propagates through the sapphire substrate 10 and is emitted outside the light emitting device 1.

  The partial conduction part 26 provided below the n-type electrode 42 conducts the current supplied to the n-type electrode 42 and supplies it to the n-type GaN layer 20. Therefore, in the region where the partial conducting portion 26 is formed, the light emitting layer 22 existing in the region before the partial conducting portion 26 is formed is destroyed and the function as the light emitting layer 22 is lost. Therefore, the light emitting layer 22 does not emit light below the n-type electrode 42.

(Effects of the first embodiment)
In the light emitting device 1 according to this embodiment, the p-type electrode 40 and the n-type electrode 42 are simultaneously formed on the p-type GaN layer 24, and the p-type electrode 40 and the n-type electrode 42 are interposed. By applying a predetermined voltage to the n-type GaN layer, a pn junction included in a partial region of the n-type GaN layer 20 can be broken from the p-type GaN layer 24 below the n-type electrode 42. Thereby, the p-type GaN layer 24 below the n-type electrode 42 and a partial region of the n-type GaN layer 20 can be electrically connected in both directions. Therefore, the step of etching from the p-type GaN layer 24 to a part of the n-type GaN layer 20 and the p-type electrode and the n-type electrode, which are essential in the conventional method for manufacturing a light emitting device, are formed separately. The process can be omitted, and the manufacturing process of the light emitting device 1 can be greatly simplified. Therefore, the manufacturing cost of the light emitting device 1 can be reduced and the throughput can be improved.

  In the present embodiment, the junction between the p-type GaN layer 24 and the n-type GaN layer 20 existing below the p-type electrode 40 is in the forward direction, but exists below the n-type electrode 42. The junction between the p-type GaN layer 24 and the n-type GaN layer 20 is in the opposite direction. Accordingly, an excessive voltage is applied to the junction below the n-type electrode 42, thereby destroying the junction below the n-type electrode 42. Here, if the area of the n-type electrode 42 is smaller than the area of the p-type electrode 40, the amount of current required to break the junction below the n-type electrode 42 is equal to the area of the n-type electrode 42. The area of the p-type electrode 40 is smaller than when the area is the same. Therefore, in the present embodiment, by making the area of the n-type electrode 42 smaller than the area of the p-type electrode 40, the amount of current increases rapidly and the junction below the p-type electrode 40 is destroyed. Can be prevented.

[Second Embodiment]
FIG. 4 shows a top view of a part of the substrate with electrode in the middle of the manufacturing process of the light emitting device according to the second embodiment of the present invention.

  The substrate with electrode 3 according to the present embodiment has been described with reference to FIG. 3C except that the outer electrode 44 is further provided and a plurality of p-type electrodes 40 and a plurality of n-type electrodes 42 are formed. Since it is substantially the same as the substrate with electrode 3, detailed description is omitted except for the difference from the substrate with electrode 3 described in FIG.

(Configuration of substrate 3 with electrode)
The substrate with electrode 3 according to the present embodiment has a unit electrode 48 in which an outer peripheral electrode 44 is formed on the p-type GaN surface 25, and a p-type electrode 40 and an n-type electrode 42 are disposed inside the outer peripheral electrode 44. Are provided. The plurality of unit electrodes 48 are formed at predetermined intervals, for example, along the shape of the outer peripheral electrode inner edge 402 which is the inner edge of the outer peripheral electrode 44. For example, the plurality of unit electrodes 48 are formed in a matrix on the p-type GaN surface 25.

(Method for manufacturing substrate 3 with electrode)
The outer peripheral electrode 44 is formed of the same material as the p-type electrode 40 and the n-type electrode 42 included in the unit electrode 48. That is, the plurality of unit electrodes 48 and the outer peripheral electrode 44 are simultaneously formed on the entire surface of the epitaxial growth substrate 2 by using a photolithography technique and a vacuum deposition technique or a sputtering method (electrode formation process).

For example, a mask such as a photoresist is formed on the epitaxial growth substrate 2, that is, on the p-type GaN surface 25 that is the upper surface of the p-type GaN layer 24 except for the region where the plurality of unit electrodes 48 and the outer peripheral electrode 44 are to be formed. To do. Then, Ni having a thickness of 300 nm is formed by sputtering on the entire surface of the p-type GaN surface 25 after the mask is formed. A plurality of unit electrodes 48 and outer peripheral electrodes 44 are formed by a lift-off method. Subsequently, the epitaxial growth substrate 2 after the formation of the plurality of unit electrodes 48 and the outer peripheral electrode 44 is subjected to heat treatment at 400 ° C. for 5 minutes in an N ₂ atmosphere (alloy process). The electrode-attached substrate 3 is obtained through this alloy process.

  In another example, ITO can be formed on the entire surface of the p-type GaN surface 25 of the epitaxial growth substrate 2. Then, a mask is formed with a photoresist or the like in a region where the plurality of unit electrodes 48 and the outer peripheral electrode 44 are to be formed. Subsequently, the ITO except for the portion covered with the mask is removed by etching. Thereby, the substrate 3 with electrodes can be formed by providing the plurality of unit electrodes 48 and the outer peripheral electrode 44 on the epitaxial growth substrate 2.

  Subsequently, the outer peripheral electrode 44 is set to the positive side, and the n-type electrode 42 included in one unit electrode 48 is set to the negative side so that a predetermined voltage is applied between the outer peripheral electrode 44 and the n-type electrode 42. Apply to. For example, in the present embodiment, by applying a voltage of about 100 V between the outer peripheral electrode 44 and the n-type electrode 42, the p-type GaN layer 24 and the light emitting layer 22 existing below the n-type electrode 42. And the semiconductor junction formed from the light emitting layer 22 and the n-type GaN layer 20 are destroyed (voltage application step). Such a voltage application step is performed on each of the plurality of n-type electrodes 42. As a result, a plurality of partial conduction portions 26 are respectively formed below the plurality of n-type electrodes 42.

  Then, after the voltage application step, for each of the plurality of unit electrodes 48, the p-type electrode 40 is set to the positive side, and the n-type electrode 42 is set to the negative side, so that the p-type electrode 40 and the n-type electrode are set. Electricity is supplied between the electrodes 42 and the electrical characteristics and optical characteristics of the electrode-equipped substrate 3 below the unit electrode 48 are measured (characteristic evaluation step).

  In addition, after passing the voltage application process and the characteristic evaluation process for one of the plurality of unit electrodes 48, the other unit electrodes 48 may be sequentially supplied to the voltage application process and the characteristic evaluation process. Alternatively, the voltage application process may be performed for all of the plurality of unit electrodes 48 to form the partial conducting portions 26 for each of the plurality of unit electrodes 48, and then the characteristic evaluation process may be performed for all of the plurality of unit electrodes 48.

  Subsequently, the sapphire substrate 10 is polished to a predetermined thickness, for example, about 100 μm (polishing step). And in the area | region where the unit electrode 48 on the board | substrate 3 with an electrode is not provided, it scribes so that the several unit electrode 48 may be separately included in a substantially square area | region by the top view. That is, scribing is performed so that a predetermined chip shape (for example, approximately square) and a chip size (for example, approximately 350 μm square) are obtained. Subsequently, by cleaving, a plurality of light emitting devices 1 are formed along the scribed shape (chip formation step).

  In the present embodiment, the outer peripheral electrode 44 is substantially square when viewed from above, but the shape of the outer peripheral electrode 44 is not limited to this. The shape of the outer peripheral electrode 44 can also be formed in a shape along the substrate outer edge 300 of the epitaxial growth substrate 2 in a top view, for example, a substantially circular shape. Then, in order to maximize the number of light emitting devices 1 that can be obtained from one epitaxial growth substrate 2, a plurality of unit electrodes 48 are arranged at predetermined intervals along the outer peripheral electrode inner edge of the substantially circular outer peripheral electrode 44. You can also.

(Effect of the second embodiment)
According to the method for manufacturing the light emitting device 1 according to this embodiment, a plurality of unit electrodes and the outer peripheral electrode 44 can be simultaneously formed on the epitaxial growth substrate 2 in the same process. Then, by applying a predetermined voltage between each of the plurality of n-type electrodes 42 and the outer peripheral electrode 44, the p-type GaN layer 24 positioned below each of the plurality of n-type electrodes 42 is changed to n-type. Up to a partial region of the GaN layer 20 can be electrically connected in both directions. As a result, the step of etching from the p-type GaN layer 24 to a part of the n-type GaN layer 20 and the p-type electrode and the n-type electrode, which are essential in the conventional method of manufacturing a light emitting device, are formed separately. The process can be omitted, and the manufacturing process of the light emitting device 1 can be greatly simplified. Thereby, compared with the manufacturing method of the conventional light-emitting device, the improvement of a yield and the significant reduction of manufacturing time and manufacturing cost are realizable.

  FIG. 5 shows an enlarged perspective view of a part of the substrate with electrode according to the embodiment of the present invention.

(Structure of substrate 4 with electrode)
The electrode-attached substrate 4 is provided on the sapphire substrate 10, the buffer layer provided on the sapphire substrate 10, the n-type GaN layer 20 provided on the buffer layer, and the n-type GaN layer 20. A light emitting layer 22, a p-type GaN layer 24 provided on the light emitting layer 22, a contact layer provided on the p-type GaN layer 24, and an electrode provided on the contact layer are formed in this order. Was obtained.

Specifically, a plurality of compound semiconductor layers were grown on the sapphire substrate 10 by MOCVD to obtain an epitaxial growth substrate 2. That is, first, AlN as a buffer layer was grown on the sapphire substrate 10 by 15 nm. Subsequently, an n-type GaN layer 20 mainly made of GaN doped with Si in the range of 1 to 4 × 10 ¹⁸ (cm ⁻³ ) was grown on the buffer layer to about 3000 to 4000 nm. On the n-type GaN layer 20, the light emitting layer 22 is composed of In _0.2 Ga _0.8 N / GaN (In _0.2 Ga _0.8 N: 3 nm, GaN: 10 to 12 nm). Six pairs of quantum wells were grown.

Subsequently, p-In _0.08 Ga _0.92 N / p-Al _0.3 Ga ₀ doped with 1 × 10 ²⁰ (cm ⁻³ ) Mg as a p-type GaN layer 24 on the light emitting layer 22. _{.7 N (p-In 0.08 Ga} 0.92 N: 1.7nm, p-Al 0.3 Ga 0.7 N: 4nm) was 5 pairs grow layer composed of, 5 × the Mg A 10 ¹⁹ (cm ⁻³ ) doped p-GaN layer was grown to 80 to 100 nm. Then, a p ⁺ -GaN layer doped with 1 × 10 ²⁰ (cm ⁻³ ) of Mg was grown as a contact layer on the p-type GaN layer 24 by 25 nm. Thereby, the epitaxial growth substrate 2 was obtained.

Next, the circular electrode 43, the ring electrode 41, and the outer peripheral electrode 45 were formed on the contact layer by using a photolithography technique and an etching technique, respectively. Specifically, first, 300 nm of ITO was formed on the entire surface of the contact layer by vacuum deposition. Subsequently, the epitaxial growth substrate 2 after depositing ITO was subjected to heat treatment at 700 ° C. for 5 minutes in an N ₂ atmosphere.

  Next, a mask made of a photoresist was formed in regions where the circular electrode 43, the ring electrode 41, and the outer peripheral electrode 45 were to be formed. Subsequently, the ITO except for the region covered with the mask was removed by etching using an ITO etching solution. Thereby, the board | substrate 4 with an electrode was obtained.

  The circular electrode 43, the ring electrode 41, and the inner edge of the outer peripheral electrode 45 are provided concentrically. The diameter of the circular electrode 43 is 200 μm, and the distance from the outer edge of the circular electrode 43 to the inner edge of the ring electrode 41. Is 5 μm. Furthermore, the distance from the outer edge of the ring electrode 41 to the inner edge of the outer peripheral electrode 45 is 20 μm.

(Voltage application process for substrate 4 with electrode)
FIG. 6 shows an IV curve when a voltage of 0 to 10 V is applied between the circular electrode and the outer peripheral electrode.

  First, the circular electrode 43 is set to the negative side, the outer peripheral electrode 45 is set to the positive side, the voltage value is sequentially increased from 0 V to about 10 V, and a voltage is applied between the circular electrode 43 and the outer peripheral electrode 45. Applied. When the voltage applied between the circular electrode 43 and the outer peripheral electrode 45 is 4.0 (V), the current flowing between the circular electrode 43 and the outer peripheral electrode 45 is about 2.0E-4 (A). It was. When the voltage applied between the circular electrode 43 and the outer peripheral electrode 45 is gradually increased from 4.0 (V), the current flowing between the circular electrode 43 and the outer peripheral electrode 45 is also increased according to the voltage increase. Increased gradually.

  FIG. 7 shows an IV curve when a voltage of 0 to 80 V is applied between the circular electrode and the outer peripheral electrode.

  As in FIG. 6, the circular electrode 43 is set to the negative side, the outer peripheral electrode 45 is set to the positive side, and the voltage value is sequentially increased from 0 V to about 80 V, so that the circular electrode 43 and the outer peripheral electrode 45 A voltage was applied between them. Until the applied voltage was about 50 V, the current flowing between the circular electrode 43 and the outer peripheral electrode 45 was about 1.0E-3 (A) or less. And the electric current increased rapidly when the voltage applied between the circular electrode 43 and the outer peripheral electrode 45 was about 60 V or more to about 80 (V). This is because a voltage of about 80 (V) is applied between the circular electrode 43 and the outer peripheral electrode 45, so that the pn junction between the p-type GaN layer 24 and the n-type GaN layer 20 below the circular electrode 43 is reduced. It is because it was destroyed and the partial conduction | electrical_connection part 26 was formed.

  FIG. 8 shows the IV curve after breaking the semiconductor junction below the circular electrode.

  Next, after applying a voltage of about 80 (V) between the circular electrode 43 and the outer peripheral electrode 45, a voltage (forward voltage) is again applied between the circular electrode 43 and the outer peripheral electrode 45 to obtain IV characteristics. It was measured. Before the pn junction between the p-type GaN layer 24 and the n-type GaN layer 20 below the circular electrode 43 is broken, the current flowing between the circular electrode 43 and the outer peripheral electrode 45 at an applied voltage of 1.0 V. Was about 0.5E-4 (A) (FIG. 6). On the other hand, after breaking the pn junction, the current flowing between the circular electrode 43 and the outer peripheral electrode 45 at an applied voltage of 1.0 V was about 1.2E-2 (A) as shown in FIG. . If the electrode-equipped substrate 4 including the circular electrode 43 and the outer peripheral electrode 45 has a size equivalent to a light emitting element having a normal size (for example, a size of about 350 μm square), the circular electrode 43 and the outer peripheral electrode 45 In FIG. 8, since the area of the outer peripheral electrode is very large, no rectification is exhibited.

(Characteristic evaluation after voltage application process)
FIG. 9 shows an IV curve when a voltage is applied between the circular electrode and the ring electrode after the partial conducting portion is formed.

  After the partial conducting portion 26 is formed below the circular electrode 43, the circular electrode 43 is set to the negative side, the ring electrode 41 is set to the positive side, and 0. 0 between the circular electrode 43 and the ring electrode 41 is set. A voltage was applied in the range of 0 (V) to 5.0 (V). In this case, a rectification characteristic was observed between the circular electrode 43 and the ring electrode 41. Further, when a voltage of about 2.8 V or higher was applied between the circular electrode 43 and the ring electrode 41, blue light emission having a peak wavelength of 460 nm was observed. In addition, as for the board | substrate 4 with an electrode, the drive voltage in 20 (mA) was about 3.9 (V).

  FIG. 10 shows an IV curve when a voltage is applied between the circular electrode and the ring electrode after the partial conducting portion is formed.

  Referring to FIG. 10, it was found that the electrode-attached substrate 4 according to this example had the same characteristics as the IV curve specific to the LED having a pn junction. That is, after the partial conducting portion 26 is formed below the circular electrode 43, the circular electrode 43 is set to the negative side, the ring electrode 41 is set to the positive side, and the circular electrode 43 is set between the circular electrode 43 and the ring electrode 41. When a forward voltage was applied, the current increased with increasing voltage at about 2.8 (V) or higher. On the other hand, when a reverse voltage was applied between the circular electrode 43 and the ring electrode 41, almost no current flowed until at least -4.0 (V). Thereby, it can be seen that the partial conduction portion 26 is formed only at least at a part below the circular electrode 43.

  The above description is about the case where the voltage is applied between the circular electrode 43 and the outer peripheral electrode 45 to form the partial conduction portion 26. However, the voltage is applied between the circular electrode 43 and the ring electrode 41. It is also possible to form the partial conduction part 26 by. Below, the case where the voltage is applied between the circular electrode 43 and the ring electrode 41 and the partial conduction | electrical_connection part 26 is formed is demonstrated.

(Voltage application process for substrate 4 with electrode)
FIG. 11 shows an IV curve when a voltage of −10 V to 10 V is applied between the circular electrode and the ring electrode.

  First, the circular electrode 43 is set to the negative side, the ring electrode 41 is set to the positive side, and the voltage value is sequentially increased from −10 V to about 10 V, so that the voltage between the circular electrode 43 and the ring electrode 41 is increased. Was applied. Under this voltage application condition, the pn junction between the p-type GaN layer 24 and the n-type GaN layer 20 below the circular electrode 43 is not broken, and almost current flows between the circular electrode 43 and the outer peripheral electrode 45. Not confirmed.

  FIG. 12 shows an IV curve when a voltage of 0 to 47 V is applied between the circular electrode and the ring electrode.

  Similarly to FIG. 11, the circular electrode 43 is set to the negative side, the ring electrode 41 is set to the positive side, and the voltage value is sequentially increased from 0 V to about 47 V, so that the circular electrode 43 and the ring electrode 41 A voltage was applied between them. Until the applied voltage was about 50 V, the current flowing between the circular electrode 43 and the ring electrode 41 was about 2.00E-3 (A) or less. Then, the current suddenly increased when the voltage applied between the circular electrode 43 and the ring electrode 41 was about 40 V or more to about 47 (V). This is because a voltage of about 47 (V) is applied between the circular electrode 43 and the ring electrode 41, so that a pn junction between the p-type GaN layer 24 and the n-type GaN layer 20 below the circular electrode 43 is formed. It is because it was destroyed and the partial conduction | electrical_connection part 26 was formed.

  FIG. 13 shows the IV curve after breaking the semiconductor junction below the circular electrode.

  Next, the voltage value was sequentially increased from −10 V to about 10 V between the circular electrode 43 and the ring electrode 41, and a voltage was applied between the circular electrode 43 and the ring electrode 41. Under the voltage application condition after the pn junction was broken, it was confirmed that when the applied voltage was +2.7 V, a current flowed between the circular electrode 43 and the ring electrode 41, and the current value increased as the applied voltage increased. It was. The applied current was 10 V, and the current flowing between the circular electrode 43 and the ring electrode 41 was about 7.50E-3 (A).

  While the embodiments and examples of the present invention have been described above, the embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.

1 is a conceptual perspective view of a light emitting device according to a first embodiment. It is a longitudinal cross-sectional view of the light-emitting device which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of the light-emitting device which concerns on 1st Embodiment. It is a top view of a part of a substrate with electrodes according to a second embodiment. It is the perspective view which expanded a part of base | substrate with an electrode which concerns on an Example. It is IV curve when the voltage of 0 to 10V is applied between the circular electrode which concerns on an Example, and an outer peripheral electrode. It is IV curve when the voltage of 0 to 80V is applied between the circular electrode which concerns on an Example, and an outer peripheral electrode. It is IV curve after destroying the semiconductor junction under the circular electrode which concerns on an Example. It is IV curve when a voltage is applied between a circular electrode and a ring electrode after forming the partial conduction | electrical_connection part which concerns on an Example. It is IV curve when a voltage is applied between a circular electrode and a ring electrode after forming the partial conduction | electrical_connection part which concerns on an Example. It is IV curve when the voltage of -10 to 10V is applied between the circular electrode which concerns on an Example, and a ring electrode. It is IV curve when the voltage of 0 to 47V is applied between the circular electrode which concerns on an Example, and a ring electrode. It is IV curve after destroying the semiconductor junction under the circular electrode which concerns on an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light-emitting device 2 Epitaxial growth substrate 3, 4 Substrate with electrodes 10 Sapphire substrate 20 N-type GaN layer 22 Light-emitting layer 24 p-type GaN layer 25 p-type GaN surface 26 Partial conduction part 40 P-type electrode 41 Ring electrode 42 N-type electrode 43 circular electrode 44, 45 outer peripheral electrode 46 electrode 48 unit electrode 50, 52 probe 300 substrate outer edge 400 outer peripheral electrode outer edge 402 outer peripheral electrode inner edge

Claims (9)

A first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type, and a forward voltage is applied to the first semiconductor layer and the second semiconductor layer. A method of manufacturing a light emitting device that emits light by applying
Forming an electrode on the first semiconductor layer, and a second electrode spaced apart from the first electrode; and
A state in which a voltage is applied between the first electrode and the second electrode formed in the electrode forming step so that the second electrode and the second semiconductor layer can be electrically connected in both directions And a voltage applying step. A method for manufacturing a light emitting device. The first conductivity type is p-type, the second conductivity type is n-type,
In the voltage application step, a voltage is applied between the first electrode and the second electrode to destroy a part of the pn junction between the first semiconductor layer and the second semiconductor layer. The method for manufacturing a light-emitting device according to claim 1, wherein the second electrode and the second semiconductor layer are electrically connected to each other in a bidirectional manner.   3. The method for manufacturing a light emitting device according to claim 1, wherein in the electrode formation step, the first electrode and the second electrode are formed so that an area of the second electrode is smaller than an area of the first electrode.   4. The method of manufacturing a light emitting device according to claim 1, wherein in the electrode forming step, the first electrode and the second electrode are formed simultaneously.   5. The method for manufacturing a light emitting device according to claim 1, wherein in the electrode forming step, the first electrode and the second electrode are formed of the same material. 6. A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type different from the first conductivity type, wherein the first semiconductor layer is provided on the first semiconductor layer;
A first electrode provided on the first semiconductor layer;
A second electrode provided separately from the first electrode on the first semiconductor layer;
A light-emitting device, comprising: a partial conduction part formed below the second electrode and electrically conducting the second electrode and the second semiconductor layer in both directions.   The light emitting device according to claim 6, wherein the partial conduction portion is formed by applying a predetermined voltage between the first electrode and the second electrode.   The light emitting device according to claim 6 or 7, wherein an area of the second electrode is smaller than an area of the first electrode.   The light emitting device according to claim 6, wherein a material forming the first electrode and a material forming the second electrode are the same.

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