JP2008293476A - Interface control circuit, image processing apparatus, and power management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a control method of a power management mode in a serial ATA application layer and to effectively control a transition to the power management mode and a return from the power management mode. <P>SOLUTION: An interface control circuit 3000 has a serial ATA interface 3002 connecting an ASIC 2002 to an HDD 3001 in an image processing apparatus; a transfer start monitoring section 3004 monitoring the start of data transfer processing between the ASIC and a storage part; a transfer completion monitoring section 3005 monitoring the completion of data transfer processing; and a power management control section 3006 managing power consumption of the ASIC and storage part based on the monitored result of the transfer start monitoring section 3004 and transfer completion monitoring section 3005. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an interface control circuit, an image processing apparatus, and power that can reduce power consumption of a storage unit during non-data transfer when the control unit and the storage unit of the image processing apparatus are connected via a serial ATA interface. It relates to the management method.

  Currently, there is ATA (AT Attachment) as an interface standard for connecting a peripheral device typified by HDD (Hard Disk Drive) and the like to a host system (host). ATA performs data transfer by a parallel transmission method, but the transfer rate is 133 MB / s (Ultra ATA 133) at the maximum, and it is very difficult to increase the transfer rate beyond this.

On the other hand, in recent years, HDDs are used not only for servers and PCs (Personal Computers), but also for home appliances, mobile devices, image processing devices (printers, copiers, MFPs (Multi Function).
Peripheral)). Along with the expansion of the application of HDDs and the rapid improvement in recording density of hard disks, it is required to cope with higher interface speeds and larger hard disk capacities.

  Therefore, serial ATA has been developed as a next-generation standard for performing higher-speed data transfer in order to cope with higher interface speeds among the above two requirements. Unlike the ATA based on the parallel transmission method, the serial ATA employs a serial transfer method, and the data transfer rate is 150 MB / s as the first generation. The speed will continue to be improved in the future, and it will be increased to 300 MB / s and 600 MB / s in the future.

  The serial ATA is composed of four layers according to functions, that is, a physical layer, a link layer, a transport layer, and an application layer. The physical layer is a layer having a function of executing high-speed signal transmission / reception, interprets the received content, transmits it to the link layer, and outputs a signal in response to a request from the link layer. The link layer issues a signal output request to the physical layer in accordance with the request content from the transport layer, and transmits the reception input from the physical layer to the transport layer. The transport layer performs conversion to operation in ATA. The application layer is a user circuit such as a DMA I / F (Direct Memory Access Interface) or software.

  Specifically, the physical layer performs, for example, serial / parallel data conversion, 8B / 10B encoding, and CDR (Clock Data Recovery). The link layer performs, for example, communication protocol generation / control, CRC (Cyclic Redundancy Check) code generation / check, and scramble. The transport layer performs, for example, embedding / decomposing the HDD command / data into the transfer format. In addition, since serial ATA considers software compatibility with ATA, software such as a driver can be used as it is. In that sense, the application layer is apparently equivalent to ATA.

  As described above, in image processing apparatuses such as printers, copiers, and MFPs, HDDs are used for image data storage and the like, but the transfer rate of the HDD affects the performance of the image processing apparatus. In view of software compatibility, the installation of a serial ATA standard interface and an HDD (serial ATA HDD) that can be connected to the interface has become essential.

  By the way, for example, Patent Document 1 discloses a power saving method for a serial ATA bus and the like, which can reduce power consumption by effectively utilizing the power saving function of the serial ATA bus defined in the serial ATA standard. In the present invention, in the electronic device having the serial ATA interface, when the predetermined command issuance or reception is detected, the power saving mode of the serial ATA interface is confirmed in response to the confirmation of the completion of the execution of the command. The transition to is controlled.

JP-A-2005-78514

  Serial ATA employs a full-duplex transfer method, and always communicates other than data transfer (that is, the physical layer and the link layer are always operating). For this reason, the constant communication consumes more power than the HDD adopting the ATA standard. In particular, the physical layer is mainly composed of analog circuits, and therefore consumes a lot of power.

  In this regard, the serial ATA employs a power management mode in which communication is interrupted (except that the serial signal line in the physical layer is neutral) except for data transfer that requires communication, which can reduce the power consumption of the HDD. Is possible. However, in the serial ATA standard, although the power management mode control method (power management transition control and return control) is specified for the physical layer, link layer, and transport layer, the control of the power management mode in the application layer. The method is not specified.

  The present invention has been made in view of the above, and realizes a power management mode control method in the application layer of serial ATA on hardware / software, and shifts to and returns from the power management mode. It is an object to provide an interface control circuit, an image processing apparatus, and a power management method that can effectively control the power.

  In order to solve the above-described problems and achieve the object, an interface control circuit according to the present invention includes a storage unit capable of storing data, and a storage control unit that controls data transfer with the storage unit, and an application function A control unit having: a serial ATA interface that connects the storage control unit and the storage unit; a transfer start monitoring unit that monitors the start of data transfer processing between the storage control unit and the storage unit; A transfer end monitoring unit that monitors the end of data transfer processing, and a power management control unit that manages power consumption of the control unit and the storage unit based on monitoring results by the transfer start monitoring unit and the transfer end monitoring unit; , Provided.

  The image processing apparatus according to the present invention includes an engine unit that is a hardware resource for image processing, a storage unit that can store image data, and a storage control unit that controls data transfer with the storage unit, A control unit having an application function for image processing, a serial ATA interface connecting the storage control unit and the storage unit, and transfer for monitoring the start of data transfer processing between the storage control unit and the storage unit Management of power consumption of the control unit and the storage unit based on monitoring results by a start monitoring unit, a transfer end monitoring unit that monitors the end of the data transfer process, and the transfer start monitoring unit and the transfer end monitoring unit And a power management control unit for performing the operation.

  A power management method according to the present invention is a power management method executed by an interface control circuit, and the interface control circuit controls a storage unit capable of storing data and data transfer between the storage units. A control unit having a storage control unit and having an application function; and a serial ATA interface for connecting the storage control unit and the storage unit, wherein a transfer start monitoring unit is connected to the storage control unit and the storage unit. A transfer start monitoring step for monitoring the start of the data transfer process, a transfer end monitoring unit for monitoring the end of the data transfer process, a power management control unit for the transfer start monitoring step, and Power management for managing power consumption of the control unit and the storage unit based on the monitoring result of the transfer end monitoring step Characterized in that it comprises a preparative controlling step.

  According to the present invention, the power management mode control method in the application layer of the serial ATA can be realized on hardware / software, and the transition to the power management mode and the return from the power management mode can be effectively controlled. .

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of an interface control circuit, an image processing device, and a power management method according to the invention will be described with reference to the drawings. In this embodiment, the configuration of the image processing apparatus, the configuration of the HDD controller as the serial ATA HDD interface, the description of the operation of the image forming process, the description of the DMA write operation of the serial ATA HDD interface, the DMA read of the serial ATA HDD interface The operation will be described in the order of description. Hereinafter, a serial ATA HDD will be described as an example of a storage medium connected to an I / O (In / Out) interface.

  FIG. 1 is a block diagram showing an outline of the internal configuration of the image processing apparatus according to this embodiment. The image processing apparatus according to the present embodiment includes a controller 2001 equipped with an HDD controller 3000 and an engine 2011.

  The controller 2001 is a board that controls the entire system that constitutes the image processing apparatus. The controller 2001 is an application specific integrated circuit (ASIC) 2002, a central processing unit (CPU) 2003, a read only memory (ROM) 2004, an MEM-C network 2005, and an MEM-C. / F2006, operation unit 2007, and HDD 3001 are installed.

  The ASIC 2002 has application functions such as an image input / output function, an image processing function, and a data communication function in the image processing apparatus. The ROM 2004, the MEM-C 2005, the operation unit 2007, the HDD 3001, a PCI (Peripheral Component Interconnect) bus 2010. Etc. are controlled. Also, an HDD controller 3000 that controls the HDD 3001 is provided. In this embodiment, the HDD controller 3000 and the HDD 3001 are connected by Serial ATA.

  A CPU 2003 controls the ASIC 2002 and the entire image processing apparatus, and a ROM 2004 stores an operation program, image data, font data, and the like of the image processing apparatus. The MEM-C 2005 is a local memory and stores application programs, image data, and the like. A network I / F 2006 is an interface for connecting to a network such as the Internet and communicating with an external device. The operation unit 2007 includes input keys for inputting data, a touch panel, a display LCD (Liquid Crystal Display), and the like. The HDD 3001 accumulates and stores image images and various data. The PCI bus 2010 is an interface for connecting the controller 2001 and the engine 2011 and performing data transfer. The engine 2011 includes a scanner unit that performs a scanner operation and a plotter unit that performs a printing operation.

  Next, the HDD controller 3000 as a serial ATA HDD interface will be described. FIG. 2 is a block diagram showing an outline of the internal configuration of the HDD controller according to the present embodiment. The HDD controller 3000 of the present embodiment controls the entire HDD access, and includes a Serial ATA I / F (serial ATA interface) 3002, an ATA register 3003, a command register write monitoring unit 3004, a transfer end monitoring unit 3005, A power management control unit 3006 and a DMAC 3007 are included. The HDD interface is a differential interface and includes a Tx signal for transmission and an Rx signal for reception. The HDD 3001 (same as the HDD 3001 in FIG. 1) is used for image data storage or the like.

The Serial ATA I / F 3002 includes a transport layer (transport layer) 3008, a link layer (link layer) 3009, and a PHY.
A layer (physical layer) 3010 is included. The Transport Layer 3008 embeds and disassembles the set value of the ATA register 3003 and the read / write data of the HDD 3001 into the serial ATA transfer format. The Link Layer 3009 performs communication protocol generation / control, CRC generation / check, and scramble. The PHY Layer 3010 performs serial / parallel data conversion, 8B / 10B encoding, and CDR.

The ATA register 3003 is composed of a register group necessary for HDD access. FIG. 3 shows the internal structure of the ATA register 3003. The ATA register 3003 includes a command register 4001, a status register 4002, a device / head register 4003, a cylinder high register 4004, and a cylinder.
Low register 4005, Sector Number register 4006, Sector
It consists of a Count register 4007, a Feature register 4008, an ERR register 4009, a DATA register 4010, a Device Control register 4011, and an Alternate Status register 4012. Note that even the same register includes a register having a different meaning at the time of reading and writing.

  The command register 4001 is a write-only register, and writes commands such as read / write to the HDD 3001. The status register 4002 is a read-only register and reflects internal information of the HDD 3001. FIG. 4 is a diagram showing the details of the Status register 4002.

The BSY bit 5001 is set to “1” at the following time.
1) When the reset bit of the Device Control register 4011 is set to “1” 2) When the command register 4001 is written 3) A command for reading data into the DATA register 4010 by PIO transfer (data transfer by the CPU), during block transfer When the DRQ bit 5004 is cleared to “0” 4) A command for writing data to the DATA register 4010 by PIO transfer (data transfer by the CPU). After the block transfer is completed, the DRQ bit is cleared to “0”. in front

The BSY bit 5001 is set to “0” at the next time.
1) After the DRQ bit is set to “1” to notify that the HDD 3001 is ready for data transfer 2) When the command is finished 3) Until the bus is released with the Overlapped command 4) Power on, During hardware reset or software reset, but ready to accept commands that can be issued ignoring the state of DRDY bit 5002

The DRDY bit 5002 is set to “1” at the next time.
1) When all the implemented commands can be executed 2) When “HDD power management function” is implemented and in idle mode or standby mode (here “HDD power management function” ATA (parallel) and different from serial ATA power management to which the present invention is applied)

The DRDY bit 5002 is set to “0” at the next time.
1) When a hardware reset, software reset, or EXECUTE DEVICE DIAGNOSTIC command is executed

The DRQ bit 5004 is set to “1” at the next time.
1) When PIO transfer (data transfer by CPU) is ready 2) When DMA transfer is performed

The DRQ bit 5004 is set to “0” at the next time.
1) At the time of the last data transfer

The ERR bit 5006 is set to “1” at the next time.
1) When an error is detected after the BSY bit 5001 or the DRQ bit 5004 is set to “1”

The ERR bit 5006 is set to “0” at the next time.
1) When a new command is written to the Command register 4001 2) When the reset bit of the Device Control register 4011 is set to “1”

  The bit definition of #bit 5003 differs depending on the command. The obs bit 5005 is a reserved bit of the ATA standard.

  A Device / Head register 4003 is a readable / writable register, and performs selection when a plurality of HDDs 3001 are connected. A Cylinder High register 4004, a Cylinder Low register 4005, and a Sector Number register 4006 are readable / writable registers, and set addresses for accessing the HDD 3001. A Sector Count register 4007 is a readable / writable register, and sets a transfer amount for accessing the HDD 3001. The Feature register 4008 is a write-only register and is used when initializing the HDD. The ERR register 4009 is a read-only register and reflects error details when an HDD error occurs. The DATA register 4010 is a 16-bit readable / writable register, and is used when data is transferred by the CPU (when the DMAC 3007 is not used). The Device Control register 4011 is a write-only register, and performs HDD interrupt enable / disable setting, HDD reset control, and the like. The Alternate Status register 4012 is a substitute register for the Status register 4002.

  The command register write monitoring unit 3004 monitors that the CPU has made a write access to the command register 4001 of the ATA register 3003. When the CPU performs a write access to the command register 4001 of the ATA register 3003, the command register write monitoring unit 3004 transmits access information to the power management control unit 3006.

  The transfer end monitoring unit 3005 has read-accessed the BSY bit 5001, the DRDY bit 5002, the DRQ bit 5004, and the ERR bit 5006 in the Status register 4002 of the ATA register 3003, and has made a write access to the Command register 4001 Monitor that. The transfer end monitoring unit 3005 uses the command register write access of the CPU as a transfer end monitoring start trigger, and the following states, that is, the BSY bit 5001 is “0”, the DRDY bit 5002 is “1”, and the DRQ bit 5004 is “0”. At this time, transfer end information is transmitted to the power management control unit 3006. If the ERR bit 5006 is set to “1” before entering the above state, the transfer end information is not transmitted.

  When the power management control unit 3006 receives the transfer end signal from the transfer end monitoring unit 3005, the power management control unit 3006 counts the threshold set in the transition counter 3011 and then instructs the serial ATA I / F 3002 to execute a power management command (a command to shift to the power management mode). ). In addition, when command register write access information is received from the command register write monitoring unit 3004, a power management return instruction (return instruction from the power management mode to the normal mode) is issued to the Serial ATA I / F 3002. When a transfer end signal and command register write access information are received simultaneously, the power management return command is prioritized.

  The DMAC 3007 transfers the transfer data from the HDD 3001 or the transfer data to the HDD 3001 to the MEM-C 2005.

  Next, the entire operation of the image forming process performed by the image processing apparatus according to the present embodiment will be described by taking a copy process as an example. FIG. 5 is an explanatory diagram of copy processing according to the present embodiment. In FIG. 5, arrows indicate the data flow.

  First, when the user presses the copy start button of the operation unit 2007, the scanner unit provided in the engine 2011 scans the document and reads the image data of the document. The read image data of the original is transferred and stored in the MEM-C 2005 via the PCI bus (step SA-01). Then, the image data stored in the MEM-C 2005 is transferred and stored in the HDD 3001 via the HDD controller 3000 (step SA-02).

  Next, the image data stored in the HD 3001 is transferred and stored in the MEM-C 2005 via the HDD controller 3000 (step SA-03). Then, the image data stored in the MEM-C 2005 is transferred to the plotter unit included in the engine 2011 (step SA-04) and printed on a recording medium such as paper.

  Here, the transfer of the image data to the HDD 3001 in step SA-02 is executed by a DMA write operation by the HDD controller 3000. Further, the transfer of the image data from the HDD 3001 in Step SA-03 is executed by a DMA read operation by the HDD controller 3000. Therefore, the details of the DMA write operation and the DMA read operation by the HDD controller 3000 will be described.

  First, a DMA write operation by the HDD controller 3000 of this embodiment will be described. FIG. 6 is a sequence diagram showing exchange of data and commands between each part of the HDD controller 3000 and between each part and the HDD 3001 in the DMA write operation of the present embodiment. FIG. 7 is a diagram for explaining the DMA write operation of the present embodiment.

  First, the CPU 2003 performs initial settings for the ATA register 3003 and the DMAC 3007 ((1) in FIG. 6).

  Next, the CPU 2003 writes a DMA write command to the command register 4001 (C in FIG. 6). Further, the Serial ATA I / F 3002 transmits the ATA register information when the command is written to the HDD 3001 as a command packet in the TX signal (step SB-01). At this time, the BSY bit 5001 of the Status register 4002 is “1”, the DRDY bit 5002 is “0”, and the DRQ bit 5004 is “1” ((2) in FIG. 6).

  When the command register 4001 is accessed, the power management control unit 3006 receives a command write signal (command register write access information) from the command register write monitoring unit 3004, and returns power management to the Serial ATA I / F 3002. Issue instructions, but do not affect transfer. The transfer end monitoring unit 3005 receives the command write signal and starts transfer end monitoring (step SB-02).

  Next, the Serial ATA I / F 3002 receives a write OK packet from the HDD 3001 via the RX signal line (step SB-03). The write OK packet is processed inside the Link Layer 3009 ((3) in FIG. 6).

  Subsequently, when the DMAC 3007 is ready for data transfer, the DMAC 3007 transmits data to the Serial ATA I / F 3002 (step SB-04). The Serial ATA I / F 3002 transmits data to the HDD 3001 via the TX signal line ((4) in FIG. 6, step SB-05).

  When a desired amount of data is written to the HDD 3001, the HDD 3001 transmits a transfer end packet to the Serial ATA I / F 3002 (step SB-06). This content is reflected in the Status register 4002. In the case of normal termination, the BSY bit is “0”, the DRDY bit is “1”, and the DRQ bit 5004 is “0”. In the case of an error, the ERR bit becomes “1” ((5) in FIG. 6).

  When the Serial ATA I / F 3002 receives the transfer end packet, it reflects the value of the packet in the Status register 4002. The HDD controller 3000 generates an interrupt, and the CPU 2003 clears the interrupt (S in FIG. 6). The transfer end monitoring unit 3005 monitors the transfer end independently of the CPU 2003 (step SB-02), the BSY bit is “0”, the DRDY bit is “1”, and the DRQ bit 5004 is “0”. If it is, a transfer end signal (data transfer end information) is transmitted to the power management control unit 3006 (step SB-07). On the other hand, if the ERR bit 5006 is “1”, the transfer end signal is not transmitted.

  When receiving the transfer end signal, the power management control unit 3006 operates the transition counter 3011 (X in FIG. 6 is a count period). If the CPU 2003 writes to the command register 4001 while the transition counter 3011 is counting, the transition counter 3011 is reset and the power management control unit 3006 does not send a power management command. That is, a transition is made to the timing (9) in the figure ((6) in FIG. 6).

  When the count by the transition counter 3011 reaches a threshold value, the power management control unit 3006 sends a power management command to the Serial ATA I / F 3002 (step SB-08). The signal line (TX / RX signal) shifted to the power management mode by the power management command is in the neutral state (A in the figure) ((7) in FIG. 6).

  Subsequently, the CPU 2003 writes a DMA write command to the command register 4001 through an initial setting (C in FIG. 6). At the same time, the power management control unit 3006 receives a command write signal from the command register write monitoring unit 3004 (step SB-09), and sends a power management return command to the Serial ATA I / F 3002 (step SB-10). Here, B in FIG. 6 indicates a power management return period. Although the command packet cannot be transmitted during the power management return period, the ATA register information is held in the Transport Layer 3008 ((8) in FIG. 6).

  When returning from the power management mode, the ATA register information held in the Transport Layer 3008 is transmitted to the HDD 3001 as command packet information ((9) in FIG. 6, step SB-11). After the command packet information is transmitted, the operation is the same as that from (3) onward in FIG.

  Next, a DMA read operation by the HDD controller 3000 of this embodiment will be described. FIG. 8 is a sequence diagram showing exchange of data and commands between each unit of the HDD controller 3000 and between each unit and the HDD 3001 in the DMA read operation of the present embodiment. FIG. 9 is a diagram for explaining the DMA read operation of the present embodiment.

  First, the CPU 2003 performs initial settings for the ATA register 3003 and the DMAC 3007 ((1) in FIG. 9).

  Next, the CPU 2003 writes a DMA read command to the command register 4001 (C in FIG. 9). The Serial ATA I / F 3002 transmits the ATA register information when the command is written to the HDD 3001 as a command packet as a TX signal (step SC-01). At this time, the BSY bit 5001 of the Status register 4002 is “1”, the DRDY bit 5002 is “0”, and the DRQ bit 5004 is “1” ((2) in FIG. 9).

  When the command register 4001 is accessed, the power management control unit 3006 receives command write information (command register write access information) from the command register write monitoring unit 3004 and returns power management to the Serial ATA I / F 3002. Issue instructions, but do not affect transfer. The transfer end monitoring unit 3005 receives the command write signal and starts transfer end monitoring (step SC-02).

  Next, when the HDD 3001 is ready for data transfer, the HDD 3001 transfers data via the RX signal line (step SC-03). The DMAC 3007 receives data via the Serial ATA I / F 3002 ((3) in FIG. 9, step SC-04).

  When the HDD 3001 finishes transferring the desired amount of data, the HDD 3001 transmits a transfer end packet to the Serial ATA I / F 3002 (step SC-05). This content is reflected in the Status register 4002. In the case of normal termination, the BSY bit is “0”, the DRDY bit is “1”, and the DRQ bit 5004 is “0”. In the case of an error, the ERR bit becomes “1” ((4) in FIG. 9).

  When the Serial ATA I / F 3002 receives the transfer end packet, it reflects the value of the packet in the Status register 4002. The HDD controller 3000 generates an interrupt, and the CPU 2003 clears the interrupt (S in FIG. 9). The transfer end monitoring unit 3005 monitors the transfer end independently of the CPU 2003 (step SC-02), the BSY bit is “0”, the DRDY bit is “1”, and the DRQ bit 5004 is “0”. If it is, a transfer end signal (data transfer end information) is transmitted to the power management control unit 3006. On the other hand, if the ERR bit 5006 is “1”, the transfer end signal is not transmitted.

  When the power management control unit 3006 receives the transfer end signal, the power management control unit 3006 operates the transition counter 3011 (X in FIG. 9 is a counting period). If the CPU 2003 writes to the command register 4001 while the transition counter 3011 is counting, the transition counter 3011 is reset and the power management control unit 3006 does not send a power management command. That is, a transition is made to the timing of (8) in FIG. 9 ((5) in FIG. 9).

  When the count by the transition counter 3011 reaches a threshold value, the power management control unit 3006 sends a power management command to the Serial ATA I / F 3002 (step SC-07). The signal line (TX / RX signal) shifted to the power management mode by the power management command is in the neutral state (A in FIG. 9) ((6) in FIG. 9).

  Subsequently, the CPU 2003 writes a DMA read command to the command register 4001 through an initial setting (C in FIG. 9). At the same time, the power management control unit 3006 receives the command write signal from the command register write monitoring unit 3004 (step SC-08), and sends a power management return command to the Serial ATA I / F 3002 (step SC-09). Here, B in FIG. 9 is a power management return period. Although the command packet cannot be transmitted during the power management return period, the ATA register information is held in the Transport Layer 3008 ((7) in FIG. 9).

  When returning from the power management mode, the ATA register information held in the Transport Layer 3008 is transmitted to the HDD 3001 as command packet information ((8) in FIG. 9, step SC-10). After the command packet information is transmitted, the operation is the same as the operation after (3) in FIG.

  Due to the DMA read / write operation of the HDD interface described above, the power management mode is shifted to the data non-transfer period, and the power consumption of the entire HDD controller can be reduced in hardware / software. In addition, transition control to the power management mode can be performed without correcting ATA (parallel) software.

  The above-described embodiment is a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiment alone, and various modifications can be made without departing from the gist of the present invention. Implementation in the applied form is possible.

  That is, the image processing apparatus according to the above-described embodiment operates by processing, means, and functions executed by a computer according to program instructions. The program sends a command to each component of the computer, and after receiving a transfer end signal from the transfer end monitoring unit 3005 by the predetermined processing or function as described above, for example, the power management control unit 3006. When a predetermined period has elapsed, a power management command is issued to the Serial ATA I / F 3002 to shift to the power management mode, and when a command write signal from the command register write monitoring unit 3004 is received, the power management is returned to the Serial ATA I / F 3002 A command is issued to return from the power management mode. As described above, each process and means in the image processing apparatus according to the above-described embodiment is realized by specific means in which the program and the computer cooperate.

  Then, the computer code of the image processing apparatus stores the program code stored in the storage medium via a computer-readable recording medium that records the program code of the software that realizes the functions of the above-described embodiments, that is, the storage medium. The object of the present invention is also achieved by executing the reading. Further, the program can be loaded and executed directly on a computer through a communication line without going through a recording medium, and the object of the present invention can be achieved similarly.

  In this case, the program code itself read from the storage medium or loaded and executed through the communication line realizes the functions of the above-described embodiment. And the storage medium which memorize | stored the program code comprises this invention.

  Examples of the storage medium for supplying the program code include a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a nonvolatile memory card, a ROM, and a magnetic tape. Can be used.

1 is a block diagram illustrating an outline of an internal configuration of an image processing apparatus according to an embodiment of the present invention. 1 is a block diagram showing an outline of an internal configuration of an HDD controller according to an embodiment of the present invention. It is the figure which showed the internal structure of the ATA register in embodiment of this invention. It is a figure for demonstrating the content of the Status register in embodiment of this invention. It is explanatory drawing of the copy process of this Embodiment. FIG. 7 is a sequence diagram showing exchange of data and commands between each part of the HDD controller and between each part and the HDD in the DMA write operation of the present embodiment. It is a figure for demonstrating the DMA write operation in this Embodiment. FIG. 6 is a sequence diagram showing exchange of data and commands between each part of the HDD controller and between each part and the HDD in the DMA read operation of the present embodiment. It is a figure for demonstrating the DMA read operation | movement in this Embodiment.

Explanation of symbols

2001 Controller 2002 ASIC
2003 CPU
2004 ROM
2005 MEM-C
2006 Network I / F
2007 Operation unit 2008, 3001 HDD
2010 PCI path 2011 engine 2012, 3000 HDD controller 3002 Serial ATA I / F
3003 ATA register 3004 Command register write monitoring unit 3005 Transfer end monitoring 3006 Power management control 3007 DMAC
3008 Transport Layer
3009 Link Layer
3010 PHY Layer
3011 Transition counter 4001 Status register 4002 Command register 4009 ERR register 5001 BSY
5002 DRDY
5004 DRQ
5006 ERR

Claims (15)

A storage unit capable of storing data;
A storage control unit for controlling data transfer with the storage unit, and a control unit having an application function;
A serial ATA interface for connecting the storage control unit and the storage unit;
A transfer start monitoring unit that monitors the start of data transfer processing between the storage control unit and the storage unit;
A transfer end monitoring unit for monitoring the end of the data transfer process;
A power management control unit that manages power consumption of the control unit and the storage unit based on monitoring results by the transfer start monitoring unit and the transfer end monitoring unit;
An interface control circuit comprising:   The interface control circuit according to claim 1, wherein the transfer start monitoring unit monitors the issuance of a command for the data transfer process. An access information holding unit for holding information necessary for access to the storage unit;
3. The interface control circuit according to claim 2, wherein the transfer start monitoring unit detects the issuance of the command when a read or write command to the storage unit is written in the access information holding unit. .   4. The interface control circuit according to claim 3, wherein the transfer start monitoring unit transmits the command issuance as command issuance information to the power management control unit when detecting the issuance of the command. 5.   The interface control circuit according to claim 4, wherein the transfer end monitoring unit monitors an internal state of the storage unit.   The interface control circuit according to claim 5, wherein the transfer end monitoring unit starts monitoring the internal state when the transfer start monitoring unit detects the issuance of the command. The access information holding unit holds an internal state of the storage unit,
The transfer end monitoring unit transmits the internal state as transfer end information to the power management control unit when the internal state indicates that the data related to the command is final data and the command has ended. The interface control circuit according to claim 6.   The power management control unit outputs a power management command for setting an interface signal line connecting the ASIC and the storage unit to a neutral state, or a power return command for returning from the neutral state to a synchronized state. The interface control circuit according to claim 7, wherein the interface control circuit transmits to the interface.   The power management control unit has a count unit that counts a period after the transfer end information is received, and when the count by the count unit exceeds a predetermined threshold, the power management command is sent to the serial ATA interface. 9. The interface control circuit according to claim 8, wherein the interface control circuit transmits the interface control circuit.   The power management control unit transmits the power return command to the serial ATA interface when the command issue information is received after the interface signal line is in a neutral state by the power management command. The interface control circuit according to claim 9.   The power management control unit resets the count and does not transmit the power management command to the serial ATA interface when the command issue information is received before the count by the count unit exceeds a predetermined threshold. The interface control circuit according to claim 10. An engine unit which is a hardware resource for image processing;
A storage unit capable of storing image data;
A control unit having a storage control unit for controlling data transfer with the storage unit, and having an application function for image processing;
A serial ATA interface for connecting the storage control unit and the storage unit;
A transfer start monitoring unit that monitors the start of data transfer processing between the storage control unit and the storage unit;
A transfer end monitoring unit for monitoring the end of the data transfer process;
A power management control unit that manages power consumption of the control unit and the storage unit based on monitoring results by the transfer start monitoring unit and the transfer end monitoring unit;
An image processing apparatus comprising: The engine unit includes a scanner unit that performs a scanning operation,
The image processing apparatus according to claim 12, wherein the storage control unit transfers and writes image data of a document scanned by the scanner unit to the storage unit. The engine unit includes a plotter unit that executes a printing operation.
The image processing apparatus according to claim 12, wherein the storage control unit reads image data stored in the storage unit and transfers the image data to the plotter unit. A power management method executed by an interface control circuit,
The interface control circuit includes a storage unit capable of storing data and a storage control unit that controls data transfer with the storage unit, and connects the control unit having an application function, the storage control unit, and the storage unit A serial ATA interface,
A transfer start monitoring unit for monitoring a start of a data transfer process between the storage control unit and the storage unit; and
A transfer end monitoring unit for monitoring the end of the data transfer process;
A power management control unit that manages power consumption of the control unit and the storage unit based on monitoring results of the transfer start monitoring step and the transfer end monitoring step;
A power management method comprising:

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