JP2008293226A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of dealing with a memory circuit for attaining a variable logic function, as a circuit equivalent to a logic circuit, and capable of providing the variable logic function with a small chip occupation area. <P>SOLUTION: This semiconductor device is provided with a plurality of function reconstitution cells having respectively the memory circuit (20) and a control circuit (21) in order to attain the variable logic function, and controls autonomously a read address of the memory circuit for storing a truth value data. The control circuit can perform random-access to a data field (27_D) and a control field (27_C), based on address information supplied from an interface control circuit, in the first operation mode, feedback-inputs control information (DAT_C) from the control field read together with the data field, in the second operation mode, and allows logic operation, by repeating operations for updating sequentially the read addresses of the data field and the control field according to input logic control information. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of variably realizing a logic function using a memory circuit, and is effective when applied to, for example, a semiconductor data processing device including a variable logic module capable of realizing a peripheral function in a programmable manner. Regarding technology.

  As a variable logic module or a variable logic device (reconfigurable device), a PLD (programmable logic device) or an FPLD (field PLD) has already been used. A typical PLD is a programmable device such as an FPGA (Field Programmable Gate Array). The FPGA is based on a look-up table, and CLB (configurable logic block), which has flip-flops on it, is connected by a MOS switch in a programmable manner to constitute a large-scale logic. The FPGA is basically an element having a rewritable logic circuit and a variable switch circuit. Patent Document 1 describes FPGA. The logic circuit that is the basis of the FPGA is composed of, for example, a 4-input LUT (Look Up Table), has an F / F (Flip-Flop) at the final stage, and has a 2-stage 2-layer logic structure. ing. This is called CLB. For example, in order to programmably configure the logic equivalent to 1 mega (M) gate, CLB of 1 kilo (k) or more is assembled and the logical information of this CLB is held in SRAM (Static Random Access Memory). Can be rewritten. These CLBs have a switch matrix to make their connections programmable. In order to provide directionality, the switch is composed of 6 MOS switch MOS, and the on / off control information of the switch MOS is also provided in the SRAM. A quantity is needed. Further, in Patent Document 2, a plurality of variable logic circuits capable of configuring arbitrary logic by storing predetermined truth value data in a memory are arranged in a matrix, and these are arranged as variable switch circuits in wiring in the X and Y directions. There is a description of a semiconductor device that is variably connected to the device.

Japanese Patent Laid-Open No. 04-242825 JP 2003-149300 A

  However, when a variable logic module is configured by connecting a large number of CLBs using a switch matrix, as represented by the above-mentioned FPGA, the number of CLBs and the switch elements of the switch matrix are changed as the required logic scale increases. The inventors have found that there is a limit to improvement of the mounting area. That is, when programming a complicated logic or sequence, it is necessary to set a large number of CLB connections using a large number of switch matrices in proportion to the required logical scale. When storing truth value data for logical configuration in the SRAM, if the truth value data read from the SRAM is only used as static information for the logical configuration, the SRAM storage is proportional to the required logical scale. Capacity must be increased. In the prior art, no consideration is given to applying the variable logic module to an actual circuit such as a peripheral circuit.

  An object of the present invention is to provide a semiconductor device capable of handling a memory circuit for realizing a variable logic function as a circuit equivalent to a logic circuit.

  Another object of the present invention is to provide a semiconductor device capable of realizing a variable logic function with a small chip occupation area.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a semiconductor device according to the present invention includes a plurality of function reconfigurable cells each having a memory circuit and a control circuit to realize a variable logic function, and a function reconfiguration of a read address of a memory circuit storing truth value data It is controlled autonomously by the stored information of the cell. For example, the control circuit can randomly access the data field and the control field based on address information supplied from the interface control circuit in the first operation mode, and is read together with the data field in the second operation mode. The control information from the control field is fed back and the operation of sequentially updating the data field and the read address of the control field according to the input control information is repeated to enable the logic operation. As a result, the memory circuit for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit, so that flexibility in the realizable logic configuration and logic scale can be obtained, and a small chip occupation area can be obtained. This makes it possible to implement variable logic functions that can handle large logic scales.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, a memory circuit for realizing a variable logic function can be handled as a circuit equivalent to a logic circuit.

  In addition, a variable logic function can be realized with a small chip occupation area. Further, it becomes easy to dynamically reconfigure the logic function.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device according to a representative embodiment of the present invention includes a plurality of function reconfigurable cells (10) having a memory circuit (20) and a control circuit (21), and the function in response to an access request. Interface control circuits (13 to 17) for controlling the reconfigurable cells. The memory circuit has a data field (27_D) and a control field (27_C) accessible based on address information output from the control circuit. The control circuit enables random access to the data field and the control field based on address information supplied from the interface control circuit in the first operation mode, and the control read together with the data field in the second operation mode. The control information (DAT_C) from the field is fed back and the operation of sequentially updating the data field and the read address of the control field according to the input control information is repeated to enable the logic operation.

  As described above, since the reading of the memory circuit can be autonomously controlled according to the memory information of the function reconfigurable cell, the memory circuit for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit. Therefore, it is possible to obtain flexibility in the feasible logic configuration and logic scale, and it is possible to realize a variable logic function that can cope with a large logic scale with a small chip occupation area.

  As one specific form, the interface control circuit designates the corresponding function reconfigurable cell using the higher-order side information of the address signal, and the control circuit of the function reconfigurable cell designated thereby In the first mode, the corresponding data field and control field are designated using the lower-order information of the address signal. As a result, the data field and the control field are randomly accessed. Further, in the second mode, the sequential control of read address update, return of the initial value of the read address, or stop of the read address update is controlled in accordance with the control information inputted in feedback. Thereby, a logic operation according to the storage information of the storage circuit is performed.

  As a more specific form, the interface control circuit outputs an interrupt signal (IRQ) when the read address update is stopped. Thereby, the result of the logic operation can be easily acquired from the outside based on the interrupt response process.

  As another specific form, the plurality of function reconfigurable cells may include a first bus used for random access of the data field and the control field of the function reconfigurable cell specified by using higher-order information of an address signal. MBUS) and a second bus (LBUS) used for the logic operation of the function reconfigurable cell designated by using higher-order information of the address signal. It becomes possible to facilitate the input / output control according to the random access operation and the logic operation in which the information input / output modes are different.

  As a more specific form, it has a buffer register (MBuff) mapped to an address different from that of the storage circuit and connected to the second bus, and the interface control circuit outputs the output of the buffer register in response to an access request. Control the behavior. The operation result by the logic operation can be acquired by register access similar to the memory mapped IO.

  In another specific form, the function reconfigurable cell is configured to variably select a path for transmitting information read from the data field and the control field to another function reconfigurable cell or the second bus. It further has a route selection circuit (22-23). It is possible to easily realize an operation mode in which a plurality of function reconfigurable cells are operated in series or in parallel to perform logic operation. At this time, the connection path selection circuit, for example, a switch circuit (22) that selects the path and a connection storage circuit (23) that retains rewritable switch control information (DAT_R) that determines the switch state of the previous switch circuit. ).

  [2] A semiconductor device according to another embodiment of the present invention includes a logic circuit (2) that can be an access request subject, and a function reconfiguration memory (8) that operates in response to an access request from the logic circuit. Have The function reconfigurable memory includes a plurality of function reconfigurable cells (10) having a storage circuit (20) and a control circuit (21), and an interface for controlling the function reconfigurable cells in response to an access request from the logic circuit. And a control circuit (13-17). The memory circuit is assigned an address (first address range) so that it can be accessed as a memory from the logic circuit in the address space of the semiconductor device, and for input / output of information necessary for performing a logic operation. An address is allocated (second address range) so as to be accessible as an IO. The storage circuit has a data field and a control field accessible based on address information output from the control circuit. The control circuit enables random access to the data field and the control field based on address information supplied from the interface control circuit in the first operation mode, and the control read together with the data field in the second operation mode. The control information from the field is fed back and the operation of sequentially updating the read address of the data field and the control field according to the input control information is repeated to enable the logic operation. Similarly to the above, the memory circuit for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit, the logic configuration that can be realized is flexible, and it can support a large logic scale with a small chip occupation area. Variable logic functions can be realized. The access request subject is, for example, a bus master module such as a central processing unit or a direct memory access controller.

  As one specific form, the logic circuit performs a write access request for the first address range for designating the first operation mode, whereby a function reassignment to which an address related to the access request is assigned. The memory circuit of the constituent cell is accessed as a memory, and information for realizing a predetermined logic function is written in the memory circuit of the function reconfigurable cell. Thereby, the access request subject can define the logical configuration of the function reconfigurable cell by writing to the storage circuit by random access designating the address in the first address range.

  Further, the logic circuit makes a read access request to the second address range for designating the second operation mode, thereby causing the function reconfigurable cell of the address related to the access request to start the logic operation. . Thereby, the access request subject can start the logical operation by the function reconfigurable cell in which the logical function is set.

  The information processing apparatus further includes a buffer register that holds information output from the function reconfigurable cell by the logic operation and is mapped to the third address range. The logic circuit makes a read access request for the third address range and reads the result of the logic operation from the buffer register. Thereby, the access request subject can easily obtain the result of the logic operation by the function reconfigurable cell by register access similar to the memory mapped IO by designating the address in the second address range.

  A memory mapped I / O assigned to a function reconfigurable cell in order to obtain a logical operation result by a function reconfigurable cell with a function set for address mapping (first address range) for random access to the memory circuit By individualizing the read address (address in the third address range) such as an address, even if the logic function for the function reconfigurable cell is dynamically reconfigured, the read address for acquiring the logic operation result is obtained. It is easy to dynamically reconfigure logic functions for function reconfigurable cells without causing changes.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 2 illustrates a data processor (DPCU) 1 according to an example of the present invention. The data processor shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique.

  The data processor 1 is not particularly limited, but includes a central processing unit (CPU) 2 that fetches and executes instructions according to a program, a read-only memory (ROM) 3 that stores programs executed by the CPU 2, and a work of the CPU 2 A random access memory (RAM) 4, an external interface circuit (EXIO) 5, a bus state controller (BSC) 6, an interrupt controller (INTC) 7 and a function reconfigurable memory (RCFGM) 8 used for areas and the like; They are connected to an internal bus (IBUS) 9. When a bus master module such as the CPU 2 issues an access request, the BSC 6 outputs a bus control strobe signal or the like according to the mapping address of the circuit related to the access request, and the number of bus cycles or the number of parallel data bits necessary for access Performs bus control.

  The function reconfigurable memory 8 is variably set in accordance with logic function setting information (configuration information) written from the internal bus 9 by the CPU 2 or the like, and data can be input / output to / from the set logic function. To be.

  In the figure, INT is representatively shown as an interrupt signal, and the interrupt controller 7 performs interrupt mask control and priority level control on the interrupt signal, receives the interrupt signal, issues a vector corresponding to the received interrupt signal, and CPU 2 Interrupt request signal IRQ is issued to cause CPU 2 to execute the interrupt processing program indicated by the vector.

  The function reconfigurable memory 8 has a plurality of function reconfigurable cells 10 arranged in a matrix. Further, as an interface control circuit for controlling the function reconfigurable cell 10 in response to an access request from the outside, a bus interface (BUSIF) 13, an access control circuit (ACCNT) 14, an input circuit (INP) 15, an output circuit ( OUTP) 16 and an address decoder (ADEC) 17. In the function reconfigurable cell 10, the logic function is variably set according to the configuration information for the logic function written by random access from the internal bus 9 by the CPU 2 or the like. For example, logical functions such as a FIFO buffer, a 16-bit pulse width modulation circuit, an 8-bit pulse width modulation circuit, a serial transmission unit, and a serial reception unit are set. The remaining function reconfigurable cells 10 to which no logic function is set are made available as an internal memory that can be randomly accessed via the internal bus 9. The address decoder 17 generates selection signals CEX and CEY for selecting the function reconfigurable cell specified by the address signal. The function reconfigurable cell selected by the selection signals CEX and CEY is made operable under the control of the outside. Writing of preset data used for the set logical operation and data reading of the logical operation result are performed via the internal bus 9.

  An example of a function reconfigurable cell 10 is shown in FIG. The function reconfigurable cell 10 includes a memory circuit (MRY) 20, a control circuit (MCONT) 21, a path selection switch circuit (RTSW) 22, and a path selection register (RTREG) 23. In the array of function reconfigurable cells 10 arranged in matrix, an address bus ABUS, a memory bus MBUS, and a logic bus LBUS are arranged in units of rows of the function reconfigurable cells 10.

  The switch circuit 22 can be connected to the switch circuit 22 of the function reconfigurable cell in the same column arranged in the upper and lower adjacent rows, and the control circuit 21 of the function reconfigurable cell 10 in the next stage arranged in the same row. To the logic bus LBUS. Which connection form is adopted is programmable according to switch control information set in the route selection register 23.

  The storage circuit 20 is constituted by, for example, a single port static random access memory (SRAM). The memory circuit 20 has a data field (DFLD) 27_D and a control field (CFLD) 27_C that are accessed by an address signal supplied from the control circuit 21. The address decoder (SDEC) 28 decodes an input address signal and selects a memory cell in an access unit from each of the data field (DFLD) 27_D and the control field (CFLD) 27_C. Addresses corresponding to the storage capacity of the storage circuit 20 are mapped to each function reconfigurable cell 10. The higher order side of the mapped address is regarded as selection information of the function reconfigurable cell 10, and the lower order side of the address is regarded as access unit selection information (ADD) in the storage circuit 20. The selection signals CEX and CEY are generated by the upper address information of the address being decoded by the address decoder 17. The control circuit 21 is activated by being selected by the selection signals CEX and CEY of the corresponding function reconfigurable cell. R / W is a read / write signal (R / W is valid in the memory mode and register setting mode, but only read is valid in the logic mode), CLK is a synchronous clock signal of the function reconfigurable cell 10, and MOD is Mode signal.

  When the memory mode is designated by the mode signal MOD, the activated control circuit 21 stores the storage circuit 20 designated by the low-order address information ADD from the address bus ABUS as illustrated in FIG. A read operation or a write operation is controlled for the area in accordance with the read / write signal R / W. Read data is output to the memory bus MBUS, and write data is supplied from the memory bus MBUS. A two-dot chain line means a main signal flow in the operation mode.

  When the control circuit 21 is activated by the selection signals CEX and CEY, the logic mode is designated by the mode signal MOD (corresponding to the instruction for setting the operation enable bit for the peripheral circuit). At this time, as illustrated in FIG. 4, the control circuit 21 starts a read operation with respect to the head address of the memory circuit 20, inputs the logic control information DAT_C from the read control field 27_C, and inputs the feedback input logic. The logic operation is controlled by repeating the operation of sequentially updating the read addresses of the data field 27_D and the control field 27_C according to the control information DAT_C. The sequential address update operation in the logic operation is, for example, sequential progress of read address update, return of the initial value of the read address, or stop of read address update in accordance with the value of the logic control information. Since the operation of the read operation from the control circuit 21, the read operation from the storage circuit 20, and the feedback input of the read information to the control circuit 21 are repeated, the operation during the logic operation is synchronized due to the influence of wiring delay and the like. It is also conceivable that the one-cycle operation of the clock CLK is not in time. The control circuit 21 controls so that the read operation instruction to the storage circuit 20 is issued in advance of 1 cycle to 1/2 cycle of the synchronous clock CLK, so that the next operation based on the read operation from the storage circuit 20 and the feedback input is performed. It is possible to pipeline access address determination. When the switch circuit 22 is set so that the information DAT_D read from the data field 27_D is loaded to the output data register (MBuff) of the output circuit 16 via the logic bus LBUS, the result of the logic operation in the logic mode is It can be obtained by a register read operation by the CPU 2 similar to the memory mapped IO register access to the output data register of the output circuit 16. That is, when the control circuit 21 is activated by the selection signals CEX and CEY, it can be read by designating the logic mode by the mode signal MOD (corresponding to the read operation instruction to the memory mapped IO register of the peripheral circuit). To be.

  When the control circuit 21 is activated by the selection signals CEX and CEY, the register setting mode is designated by the mode signal MOD and the write operation is instructed by the read / write signal R / W is illustrated in FIG. As described above, the control circuit 21 selects the corresponding path selection register 23 and stores the connection control information DAT_R from the logic bus LBUS in the path selection register 23. The connection control information DAT_R stored in the route selection register 23 is supplied to the switch circuit 22 to determine route selection. Further, the connection control information DAT_R stored in the path selection register 23 is also supplied to the control circuit 21, and the function re-use that is used only in the memory mode by selecting the feedback input of the logic control information DAT_C and the input from the logic bus LBUS. Blocking the input of unnecessary information to the control circuit 21 of the configuration cell 10 and selecting to block the input from the memory bus MBUS to the control circuit 21 of the function reconfigurable cell 10 used only in the logic mode. The input of unnecessary information is blocked. Such control is useful for preventing malfunction of the logic operation of the function reconfigurable cell.

  According to the function reconfigurable cell 10, reading of the memory circuit 20 can be autonomously controlled by the logic control information held by the function reconfigurable cell 10. For example, the control circuit 21 determines whether to advance the next read address of the storage circuit 20 based on the information DAT_C of the control field CFDL previously read from the storage circuit 20, return to the initial value, or stop. It can be controlled autonomously. Thereby, the memory circuit 20 for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit. Therefore, it is possible to obtain flexibility in the feasible logic configuration and logic scale, and it is possible to realize a variable logic function that can cope with a large logic scale with a small chip occupation area.

  FIG. 6 illustrates the overall configuration of the function reconfiguration memory 8. In the figure, reference numeral 25 denotes an array of function reconfigurable cells 10. The address bus ABUS is not shown. The input circuit 15 includes a memory bus and address bus input circuit (MINP) 15_M and a logic bus input circuit (LINP) 15_L. The input circuit 15_M is connected to the bus interface circuit 13 via the main input memory address bus GITAB, and has an input selector switch MSW that selectively connects the main input memory address bus GITAB to the memory bus MBUS and the address bus ABUS. The input circuit 15_L is connected to the bus interface circuit 13 via the main input logic bus GILB, and has an input selector switch LSW that selectively connects the main input logic bus GILB to the logic bus LBUS. The output circuit 16 includes a memory bus output circuit (MOUTP) 16_M and a logic bus output circuit 16_L. The output circuit 16_M has a data output register MBuff corresponding to each memory bus MBUS, temporarily holds memory read data, and the held read data can be selectively output to the main output data bus GOMAB. . The output circuit 16_L has a data output register LBuff corresponding to each logic bus MBUS, temporarily holds the logic data, and the held logic data can be selectively output to the main output logic bus GOLB. Although not particularly limited, the data output register LBuff and the path selection register 23 are memory mapped IO registers.

  The address decoder 17 decodes the address signal ADRS to generate selection signals CEX and CEY. At this time, in the memory mode, the address decoder 17 selects the input selector switch MSW corresponding to the column selected by the selection signal CEY with the selection signal SBS, and further outputs the data output register MBuff when the read operation is designated. The operation is selected by the selection signal SBS. In the logic mode, the address decoder 17 selects the output operation of the data output register LBuff corresponding to the column selected by the selection signal CEY by the selection signal SBS. In the register setting mode, the address decoder 17 can select the input selector switch LSW corresponding to the column selected by the selection signal CEY with the selection signal SBS, and set the connection control information to the path selection register 23 via the corresponding logic bus LBUS. To.

  The access control circuit 14 receives a system reset signal RES and a system clock signal SCLK from the outside, and receives a memory access strobe signal MAC, a register access strobe signal RAC, a read signal RD, and a write signal WT from the bus state controller 6. To do. Although not particularly limited, in the function reconfiguration memory 8, the mapping address for the memory mode, the mapping address for the logic mode, and the mapping address for the register setting mode are set separately. As described above, each mapping address is determined so that the upper side of the address information for generating the selection signals CEX and CEY is commonly used in any operation mode. When there is an access request by the CPU 2, the bus state controller 6 enables the memory access strobe signal MAC if the access target address corresponds to the mapping address for the memory mode, and if a write operation is requested at this time The write signal WT is enabled and the read signal RD is enabled if a read operation is required, whereby the access control circuit 14 controls the inside in the memory mode by the mode signal MOD and the read / write signal R / W. In this way, configuration information for setting a logic function is set in the function reconfigurable cell 10, and random access to a function reconfigurable cell that is not used for logic operation is enabled. The bus state controller 6 enables the register access strobe signal RAC when the access target address corresponds to the mapping address for the logic mode, and enables the write signal WT if a write operation is requested at this time. If a read operation is requested, the read signal RD is enabled, whereby the access control circuit 14 controls the inside in the register mode by the mode signal MOD and the read / write signal R / W. Incidentally, if the write operation is instructed, the logic operation can be started based on the function reconfigurable cell 10 specified by the address, and if the read operation is instructed, the data register MBuff specified by the address The reading operation of the data held by can be started. The bus state controller 6 enables the register access strobe signal RAC and the write signal WT when the access target address corresponds to the mapping address for the register setting mode, whereby the access control circuit 14 reads the mode signal MOD and the read signal. The operation of controlling the inside in the register setting mode by the write signal R / W and setting the connection control information in the register 23 can be started.

  FIG. 7 shows an example in which an 8-bit counter is realized using the function reconfigurable cell 10. The example shown here is an example in which the operation ends after 256 counts are performed once. An example of configuration information set in the memory circuit 20 is shown in FIG. The data field 27_D has a value of “add + 1” in order from the start address “0”, and the value of the final address “255” is set to all 0. Control flags A, B, C, and D are stored in the control field 27_C. Control flag A indicates a continuous count operation ("1" = counts, "0" = does not count), and control flag B indicates a repeat count operation ("1" = repeates) , “0” = do not repeat), the control flag C is a carry flag (“1” indicates a count end notification), and the control flag D is a trigger signal (a start trigger when a counter is added to the next stage). A flowchart from the implementation of the 8-bit counter to the end of the operation is illustrated in Fig. 9. First, the function reconfiguration memory 8 is reset (S1), and the logic operation is performed. The configuration information is written into the performance reconfigurable cell in the memory mode (S2) According to the example of Fig. 7, the function reconfigurable cell 10 corresponding to the data information DAT_C and the logic control information DAT_C illustrated in Fig. 8 Next, the path by the switch circuit 22 and the feedback path of the logic control information DAT_C to the control circuit 21 are set in the register setting mode (S3) After this, the function reconfigurable cell 10 that is the target of the counter operation. Is selected by signals CEX and CEY and the logic mode is designated (S4), the function reconfigurable cell 10 starts a counter operation (S5). Count-up operation by address step as long as flag A = 1 continues with the feedback logic control information DAT_C Continued (S6), the flag A = 0, the count in the flag B = 0 is finished, an interrupt signal INT is output to the interrupt controller 7 by the flag C = 1 (S7).

  FIG. 10 and FIG. 11 show another example when an 8-bit counter is realized using the function reconfigurable cell 10. The example shown here is an example in which 256 counts are repeated a plurality of times. The difference from FIGS. 7 and 8 is that the configuration information in which the flag B = 1 is stored in the storage circuit 20 when add = 254. FIG. 12 illustrates a flowchart from the implementation of the 8-bit counter to the end of the operation. The difference from FIG. 9 is that the function reconfigurable cell 10 that has started the count operation continues the count-up operation by the address step as long as the flag A = 1 continues based on the fed back logic control information DAT_C (S6A). The point is that the address add is returned to the initial value when A = 1 and flag B = 1 (S6B).

  The data processor 1 described above has the following operational effects.

  (1) Reading of the memory circuit 20 can be autonomously controlled according to the logic control information of the function reconfigurable cell 10. Therefore, the memory circuit 20 for realizing the variable logic function can be handled as a circuit equivalent to the logic circuit, the logic configuration that can be realized is flexible, and it can cope with a large logic scale with a small chip occupation area. A variable logic function can be realized.

  (2) The CPU 2 can arbitrarily define configuration information for realizing a predetermined logic function in the function reconfigurable cell 20 by randomly accessing the function reconfigurable cell 10 in the memory mode.

  (3) For the random access address mapping of the function reconfigurable cell 10 in the memory mode, the address mapping of the register for storing the operation result in the logic mode is individualized, whereby the logic for the function reconfigurable cell 20 and the data register MBuff is determined. Even if the function is dynamically reconfigured, it is easy to dynamically reconfigure the logic function for the function reconfigurable cell 10 without changing the read address or the like for acquiring the logic operation result.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the method of address mapping for the function reconfigurable cell 20, the connection register 23, and the data register MBuff, and the method of specifying the operation mode such as the memory mode, the logic mode, and the register setting mode are not limited to the above description, and are appropriately changed. Is possible. The bus configuration to which the function reconfigurable memory is connected is not limited to the above, and may be a configuration in which the CPU is connected to a CPU bus and a peripheral bus is connected to the CPU bus via a bus state controller. . As a connection form between the function reconfigurable cells arranged in matrix and the bus, a connection form in which buses are arranged in the X and Y directions and addressed from the X and Y directions and connected to the bus may be employed. The peripheral functions realized by the function reconfigurable cell are not limited to the above and can be changed as appropriate. Moreover, it is not limited to so-called peripheral functions for the CPU. It is also possible to assign a calculation function or the like that reduces the burden on the CPU, such as an accelerator. The circuit mounted on the semiconductor device together with the function reconfigurable memory is not limited to that shown in FIG. 2, and can be appropriately changed according to the function and application of the semiconductor integrated circuit. The semiconductor device is not limited to a single chip, and can also be applied to a semiconductor device such as a system-in-package in which a multichip is mounted on a module substrate and sealed.

It is a block diagram which shows an example of the function reconfiguration cell with which the semiconductor device of this invention is provided. It is a block diagram of a data processor according to an example of the present invention. It is a block diagram which shows the main signal flows in the function reconfiguration cell when the memory mode is designated by the mode signal MOD. It is a block diagram which shows the main signal flows in the function reconfiguration cell when a logic mode is designated by the mode signal MOD. It is a block diagram which shows the main signal flows in the function reconfiguration cell when the register setting mode is designated by the mode signal MOD. It is a block diagram which illustrates the whole structure of a function reconfiguration memory. It is a schematic block diagram which shows the example in the case of implement | achieving an 8-bit counter which performs 256 count once and complete | finishes an operation | movement with a function reconfigurable cell. It is explanatory drawing which illustrates the function structure information set to the memory circuit of the function reconfigurable cell of FIG. It is a flowchart which shows from mounting of the 8-bit counter of FIG. It is a schematic block diagram which shows the example in the case of implement | achieving the 8-bit counter which repeats 256 counts in multiple times with a function reconfiguration | reconstruction cell. FIG. 11 is an explanatory diagram illustrating function configuration information set in the memory circuit of the function reconfigurable cell in FIG. 10. It is a flowchart which shows from the implementation of the 8-bit counter of FIG. 10 to the end of the operation.

Explanation of symbols

1 Data processor 1
2 Central processing unit (CPU)
6 Bus state controller (BSC)
7 Interrupt controller (INTC)
8 Function reconfiguration memory (RCFGM)
9 Internal bus (IBUS)
INT interrupt signal 10 function reconfigurable cell 13 bus interface (BUSIF)
14 Access control circuit (ACCNT)
15 Input circuit (INP)
16 Output circuit (OUTP)
17 Address decoder (ADEC)
20 Memory circuit (MRY)
21 Control circuit (MCONT)
22 Switch circuit (RTSW) for route selection
23 Route selection register (RTREG)
ABUS Address bus MBUS Memory bus LBUS Logic bus 27_D Data field (DFLD)
27_C Control field (CFLD)
28 Address decoder (SDEC)
CEX, CEY selection signal R / W read / write signal CLK synchronous clock signal MOD mode signal DAT_D data information DAT_C logic control information DAT_R connection control information

Claims (14)

A plurality of function reconfigurable cells having a memory circuit and a control circuit;
An interface control circuit for controlling the function reconfigurable cell in response to an access request,
The storage circuit has a data field and a control field accessible based on address information output from the control circuit,
The control circuit enables random access to the data field and the control field based on address information supplied from the interface control circuit in the first operation mode, and the control read together with the data field in the second operation mode. A semiconductor device capable of performing a logic operation by repeating an operation of feedback-inputting control information from a field and sequentially updating a read address of a data field and a control field according to the input control information.   The semiconductor device according to claim 1, wherein the second operation mode is designated by activation of a predetermined external event signal for the interface control circuit.   The interface control circuit designates the corresponding function reconfigurable cell using the higher-order side information of the address signal, and the control circuit of the function reconfigurable cell designated by this designates the lower order of the address signal in the first mode. The corresponding data field and control field are specified using the side information, and in the second mode, the read address update for the data field and the control field is sequentially progressed according to the feedback input control information, the initial value of the read address is restored, or the read address The semiconductor device according to claim 2, wherein stop of update is controlled.   4. The semiconductor device according to claim 3, wherein the interface control circuit outputs an interrupt signal when the read address update is stopped.   The plurality of function reconfigurable cells are configured to use a first bus used for random access of the data field and the control field of the function reconfigurable cell designated by using higher-order information of an address signal, and higher-order information of an address signal. 4. The semiconductor device according to claim 3, wherein the semiconductor device is commonly connected to a second bus used for the logic operation of the designated function reconfigurable cell. A buffer register mapped to an address different from the memory circuit and connected to the second bus;
6. The semiconductor device according to claim 5, wherein the interface control circuit controls an output operation of the buffer register in response to an access request.   The function reconfigurable cell further includes a connection path selection circuit that variably selects a path for transmitting information read from the data field and the control field to another function reconfigurable cell or the second bus. 5. The semiconductor device according to 5.   The semiconductor device according to claim 7, wherein the connection path selection circuit includes a switch circuit that selects the path, and a connection storage circuit that retains rewritable switch control information that determines a switch state of the switch circuit. A semiconductor device comprising a logic circuit that can be an access request subject and a function reconfigurable memory that operates in response to an access request from the logic circuit,
The function reconfigurable memory includes a plurality of function reconfigurable cells having a storage circuit and a control circuit, and an interface control circuit that controls the function reconfigurable cells in response to an access request from the logic circuit,
The storage circuit has a data field and a control field accessible based on address information output from the control circuit,
The control circuit enables random access to the data field and the control field based on address information supplied from the interface control circuit in the first operation mode, and the control read together with the data field in the second operation mode. A semiconductor device capable of performing a logic operation by repeatedly performing an operation of feedback-inputting control information from a field and sequentially updating a read address of a data field and a control field according to the input control information.   The logic circuit makes a read access request to the first address range for designating the first operation mode, thereby randomly setting the memory circuit of the function reconfigurable cell to which an address related to the access request is assigned. 10. The semiconductor device according to claim 9, wherein the semiconductor device is accessed to write information for realizing a predetermined logic function in a memory circuit of the function reconfigurable cell.   The logic circuit performs a write access request for the second address range for designating the second operation mode, thereby causing the function reconfigurable cell of an address related to the access request to start the logic operation. 10. The semiconductor device according to 10. A buffer register holding information output from the function reconfigurable cell by the logic operation and mapped to a third address range;
12. The semiconductor device according to claim 11, wherein the logic circuit makes a read access request for the third address range and reads a result of the logic operation from the buffer register.   The interface control circuit designates the corresponding function reconfigurable cell using the higher-order side information of the address signal, and the control circuit of the function reconfigurable cell designated by this designates the lower order of the address signal in the first mode. The corresponding data field and control field are specified using the side information, and in the second mode, the read address update for the data field and the control field is sequentially progressed according to the feedback input control information, the initial value of the read address is restored, or the read address The semiconductor device according to claim 9, wherein the stop of update is controlled.   14. The semiconductor device according to claim 13, wherein the interface control circuit outputs an interrupt signal when the read address update is stopped.

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