JP2008269222A - On-board information terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform processing to arbitrate an access right to an HDD storing map data and music data by hardware. <P>SOLUTION: A main CPU 10A and a sub CPU 10B exchange data and commands between the HDDs 50 to execute navigation processing and music reproduction and other processing. Each CPU outputs an ATAPI use request level signal depending on the processing content. An arbitration control table in a switch control circuit 25 of an arbitration circuit 20 is set and registered according to the ATAPI use request level signal. A switch circuit 24 is switched according to the arbitration control table to set a bus right. The bus right is thus arbitrated between the main CPU 10A and sub CPU 10B, and the HDDs 50. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to bus arbitration for a plurality of processors accessing a storage medium such as a hard disk.

  A vehicle-mounted navigation device having a navigation function for guiding a vehicle to a destination and a function for reproducing and outputting music data ripped from a music CD to a hard disk (HDD) is known (Non-patent Document 1).

Fujitsu Ten Technical Bulletin Vol.22 No.1 Pages 3-11

  In the device of Non-Patent Document 1, music data ripped from a music CD is stored together with map data and point data necessary for navigation on one hard disk. In this apparatus, navigation processing is performed by a navigation CPU (main CPU), music data is reproduced by a music CPU (sub CPU), and ripping processing for encoding music data and storing it in an HDD is performed.

  When a request for music processing is input while the navigation CPU is executing navigation processing, the ATA arbitration unit connects one of the CPUs to the hard disk by software processing. Conventional ATA arbitration is realized by software processing, and every time the main CPU and sub CPU access the HDD, it is necessary to execute ATA arbitration processing by software, which complicates the system.

(1) An in-vehicle information terminal according to the invention of claim 1 performs a first process by exchanging data between a storage medium for storing data and the storage medium, and performs a first process according to the processing contents of the first process. 1st processor which outputs 1 request signal, and 2nd processor which performs 2nd process by exchanging data between storage media, and outputs the 2nd request signal according to the processing contents of the 2nd process And a hardware arbitration circuit that receives the first and second request signals and arbitrates access to the storage medium of the first and second processors in response thereto.
(2) According to a second aspect of the present invention, in the in-vehicle information terminal according to the first aspect, the hardware arbitration circuit includes: a switching circuit that connects one of the first and second processors to the storage medium; And a switching control circuit that switches the switching circuit according to the level of the second request signal.
(3) According to the invention of claim 3, in the in-vehicle information terminal according to claim 1 or 2, the processor whose connection with the storage medium is interrupted by the arbitration circuit continues data processing, and continues data processing. A temporary storage circuit that temporarily stores data obtained by the processing is further provided, and the processor whose connection with the storage medium is resumed by the arbitration circuit transfers the data stored in the temporary storage circuit to the storage medium. And
(4) According to the invention of claim 4, in the in-vehicle information terminal according to claim 3, the arbitration circuit stores the processor whose connection with the storage medium is interrupted when the storage capacity of the temporary storage circuit exceeds a predetermined value. The data processing by the processor is resumed by connecting to the means.
(5) The invention of claim 5 is the in-vehicle information terminal according to any one of claims 1 to 4, wherein the first data processing is data processing using map data, and the second data processing is It is characterized by data processing using AV data such as music data and video data.
(6) The invention of claim 6 is the in-vehicle information terminal according to any one of claims 1 to 5, wherein data exchange between the first and second processors and the storage medium is via an arbitration circuit. It is characterized in that it is performed by an ATAPI compliant interface.

  According to the present invention, the bus arbitration is performed by the hardware circuit based on the request signal output from the first and second processors according to the processing contents. As a result, the arbitration circuit is simplified compared to the case where the bus arbitration is performed by software.

-First embodiment-
A configuration of a first embodiment in which an in-vehicle information terminal according to the present invention is applied to a navigation device is shown in FIG. 1 has music and video playback functions in addition to normal navigation functions such as map display and route guidance. In this embodiment, a description will be given on the assumption that the navigation apparatus has a music playback function, a music ripping function, a digital terrestrial broadcast viewing and recording function.

  The navigation apparatus includes a navigation main CPU (processor) 10A, a music / video playback sub CPU (processor) 10B, and a control circuit 10 having an arbitration circuit 20 composed of an FPGA or the like as a main part. The control circuit 10 includes a hard disk drive (HDD) 50, a DVD drive 60 that reads music data and video data from a loaded CD or DVD, a position detection device 71 that detects the current position of the host vehicle, and digital terrestrial Broadcast receiving circuit 72, display monitor 73 for displaying a map or terrestrial digital broadcast video, speaker 74 for outputting route guidance audio or receiving received digital terrestrial broadcast audio, and various input devices 75 And are connected.

  The main CPU 10A of the control circuit 10 temporarily stores a flash memory 11 in which a program or the like is written, an ASIC 12 that performs arithmetic processing when a display image such as a map is drawn, and various data used in the arithmetic processing of the main CPU 10A. The DRAM 13 is connected by a bus. The sub CPU 10B of the control circuit 10 temporarily stores a flash memory 14 in which a program or the like is written, a DSP 15 that reproduces or rips music data acquired from a music CD, and various data obtained by the DSP 15 signal processing. The DRAM 16 is connected to the DRAM 17 that temporarily stores various data used in the arithmetic processing of the sub CPU 10B. Connected to the arbitration circuit 20 are DRAMs 41 and 42 for storing data interrupted during ATAPI processing, which will be described later.

  The HDD 50 is a high-speed and large-capacity storage medium and a reading device that read / write map data and music data stored in a built-in magnetic hard disk. The music data in the HDD 50 is music data encoded by the ripping process. The DVD drive 60 is a reading device that reads music data stored on a set music CD or video data stored on a video DVD. The music CD and the video DVD are low-speed and small-capacity storage media compared to the HDD 50.

  The hard disk drive (HDD) 50 and the DVD drive 60 exchange commands or data with the main CPUs 10A and 10B using an IDE (Integrated Drive Electronics) interface compliant with ATAPI (AT Attachment Packet Interface). The arbitration circuit 20 arbitrates the bus right (access right) for the HDD 50 and the DVD driver 60 of the main CPUs 10A and 10B.

  The main CPU 10A executes various navigation processes by executing a control program stored in the flash memory 11. The DRAM 13 temporarily stores data and calculation data used in navigation processing. The main CPU 10 </ b> A inputs the current position of the vehicle detected by the position detection device 71, and displays a map around the vehicle position on the display monitor 73 based on the map data in the HDD 50. Alternatively, the route from the vehicle position to the destination is searched, and route guidance for guiding the passenger along the recommended route is performed.

  The sub CPU 10B executes a control program stored in the flash memory 14 to perform music playback processing, video playback processing, and the like. The sub CPU 10 </ b> B reproduces the music data stored in the music CD set in the DVD drive 60 on the DSP 15 and outputs it from the speaker 74. Under the control of the sub CPU 10B, the DSP 15 rips the music data read from the DVD drive 60, and the sub CPU 10B stores the music data encoded by the rip processing in the HDD 50.

  The sub CPU 10 </ b> B displays the terrestrial digital broadcast video received by the terrestrial digital broadcast reception circuit 72 on the display monitor 73 and outputs the sound from the speaker 74, thereby performing so-called terrestrial digital broadcast viewing processing. Processing for recording digital terrestrial broadcasting is also performed by the sub CPU 10B. In this case, the received video is temporarily stored in the DRAM 17 and stored in the HDD 50 at a predetermined timing. The DRAM 17 also temporarily stores data and arithmetic data used in music data and video data processing (entertainment processing).

  As shown in detail in FIG. 2, the arbitration circuit 20 includes a Host I / F 21, Device I / Fs 22 and 23, a switching circuit 24 called ARBITER, and a switching control circuit (arbitration control circuit called REGISTER) that controls the switching circuit 24. ) 25 and a programmable gate array circuit.

  The Host I / F 21 is connected to the HDD 50 and the DVD drive 60, the Device I / F 22 is connected to the main CPU 10A, and the Device I / F 23 is connected to the sub CPU 10B. The main CPU 10 </ b> A and the sub CPU 10 </ b> B transmit ATAPI use request levels corresponding to the respective processes to the switching control circuit 25. On the other hand, via the switching control circuit 25, the main CPU 10A receives the ATAPI use request level of the sub CPU 10B, and the sub CPU 10B receives the ATAPI use request level of the main CPU 10A.

  Therefore, the main CPU 10A communicates with the switching control circuit 25 by two ATAPI use request level signals GPIO (general purpose input output) 1-1, 2 of the main CPU 10A and two ATAPI use request level signals GPIO2 of the sub CPU 10B. A total of four request signals of −1 and 2 are input / output. The sub CPU 10B, with respect to the switching control circuit 25, has four requests in total: two ATAPI use request level signals GPIO2-1 and 2 of the sub CPU 10B and two ATAPI use request level signals GPIO1-1 and 2 of the main CPU 10A. Input and output signals.

The following four levels 0, 1, 2, and 3 are defined by the two ATAPI use request level signals GPIO1-1 and 2 of the main CPU 10A.
(A) ATAPI use request level 0 (00) of main CPU 10A: main CPU 10A not used (b) ATAPI use request level 1 (01) of main CPU 10A: route search processing (c) ATAPI use request level 2 (10) of main CPU 10A ): Map scroll process (d) ATAPI use request level 3 (11) of main CPU 10A: Map data read process

The following four levels 0, 1, 2, 3 are defined by the two ATAPI use request level signals GPIO2-1, 2 of the sub CPU 10B.
(A) Sub-CPU 10B ATAPI use request level 0 (00): Sub CPU 10B not used (b) Sub CPU 10B ATAPI use request level 1 (01): Ripping process (c) Sub CPU 10B ATAPI use request level 2 (10) : CD / DVD data reading process (d) Sub-CPU 10B ATAPI use request level 3 (11): Terrestrial digital broadcast recording process

  Each ATAPI use request level is represented by signal levels of ATAPI use request level signals GPIO1-1, 2 and GPIO2-1, 2 as shown in parentheses. Further, in the main CPU 10A and the sub CPU 10B, level 3 is a process that is more urgent than level 2, level 2 is a process that is more urgent than level 1, and level 1 is a process that is more urgent than level 0.

  The two ATAPI use request level signals GPIO1-1, 2 of the main CPU 10A and the two ATAPI use request level signals GPIO2-1, 2 of the sub CPU 10B are input to the switching control circuit 25 of the arbitration circuit 20 to set the arbitration control table. To do. The switching circuit 24 is switched by the arbitration control table based on these four use request level signals, and the bus right is controlled. FIG. 3 is a diagram for explaining the bus right of each CPU in accordance with the two ATAPI use request level signals GPIO1-1, 2 of the main CPU 10A and the two ATAPI use request level signals GPIO2-1, 2 of the sub CPU 10B. . FIG. 3 shows a case where the main CPU 10A is defined to have a bus right in preference to the sub CPU 10B.

An example will be described with reference to FIG.
(1) When the request level of the main CPU 10A is 0 (00) If the request level of the sub CPU 10B is 0, the bus right is given to the main CPU 10A, and if the request level of the sub CPU 10B is 1 to 3, the bus right is the sub CPU 10B. Given to.
(2) When the request level of the main CPU 10A is 1 (01) If the request level of the sub CPU 10B is 0 or 1, the bus right is given to the main CPU 10A, and if the request level of the sub CPU 10B is 2 or 3, the bus right is It is given to the sub CPU 10B.

(3) When the request level of the main CPU 10A is 2 (10) If the request level of the sub CPU 10B is 0-2, the bus right is given to the main CPU 10A, and if the request level of the sub CPU 10B is 3, the bus right is sub It is given to the CPU 10B.
(4) When the request level of the main CPU 10A is 3 (11) The bus right is given to the main CPU 10A regardless of the request level of the sub CPU 10B.

FIG. 4 is a flowchart for explaining the entire processing by the control circuit 10.
In step S1, an initial setting process is performed. In the initial setting process, the ATAPI use request level of the main CPU 10A and the sub CPU 10B is set to 0 (00), and the bus right is given to the main CPU 10A. That is, the arbitration control table is rewritten as indicated by reference numeral 3a in FIG. The switching circuit 24 refers to the initially set arbitration control table and switches the bus arbitration to connect the main CPU 10A and the HDD 50. Further, both the main CPU 10A and the sub CPU 10B are set in a ready state in which data transfer by ATAPI processing is possible. As will be described later, when the main CPU 10A and the sub CPU 10B are set to the busy state, data transfer by the ATAPI process is prohibited.

  Here, the data transfer by ATAPI processing is data transfer performed by the main CPU 10A and the sub CPU 10B under the control of the arbitration of the arbitration circuit 20. Therefore, even if the main CPU 10A and the sub CPU 10B are set in the busy state, data transfer performed between the main CPU 10A and the sub CPU 10B and the DRAMs 41 and 42 is not prohibited.

  Note that the main CPU 10A and the sub CPU 10B can always rewrite the arbitration control table in response to a user's ATAPI usage request by a processing procedure (not shown). The ATAPI use request is a use request based on an operation on a navigation device such as a map scroll operation by a user.

  In step S2, input of an ATAPI use request is awaited. If there is a request, the process proceeds to step S3, and it is determined whether or not the request level of the main CPU 10A is equal to or higher than the request level of the sub CPU 10B. If the request level of the main CPU 10A is equal to or higher than the request level of the sub CPU 10B, step S3 is affirmed, and the sub CPU 10B is set in a busy state in step S3A, and the process proceeds to step S4. In step S <b> 4, the main CPU 10 </ b> A to which the bus right is given starts sending / receiving various data to / from the HDD 50.

  When step S3 is affirmed, the arbitration control table is rewritten based on the ATAPI use request level signal by a procedure not shown, but the arbitration control table maintains the initial setting state in step S1.

  In step S5, it is determined whether or not there is a new ATAPI use request. If there is no new request, the process proceeds to step S6. In step S6, it is determined whether or not the data transfer to the HDD 50 by the main CPU 10A has been completed. If step S6 is negative, the process returns to step S4 to continue data transfer. When the data transfer is completed and step S6 is affirmed, the process proceeds to step S6A, and the sub CPU 10B is set in a ready state. In step S7, it is determined whether or not there is a use request for the sub CPU 10B. If there is no use request from the sub CPU 10B, the process returns to step S2, and if there is a use request from the sub CPU 10B, the process proceeds from step S7 to step S13.

  If it is determined in step S5 that there is a new ATAPI use request, the process proceeds to step S8, and it is determined whether or not the request level of the main CPU 10A is equal to or higher than the request level of the sub CPU 10B. If step S8 is positive, the process proceeds to step S6. If it is determined in step S5 that the new ATAPI use request is a request from the sub CPU 10B and the request level of the sub CPU 10B exceeds the request level of the main CPU 10A, step S8 is denied and the process proceeds to step S9. In step S9, a process for interrupting the data transfer of the main CPU 10A is performed, and the process proceeds to step S10 through step S10A. If step S8 is negative, the arbitration control table rewriting process based on the ATAPI use request level signal is performed by a procedure not shown, and the bus right is switched to the sub-sub CPU 10B. However, the sub sub CPU 10B is still busy and data transfer is not started.

  In step S10A, the main CPU 10A is set in a busy state and the sub CPU 10B is set in a ready state. Thereby, in step S10, data transfer is started between the sub CPU 10B and the HDD 50. On the other hand, the main CPU 10 </ b> A that has handed over the bus right continues the ATAPI process, and temporarily stores the transfer data to the HDD 50 in the DRAM 41.

  When the data transfer from the sub CPU 10B is completed in step S11, the process proceeds to step S12 through step S11A. In step S11A, when the main CPU 10A is set to the ready state and the sub CPU 10B is set to the busy state, the arbitration control table is rewritten in step S12, and the bus right is switched to the main CPU 10A. Thereby, the interrupted data transfer of the main CPU 10A is resumed. That is, data temporarily stored in the DRAM 41 is transferred to the HDD 50. Thereafter, the process proceeds to step S4.

  If it is determined in step S3 that the required level of the sub CPU 10B is equal to or higher than the required level of the main CPU 10A, the process proceeds to step S3B, and the main CPU 10A is set to the busy state. If step S3 is negative, the arbitration control table rewriting process based on the ATAPI use request level signal is performed by a procedure not shown, and the bus right is switched to the sub-sub CPU 10B. In step S13, the sub-sub CPU 10B starts data transfer and starts exchange of various data with the HDD 50.

  In step S14, it is determined whether or not there is a new ATAPI use request. If there is no new request, the process proceeds to step S15. In step S15, it is determined whether or not the data transfer from the sub CPU 10B to the HDD 50 has been completed. If step S15 is negative, the process returns to step S13. When the data transfer is completed and step S15 is affirmed, the process proceeds to step S16 through step S15A. In step S15A, the main CPU 10A is set in a ready state. In step S16, it is determined whether there is a request for using the ATAPI of the main CPU 10A. If there is no ATAPI use request from the main CPU 10A, the process returns to step S2, and if there is an ATAPI use request from the main CPU 10A, the process returns from step S16 to step S4.

  If it is determined in step S14 that there is a new ATAPI use request, the process proceeds to step S17, and it is determined whether or not the request level of the main CPU 10A is equal to or higher than the request level of the sub CPU 10B. If step S17 is negative, the process proceeds to step S15. If step S17 is positive, the process proceeds to step S18, and the data transfer of the sub CPU 10B is interrupted. Thereafter, the process proceeds to step S19 through step S18A. In step S18A, the main CPU 10A is set in a ready state, and the sub CPU 10B is set in a busy state. In step S19, the arbitration control table is rewritten to switch the bus right to the main CPU 10A. Thereby, data transfer from the main CPU 10A to the HDD 50 starts.

  On the other hand, the sub CPU 10B that has handed over the bus right continues the ATAPI process and temporarily stores the transfer data to the HDD 50 in the DRAM 42. When the data transfer from the main CPU 10A is completed in step S20, the process proceeds to step S21 through step S20A. In step S20A, the main CPU 10A is set in a ready state, and the sub CPU 10B is set in a busy state. In step S21, the arbitration control table is rewritten, and the bus right is switched to the sub-sub CPU 10B. Thereby, the data transfer of the suspended sub CPU 10B is resumed. That is, data temporarily stored in the DRAM 42 is transferred to the HDD 50. Thereafter, the process proceeds to step 13.

The operation of the navigation device according to the above embodiment will be described by taking as an example the case where a map scroll request is generated during digital terrestrial broadcast recording.
During recording of terrestrial digital broadcasting under the control of the sub CPU 10B, the recorded data is transferred to the HDD 50 (step S13). When the main CPU 10A accepts the map data reading process by the user's operation, the ATAPI use request level of the main CPU 10A becomes level 3 equal to the ATAPI use request level of the sub CPU 10B, and the arbitration circuit 20 transfers the bus right to the main CPU 10A. The data transfer of the sub CPU 10B is interrupted (step S18). At this time, even after the bus right is passed, the CPU 10B continues the recording process and temporarily stores the recorded video data in the DRAM 42. After obtaining the bus right, the sub CPU 10B transfers the recorded data of the DRAM 42 to the HDD 50 (step S21).

  By such ATAPI arbitration processing, inconvenience such as recording data being interrupted can be solved.

According to the navigation device according to the first embodiment described above, the following operational effects can be obtained.
(1) The main CPU 10A and the sub CPU 10B set the ATAPI use request signals GPIO1-1, 2 and GPIO2-1, 2 in accordance with their processing contents. The arbitration control table is registered in the switching control circuit 25 by the ATAPI use request signals GPIO1-1, 2 and GPIO2-1, 2. The switching circuit 24 gives the bus right to the main CPU 10A or the sub CPU 10B according to the registered arbitration control table. It switches as follows. Therefore, in the arbitration circuit 20, ATA arbitration by software processing as described in the prior art becomes unnecessary each time the main CPU and sub CPU access the HDD. As a result, the system related to the ATA arbitration process is simplified.

(2) When one CPU delivers the bus right to the other CPU during execution of ATAPI processing, the main CPU 10A or the sub CPU 10B that has given the bus right during ATAPI processing interrupts only the data transfer and continues the subsequent data processing. The transfer data is temporarily stored in the DRAM 41 or 42. Therefore, there is no inconvenience that transfer of necessary data to the HDD 50 is interrupted.

  In the navigation device of the first embodiment, when an ATAPI use request having a high priority is generated in the other CPU regardless of the ATAPI use request level, the data transfer by the ATAPI process being executed is interrupted, and the interrupted transfer data Is temporarily stored in the DRAM 41 or 42. Such processing may be performed only for a predetermined level or higher, and for a level less than a predetermined value, not only data transfer but also ATAPI processing itself may be interrupted. An example of performing such processing will be described as a second embodiment.

-Second Embodiment-

  FIG. 5 shows the configuration of a navigation device that is a second embodiment of the in-vehicle information terminal of the present invention. Differences from the navigation device of the first embodiment will be mainly described. As shown in FIG. 5, the DRAM 42 is connected to the Device I / F 23 of the sub CPU 10B, but the DRAM 41 is not connected to the Device I / F 22 of the main CPU 10A. This configuration is the main difference.

  In the navigation device according to the first embodiment, the main CPU 10A and the sub CPU 10B are compared with the ATAPI use request level, and the bus right is given to the CPU having a high request level. This point is the same in the second embodiment, and detailed description thereof is omitted. In the navigation device of the second embodiment, when a processing request of ATAPI usage request level 3 is generated in the main CPU 10A while the sub CPU 10B is executing processing of ATAPI usage request level 3, only data transfer by ATAPI processing of the sub CPU 10B is performed. And the process itself continues. Then, data that needs to be recorded in the HDD 50 is temporarily stored in the DRAM 42 connected to the Device I / F 23. The sub CPU 10B that has transferred the bus right transfers the data temporarily stored in the DRAM 42 to the HDD 50 after acquiring the bus right.

  The reason why the DRAM 41 of the main CPU 10A is omitted in the navigation device of the second embodiment is as follows. In the navigation device according to the second embodiment, when the sub CPU 10B generates an ATAPI use request level 3 processing request to the main CPU 10A while the sub CPU 10B executes the ATAPI use request level 3 processing as described above, the sub CPU 10B has the bus right. , But data processing continues. Therefore, the DRAM 42 is necessary to temporarily store the transfer data obtained by the sub CPU 10B. However, each CPU that has given the bus right under conditions other than those described above also ends the data processing itself. That is, the main CPU 10A does not continue data processing after handing over the bus right. Therefore, the DRAM 41 of the main CPU 10A is not necessary.

  According to the navigation apparatus according to the second embodiment as described above, when the bus right is handed over and the transfer to the HDD 50 is stopped during the execution of the ATAPI process, the use request level 3 is likely to cause trouble especially when data is interrupted. The transfer data is temporarily saved only in the case, and the transfer of the temporarily saved data is resumed when the bus right is handed over again. Therefore, processing such as temporary storage of transfer data and resumption of data transfer are not executed unnecessarily, and the system configuration can be simplified.

The navigation device of the second embodiment may be modified as follows. The system configuration in this case is the same as that of the navigation apparatus shown in FIG.
In the navigation device of the second embodiment, the sub CPU 10B that has handed over the bus right to the main CPU 10A continues the ATAPI process and temporarily stores data to be transferred in the DRAM 42. However, when the data storage capacity of the DRAM A 42 reaches, for example, 80% of the maximum storage capacity, the switching control circuit 25 may be interrupted from the DRAM 42 and the bus right may be handed over to the sub CPU 10B. That is, the switching control circuit 25 immediately ends the ATAPI process of the main CPU 10A currently being executed by interruption, and transfers the bus right to the sub CPU 10B. The main CPU 10A that has handed over the bus right continues processing, and temporarily stores data that needs to be stored in the HDD 50 in the DRAM 41. When the data storage capacity of the DRAM 10B of the sub CPU 10B decreases to, for example, 30%, the bus right is transferred to the main CPU 10A, and the data to be transferred temporarily stored in the DRAM 41 is transferred to the HDD 50.

  Note that the threshold of the data storage capacity that the DRAM 42 interrupts may be determined in consideration of the maximum access time to the HDD 50 of the main CPU 10A. That is, the threshold value of the data storage capacity may be determined according to the access time to the HDD 50 of the main CPU 10A after the bus right is handed over.

According to such a modification, the following effects can be obtained.
For example, after the bus right is handed over to the main CPU 10A, when the storage capacity of the DRAM 42 reaches 80% while the sub CPU 10B is recording digital terrestrial broadcasting, the bus right is transferred to the sub CPU 10B, and the recorded data of the DRAM 42 is transferred to the HDD 50. Forward. Thereby, the capacity of the DRAM 42 can be used effectively, and the recorded video can be prevented from being interrupted.

The following modifications are also within the scope of the present invention.
(1) Although the in-vehicle information terminal has been described as a navigation device, it is not limited to a navigation device. In other words, the first and second processors, each executing different data processing, can be used for any in-vehicle information terminal that uses the same storage medium in common. For example, the present invention can be suitably used when the main processor is used for a so-called drive recorder and the sub-processor handles entertainment data such as music and video.
(2) Although the data transfer between the CPU and the HDD has been described, the same applies to the data transfer with other storage media such as a DVD. Further, the number of CPUs is not limited to two.
(3) The interface is not limited to ATAPI as long as the bus arbitration is required.

  As long as the characteristics of the present invention are not impaired, the present invention is not limited to the above-described embodiments, and other forms conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention. .

In addition, the correspondence between each component of the navigation device in the embodiment described above and each component of the claims is as follows.
The main CPU 10A constitutes a first processor, the sub CPU 10B constitutes a second processor, the HDD 50 constitutes a storage medium, the FPGA arbitration circuit 20 constitutes a hardware arbitration circuit, and the DRAMs 41 and 42 constitute temporary storage circuits. Note that the above description of the correspondence relationship is merely an example, and is not constrained when interpreting rights.

The block diagram which shows the structure of the navigation apparatus in 1st Embodiment. Block diagram showing details of the arbitration circuit of FIG. The figure which shows the arbitration control table in 1st Embodiment The flowchart explaining the process of the navigation apparatus in 1st Embodiment The block diagram which shows the structure of the navigation apparatus in 2nd Embodiment.

Explanation of symbols

10: Control circuit 10A: Main CPU
10B: Sub CPU 20: Arbitration circuit
21: Host I / F 22, 23: Device I / F
24: switching circuit 25: switching control circuit 41, 42: DRAM 50: HDD
60: DVD drive 72: Digital terrestrial broadcast receiving circuit

Claims (6)

A storage medium for storing data;
A first processor that exchanges data with the storage medium to perform a first process and outputs a first request signal corresponding to the processing content of the first process;
A second processor for performing a second process by exchanging data with the storage medium and outputting a second request signal according to the processing content of the second process;
A vehicle-mounted information terminal comprising: a hardware arbitration circuit that receives the first and second request signals and arbitrates access to the storage medium of the first and second processors according to the first and second request signals. . The in-vehicle information terminal according to claim 1,
The hardware arbitration circuit is
A switching circuit for connecting one of the first and second processors to the storage medium;
An in-vehicle information terminal comprising: a switching control circuit that switches the switching circuit according to the levels of the first and second request signals. In the in-vehicle information terminal according to claim 1 or 2,
The processor whose connection with the storage medium is interrupted by the arbitration circuit continues to process data,
A temporary storage circuit for temporarily storing data obtained by the data processing to be continued;
The in-vehicle information terminal, wherein the processor whose connection with the storage medium is resumed by the arbitration circuit transfers the data stored in the temporary storage circuit to the storage medium. The in-vehicle information terminal according to claim 3,
When the storage capacity of the temporary storage circuit exceeds a predetermined value, the arbitration circuit connects a processor that has been disconnected from the storage medium to the storage unit, and resumes data processing by the processor. In-vehicle information terminal. The in-vehicle information terminal according to any one of claims 1 to 4,
The in-vehicle information terminal characterized in that the first data processing is data processing using map data, and the second data processing is data processing using AV data such as music data and video data. The in-vehicle information terminal according to any one of claims 1 to 5,
An in-vehicle information terminal characterized in that data exchange between the first and second processors and the storage medium is performed by an ATAPI-compliant interface via the arbitration circuit.

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