JP2008251108A - Information recording and reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile information recording device of low power consumption and high thermal stability. <P>SOLUTION: The information recording and reproducing device includes a recording layer containing a first compound: the compound has a pyrochlore structure represented by Al<SB>a</SB>M1<SB>2</SB>X1<SB>x</SB>(0.5≤a≤2, 6≤x<7), where A1 and M1 are elements different from each other, at least one of A1 and M1 is a transition element, and X1 contains at least one selected from (oxygen), F (fluorine), N (nitrogen), and S (sulfur), and a voltage application part for applying a voltage to the recording layer to cause a phase change in the recording layer, thereby recording information. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information recording / reproducing apparatus, and more particularly to a nonvolatile information recording / reproducing apparatus.

  In recent years, small portable devices have spread worldwide, and at the same time, with the rapid progress of high-speed information transmission networks, the demand for small and large-capacity nonvolatile memories has been rapidly expanding. Among them, the NAND flash memory and the small HDD (hard disk drive), in particular, have rapidly evolved in recording density and formed a large market.

  On the other hand, several new memory ideas aiming to greatly exceed the limit of recording density have been proposed. For example, ternary oxides containing transition metal elements such as perovskite (for example, see Patent Documents 1 and 2), binary oxides of transition metals (for example, see Patent Document 3), and the like have been studied. Yes. When these materials are used, a high resistance state (off) and a low resistance state (on) can be repeatedly changed by applying a voltage pulse, and these two states are represented by binary data “0”, “1”. The principle that data is recorded in correspondence with "is adopted.

  For writing / erasing, for example, there are three ways to apply reverse pulses when changing from a low resistance state phase to a high resistance state phase and when changing from a high resistance state phase to a low resistance state phase. Used in system oxides. On the other hand, in binary oxides, writing / erasing may be performed by applying pulses having different pulse amplitudes and pulse widths.

Reading is performed by passing a small read current that does not cause writing / erasing to the recording material and measuring the electrical resistance of the recording material. In general, the ratio of the resistance in the high resistance state phase to the resistance in the low resistance state phase is about 10 ³ .

  The greatest feature of these materials is that they can be operated in principle even if the element size is reduced to about 10 nm. In this case, a recording density of about 10 Tbpsi (tera bite par square inch) can be realized. One of the candidates for higher recording density.

  As an operation mechanism of such a new memory, there are the following proposals. For perovskite materials, diffusion of oxygen vacancies, charge accumulation at interface states, and the like have been proposed. On the other hand, the binary oxide includes oxygen ion diffusion and Mott transition. Although it is difficult to say that the details of the mechanism have been clarified, the same resistance change has been observed in various material systems, and therefore, it has been attracting attention as one candidate for increasing the recording density.

  In addition to these, a MEMS memory using MEMS (micro electro mechanical systems) technology has been proposed. The greatest feature of such a MEMS memory is that the recording density can be drastically improved because it is not necessary to provide a wiring in each recording section for recording bit data. Various recording media and recording principles have been proposed, and attempts have been made to achieve great improvements in terms of power consumption, recording density, operating speed, etc. by combining MEMS technology and new recording principles.

However, a new information recording medium using such a new recording material has not been realized. One of the reasons is pointed out that the power consumption is large and the thermal stability of each resistance state is low (see, for example, Non-Patent Document 1).
The pyrochlore structure is described in Non-Patent Document 2, for example.
JP-A-2005-317787 JP 2006-80259 A JP 2006-140464 A S. Seo et al., Applied Physics Letters, vol.85, pp5655-5657, (2004) H. Wiggers et al., Solid State Ionics vol.107, pp111-116 (1998)

  The present invention proposes a nonvolatile information recording / reproducing apparatus with low power consumption and high thermal stability.

According to one embodiment of the present invention, a pyrochlore structure represented by A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 2, 6 ≦ x <7), wherein A1 and M1 are different elements from each other. And at least one of the A1 and the M1 is a transition element having d orbital incompletely filled with electrons, and the X1 includes O (oxygen), F (fluorine), N (nitrogen), and S ( A recording layer having a first compound containing at least one selected from the group consisting of sulfur), and a voltage application unit for recording information by applying a voltage to the recording layer to cause a phase change in the recording layer An information recording / reproducing apparatus including the above is provided.

  According to the present invention, a nonvolatile information recording / reproducing apparatus with low power consumption and high thermal stability is provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a conceptual diagram for explaining the basic principle of information recording / reproduction in the information recording / reproducing apparatus according to the first embodiment of the present invention.
FIG. 1A is a cross-sectional view of the recording unit. This recording part has a structure in which both sides of a recording layer 12 containing a pyrochlore structure material are sandwiched between electrode layers 11 and 13A. That is, the recording layer 12 has a pyrochlore structure represented by A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 2, 6 ≦ x <7), and A1 and M1 are elements different from each other. At least one of M1 is a transition element having d orbital incompletely filled with electrons, and X1 is selected from the group consisting of O (oxygen), F (fluorine), N (nitrogen), and S (sulfur) A first compound comprising at least

  Note that the electrode 13A may have a role as a protective layer. In FIG. 1, large white circles represent X1 ions, small black circles represent M1 ions, and small white circles represent A1 ions. In the structure shown in FIG. 1A, since the diffusion path of A1 ions exists in a straight line, it is possible to select the atomic species so that the A1 ions can be easily diffused by an external electric field.

  When a voltage is applied to the recording layer 12 to generate a potential gradient in the recording layer 12, some of the A1 ions move in the crystal. Thus, in the present embodiment, the initial state of the recording layer 12 is an insulator (high resistance state phase), the recording layer 12 is phase-changed by a potential gradient, and the recording layer 12 is made conductive (low resistance state phase). To record information.

  First, for example, a state in which the potential of the electrode layer 13A is relatively lower than the potential of the electrode layer 11 is created. If the electrode layer 11 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the electrode layer 13A.

  At this time, some of the A1 ions in the recording layer 12 move to the electrode layer (cathode) 13A side, and the number of A1 ions in the recording layer (crystal) 12 decreases relative to the X1 ions. The A1 ions that have moved to the electrode layer 13A side receive electrons from the electrode layer 13A and precipitate as A1 atoms that are metal to form the metal layer 14. Therefore, in the region close to the electrode layer 13A, the A1 ions are reduced and behave like a metal, so that the electrical resistance is greatly reduced.

  Inside the recording layer 12, X1 ions become excessive, and as a result, the valence of A1 ions or M1 ions left in the recording layer 12 is increased. At this time, if the A1 ion or the M1 ion is selected so that the electric resistance is reduced when the valence is increased, the electric resistance is reduced by the movement of the A1 ion in both the metal layer 14 and the recording layer 12, so that the recording layer As a whole, the phase changes to the low resistance state phase. That is, information recording (set operation) is completed.

  Information reproduction can be easily performed by, for example, applying a voltage pulse to the recording layer 12 and detecting the resistance value of the recording layer 12. However, the amplitude of the voltage pulse needs to be a minute value that does not cause movement of A1 ions.

  The process described above is a kind of electrolysis, in which an oxidizing agent is generated by electrochemical oxidation on the electrode layer (anode) 11 side, and a reducing agent is generated by electrochemical reduction on the electrode layer (cathode) 13A side. Can be considered.

  Therefore, in order to return the low resistance state phase to the high resistance state phase, for example, the recording layer 12 may be Joule-heated with a large current pulse to promote the oxidation-reduction reaction of the recording layer 12. That is, due to Joule heat due to a large current pulse, A1 ions return into the thermally more stable crystal structure 12, and an initial high resistance state phase appears (reset operation).

  Alternatively, the reset operation can be performed by applying a voltage pulse in the opposite direction to that in the set operation. That is, if the electrode layer 11 is set to a fixed potential as in the setting, a positive potential may be applied to the electrode layer 13A. Then, A1 atoms in the vicinity of the electrode layer 13A give electrons to the electrode layer 13A to become A1 ions, and then return to the crystal structure 12 due to a potential gradient in the recording layer 12. As a result, some of the A1 ions whose valences have increased have their valences reduced to the same values as in the initial stage, so that they change to the initial high resistance state phase.

However, in order to put this operating principle into practical use, it must be confirmed that the reset operation does not occur at room temperature (a sufficiently long retention time is ensured) and that the power consumption of the reset operation is sufficiently small.
The former can be dealt with by controlling the ion radius. That is, in the pyrochlore structure, since the radius of the A1 ion is large, the movement of the A1 ion at room temperature and without a potential gradient can be prevented.

  Further, the latter can be dealt with by finding a movement path of A1 ions moving in the recording layer (crystal) 12 without causing crystal destruction. As described above, since the diffusion path of A1 ions is linear in the pyrochlore structure, the diffusion of A1 ions is likely to occur, which is suitable for use as such a recording layer 12.

Here, either the A1 ion or the M1 ion needs to change its valence with the diffusion of the A1 ion. In order to produce a valence change efficiently, either the A1 ion or the M1 ion needs to be a transition element having a d orbital incompletely filled with electrons.
In particular, when the A1 ion is a transition element having d orbital incompletely filled with electrons, the valence of the A1 ion remaining in the crystal structure 12 without being diffused after the A1 ion diffuses is determined. The neutral condition of the charge can also be satisfied by increasing. In particular, when the valence of the M1 ion cannot be increased any more, if all of the A1 ions diffuse, the neutral condition of the charge cannot be satisfied only by the M1 ions. Therefore, after a certain proportion of A1 ions diffuse, if further A1 ions try to diffuse, the Coulomb force prevents the diffusion. That is, the diffusion amount of A1 ions has an upper limit, and the valence change amount of A1 ions that contributes to lowering the resistance has an upper limit. Therefore, the resistance in the low resistance state becomes a relatively large value. When heat is applied to the recording layer to move the A1 ions back into the host structure as in the reset process described above, heat is more efficiently generated when the resistance in the low resistance state is larger, and power consumption is lower. This is preferable because it is possible to achieve the above.

In the pyrochlore structure, the ionic radius of A1 ions is relatively large, and diffusion of A1 ions does not easily occur efficiently in a crystal without void sites. Therefore, in order to use the pyrochlore structure as a recording film of such a resistance variable element, it is important that there are void sites in the crystal lattice as shown in FIG. Therefore, in the present embodiment, as the recording layer, a material having a gap at least at the X1 site is used as shown in Chemical Formula 1: A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 2, 6 ≦ x <7). . In order for the diffusion of A1 ions to occur easily, it is more desirable that 6 ≦ x ≦ 6.5.

As a material having a pyrochlore structure, a film using O (oxygen) as X1 can be most easily formed, so it is desirable to use O as X1.
Furthermore, in order to produce a pyrochlore structure with voids at such an X1 site, as A1, 1A group, 2A group, rare earth, Ln (lanthanoid), 4A group, 1B group, 2B group, Al, Ga, In, Using at least one element selected from the group of Tl, Sn, Pb, Bi, and at least one element selected from the group of 4A group, 5A group, 6A group, 7A group, 8 group, Sn, Sb as M1 It is desirable to use these elements.

  Furthermore, in order to easily produce a pyrochlore structure, A1 is Rb, Cs, Ca, Sr, Ba, rare earth, Ln (lanthanoid), Zr, Ag, Au, Cd, Hg, Tl, Sn, Pb, Bi. It is more desirable to include at least one element selected from these groups. On the other hand, M1 contains at least one element selected from the group of Ti, Zr, Hf, V, Nb, Ta, Mo, W, Mn, Tc, Re, Ru, Os, Sn, and Sb. desirable.

Further, when the radius of A1 ions is large, if the valence of A1 ions is monovalent, diffusion of A1 ions occurs easily when a voltage is applied, but if no voltage is applied, A1 ions are diffused. This is desirable in terms of stability of each resistance state. For this purpose, A1 is more preferably Rb, Cs, Ag, Au, Hg, and Tl.
In this case, M1 preferably contains at least one element selected from the group of V, Nb, Ta, Mo, W, Mn, Ru, Os, and Sb, which can be pentavalent ions.

  If the A1 ion is monovalent, the valence of the M1 ion is about five in order to satisfy the neutral condition of the charge. Thus, when the valence of the M1 ion is large, a large Coulomb repulsive force acts on the deviation of the M1 ion from the crystal lattice, and the M1 ion tends to exist stably without changing its position. Furthermore, when Nb, Ta, Mo, W, Ru, Os, and Sb are used as M1 ions, the mass is large, so that the movement of M1 ions is hardly caused. Therefore, when M1 ions composed of these elements are used, the position of the M1 ions is thermally stable, and as a result, the crystal structure is not easily broken. For this reason, the diffusion path of A1 ions is thermally stable.

  In addition, in order for the intercalation / deintercalation of X ions as shown in FIG. 1 to occur efficiently with respect to the applied voltage, the direction in which the X ions diffuse and the direction in which the electric field is applied are the same. It is desirable to do it. As shown in FIG. 1, when the recording layer is oriented in the [1-10] direction, the X ion diffusion path is arranged in parallel to the electric field direction, so the recording layer is oriented in the [1-10] direction. It is desirable that

The optimum value of the mixing ratio of each atom will be described.
As described with reference to FIG. 1, since the crystal structure can exist stably even when there are void sites in the A1 ion site, the resistance of each state or the diffusion coefficient of the A1 ion has an optimum value. It is possible to optimize the mixing ratio. If the mixing ratio of A1 ions is too small, it is difficult to stably produce and maintain the crystal structure, and if the mixing ratio of A1 ions is too large, diffusion of ions becomes difficult. Therefore, the mixing ratio of A1 ions is preferably 0.5 ≦ a ≦ 2. In order to suppress manufacturing unevenness, the mixing ratio of A1 ions is more preferably 1.5 ≦ a ≦ 2.0.
Even if X1 ions have a certain amount of defects, the crystal structure can exist stably. However, since the diffusion of A1 ions hardly occurs in a crystal having no void at the site of X1 ions, the mixing ratio of X1 ions is preferably 6 ≦ x <7. Further, in order to facilitate diffusion, it is more preferable that 6 ≦ x ≦ 6.5.

  By the way, since an oxidizing agent is generated on the electrode layer (anode) 11 side after the setting operation, the electrode layer 11 is made of a material that is not easily oxidized (for example, electrically conductive nitride, electrically conductive oxide, etc.). It is desirable. Alternatively, it is desirable that a material that is difficult to be oxidized is provided between the recording layer 12 and the electrode layer 11. Moreover, as such a material, the thing which does not have ion conductivity is good.

  Examples of such materials include those shown below, and among these, TiN and SiN can be said to be the most desirable materials from the viewpoint of overall performance taking into account good electrical conductivity and the like.

・ MN
M is at least one element selected from the group consisting of Si, Ti, Zr, Hf, V, Nb, Ta, and W. N is nitrogen.

・ MO _x
M is selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, and Pt. At least one element. The molar ratio x shall satisfy 1 ≦ x ≦ 4.

・ AMO ₃
A is at least one element selected from the group of La, K, Ca, Sr, Ba, and Ln (lanthanoid).
M is selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, and Pt. At least one element.
O is oxygen.

・ A ₂ MO ₄
A is at least one element selected from the group of K, Ca, Sr, Ba, and Ln (lanthanoid).
M is selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, and Pt. At least one element.
O is oxygen.

Further, since a reducing agent is generated on the protective layer (cathode) 13 side after the setting operation, the protective layer 13 preferably has a function of preventing the recording layer 12 from reacting with the atmosphere.
Examples of such a material include semiconductors such as amorphous carbon, diamond-like carbon, and SnO ₂ .

The electrode layer 13A may function as a protective layer for protecting the recording layer 12, or a protective layer may be provided instead of the electrode layer 13A. In this case, the protective layer may be an insulator or a conductor.
In order to efficiently heat the recording layer 12 in the reset operation, a heater layer (a material having a resistivity of about 10 ⁻⁵ Ωcm or more) may be provided on the cathode side, here, on the electrode layer 13A side.

  As described above, according to the present embodiment, by using the above-described material for the recording layer 12, cation diffusion can be facilitated, power consumption required for resistance change can be reduced, and thermal stability can be achieved. Can increase the sex.

(Second Embodiment)
Next, the basic principle of recording / erasing / reproducing information in the information recording / reproducing apparatus according to the second embodiment of the present embodiment will be described.
FIG. 2 is a conceptual diagram showing the structure of the recording unit of the present embodiment.
The recording portion of this embodiment also has a structure in which both sides of the recording layer 12 made of a pyrochlore structure material are sandwiched between the electrode layers 11 and 13A. Again, the electrode 13A may have a role as a protective layer.

The recording layer 12 includes a first layer 12A containing a first compound and a second layer 12B containing a second compound. The first layer 12A is disposed on the electrode layer 11 side and includes a first compound represented by the chemical formula 1: A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 2, 6 ≦ x <7). The second layer 12B is disposed on the electrode layer 13A side and includes a second compound that can release and accommodate O ions.

  In addition, the Fermi level of the electrons of the first compound included in the first layer 12A is set lower than the Fermi level of the electrons of the second compound included in the second layer 12B. This is one of the desirable conditions for imparting reversibility to the state of the recording layer 12. Here, all the Fermi levels are values measured from the vacuum level.

  By using such a combination of materials for the recording layer and facilitating exchange of O (oxygen) ions between the first layer 12A and the second layer 12B, the power consumption required for resistance change can be reduced. In addition, thermal stability can be improved.

Large white circles in the first layer 12A represent X1 ions, small black circles represent M1 ions, and small white circles represent A1 ions. Further, a small white circle with a thick line in the second layer 12B represents an M2 ion, and a large white circle filled with a diagonal line represents an O (oxygen) ion.
As illustrated in FIG. 3, the first and second layers 12A and 12B constituting the recording layer 12 may be formed by alternately laminating two or more layers.

  In such a recording unit, when a potential gradient is generated in the recording layer 12 by applying a potential to the electrode layers 11 and 13A so that the first layer 12A is on the anode side and the second layer 12B is on the cathode side, Some of the O ions in the second layer 12B move through the crystal and enter the first layer 12A on the anode side.

Since there are anion void sites in the crystal of the first layer 12A, O ions that have moved from the second layer 12B are accommodated in the void sites.
Accordingly, the valence of a part of A1 ions or M1 ions increases in the first layer 12A, and the valence of M2 ions decreases in the second layer 12B. Therefore, the M2 ion needs to be an ion composed of a transition element.

That is, assuming that the first and second layers 12A and 12B are in the low resistance state in the initial state (reset state), a part of the O ions in the second layer 12B is in the first layer 12A. By moving to, conductive carriers disappear from the crystals of the first and second layers 12A and 12B, and both become insulators.
As described above, by applying the current / voltage pulse to the recording layer 12, the electric resistance value of the recording layer 12 is increased, so that the set operation (recording) is realized.

At the same time, electrons move from the first layer 12A toward the second layer 12B, but the electron Fermi level of the second layer 12B is higher than the electron Fermi level of the first layer 12A. Therefore, the total energy of the recording layer 12 increases.
Further, even after the set operation is completed, such a high energy state is continued, so that the recording layer 12 may naturally return from the set state (high resistance state) to the reset state (low resistance state). There is sex.
However, such a concern can be avoided by using the recording layer 12 according to the example of the present embodiment. That is, the set state can be maintained.

This is because so-called ion movement resistance works. When the elements forming A1 and M1 are selected so that the average number of A1 ions and M1 ions is larger than trivalent, a large Coulomb repulsive force acts on the diffusion of A1 ions and M1 ions. The diffusion of M1 ions is difficult to occur. On the other hand, in the pyrochlore structure, the oxygen site originally has voids, but in the first compound in which the oxygen content is smaller than the stoichiometric composition, oxygen having a linear diffusion path is applied by applying an external voltage. Ion diffusion easily occurs. At the same time, since oxygen ions are divalent, Coulomb repulsive force works and oxygen ions do not diffuse in a situation where no external voltage is applied.
Thus, when the valence of the A1 ion is trivalent, both the A1 ion and the M1 ion become ions having a large valence, and the diffusion of the cation can be restricted. In addition, since the valence of O ions is bivalent, diffusion resistance due to Coulomb repulsion acts. Therefore, it is desirable that A1 contains at least one element selected from the group consisting of rare earth, Ln (lanthanoid), In, Tl, Sn, Pb, and Bi.

  By the way, since the oxidizing agent is generated on the anode side after the setting operation is completed, in this case as well, the electrode layer 11 is difficult to be oxidized and does not have ionic conductivity (for example, electrically conductive oxidation). It is desirable to use Alternatively, it is desirable that a layer made of a material that is difficult to be oxidized is provided between the electrode layer 11 and the recording layer 12. Suitable examples thereof are as described above.

  The reset operation (erase) may be performed by heating the recording layer 12 and promoting the phenomenon that the O ions stored in the void sites of the first layer 12A return to the second layer 12B.

Specifically, the recording layer 12 can be easily returned to the original low resistance state (conductor) by using Joule heat generated by applying a large current pulse to the recording layer 12 and its residual heat. it can.
As described above, by applying a large current pulse to the recording layer 12, the electrical resistance value of the recording layer 12 is increased, so that a reset operation (erasing) is realized. Alternatively, the reset operation can be performed by applying an electric field in the opposite direction to that at the time of setting.

Here, in order to realize low power consumption, it is important that an oxidation-reduction reaction easily occurs by applying electric energy without causing crystal destruction.
Chemical formula 2: M2O _y (0.5 ≦ y ≦ 2.5) (wherein M2 is at least one element selected from Group 4A, Group 5A, Group 6A, Group 7A, Group 8 and Group 1B) ) Is used as the second layer 12B, it is effective to satisfy such conditions and realize low power consumption. Here, in particular, when any one of Ti, Zr, V, Nb, Cr, Mn, Fe, Co, Ni, and Cu is used as M2, a redox reaction may occur with low power consumption. Furthermore, particularly when Cr, Mn, Fe, or Co is used as M2, a redox reaction occurs with lower power consumption.
Further, in the first compound having a pyrochlore structure with void sites, the diffusion path of O ions is formed in a straight line, and the diffusion easily occurs, so that it is suitable for use as the first compound.

The optimum value of the mixing ratio of each atom will be described.
Since the crystal structure can exist stably even when there are void sites at the A1 ion site, it is possible to optimize the mixing ratio of A1 ions so that the resistance of each state or the diffusion coefficient of O ions becomes an optimum value. Is possible. If the mixing ratio of A1 ions is too small, it is difficult to stably produce and maintain the crystal structure, and if the mixing ratio of A1 ions is too large, diffusion of ions becomes difficult. Therefore, the mixing ratio of A1 ions is preferably 0.5 ≦ a ≦ 2. In order to suppress manufacturing unevenness, the mixing ratio of A1 ions is more preferably 1.5 ≦ a ≦ 2.0.
Even if X1 ions have a certain amount of defects, the crystal structure can exist stably. However, since the diffusion of O ions hardly occurs in a crystal having no voids at the site of X1 ions, the mixing ratio of X1 ions is more preferably 6 ≦ x ≦ 6.5.

Next, a preferable range of the film thickness of the second compound will be described.
In order to supply a sufficient amount of oxygen ions and obtain a sufficient resistance change effect, the film thickness of the second compound is desirably 3 nm or more.

On the other hand, if the film thickness of the second compound becomes too large, it becomes difficult for oxygen ions in a region far from the first compound to contribute to the resistance change, and as a result, the resistance change amount of the second compound becomes small. For this reason, it is desirable that the film thickness of the second compound be 10 nm or less.
The second compound may have any crystal structure, but when it exists in the form of a microcrystal, it is desirable because release and absorption of oxygen easily occur on the surface.
In general, a heater layer (a material having a resistivity of about 10 ⁻⁵ Ωcm or more) for further promoting the reset operation may be provided between the first compound and the lower electrode or between the second compound and the upper electrode.

In the probe memory, since a reducing material is deposited on the cathode side, it is desirable to provide a surface protective layer in order to prevent reaction with the atmosphere.
The heater layer and the surface protective layer can be formed of one material having both functions. For example, semiconductors such as amorphous carbon, diamond-like carbon, and SnO ₂ have both a heater function and a surface protection function.

Reproduction can be easily performed by passing a current pulse through the recording layer 12 and detecting the resistance value of the recording layer 12.
However, the current pulse needs to be a minute value that does not cause a resistance change in the material constituting the recording layer 12.

(Third embodiment)
Next, the basic principle of information recording / erasure / reproduction in the information recording / reproducing apparatus according to the third embodiment of the present embodiment will be described.
FIG. 4 is a schematic diagram showing the structure of the recording unit of the present embodiment.
The recording portion of this embodiment also has a structure in which both sides of the recording layer 12 made of a pyrochlore structure material are sandwiched between the electrode layers 11 and 13A. Again, the electrode 13A may have a role as a protective layer.
The recording layer 12 includes a third layer 12C and a first layer 12A. The third layer 12C is disposed on the electrode layer 11 side, and is composed of a composite compound having at least two kinds of cation elements. At least one of the cation elements is d orbital in which electrons are incompletely filled. It is considered as a transition element having The first layer 12A is disposed on the electrode layer 13A side and includes a third compound represented by chemical formula 1: A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 1, 6 ≦ x <7).

  The electron Fermi level of the first layer 12A is set higher than the electron Fermi level of the third layer 12C. This is one of the desirable conditions for imparting reversibility to the state of the recording layer 12. Here, all the Fermi levels are values measured from the vacuum level.

  By using such a combination of materials for the recording layer and facilitating the exchange of cations between the first layer 12A and the third layer 12C, the power consumption required for resistance change is reduced, and the heat Stability can be increased.

Large white circles in the first layer 12A represent X1 ions, small black circles represent M1 ions, and small white circles represent A1 ions. Further, a large white circle filled with a dotted line in the third layer 12C represents X3 ions, a small white circle with thick lines represents M3 ions, and a small white circle filled with diagonal lines represents A3 ions.
As in the case described above with reference to FIG. 3, each of the first and third compounds 12A and 12C constituting the recording layer 12 may be formed by alternately stacking two or more layers.

  In such a recording portion, when a potential gradient is generated in the recording layer 12 by applying a potential to the electrode layers 11 and 13A so that the first layer 12A is on the cathode side and the third layer 12C is on the anode side, Part of the A3 ions in the third layer 12C containing the third compound moves in the crystal and enters the first layer 12A on the cathode side.

Since there are void sites of A1 ions in the crystal of the first layer 12A, A3 ions that have moved from the third layer 12C containing the third compound are accommodated in the void sites.
Accordingly, the valence of a part of A1 ions or M1 ions decreases in the first layer 12A, and the valence of A3 ions or M3 ions increases in the third layer 12C. Therefore, at least one of the A3 ion and the M3 ion needs to be a transition element having a d orbital in which electrons are incompletely filled so that the valence can be easily changed.

  That is, assuming that the first and third layers 12A and 12C are in a high resistance state (insulator) in the initial state (reset state), a part of the A3 ions in the third layer 12C is the first. By moving into the first layer 12A, conductive carriers are generated in the crystals of the first and third layers 12A and 12C, and both of them have electric conductivity.

As described above, by applying the current / voltage pulse to the recording layer 12, the electric resistance value of the recording layer 12 is reduced, so that the set operation (recording) is realized.
At the same time, electrons move from the third layer 12C toward the first layer 12A, but the electron Fermi level of the third layer 12C is higher than the electron Fermi level of the first layer 12A. Therefore, the total energy of the recording layer 12 increases.
Further, even after the set operation is completed, such a high energy state is continued, so that the recording layer 12 may naturally return from the set state (low resistance state) to the reset state (high resistance state). There is sex.

However, such a concern can be avoided by using the recording layer 12 according to the example of the present embodiment. That is, the set state can be maintained.
As described above, the ion radius and the valence of ions may be selected as appropriate. For example, if a divalent cation with a small ionic radius is selected as the A3 ion, the A3 ion can easily travel within the pyrochlore structure in which the diffusion path of the A1 ion is formed linearly when an external voltage is applied. However, when an external voltage is not applied, the Coulomb repulsive force works to limit the diffusion of A3 ions.

  Moreover, if diffusion of A1 ions and M1 ions occurs in the first compound, the total energy required for switching increases due to the energy required for the diffusion. In order to avoid this, it is desirable that both the A1 ion and the M1 ion are ions that do not diffuse. As described above, by making the valence of the A1 ion trivalent, the diffusion of the A1 ion and the M1 ion can be prevented, so that A1 is rare earth, Ln (lanthanoid), In, Tl, Sn, Pb, It is desirable to include at least one element selected from Bi. Alternatively, even if the valence of A1 ions is small, diffusion of A1 ions and M1 ions can be prevented by using ions having a large ion radius. For this purpose, it is desirable to use monovalent Cs, divalent Sr, Ba or the like as the A1 ion.

The optimum value of the mixing ratio of each atom will be described.
As described with reference to FIG. 1, since the crystal structure can exist stably even when there are void sites at the A1 ion site, the resistance of each state or the diffusion coefficient of A3 ions in the first compound becomes an optimum value. Thus, it is possible to optimize the mixing ratio of A1 ions. If the mixing ratio of A1 ions is too small, it is difficult to stably produce and maintain the crystal structure, and if the mixing ratio of A1 ions is too large, diffusion of A3 ions becomes difficult. Therefore, the mixing ratio of A1 ions is preferably 0.5 ≦ a ≦ 1.

  Even if X1 ions have a certain amount of defects, the crystal structure can exist stably. However, in the crystal where there is no void at the site of X1 ions, the diffusion of A3 ions hardly occurs. Therefore, the mixing ratio of X1 ions is preferably 6 ≦ x <7. Further, in order to facilitate diffusion, it is more preferable that 6 ≦ x ≦ 6.5.

By the way, since the oxidizing agent is generated on the anode side after the setting operation is completed, in this case as well, the electrode layer 11 is difficult to be oxidized and does not have ionic conductivity (for example, electrically conductive oxidation). It is desirable to use Suitable examples thereof are as described above.
The reset operation (erasing) may be performed by heating the recording layer 12 and promoting the phenomenon that the A3 ions stored in the void sites of the first layer 12A return to the third layer 12C.

Specifically, the recording layer 12 can be easily returned to the original high resistance state (insulator) by using Joule heat generated by applying a large current pulse to the recording layer 12 and its residual heat. it can.
As described above, by applying a large current pulse to the recording layer 12, the electrical resistance value of the recording layer 12 is increased, so that a reset operation (erasing) is realized. Alternatively, the reset operation can be performed by applying an electric field in the opposite direction to that at the time of setting.

Here, in order to realize low power consumption, it is important that A3 ions diffuse easily by applying electric energy without causing crystal destruction.
For this reason, in order to reduce power consumption, it is desirable that A3 ions be easily diffused in the third compound. That is, it is desirable that an A3 ion diffusion path is formed in the third compound. Therefore, the third compound preferably has a spinel structure, an ilmenite structure, a cryptomelane structure, a hollandite structure, a heterolite structure, a delafossite structure, or a wolframite structure. In these structures, since the diffusion path of A3 ions is formed in a straight line, the diffusion of A3 ions easily occurs when an external voltage is applied.

Furthermore, the stability after A3 ions diffuse from the third compound will be considered. If a cation diffuses from a continuous region in the third compound, it becomes difficult to stably maintain the structure of the region. Therefore, in the third compound, it is necessary that the diffusing A3 ion and the M3 ion that retains the base structure without diffusing are formed from different atoms.
In addition, in order to satisfy the neutral condition of the charge after the A3 ion diffuses, at least one of the A3 ion and the M3 ion can easily change its valence, and the electrons are incompletely filled. It is necessary to be a transition element having d orbitals.
Therefore, the third compound is composed of a composite compound having at least two types of cations, and at least one of the cations needs to be a transition element having a d orbital incompletely filled with electrons. .

Next, a preferable range of the film thickness of the third compound will be described.
In order to supply a sufficient amount of A3 ions and obtain a sufficient resistance change effect, the film thickness of the third compound is preferably 3 nm or more.

  On the other hand, when the film thickness of the third compound becomes too large, the ratio of A3 ions diffusing from the third compound to the first compound decreases, and resistance change due to diffusion of A3 ions becomes difficult to obtain in the third compound. For this reason, it is desirable that the film thickness of the third compound be 50 nm or less.

In general, a heater layer (a material having a resistivity of about 10 ⁻⁵ Ωcm or more) for further promoting the reset operation may be provided between the first compound and the lower electrode or between the third compound and the upper electrode.

In the probe memory, since a reducing material is deposited on the cathode side, it is desirable to provide a surface protective layer in order to prevent reaction with the atmosphere.
The heater layer and the surface protective layer can be formed of one material having both functions. For example, semiconductors such as amorphous carbon, diamond-like carbon, and SnO ₂ have both a heater function and a surface protection function.

Reproduction can be easily performed by passing a current pulse through the recording layer 12 and detecting the resistance value of the recording layer 12.
However, the current pulse needs to be a minute value that does not cause a resistance change in the material constituting the recording layer 12.

An embodiment of the information recording / reproducing apparatus will be described.
The following describes three cases where the recording unit of the first to third embodiments is applied to a probe memory, applied to a semiconductor memory, and applied to a flash memory.

(Probe memory)
5 and 6 are schematic views showing the probe memory according to the present embodiment.
On the XY scanner 16, a recording medium provided with the recording unit of any one of the first to third embodiments is disposed. A probe array is arranged to face the recording medium.

The probe array includes a substrate 23 and a plurality of probes (heads) 24 arranged in an array on one surface side of the substrate 23. Each of the plurality of probes 24 is constituted by a cantilever, for example, and is driven by multiplex drivers 25 and 26.
Each of the plurality of probes 24 can be individually operated using the microactuator in the substrate 23. Here, an example will be described in which all of the probes 24 are collectively operated to access the data area of the recording medium. .

First, using the multiplex drivers 25 and 26, all the probes 24 are reciprocated in the X direction at a constant cycle, and the position information in the Y direction is read from the servo area of the recording medium. The position information in the Y direction is transferred to the driver 15.
The driver 15 drives the XY scanner 16 based on this position information, moves the recording medium in the Y direction, and positions the recording medium and the probe.
When the positioning of both is completed, data reading or writing is performed simultaneously and continuously on all the probes 24 on the data area.
Data reading and writing are continuously performed because the probe 24 reciprocates in the X direction. Data reading and writing are performed line by line in the data area by sequentially changing the position of the recording medium in the Y direction.
Note that the recording medium may be reciprocated in the X direction at a constant period to read position information from the recording medium, and the probe 24 may be moved in the Y direction.

The recording medium includes, for example, a substrate 20, an electrode layer 21 on the substrate 20, and a recording layer 22 on the electrode layer 21.
The recording layer 22 has a plurality of data areas and servo areas arranged at both ends of the plurality of data areas in the X direction. The plurality of data areas occupy the main part of the recording layer 22.

  A servo burst signal is recorded in the servo area. The servo burst signal indicates position information in the Y direction within the data area.

In addition to these pieces of information, an address area for recording address data and a preamble area for synchronization are arranged in the recording layer 22.
The data and servo burst signal are recorded on the recording layer 22 as recording bits (electric resistance fluctuation). The “1” and “0” information of the recording bit is read by detecting the electric resistance of the recording layer 22.

In this example, one probe (head) is provided corresponding to one data area, and one probe is provided for one servo area.
The data area is composed of a plurality of tracks. A track in the data area is specified by an address signal read from the address area. The servo burst signal read from the servo area is used to move the probe 24 to the center of the track and eliminate the recording bit reading error.
Here, by making the X direction correspond to the down-track direction and the Y direction correspond to the track direction, it becomes possible to use the head position control technology of the HDD.

  Next, the recording / reproducing operation of the probe memory will be described.

FIG. 7 is a conceptual diagram for explaining a state during recording (set operation).
The recording medium is composed of an electrode layer 21 on a substrate (for example, a semiconductor chip) 20, a recording layer 22 on the electrode layer 21, and a protective layer 13B on the recording layer 22. The protective layer 13B is made of, for example, a thin insulator.
The recording operation is performed by applying a voltage to the surface of the recording bit 27 of the recording layer 22 and generating a potential gradient inside the recording bit 27. Specifically, a current / voltage pulse may be given to the recording bit 27.

(When using the recording unit of the first embodiment)
Here, a case where the recording unit of the first embodiment described above with reference to FIG. 1 is used will be described.

FIG. 8 is a schematic diagram showing recording.
First, as shown in FIG. 8, a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.
The current pulse is generated by emitting electrons from the probe 24 toward the electrode layer 21 using, for example, an electron generation source or a hot electron source. Alternatively, the voltage pulse may be applied by bringing the probe 24 into contact with the surface of the recording bit 27.

At this time, for example, in the recording bit 27 of the recording layer 22, a part of the A1 ions moves to the probe (cathode) 24 side, and the A1 ions in the crystal decrease relative to the X1 ions. The A1 ions that have moved to the probe 24 side receive electrons from the probe 24 and are deposited as metal.
In the recording bit 27, the X1 ion becomes excessive, and as a result, the valence of the A1 ion or M1 ion in the recording bit 27 is increased. That is, since the recording bit 27 has electron conductivity due to carrier injection due to phase change, the resistance in the film thickness direction decreases, and recording (set operation) is completed.
The current pulse for recording can also be generated by creating a state in which the potential of the probe 24 is relatively higher than the potential of the electrode layer 21.

FIG. 9 is a schematic diagram showing reproduction.
Reproduction is performed by passing a current pulse through the recording bit 27 of the recording layer 22 and detecting the resistance value of the recording bit 27. However, the current pulse has a minute value that does not cause a change in resistance of the material constituting the recording bit 27 of the recording layer 22.

For example, a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 24 to the recording bit 27, and the resistance value of the recording bit 27 is measured by the sense amplifier S / A.
If the material according to the first embodiment is used, a difference of 103 or more in the resistance value in the set / reset state can be secured.
In reproduction, continuous reproduction is possible by scanning the recording medium with the probe 24 (scanning).

The erase (reset) operation is performed by heating the recording bit 27 of the recording layer 22 with a large current pulse to promote the redox reaction in the recording bit 27. Alternatively, a pulse that gives a potential difference in the opposite direction to that in the set operation may be applied.
The erasing operation can be performed for each recording bit 27, or can be performed in units of a plurality of recording bits 27 or blocks.

(When the recording unit of the second embodiment is used)
Next, the case where the recording unit of the second embodiment described above with reference to FIGS. 2 and 3 is used will be described.

FIG. 10 is a schematic diagram showing a recording state.
First, as shown in FIG. 10, a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.
At this time, a part of the O ions in the second compound (cathode side) 12B of the recording layer 22 moves in the crystal and falls in the void sites of the first compound (anode side) 12A. Along with this, the valence of M2 ions in the second layer 12B decreases, and the valence of A1 ions or M1 ions in the first compound 12A increases. As a result, conductive carriers disappear from the crystals of the first and second layers 12A and 12B, and both become insulators.
Thereby, the set operation (recording) is completed.
Regarding the recording operation, if the positional relationship between the first and second layers 12A and 12B is reversed, the set operation is performed with the potential of the probe 24 relatively higher than the potential of the electrode layer 21. You can also.

FIG. 11 is a schematic diagram showing a state during reproduction.
The reproduction operation is performed by passing a current pulse through the recording bit 27 and detecting the resistance value of the recording bit 27. However, the current pulse has a minute value that does not cause a change in resistance of the material constituting the recording bit 27.

For example, a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 24 to the recording layer (recording bit) 22 and the resistance value of the recording bit is measured by the sense amplifier S / A. If the new material described above is adopted, the difference in resistance value between the set / reset states can be 103 or more.
The reproduction operation can be continuously performed by scanning the probe 24.

The reset (erase) operation uses Joule heat generated by flowing a large current pulse to the recording layer (recording bit) 22 and its residual heat to cause O ions to be second from the void sites in the first layer 12A. What is necessary is just to accelerate | stimulate the effect | action which tries to return in the layer 12B of this. Alternatively, a pulse that gives a potential difference in the opposite direction to that in the set operation may be applied.
The erasing operation can be performed for each recording bit 27, or can be performed in units of a plurality of recording bits 27 or blocks.

(When the recording unit of the third embodiment is used)
Next, the case where the recording unit of the third embodiment described above with reference to FIG. 4 is used will be described.
FIG. 12 is a schematic diagram showing a recording state.
First, as shown in FIG. 12, a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.

  At this time, a part of A3 ions in the third layer (anode side) 12C of the recording layer 22 moves in the crystal and falls in the void sites of the first compound (cathode side) 12A. Along with this, the valence of A3 ions or M3 ions in the third layer 12C increases, and the valence of A1 ions or M1 ions in the first compound 12A decreases. As a result, conductive carriers are generated in the crystals of the first and third layers 12A and 12C, and both of them have electric conductivity.

Thereby, the set operation (recording) is completed.
As for the recording operation, if the positional relationship between the first and third layers 12A and 12C is reversed, the setting operation is performed with the potential of the probe 24 relatively lower than the potential of the electrode layer 21. You can also.

FIG. 13 is a schematic diagram showing a state during reproduction.
The reproduction operation is performed by passing a current pulse through the recording bit 27 and detecting the resistance value of the recording bit 27. However, the current pulse has a minute value that does not cause a change in resistance of the material constituting the recording bit 27.
For example, a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 24 to the recording layer (recording bit) 22 and the resistance value of the recording bit is measured by the sense amplifier S / A. If the new material described above is adopted, the difference in resistance value between the set / reset states can be 103 or more.
The reproduction operation can be continuously performed by scanning the probe 24.
The reset (erase) operation uses Joule heat generated by flowing a large current pulse to the recording layer (recording bit) 22 and its residual heat, so that A3 ions are third from the void sites in the first layer 12A. What is necessary is just to accelerate | stimulate the effect | action which is going to return in this layer 12C. Alternatively, a pulse that gives a potential difference in the opposite direction to that in the set operation may be applied.
The erasing operation can be performed for each recording bit 27, or can be performed in units of a plurality of recording bits 27 or blocks.

(Example)
As a sample, a recording medium having the structure shown in FIG. 8 is used, and evaluation uses a probe pair whose tip diameter is sharpened to 10 nm or less.
The electrode layer 21 is, for example, a Pt film formed on a semiconductor substrate. In order to improve the adhesiveness between the semiconductor substrate and the lower electrode, Ti of about 5 nm may be used as the adhesive layer. The recording layer 22 is obtained by performing RF magnetron sputtering in a mixed gas of argon and oxygen while using a target whose component is adjusted so as to obtain a desired composition ratio and maintaining the temperature of the disk at a high temperature of about 600 ° C. Can be obtained. Furthermore, as a protective layer, for example, diamond-like carbon may be formed by a CVD method. The thickness of each layer can be designed to optimize the resistance ratio between the low resistance state and the high resistance state, the energy required for switching, the switching speed, and the like. For example, a desired film thickness can be obtained by adjusting the sputtering time.

The probe pair is brought into contact with the protective layer 13B, and writing / erasing is performed using one of them. For example, writing is performed by applying a voltage pulse of 1 V to the recording layer 22 with a width of, for example, 50 nsec. On the other hand, for example, erasing can be performed by applying a voltage pulse of 0.2 V to the recording layer 22 with a width of, for example, 200 nsec.
Also, reading is performed using the other one of the probe pair between the writing / erasing. Reading can be performed by applying a voltage pulse of 0.1 V with a width of 10 nsec to the recording layer 22 and measuring the resistance value of the recording layer (recording bit) 22.
Specific examples to which the first to third embodiments described above are applied will be described below.

(When using the recording unit of the first embodiment)
When AgSbO ₃ (Ag ₂ Sb ₂ O ₆ ) having a pyrochlore structure is used as the recording layer, the diffusion path of Ag ⁺ ions exists in a straight line, so that diffusion of Ag ⁺ ions occurs efficiently. Further, after the Ag ⁺ ions are diffused is the valence of Ag ⁺ ions left in the recording layer is increased to bivalent, it can realize the resistance of the recording layer. At this time, pentavalent and large atomic weight Sb ions have the same valence regardless of the presence or absence of Ag ions, and the bond length with O ions does not change, so that the crystal structure is stable even after Ag ions diffuse. Easy to hold. Further, since all the Ag ions cannot be diffused in order to satisfy the neutral condition of the charge, the resistance in the low resistance state is not excessively reduced, and the power required for switching can be reduced.

(When the recording unit of the second embodiment is used)
When Gd ₂ Zr ₂ O ₆ having a pyrochlore structure is used as the first compound and MnO ₂ is used as the second compound, the diffusion path of Gd ions exists linearly, but the valence of Gd ions is trivalent. Since the average valence of Zr ions is trivalent and the valence of the cation is large, and a large Coulomb repulsive force acts, the diffusion of the cation in the first compound hardly occurs. For this reason, O ions diffuse from the second compound to the first compound by the application of the electric field. At this time, in the first compound, since the O ions are accommodated in the void sites, the valence of the Zr ions increases. On the other hand, in the second compound, the valence of Mn ions decreases. In either case, since the resistance of each compound is increased, the entire recording layer changes from a low resistance state to a high resistance state by the diffusion of O ions.

(When the recording unit of the third embodiment is used)
When Cs _0.88 W ₂ O _6.44 having a pyrochlore structure is used as the first compound and MgMn ₂ O ₄ having a spinel structure is used as the third compound, the diffusion path of Cs ions in the first compound However, since the ionic radius of Cs ions is large and the valence of W ions is large, diffusion of cations does not easily occur. On the other hand, in the spinel structure, Mg ions, Mn ions, and O ions are present in layers, and Mg ions diffuse easily because the ion radius of Mg ions is small. Therefore, the Mg ions diffuse from the third compound into the first compound by applying the electric field. At this time, the valence of W ions decreases in the first compound, and the valence of Mn ions increases in the third compound. In either case, since the resistance of each compound is reduced, the recording layer as a whole changes phase from a high resistance state to a low resistance state due to diffusion of Mg ions.
As described above, according to the probe memory of this embodiment, higher recording density and lower power consumption can be realized than the current hard disk and flash memory.

(Semiconductor memory)
Next, an information recording / reproducing apparatus combined with a semiconductor element will be described.
FIG. 14 is a schematic diagram illustrating a cross-point type semiconductor memory including the recording layer according to any one of the first to third embodiments.
Word lines WLi−1, WLi, and WLi + 1 extend in the X direction, and bit lines BLj−1, BLj, and BLj + 1 extend in the Y direction.
One end of the word lines WLi-1, WLi, WLi + 1 is connected to the word line driver & decoder 31 via a MOS transistor RSW as a selection switch, and one end of the bit lines BLj-1, BLj, BLj + 1 is used as a selection switch. The bit line driver & decoder & read circuit 32 is connected via the MOS transistor CSW.

Selection signals Ri-1, Ri, Ri + 1 for selecting one word line (row) are inputted to the gate of the MOS transistor RSW, and one bit line (column) is inputted to the gate of the MOS transistor CSW. Selection signals Ci-1, Ci, Ci + 1 are input to select.
Memory cell 33 is arranged at the intersection of word lines WLi-1, WLi, WLi + 1 and bit lines BLj-1, BLj, BLj + 1. This is a so-called cross-point cell array structure.
The memory cell 33 is provided with a diode 34 for preventing a sneak current during recording / reproduction.

FIG. 15 is a schematic diagram showing the structure of the memory cell array portion of the semiconductor memory of FIG.
On the semiconductor chip 30, word lines WLi-1, WLi, WLi + 1 and bit lines BLj-1, BLj, BLj + 1 are arranged, and memory cells 33 and diodes 34 are arranged at intersections of these wirings.
The feature of such a cross-point cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33. For example, as shown in FIGS. 17 and 18, it is possible to stack the memory cells 33 so that the memory cell array has a three-dimensional structure.

  For example, as shown in FIG. 16, the memory cell 33 having the recording layer of any one of the first to third embodiments includes a stack structure of the recording layer 22, the protective layer 13 </ b> B, and the heater layer 35. One memory cell 33 stores 1-bit data. The diode 34 is disposed between the word line WLi and the memory cell 33.

FIGS. 17 and 18 are schematic views showing other specific examples of the memory cell array.
In the specific example shown in FIG. 17, word lines WLi−1, WLi, and WLi + 1 extending in the X direction are provided above and below the bit lines BLj−1, BLj, and BLj + 1 extending in the Y direction, respectively. Memory cells 33 and 34 are arranged at the cross points of these bit lines and word lines, respectively. That is, the bit line is shared by the upper and lower memory cells.

In the specific example shown in FIG. 18, a structure in which bit lines BLj-1, BLj, BLj + 1 extending in the Y direction and word lines WLi-1, WLi, WLi + 1 extending in the X direction are alternately stacked. Have. Memory cells 33 and 34 are arranged at the cross points of these bit lines and word lines, respectively. That is, the bit line and the word line are shared by the upper and lower memory cells.
By adopting a laminated structure as exemplified in FIGS. 17 and 18, the recording density can be increased.

Next, the recording / reproducing operation of the semiconductor memory using the recording layer of the first to third embodiments will be described with reference to FIGS.
Here, a case will be described in which the memory cell 33 surrounded by the dotted line A in FIG. 14 is selected and the recording / reproducing operation is executed for this.

(When the recording layer of the first embodiment is used)
In recording (set operation), it is only necessary to apply a voltage to the selected memory cell 33 and generate a potential gradient in the memory cell 33 to flow a current pulse. For example, the potential of the word line WLi is set to the bit line BLj. It creates a state that is relatively lower than the potential. If the bit line BLj is set to a fixed potential (eg, ground potential), a negative potential may be applied to the word line WLi.

  At this time, in the selected memory cell 33 surrounded by the dotted line A, some of the A1 ions move to the word line (cathode) WLi side, and the A1 ions in the crystal decrease relative to the X1 ions. . The A1 ions that have moved to the word line WLi side receive electrons from the word line WLi and are deposited as metal.

  In the selected memory cell 33 surrounded by the dotted line A, X1 ions become excessive, and as a result, the valence of A1 ions or M1 ions in the crystal is increased. That is, since the selected memory cell 33 surrounded by the dotted line A has electron conductivity due to carrier injection due to phase change, recording (set operation) is completed.

During recording, it is desirable that the unselected word lines WLi−1 and WLi + 1 and the unselected bit lines BLj−1 and BLj + 1 are all biased to the same potential.
It is desirable to precharge all word lines WLi-1, WLi, WLi + 1 and all bit lines BLj-1, BLj, BLj + 1 during standby before recording.
The current pulse for recording may be generated by creating a state in which the potential of the word line WLi is relatively higher than the potential of the bit line BLj.

  Reproduction is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.

For example, a read current (current pulse) generated by the read circuit is passed from the bit line BLj to the memory cell 33 surrounded by the dotted line A, and the resistance value of the memory cell 33 is measured by the read circuit. If the new material already described is adopted, the difference in resistance value between the set / reset states can be 10 ₃ or more.

  The erase (reset) operation is performed by heating the selected memory cell 33 surrounded by the dotted line A with a large current pulse to promote the oxidation-reduction reaction in the memory cell 33.

(When the recording layer of the second embodiment is used)
In the recording operation (set operation), it is only necessary to apply a voltage to the selected memory cell 33 and generate a potential gradient in the memory cell 33 to flow a current pulse. For example, the potential of the word line WLi is set to the bit line. It is relatively lower than the potential of BLj. If the bit line BLj is set to a fixed potential (eg, ground potential), a negative potential may be applied to the word line WLi.
At this time, in the selected memory cell 33 surrounded by the dotted line A, a part of the O ions in the second compound moves to the void site of the first compound. For this reason, the valence of the A1 ion or M1 ion in the first compound is increased, and the valence of the M2 ion in the second compound is decreased. As a result, the conductive carriers disappear from the crystals of the first and second compounds, and both become insulators.

  Thereby, the set operation (recording) is completed.

During recording, it is desirable that the unselected word lines WLi−1 and WLi + 1 and the unselected bit lines BLj−1 and BLj + 1 are all biased to the same potential.
It is desirable to precharge all word lines WLi-1, WLi, WLi + 1 and all bit lines BLj-1, BLj, BLj + 1 during standby before recording.
The current pulse may be generated by creating a state in which the potential of the word line WLi is relatively higher than the potential of the bit line BLj.
The reproduction operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.

For example, a read current (current pulse) generated by the read circuit is passed from the bit line BLj to the memory cell 33 surrounded by the dotted line A, and the resistance value of the memory cell 33 is measured by the read circuit. If the new material already described is adopted, the difference in resistance value between the set / reset states can be 10 ³ or more.
The reset (erase) operation uses Joule heat generated by flowing a large current pulse to the selected memory cell 33 surrounded by the dotted line A and its residual heat, so that the O ion element is a void in the first compound. What is necessary is just to accelerate | stimulate the effect | action which tries to return in a 2nd compound from a site.

(When the recording layer of the third embodiment is used)
In the recording operation (set operation), it is only necessary to apply a voltage to the selected memory cell 33 and generate a potential gradient in the memory cell 33 to flow a current pulse. For example, the potential of the word line WLi is set to the bit line. It is relatively lower than the potential of BLj. If the bit line BLj is set to a fixed potential (eg, ground potential), a negative potential may be applied to the word line WLi.
At this time, in the selected memory cell 33 surrounded by the dotted line A, a part of the A3 ions in the third compound moves to the void site of the first compound. For this reason, the valence of A1 ion or M1 ion in the first compound decreases, and the valence of A3 ion or M3 ion in the third compound increases. As a result, conductive carriers are generated in the crystals of the first and third compounds, and both have electrical conductivity.
Thereby, the set operation (recording) is completed.

During recording, it is desirable that the unselected word lines WLi−1 and WLi + 1 and the unselected bit lines BLj−1 and BLj + 1 are all biased to the same potential.
It is desirable to precharge all word lines WLi-1, WLi, WLi + 1 and all bit lines BLj-1, BLj, BLj + 1 during standby before recording.
The current pulse may be generated by creating a state in which the potential of the word line WLi is relatively higher than the potential of the bit line BLj.

The reproduction operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.
For example, a read current (current pulse) generated by the read circuit is passed from the bit line BLj to the memory cell 33 surrounded by the dotted line A, and the resistance value of the memory cell 33 is measured by the read circuit. If the new material already described is adopted, the difference in resistance value between the set / reset states can be 10 ³ or more.

The reset (erase) operation uses Joule heat generated by flowing a large current pulse to the selected memory cell 33 surrounded by the dotted line A and its residual heat, and the A3 ionic element becomes a void in the first compound. What is necessary is just to accelerate | stimulate the effect | action which tries to return in a 3rd compound from a site.
As described above, according to the semiconductor memory of this embodiment, higher recording density and lower power consumption can be realized than the current hard disk and flash memory.

(Flash memory)
This embodiment can also be applied to a flash memory.
FIG. 19 is a schematic cross-sectional view showing a memory cell of a flash memory.
The memory cell of the flash memory is composed of a MIS (metal-insulator-semiconductor) transistor.

A diffusion layer 42 is formed in the surface region of the semiconductor substrate 41. A gate insulating layer 43 is formed on the channel region between the diffusion layers 42. On the gate insulating layer 43, a recording layer (RRAM: Resistive RAM) 44 included in any of the recording layers of the first to third embodiments is formed. A control gate electrode 45 is formed on the recording unit 44.
The semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types. The control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.
The recording layer 44 is formed of the material constituting the recording layer 12 described above with respect to the first to third embodiments.

The basic operation will be described with reference to FIG.
The set (write) operation is performed by applying the potential V1 to the control gate electrode 45 and applying the potential V2 to the semiconductor substrate 41.
The difference between the potentials V1 and V2 needs to be large enough for the recording layer 44 to undergo phase change or resistance change, but the direction is not particularly limited.
That is, either V1> V2 or V1 <V2 may be used.
For example, assuming that the recording layer 44 is an insulator (high resistance) in the initial state (reset state), the gate insulating layer 43 is substantially thickened, so that the threshold value of the memory cell (MIS transistor) is reached. Get higher.

If the recording layer 44 is changed to a conductor (low resistance) by applying the potentials V1 and V2 from this state, the gate insulating layer 43 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is , Get lower.
The potential V2 is applied to the semiconductor substrate 41, but instead, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell.

The reset (erase) operation is performed by applying the potential V1 ′ to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 (<V3) to the other of the diffusion layers 42.
The potential V1 ′ is set to a value exceeding the threshold value of the memory cell in the set state.
At this time, the memory cell is turned on, electrons flow from one side of the diffusion layer 42 to the other side, and hot electrons are generated. Since the hot electrons are injected into the recording layer 44 through the gate insulating layer 43, the temperature of the recording layer 44 rises.
As a result, the recording layer 44 changes from a conductor (low resistance) to an insulator (high resistance), so that the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is , Get higher.
As described above, since the threshold value of the memory cell can be changed based on a principle similar to that of the flash memory, the information recording / reproducing apparatus according to the example of the present embodiment can be put into practical use by using the technology of the flash memory.

(NAND flash memory)
FIG. 20 is a circuit diagram of the NAND cell unit.
FIG. 21 is a schematic diagram showing the structure of the NAND cell unit according to this embodiment.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NAND cell unit according to the example of the present embodiment is formed in the P-type well region 41c.
The NAND cell unit is composed of a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to the both ends one by one.
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording layer (RRAM) 44 on the gate insulating layer 43, and a recording layer 44. And the upper control gate electrode 45.

The state (insulator / conductor) of the recording layer 44 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording layer 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (low resistance).
One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.

It is assumed that all memory cells in the NAND cell unit are in a reset state (resistance is large) before the set (write) operation.
The set (write) operation is sequentially performed one by one from the memory cell MC on the source line SL side to the memory cell on the bit line BL side.
V1 (plus potential) is applied to the selected word line (control gate electrode) WL as a write potential, and Vpass is applied to the unselected word line WL as a transfer potential (a potential at which the memory cell MC is turned on).

The select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
For example, when the program data is “1”, a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording layer 44 of the selected memory cell MC is transferred. The resistance value should not change from a high state to a low state.
When the program data is “0”, V2 (<V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording layer 44 of the selected memory cell MC is changed from a high state to a low state. To change.

In the reset (erase) operation, for example, V1 ′ is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 (<V3) is applied to the source line SL.
At this time, since hot electrons are injected into the recording layers 44 of all the memory cells MC in the NAND cell unit, a reset operation is collectively executed for all the memory cells MC in the NAND cell unit.

In the read operation, a read potential (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL. A potential to be turned on without fail is given.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
When a read potential is applied to the selected memory cell MC, the selected memory cell MC is turned on or off according to the value of the data stored therein. For example, data can be read by detecting a change in the read current. it can.

  In the structure shown in FIG. 21, the select gate transistor ST has the same structure as that of the memory cell MC. For example, as shown in FIG. 22, the select gate transistor ST is formed with a recording layer. Alternatively, a normal MIS transistor can be used.

FIG. 23 is a schematic diagram showing a modification of the NAND flash memory.
This modification is characterized in that the gate insulating layers of the plurality of memory cells MC constituting the NAND string are replaced with a P-type semiconductor layer 47.
When the high integration progresses and the memory cell MC is miniaturized, the P-type semiconductor layer 47 is filled with a depletion layer without applying a voltage.

At the time of setting (writing), a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and a positive transfer potential is applied to the control gate electrode 45 of the non-selected memory cell MC. (For example, 1V).
At this time, the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.

  Therefore, as described above, the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.

  The reset (erase) is performed, for example, by applying a negative erase potential (for example, −3.5 V) to all the control gate electrodes 45 and applying a ground potential (0 V) to the P-type well region 41 c and the P-type semiconductor layer 47. This can be performed collectively for all the memory cells MC constituting the NAND string.

  At the time of reading, a positive read potential (for example, 0.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the memory cell MC receives the data “ A transfer potential (for example, 1 V) that always turns on regardless of 0 ”or“ 1 ”is applied.

However, the threshold voltage Vth “1” of the memory cell MC in the “1” state is in the range of 0V <Vth ”1” <0.5 V, and the threshold voltage Vth ”of the memory cell MC in the“ 0 ”state is It is assumed that 0 ″ is in the range of 0.5V <Vth ″ 0 ″ <1V.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
In such a state, since the amount of current flowing through the NAND string changes according to the value of the data stored in the selected memory cell MC, data can be read by detecting this change.

In this modification, the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0 than that of the P-type well region 41c. It is desirable that the depth is about 5V.
This is because when a positive potential is applied to the control gate electrode 45, inversion from the P-type to N-type starts from the surface portion of the P-type well region 41c between the N-type diffusion layers 42, and a channel is formed. It is for doing so.
Thus, for example, at the time of writing, the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed. The channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
That is, even if the recording layer 44 of the memory cell MC is a conductor (set state), the diffusion layer 42 and the control gate electrode 45 are not short-circuited.

(NOR flash memory)
FIG. 24 is a circuit diagram of the NOR cell unit.
FIG. 25 is a schematic diagram showing the structure of the NOR cell unit according to the example of the present embodiment.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NOR cell according to the example of this embodiment is formed in the P-type well region 41c.
The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
The memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording layer (RRAM) 44 on the gate insulating layer 43, and a control on the recording layer 44. And a gate electrode 45.
The state (insulator / conductor) of the recording layer 44 of the memory cell MC can be changed by the basic operation described above.

(2-transistor flash memory)
FIG. 26 is a circuit diagram of a two-transistor cell unit.
FIG. 27 is a schematic diagram showing the structure of a two-tracell unit according to the example of the present embodiment.

The two-transistor cell unit has been recently developed as a new cell structure that combines the characteristics of a NAND cell unit and the characteristics of a NOR cell.
An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A two-transistor cell unit according to the example of the present embodiment is formed in the P-type well region 41c.

The two-transistor type cell unit includes one memory cell MC and one select gate transistor ST connected in series.
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording layer (RRAM) 44 on the gate insulating layer 43, and a recording layer 44. And the upper control gate electrode 45.
The state (insulator / conductor) of the recording layer 44 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording layer 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (low resistance).

Select gate transistor ST is connected to source line SL, and memory cell MC is connected to bit line BL.
The state (insulator / conductor) of the recording layer 44 of the memory cell MC can be changed by the basic operation described above.
In the structure shown in FIG. 27, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 28, the select gate transistor ST is not formed with a recording layer. In addition, a normal MIS transistor can be used.

  As described above with reference to FIGS. 1 to 28, according to the present embodiment, since information recording (writing) is performed only in a portion (recording unit) to which an electric field is applied, a very fine region is obtained. In addition, information can be recorded with extremely low power consumption.

  Erasing is performed by applying heat. However, if the material proposed in the example of this embodiment is used, the structure of the oxide hardly changes, so that erasing can be performed with low power consumption. Alternatively, erasing can be performed by applying an electric field in the opposite direction to that during recording. In this case, since there is little energy loss of heat diffusion, erasing can be performed with smaller power consumption.

  As described above, according to the example of the present embodiment, it is possible to perform information recording with a recording density that cannot be achieved by the conventional technique, despite the extremely simple mechanism. Therefore, the example of this embodiment has a great industrial advantage as a next-generation technology that breaks down the recording density barrier of the current nonvolatile memory.

  In addition, the example of this embodiment is not limited to the above-mentioned embodiment, Each component can be deform | transformed and embodied in the range which does not deviate from the summary. In the example of the present embodiment, the state immediately after film formation is defined as the initial state, and the set and the reset are defined. However, the definition of the set and the reset is arbitrary, and is limited to the example of the present embodiment. It is not a thing. Furthermore, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

It is a conceptual diagram for demonstrating the basic principle of the recording / reproduction | regeneration of information in the information recording / reproducing apparatus concerning the 1st Embodiment of this invention. It is a conceptual diagram showing the structure of the recording part of 2nd Embodiment. 3 is a schematic diagram illustrating a specific example in which first and second layers 12A and 12B constituting a recording layer 12 are alternately stacked. FIG. It is a schematic diagram showing the structure of the recording part of 3rd Embodiment. It is a schematic diagram showing the probe memory which concerns on embodiment of this invention. It is a schematic diagram showing the probe memory which concerns on embodiment of this invention. It is a conceptual diagram for demonstrating the state at the time of recording (set operation | movement). It is the schematic diagram represented about recording. It is the schematic diagram showing reproduction | regeneration. It is a schematic diagram showing the state to record. It is a schematic diagram showing the state at the time of reproduction | regeneration. It is a schematic diagram showing the state to record. It is a schematic diagram showing the state at the time of reproduction | regeneration. It is a schematic diagram showing the crosspoint type | mold semiconductor memory provided with the recording layer in any one of 1st-3rd embodiment. It is a schematic diagram showing the structure of the memory cell array part of the semiconductor memory of FIG. 3 is a schematic view illustrating the structure of a memory cell 33. FIG. It is a schematic diagram showing the other specific example of a memory cell array. It is a schematic diagram showing the other specific example of a memory cell array. It is a schematic cross section showing the memory cell of flash memory. It is a circuit diagram of a NAND cell unit. It is a schematic diagram showing the structure of the NAND cell unit which concerns on embodiment of this invention. It is a schematic diagram showing the specific example using a normal MIS transistor. FIG. 10 is a schematic diagram illustrating a modification of a NAND flash memory. It is a circuit diagram of a NOR cell unit. It is a schematic diagram showing the structure of the NOR cell unit which concerns on embodiment of this invention. It is a circuit diagram of a two-transistor type cell unit. It is a schematic diagram showing the structure of the 2 tracell unit which concerns on embodiment of this invention. It is a schematic diagram showing the specific example using a normal MIS transistor.

Explanation of symbols

11 Electrode layer 12 Recording layer 12A First layer 12B Second layer 12C Third layer 13A Electrode (protective layer)
13B Protective layer 14 Metal layer 15 Driver 16 Scanner 20 Substrate 21 Electrode layer 22 Recording layer 23 Substrate 24 Probe 25, 26 Multiplex driver 27 Recording bit 30 Semiconductor chip 31 Decoder 32 Read circuit 33 Memory cell 34 Diode 35 Heater layer 41 Semiconductor substrate 41a semiconductor substrate 41b well region 41c well region 42 diffusion layer 42 diffusion layer 43 gate insulating layer 44 recording layer 45 control gate electrode 47 semiconductor layer

Claims (20)

A pyrochlore structure represented by A1 _a M1 ₂ X1 _x (0.5 ≦ a ≦ 2, 6 ≦ x <7), wherein A1 and M1 are different from each other, and at least one of A1 and M1 Any one is a transition element having d orbital incompletely filled with electrons, and X1 is selected from the group consisting of O (oxygen), F (fluorine), N (nitrogen), and S (sulfur) A recording layer having a first layer containing a first compound containing at least one of the following:
A voltage applying unit for recording information by applying a voltage to the recording layer to generate a phase change in the recording layer;
An information recording / reproducing apparatus comprising:   2. The information recording / reproducing apparatus according to claim 1, wherein X1 is O (oxygen). The A1 is at least one selected from the group consisting of 1A group, 2A group, rare earth, Ln (lanthanoid), 4A group, 1B group, 2B group, Al, Ga, In, Tl, Sn, Pb and Bi. Element,
The information according to claim 1 or 2, wherein said M1 includes at least one element selected from the group consisting of 4A group, 5A group, 6A group, 7A group, 8 group, Sn and Sb. Recording / playback device.   The M1 includes at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, Mo, W, Mn, Tc, Re, Ru, Os, Sn, and Sb. The information recording / reproducing apparatus according to claim 1.   A1 is at least one element selected from the group consisting of Rb, Cs, Ca, Sr, Ba, rare earth, Ln (lanthanoid), Zr, Ag, Au, Cd, Hg, Tl, Sn, Pb, and Bi. The information recording / reproducing apparatus according to claim 1, wherein the information recording / reproducing apparatus comprises:   5. The information recording / reproducing apparatus according to claim 1, wherein the A <b> 1 includes at least one selected from the group consisting of a group 4A and a group 1B.   The information recording / reproducing according to any one of claims 1 to 4, wherein the A1 includes at least one element selected from the group consisting of Rb, Cs, Ag, Au, Hg, and Tl. apparatus.   The M1 includes at least one element selected from the group consisting of V, Nb, Ta, Mo, W, Mn, Ru, Os, and Sb. The information recording / reproducing apparatus described in 1. The recording layer further includes a second layer provided in contact with the first layer,
The second layer is represented by M 2 O _y (0.5 ≦ y ≦ 2.5), and the M 2 is selected from the group consisting of 4A group, 5A group, 6A group, 7A group, 8 group and 1B group. The information recording / reproducing apparatus according to claim 1, further comprising a second compound which is at least one kind of element.   10. The information recording / reproducing apparatus according to claim 9, wherein M2 is at least one selected from the group consisting of Cr, Mn, Fe, and Co.   11. The information recording / reproducing according to claim 9, wherein the A1 includes at least one element selected from the group consisting of rare earth, Ln (lanthanoid), In, Tl, Sn, Pb, and Bi. apparatus.   The information recording / reproducing apparatus according to claim 9, wherein the Fermi level of electrons of the second compound is higher than the Fermi level of electrons of the first compound. The composition ratio a of A1 satisfies 0.5 ≦ a ≦ 1,
The recording layer further includes a third layer provided in contact with the first layer,
The third layer includes at least two kinds of cationic elements, and at least one of the two kinds of cationic elements is a third compound that is a transition element having d orbital incompletely filled with electrons. The information recording / reproducing apparatus according to claim 1, further comprising:   14. The third compound according to claim 13, wherein the third compound has any one selected from the group consisting of a spinel structure, an ilmenite structure, a cryptomelane structure, a hollandite structure, a heterolite structure, a delafossite structure, and a wolframite structure. Information recording / reproducing apparatus.   The A1 includes at least one element selected from the group consisting of Cs, Sr, Ba, rare earth, Ln (lanthanoid), In, Tl, Sn, Pb, and Bi. The information recording / reproducing apparatus described in 1.   16. The information recording / reproducing apparatus according to claim 13, wherein the Fermi level of the electrons of the third compound is lower than the Fermi level of the electrons of the first compound.   17. The information recording / reproducing according to claim 1, wherein the voltage application unit includes a probe for locally applying the voltage to a recording unit of the recording layer. apparatus.   The information recording / reproducing apparatus according to claim 1, wherein the voltage applying unit includes a word line and a bit line sandwiching the recording layer. The voltage application unit includes a MIS transistor having a gate electrode and a gate insulating film,
The information recording / reproducing apparatus according to claim 1, wherein the recording layer is provided between the gate electrode of the MIS transistor and the gate insulating layer. The voltage application unit includes two second conductivity type diffusion layers provided in the first conductivity type semiconductor substrate, and a first on the first conductivity type semiconductor substrate between the two second conductivity type diffusion layers. A conductive type semiconductor layer, and a gate electrode for controlling conduction / non-conduction between the two second conductivity type diffusion layers,
The information recording / reproducing apparatus according to claim 1, wherein the recording layer is provided between the gate electrode and the first conductivity type semiconductor layer.