JP2008206101A - Data transmission/reception system, and transmission circuit and reception circuit for use therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of transmission lines for clock signals of different frequencies and to simplify a circuit scale of a reception circuit even if a frequency difference of clocks is a small, in a system for transmitting and receiving a plurality of data signals in an asynchronous relationship and synchronized with the clock signals of different frequencies. <P>SOLUTION: A fastest clock selecting means 111 transmits only a clock signal of a highest frequency among input clock signals A4-A6 which are asynchronous to one another but in a frequency relation where frequencies are not largely different, as a fastest clock signal together with data input signals A1-A3. Each of clock generating means 121-123 in a reception circuit 12 detects a phase difference between a received data signal and the received fastest clock signal, generates a phase information signal and selects a forward phase or a backward phase of the received fastest clock signal according to a logic level of the generated phase information signal, thereby generating a generation clock signal of a pseudo frequency of a data signal for retiming the data signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transmission / reception system and a transmission circuit and a reception circuit used therefor, and in particular, by synchronizing with a clock signal having a different frequency, a plurality of data signals that are asynchronous with each other, and a plurality of transmission lines from the transmission circuit. The present invention relates to a data transmission / reception system that transmits data to a reception circuit through the transmission circuit, and a transmission circuit and a reception circuit used therefor.

  FIG. 11 is a block diagram showing an example of a conventional data transmission / reception system. This data transmission / reception system includes a transmission circuit 51 and a reception circuit 52 connected to each other via a transmission line. The transmission circuit 51 includes a retiming unit 511, a retiming unit 512, and a retiming unit 513. The receiving circuit 52 includes a retiming unit 521, a retiming unit 522, and a retiming unit 523.

  In FIG. 11, the retiming means 511 of the transmission circuit 51 receives as input the data input signal C1 and the clock input signal C2 synchronized with the data input signal C1, and outputs the clock input signal C2 as it is as the clock signal C8. At the falling (or rising) timing of the clock input signal C2, the data input signal C1 is latched, and the latched data signal C7 is output.

  Similarly, the retiming means 512 of the transmission circuit 51 receives the data input signal C3 and the clock input signal C4 synchronized with the data input signal C3 as inputs, outputs the clock input signal C4 as it is as the clock signal C10, At the falling (or rising) timing of the input signal C4, the data input signal C3 is latched, and the latched data signal C9 is output. The retiming means 513 of the transmission circuit 51 receives the data input signal C5 and the clock input signal C6 synchronized with the data input signal C5 as inputs, outputs the clock input signal C6 as it is as the clock signal C12, and inputs the clock input. The data input signal C5 is latched at the falling (or rising) timing of the signal C6, and the latched data signal C11 is output.

  Here, since the clock input signals C2, C4, and C6 have different frequencies and the data input signals C1, C3, and C5 are in an asynchronous relationship, the data signals C7, C9, and C11 are also in an asynchronous relationship with each other.

  The retiming means 521 of the receiving circuit 52 receives the data signal C7 and the clock signal C8 from the transmitting circuit 51 as inputs, outputs the clock signal C8 as it is as the clock output signal C14, and also causes the falling edge of the clock signal C8 ( Alternatively, the data signal C7 is latched at the rising timing, and the latched data signal is output as the data output signal C13.

  Similarly, the retiming means 522 of the reception circuit 52 receives the data signal C9 from the transmission circuit 51 and the clock signal C10 as inputs, outputs the clock signal C9 as it is as the clock output signal C16, and also outputs the clock signal C9. The data signal C9 is latched at the falling (or rising) timing, and the latched data signal is output as the data output signal C15. The retiming means 523 of the receiving circuit 52 receives the data signal C11 and the clock signal C12 from the transmitting circuit 51 as inputs, outputs the clock signal C12 as it is as the clock output signal C18, and also rises the clock signal C12. At the falling (or rising) timing, the data signal C11 is latched, and the latched data signal is output as the data output signal C17.

  FIG. 12 shows a block diagram of another example of a conventional data transmission / reception system. The data transmission / reception system includes a transmission circuit 61 and a reception circuit 62 that are connected to each other via a transmission line. The transmission circuit 61 includes a multiplexing unit 611, a multiplexing unit 612, and a multiplexing unit 613. The receiving circuit 62 includes a clock / data extraction unit 621, a clock / data extraction unit 622, and a clock / data extraction unit 623.

  In FIG. 12, the multiplexing means 611 of the transmission circuit 61 receives the data input signal D1 and the clock input signal D2 as inputs, multiplexes them, and outputs a multiplexed signal D7. Similarly, the multiplexing means 612 of the transmission circuit 61 receives the data input signal D3 and the clock input signal D4 as inputs, multiplexes them, and outputs a multiplexed signal D8. Further, the multiplexing means 613 of the transmission circuit 61 receives the data input signal D5 and the clock input signal D6 as inputs, multiplexes them, and outputs a multiplexed signal D9. Here, the clock input signals D2, D4, and D6 have different frequencies, and the data input signals D1, D3, and D5 are in an asynchronous relationship.

  There are several multiplexing methods for multiplexing data and clocks by the multiplexing means 611, 612, and 613. For example, there is a method using Manchester code. That is, there is a method of multiplexing the clock shown in FIG. 14A and the data shown in FIG. 14B as the Manchester code shown in FIG.

  The clock / data extracting means 621 of the receiving circuit 62 receives the multiplexed signal D7 from the transmitting circuit 61 as an input, separates and extracts the multiplexed data signal and the clock signal, and outputs them as a data output signal D10 and a clock signal D11, respectively. Output. Similarly, the clock / data extraction means 622 of the reception circuit 62 receives the multiplexed signal D8 from the transmission circuit 61 as an input, separates and extracts the multiplexed data signal and the clock signal, and outputs the data output signal D12 and the clock, respectively. Output as signal D13. The clock / data extracting means 623 of the receiving circuit 62 receives the multiplexed signal D9 from the transmitting circuit 61 as an input, separates and extracts the multiplexed data signal and the clock signal, and outputs the data output signal D14 and the clock signal, respectively. Output as D15.

  In the data transmission / reception system shown in FIG. 11, since the same number of clock lines as the data lines are required to transmit / receive data signals, the total number of transmission lines is six, whereas FIG. In the data transmission / reception system shown, a set of data signals and a clock signal are multiplexed and transmitted / received as one multiplexed signal, so that the number of transmission lines is three and the number of transmission lines can be reduced. That is, the conventional data transmission / reception system shown in FIG. 11 uses N clock lines synchronized with each data line in addition to N data lines in order to transmit N non-synchronized data signals. The number of transmission lines increases as the number of data signals to be transmitted and received increases.

  On the other hand, as shown in FIG. 12, in the conventional data transmission / reception system that multiplexes the clock component to the data and outputs it as a single line, each of the transmission circuit 61 and the reception circuit 62 has a complicated transmission system and circuit. It is necessary to use an expensive device such as a configuration, a voltage controlled oscillator (VCO), and there is a problem that the cost increases. For example, in FIG. 12, when a multiplexing method using Manchester code is adopted as the multiplexing means 611, 612, 613, the clock data extraction means 621, 622, 623 require a phase locked loop (PLL) circuit, The circuit scale is expensive and expensive, including the VCO in the PLL circuit.

  Therefore, as a transmission system (data transmission / reception system) that transmits a plurality of data from the transmission circuit to the reception circuit at different signal speeds, the transmission circuit generates a reference clock for transmitting the fastest data from the plurality of data. In addition to transmitting the fastest data together with the reference clock in synchronization with the reference clock, a clock for transmitting the remaining data other than the fastest data among the plurality of data is generated from the reference clock, and this clock is used as the clock. The remaining data is transmitted synchronously, and the receiving circuit receives each signal from the transmitting circuit and captures the fastest data received using the receiving reference clock, and also receives the above-mentioned data from the received reference clock. Generate a clock to capture the remaining data, and send / receive data configured to capture the remaining received data System (signal transmission system) is known (e.g., see Patent Document 1).

  According to this conventional data transmission / reception system, since the clock to be transmitted is only the reference clock, even if the number of data to be transmitted / received increases, it is not necessary to transmit the number of clocks corresponding to the number of data to be transmitted / received, The number of transmission lines can be reduced.

Japanese Patent Laid-Open No. 8-298531

  However, the conventional data transmission / reception system described above has a configuration in which the transmission circuit 100 and the reception circuit 120 are connected by transmission lines 110 and 111 as shown in the block diagram of FIG. Since the generator 101 is necessary, there is a problem that the configuration of the transmission circuit 100 is necessary and the cost is high.

  In addition, since the reference clock transmitted through the transmission line 111 is fixed, when the reference clock changes, the reference clock CLK1 ′ received by the receiving circuit 120 changes. Therefore, the reception reference clock is divided inside the receiving circuit 120. The clocks CLK2 ′ and CLK3 ′ output from the frequency dividing circuits 121 and 122 that generate the clocks CLK2 ′ and CLK3 ′ to circulate and capture other data also change instead of the original frequencies. It is difficult to capture data normally.

  In the above conventional data transmission / reception system, it is necessary to fix the frequency dividing ratio of the frequency dividing circuits 121 and 122 for generating the non-fastest clocks CLK2 ′ and CLK3 ′. If the frequency difference is small, there is a problem that the circuit scale of the receiving circuit 120 becomes large. Further, in the conventional data transmission / reception system described above, if the delay time between the data DATA1, DATA2, DATA3 transmitted through the transmission line 110 and the reference clock transmitted through the transmission line 111 becomes large, the data is captured by the reception circuit 120. An error occurs in the recorded data.

  The present invention has been made in view of the above points. A data transmission / reception system capable of reducing the number of transmission lines of a clock for transmitting / receiving data and reducing the configuration and cost of a transmission circuit, and a transmission circuit and a reception circuit used therefor The purpose is to provide.

  Another object of the present invention is to provide a data transmission / reception system capable of simplifying the circuit scale of a reception circuit even if the frequency difference between clocks of a plurality of data to be transmitted is small, and a transmission circuit and a reception circuit used therefor. is there.

  Furthermore, another object of the present invention is to allow the receiving circuit to operate normally even if the fastest clock to be transmitted fluctuates, and to delay time between a plurality of data to be transmitted and the clock to be transmitted. An object of the present invention is to provide a data transmission / reception system capable of operating a reception circuit normally even if large, and a transmission circuit and a reception circuit used therefor.

  In order to achieve the above object, the data transmission / reception system according to the first aspect of the invention transmits N data signals synchronized with each of N clock signals of different frequencies (N is a natural number of 2 or more) from the transmission circuit. The data transmission / reception system transmits data to the reception circuit separately via the data line, and the transmission circuit transmits N data signals in an asynchronous relationship with each other and transmits N clock signals input from the outside. Among them, the clock signal having the highest frequency is selected and output to the receiving circuit as the fastest clock signal. The receiving circuit receives the N data signals transmitted from the transmitting circuit, and transmits from the transmitting circuit. Clock receiving means for receiving the fastest clock signal received, and clock reception at the logic change timing of the data signal received by the data receiving means The pseudo frequency of the input data signal for retiming the input data signal by controlling the phase of the received fastest clock signal based on the phase shift amount of the fastest clock signal received at the stage And N clock generating means for generating the generated clock signal.

In order to achieve the above object, the second aspect of the invention provides N data signals synchronized with each of N clock signals of different frequencies (N is a natural number of 2 or more) from the transmission circuit. A data transmission / reception system for separately transmitting data to a receiving circuit via a data line, wherein the transmitting circuit outputs N data signals that are asynchronously connected to each other to the N data lines, and an external input A fastest clock selecting means for selecting a clock signal having the highest frequency among the N clock signals thus generated and outputting the selected clock signal as a fastest clock signal to the receiving circuit via one clock line;
The reception circuit receives the data reception means for receiving N data signals via N data lines, the clock reception means for receiving the fastest clock signal via one clock line, and the data reception means. Provided for each of the N data signals, detects the phase difference between the received input data signal and the fastest clock signal received by the clock receiving means to generate a phase information signal, and the logical level of the phase information signal N clock generation that generates a pseudo clock signal of a pseudo frequency of the input data signal for retiming the input data signal by selecting the normal phase or the reverse phase of the received fastest clock signal according to Means.

  In the first and second aspects of the invention, the clock signal to be transmitted can be only the fastest clock signal regardless of the number of data signals to be transmitted and received, so that the number of clock lines can be reduced and the transmission circuit can receive a clock signal from the outside. Therefore, it is not necessary to provide a reference clock generator in the transmission circuit. Further, the clock generating means generates a toothless clock without dividing the fastest clock signal as the non-fastest clock signal.

  In order to achieve the above object, according to a third aspect, the fastest clock selection means in the second aspect is supplied with N clock signals inputted from outside and counts the input clock signals. N M-ary (M is a natural number greater than or equal to 3) counters, and each counter value of N M-ary counters and N clock signals are received as input, and among the input N clock signals, An M-ary indicating a specific count value other than the predetermined value among the other (N−1) M-ary counters at the timing when the count value of the M-ary counter that counts the selected clock signal becomes a predetermined value. It is characterized by having a selection means for selecting the input clock signal of the counter as the fastest clock signal. In the present invention, the fastest clock signal having the highest frequency among the clock signals can be automatically selected.

  In order to achieve the above object, according to a fourth aspect of the invention, the clock generation means according to the second aspect of the invention generates a phase information signal by detecting a phase difference between the received data signal and the received fastest clock signal. A phase detection means; an inverting means for inverting the polarity of the fastest clock signal; and a fastest clock selecting means for selecting the received fastest clock signal or the fastest clock signal inverted by the inverting means according to the logic level of the phase information signal; The clock signal output from the fastest clock selection means is received as an input, and generated by removing pulses with a pulse width that is determined to be not the clock of the fastest clock signal (for example, ¼ clock length or less). The present invention is characterized by comprising a noise removal means for outputting as a clock signal.

  In this invention, the clock generation means generates the clock signal that can reliably retime the data signal without error from the fastest clock signal, so that the delay time between the data signal and the fastest clock signal is automatically adjusted. it can.

In order to achieve the above object, according to a fifth aspect of the present invention, N data signals synchronized with each of N clock signals having different frequencies (N is a natural number of 2 or more) are transmitted from the transmission circuit to N data signals. A data transmission / reception system for separately transmitting to a receiving circuit via a data line,
The transmission circuit has data output means for outputting N data signals that are asynchronous with each other to N data lines, and the reception circuit receives N data signals via the N data lines. For each of the data receiving means, the fastest clock generating means for generating the fastest clock signal equal to or higher than the frequency of the clock signal having the highest frequency among the N clock signals, and each of the N data signals received by the data receiving means A phase information signal is generated by detecting a phase difference between the received input data signal and the fastest clock signal generated by the fastest clock generating means, and the correctness of the fastest clock signal is determined according to the logic level of the phase information signal. Generate a pseudo clock signal with a pseudo frequency of the input data signal for retiming the input data signal by selecting the phase or reverse phase And having a number of clock generating means. In the present invention, since the receiving circuit has the fastest clock generation means, it is possible to eliminate the need for transmission / reception of the clock signal.

  In order to achieve the above object, according to a sixth aspect of the present invention, there is provided data for transmitting N data signals synchronized with each of N clock signals having different frequencies (N is a natural number of 2 or more) to a receiving circuit. In a transmission circuit used in a transmission / reception system, a data output means for transmitting N data signals that are asynchronous with each other, and a reception circuit that selects a clock signal with the highest frequency among N clock signals input from the outside And a fastest clock selection means for outputting as a fastest clock signal.

  Here, the fastest clock selection means includes N M clock signals input from the outside, respectively, and N M-ary (M is a natural number of 3 or more) counters for counting the input clock signals; Each counter value of N M-ary counters and N clock signals are received as inputs, and a count of an M-ary counter that counts the currently selected clock signal among the input N clock signals. Selecting means for selecting, as the fastest clock signal, an input clock signal of an M-ary counter indicating a specific count value other than the predetermined value among the other (N-1) M-ary counters at a timing when the value becomes a predetermined value; It is characterized by having. In the present invention, the fastest clock signal having the highest frequency among the clock signals can be automatically selected.

  In order to achieve the above object, according to an eighth aspect of the present invention, N data signals synchronized with each of N clock signals (N is a natural number of 2 or more) having different frequencies transmitted from a transmission circuit. And a data receiving system used for a data transmission / reception system that receives the fastest clock signal that is a clock signal having the highest frequency among the N clock signals, the data receiving the N data signals transmitted from the transmission circuit Receiving means, a clock receiving means for receiving the fastest clock signal transmitted from the transmitting circuit, and N data signals received by the data receiving means are provided for each of the received input data signal and the clock receiving means. The phase information signal is generated by detecting the phase difference from the received fastest clock signal, and the received fastest clock signal is generated according to the logic level of the phase information signal. And N clock generation means for generating a generation clock signal of a pseudo frequency of the input data signal for retiming the input data signal by selecting the positive phase or the reverse phase of the clock signal. And

  In this invention, the clock generation means generates the clock signal that can reliably retime the data signal without error from the fastest clock signal, so that the delay time between the data signal and the fastest clock signal is automatically adjusted. it can.

  In order to achieve the above object, according to a ninth aspect, the clock generation means of the eighth aspect generates a phase information signal by detecting a phase difference between the received data signal and the received fastest clock signal. A phase detection means, an inverting means for inverting the polarity of the fastest clock signal, and a clock selection means for selecting the received fastest clock signal or the fastest clock signal inverted by the inverting means according to the logic level of the phase information signal; A clock signal generated by receiving a clock signal output from the clock selection means and removing a pulse whose pulse width is determined to be not the clock of the fastest clock signal (for example, ¼ clock length or less). It is characterized by comprising noise removing means for outputting as follows.

  Furthermore, in order to achieve the above object, according to a tenth aspect of the present invention, N data signals synchronized with each of N clock signals (N is a natural number of 2 or more) having different frequencies transmitted from a transmission circuit. Receiving circuit for receiving and transmitting data, and receiving means for receiving N data signals, and generating a fastest clock signal equal to or higher than the frequency of the clock signal having the highest frequency among the N clock signals. Provided for each of the N data signals received by the fastest clock generating means and the data receiving means, and detecting the phase difference between the received input data signal and the fastest clock signal generated by the fastest clock generating means. The input data signal is generated by generating an information signal and selecting the positive or negative phase of the fastest clock signal according to the logic level of the phase information signal. The characterized as having a N clock generating means for generating a pseudo-frequency generation clock signal of the input data signal for retiming. According to the present invention, since the clock signal synchronized with the data signal received in the receiving circuit can be generated, it is not necessary for the transmitting circuit to transmit all the clock signals including the fastest clock signal.

  According to the present invention, since the clock signal to be transmitted / received is only the fastest clock signal regardless of the number of data signals to be transmitted / received, the number of clock lines can be reduced, and a clock signal is input to the transmission circuit from the outside. Therefore, it is not necessary to provide a reference clock generator in the transmission circuit, and the configuration of the transmission circuit can be simplified.

  Further, according to the present invention, since the clock generating means in the receiving circuit generates the tooth missing clock without dividing the fastest clock signal as the non-fastest clock signal, an expensive device such as a VCO is used. The clock signal can be generated without using the circuit, the cost at the interface can be reduced, and even if the frequency difference of the clock signal is small, the circuit scale of the receiving circuit can be made smaller and cheaper than the frequency dividing circuit, Further, the receiving circuit can operate normally even if the frequency ratio with the fastest clock fluctuates.

  Also, according to the present invention, the fastest clock signal having the highest frequency is automatically selected by the fastest clock selection means, so that the fastest clock signal can be normally selected even if the fastest clock signal is switched.

  Further, according to the present invention, the clock generation means in the receiving circuit generates the clock signal that can reliably retime the data input signal without error from the fastest clock signal. The delay time with respect to the signal can be automatically adjusted, and even if a delay occurs, a reception error of the data signal does not occur on the receiving circuit side, and transmission can be performed without considering the clock timing.

  Further, according to the present invention, the clock line can be completely reduced by providing the fastest clock generating means on the receiving circuit side.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings. Here, in this specification, “rising” means a transition of the signal level from the base line to the top line, and “falling” means a transition from the top line to the base line. In this specification, the polarity of a signal is positive (that is, the base line is at a low level and the top line is at a high level). “H” represents a high level, and “L” represents a low level.

  FIG. 1 shows a system configuration diagram of an embodiment of a data transmission / reception system according to the present invention. The data transmission / reception system includes a transmission circuit 11 that transmits data and a clock signal, a reception circuit 12 that receives data and a clock signal, and a data transmission line provided between the transmission circuit 11 and the reception circuit 12. Data line 13 and a clock line 14 which is a transmission line for clock signals. The number of data lines 13 equal to the number of data transmitted / received in parallel is provided, and one clock line 14 is provided regardless of the number of data transmitted / received. In the present embodiment, a plurality of non-synchronized multiples having slightly different frequencies are used in a relatively short distance interface such as an interface between packages constituting the device or an interface between devices of the device placed in the same station. The number of clock signal lines is reduced to one.

  The transmission circuit 11 transmits the first data input signal A1, the second data input signal A2, and the third data input signal A3 to the reception circuit 12 through the data line 13, and is synchronized with the data input signal A1. The first clock signal A4, the second clock signal A5 synchronized with the data input signal A2 and the third clock signal A6 synchronized with the data input signal A3 are received as inputs, and the fastest clock selection means 111 receives these input clock signals. The clock signal having the highest frequency among A4 to A6 is selected as the fastest clock signal and transmitted to the receiving circuit 12 via the clock line 14.

  Here, the clock signals A4, A5, and A6 are asynchronous with each other, but have a frequency relationship that does not greatly differ in frequency. Since the clock signals A4, A5 and A6 are asynchronous with each other, the data signals A1, A2 and A3 are also asynchronous with each other.

  FIG. 2 is a block diagram showing an example of the fastest clock selection means 111 provided in the transmission circuit 11. As shown in FIG. 2, the fastest clock selection unit 111 includes a ternary counter 21, a ternary counter 22, a ternary counter 23, and a clock selector 24. The ternary counter 21 is configured by a loop counter that counts up at the timing when the first clock input signal A4 rises and sets the count value to the minimum count value “1” when the count value reaches the maximum count value “3”. The count value is always output as the first count signal A14. Similarly, the ternary counter 22 counts up at the timing when the second clock input signal A5 rises, and outputs the count value as the second count signal A15. Similarly, the ternary counter 23 counts up at the timing when the third clock input signal A6 rises, and outputs the count value as the third count signal A6.

  The clock selector 24 selects the clock having the highest frequency from the three clock input signals A4, A5, A6 (from N clock input signals when the number of input signals is N), and the fastest clock signal A13. Among the three input count signals A14, A15, A16 (of N count signals when the number of signals is N), the count value of the count signal corresponding to the currently selected clock At the timing when becomes “1”, the count value of the count signal corresponding to the clock not currently selected is confirmed. If the confirmed count value is “2”, the clock signal is output as the fastest clock signal A13 (if there are two or more count values of “2”, select one of them and select the fastest clock signal). Output as a clock signal A13), and an H reset signal A17 is output. If all of the confirmed count values are “3”, an H reset signal A17 is output.

  The reset signal A17 is supplied to each of the ternary counters 21, 22 and 23 (if the number of input signals is N, it is supplied to all N ternary counters), and each of the ternary counters 31, 32 and 33 is When the reset signal A17 is H, the count value is set to “1”. When the output of the reset signal A17 is H, the clock selector 24 outputs the L reset signal A17 at the falling timing of the fastest clock signal A13.

  When a counter other than the above ternary counter is used, it is necessary to set the clock selection condition of the clock selector 24 according to the counter. This embodiment is an example when the number of signals is three. However, when the number of signals is N, N ternary counters are required. Here, the ternary counter can be realized by an M-ary counter (M is a natural number of 3 or more). Also, the counting method can be realized by a method other than the above as long as the counter can count how many times the clock has come.

  Further, the fastest clock selection means in FIG. 2 is an example, and can be replaced by another fastest clock selection means that can select a clock having the highest frequency from a plurality of input clock signals.

  Returning again to FIG. The reception circuit 12 includes a clock generation unit 121, a clock generation unit 122, and a clock generation unit 123, and includes a first data input signal A1, a second data input signal A2, a third data input signal A3, and a fastest clock signal A13. The first data output signal A7, the second data output signal A8, the third data output signal A9, the first generated clock signal A10, the second generated clock signal A11, and the third generated clock signal. A12 is output.

  In the receiving circuit 12, the clock generation means 121 receives the fastest clock signal A13 and the data input signal A7 as inputs, and generates and outputs a first generated clock signal A10. Similarly, the clock generator 122 receives the fastest clock signal A13 and the second data input signal A8 as inputs, and generates and outputs a second generated clock signal A11. Similarly, the clock generator 123 receives the fastest clock signal A13 and the third data input signal A12 as inputs, and generates and outputs a third generated clock signal A12.

  Here, since the clock generation units 121, 122, and 123 have the same configuration, a configuration example of the clock generation unit 121 will be described as a representative. FIG. 3 shows a block diagram of an example of the clock generation means 121. As shown in the figure, the clock generation means 121 includes a phase detection means 31, an inverting circuit 32, a clock selector 33, and a noise removal means 34. The phase detector 31 detects the logic level (H / L) of the fastest clock signal A13 at the timing when the logic level (H / L) of the data input signal A1 changes, and outputs it as the phase information signal A21.

  The inverting circuit 32 generates an inverted clock of the fastest clock signal A13 and outputs it as the inverted clock A18. The clock selector 33 selects the fastest clock signal A13 or the inverted clock a18 according to the logic level (H / L) of the phase information signal A21 from the phase detector 31 and outputs the intermediate clock signal A24. The noise removing unit 34 removes a pulse having a certain width or less that is determined not to be a clock from the intermediate clock signal A24, and outputs it as a generated clock signal A10.

  Here, the phase detection means 31 detects that the phase difference between the data input signal A1 and the fastest clock signal A13 (or the generated clock signal A10) is greater than or equal to a certain value (or less than a certain value), and the detected result is the phase information signal A21. Can be substituted by other means for outputting as

  Further, the clock generation means of FIG. 3 is an implementation example, and another clock generation capable of generating a clock signal that can reliably retime the data input signal without error from the input fastest clock signal A13. It can be replaced by means.

  Next, the operation of the embodiment of FIG. 1 will be described using the timing charts shown in FIGS. In FIG. 1, when the data input signals A1, A2, and A3 shown in FIG. 4 are given to the transmission circuit 11, the transmission circuit 11 supplies the data input signals A1, A2, and A3 shown in FIG. When receiving the data input signals A1, A2, A3, the receiving circuit 12 outputs the received data input signals A1, A2, A3 as data output signals A7, A8, A9 shown in FIG.

  Further, the transmission circuit 11 includes a first clock input signal A4 synchronized with the data input signal A1, a second clock input signal A5 synchronized with the data input signal A2, and a data input signal as shown in FIGS. A third clock input signal A6 synchronized with A3 is supplied to the fastest clock selection means 111. The ternary counter 21 of the fastest clock means 111 having the configuration shown in FIG. 2 receives the clock input signal A4 as an input, and counts up as shown by the first count signal A14 in FIG. 5 at the rising edge of the clock signal A4. (When the count value is the maximum value “3”, it returns to the minimum value “1”), and the current count value is output to the clock selector 24 as the first count signal A14.

  Similarly, the ternary counter 22 shown in FIG. 2 counts up as indicated by A15 in FIG. 5 at the rising edge of the clock input signal A5 (when the count value is the maximum value “3”, the minimum value “1” is counted). The current count value is output to the clock selector 24 as the second count signal A15. Similarly, the ternary counter 23 counts up as indicated by A16 in FIG. 5 in accordance with the rise of the clock input signal A6 (when the count value is the maximum value “3”, it returns to the minimum value “1”). ), And outputs the current count value to the clock selector 24 as the third count signal A16.

  The clock selector 24 reads the count values of the other two count signals at the timing when the count value of the count signal corresponding to the currently selected clock input signal becomes “1”. If the read count value is “2”, the clock input signal corresponding to the count value is selected and output as the fastest clock signal (if there are multiple signals with the count value “2”, either And H reset signal A17 is output. When all the read count values are “3”, an H reset signal A17 is output.

  In the example of FIG. 5, the clock signal A4 is selected as the initial state. In this state, the count value of the count signal A16 read at the timing time t1 when the count value of the count signal A14 becomes “1” is “2”. Therefore, the clock selector 24 selects the clock input signal A6 corresponding to the count signal A14 instead of the clock input signal A4 selected so far, and outputs it as the fastest clock signal A13, and also resets H. The signal A17 is output as shown in FIG. In FIG. 5, when all the read count values are “3” at times t2, t3, and t4, an H reset signal A17 is output as shown in FIG. When the output of the reset signal A17 is H, the clock selector 24 outputs L to the reset signal A17 at the timing when the fastest clock signal A13 falls.

  In this way, the clock selector 24 selects the clock input signal having the highest frequency among the three clock input signals A4, A5, A6 as shown in FIG. 5 as the selection system clock, and outputs it as the fastest clock signal A13. Is done.

  Returning to FIG. 1 again, the receiving circuit 12 supplies the received fastest clock signal A13 to the clock generating means 121, the clock generating means 122, and the clock generating means 123. With the configuration shown in FIG. 3, the clock generation means 121 receives the data input signal A1 and the fastest clock signal A13 as inputs, and receives a clock signal that can reliably retime the data input signal A1 without error as the fastest clock signal A13. And output as a generated clock signal A10 shown in FIG.

  Similarly, the clock generation means 122 receives the data input signal A2 and the fastest clock signal A13 as inputs, and generates a clock signal from the fastest clock signal A13 that can reliably retime the data input signal A2 without error. 4 is generated as the generated clock signal A11. Similarly, the clock generator 123 receives the data input signal A3 and the fastest clock signal A13 as inputs, and generates a clock signal from the fastest clock signal A13 that can reliably retime the data input signal A3 without error. 4 is generated as a generated clock signal A12.

  Next, the operation of the clock generation means 121 having the configuration shown in FIG. 3 will be described with reference to the timing chart of FIG. In FIG. 3, the phase detector 31 detects the phase difference between the fastest clock signal A13 and the data input signal A1 shown in FIG. 6, and outputs a phase information signal A21 according to the amount of the phase difference. That is, when the fastest clock signal A13 and the data input signal A1 are input, the phase detector 31 internally generates a delay clock A27 whose phase is delayed by 90 degrees with respect to the fastest clock signal A13 as shown in FIG. At the timing when the logic level of the data input signal A1 changes, the logic level (H / L) of the delay clock A27 is latched and read, and the result is output as the phase information signal A21 shown in FIG. L is held until the timing at which the logic level of the next data input signal A1 changes).

  The inverting circuit 32 inverts the polarity of the fastest clock signal A13 and supplies it to the clock selector 33 as the inverted clock A18. The clock selector 33 selects the fastest clock signal A13 when the phase information signal A21 is H, and selects the inverted clock A18 when the phase information signal A21 is L. The clock signal selected by the clock selector 33 is output to the noise removing means 34 in FIG. 3 as the intermediate clock signal A24 shown in FIG.

  The noise removing means 34 receives the intermediate clock signal A24 as an input, removes a pulse whose pulse width is 1/4 clock length or less of the fastest clock signal A13, and outputs it as a generated clock signal A10 shown in FIG. The generated clock signal A10 output from the clock generation means 121 latches the logic level of the data input signal A1 received at the rising timing, so that the received data input signal A1 is retimed as indicated by A7 in FIG. Can be output as a data output signal.

  Although only the configuration of the clock generation unit 121 has been described here, the circuit configuration is the same as that of the clock generation unit 121 shown in FIG. 3 except that the clock generation unit 122 and the clock generation unit 123 also have different input / output signals. . Accordingly, as shown in FIG. 7, when the fastest clock signal A13 and the data input signal A2 are input, the clock generation means 122 generates a delay clock A28 and sets the logical level (H / L) of the delay clock A28. When the logical level of the data input signal A2 changes, it is latched and read, the result is output as the phase information signal A22, and the fastest clock signal A13 or its inverted clock is selected according to the logical level of the phase information signal A22. An intermediate clock signal A25 is generated, and a pulse whose pulse width is less than ¼ clock length of the fastest clock signal A13 is removed and output as a generated clock signal A11 shown in FIG.

  The generated clock signal A11 output from the clock generating means 122 latches the logic level of the data input signal A2 received at the rising timing thereof, so that the received data input signal A2 is retimed as indicated by A8 in FIG. Can be output as a data output signal.

  Similarly, as shown in FIG. 8, when the fastest clock signal A13 and the data input signal A3 are input, the clock generation means 123 generates a delay clock A29, and the logic level (H / L) of the delay clock A29. Is latched and read when the logic level of the data input signal A3 changes, the result is output as the phase information signal A23, and the fastest clock signal A13 or its inverted clock is selected according to the logic level of the phase information signal A23. The intermediate clock signal A26 is generated, and a pulse whose pulse width is equal to or less than ¼ clock length of the fastest clock signal A13 is removed and output as the generated clock signal A12 shown in FIG.

  The generated clock signal A12 output from the clock generating means 123 latches the logic level of the data input signal A3 received at the rising timing thereof, so that the received data input signal A3 is retimed as indicated by A9 in FIG. Can be output as a data output signal.

  FIG. 9A shows transmission data read from the data input signal A1 at the falling edge of the clock input signal A4, and FIG. 9B shows reception data read from the data output signal A7 at the rising edge of the generated clock signal A10. FIG. 8C shows transmission data read from the data input signal A2 at the falling edge of the clock input signal A5, and FIG. 10D shows reception data read from the data output signal A8 at the rising edge of the generated clock signal A11. FIG. 5E shows transmission data obtained by reading the data input signal A3 at the falling edge of the clock input signal 3, and FIG. 5F shows reception data read by the data output signal A9 at the rising edge of the generated clock signal A12.

  As described above, according to the present embodiment, only the fastest clock signal A13 needs to be transmitted regardless of the number of data signals to be transmitted / received, so that the number of clock lines can be reduced and the transmission circuit 11 includes Since the clock input signals A4, A5, A6 are input from the outside, it is not necessary to provide a reference clock generator in the transmission circuit 11, so that the configuration of the transmission circuit 11 can be simplified, and the reception circuit 12 is also connected to the clock signal. Compared with a configuration provided with means for separating / extracting a multiplexed signal from a data signal, a clock signal can be generated without using an expensive device such as a VCO, so the cost of the receiving circuit 12 can be reduced. In the present embodiment, the fastest clock signal having the highest frequency among the clock input signals A4, A5, and A6 is automatically selected by the fastest clock selection means 111 having the configuration shown in FIG. Even if is switched, the fastest clock signal can be normally selected.

  Further, according to the present embodiment, the clock generation means 121, 122, and 123 in the reception circuit 12 generates a toothless clock as a non-fastest clock signal without dividing the fastest clock signal. Therefore, even if the frequency difference between the clock input signals A4, A5 and A6 is small, the circuit scale of the receiving circuit 12 can be made smaller than that of the frequency dividing circuit, and it operates normally even if the frequency ratio with the fastest clock varies. can do. Furthermore, according to the present embodiment, the clock generation means 121, 122, and 123 generate a clock signal that can reliably retime the data input signal without error from the fastest clock signal. And the fastest clock signal can be automatically adjusted, and even if a delay occurs, no data signal reception error occurs on the receiving circuit side, and transmission can be performed without considering the clock timing.

  FIG. 10 shows a system configuration diagram of another embodiment of a data transmission / reception system according to the present invention. The data transmission / reception system includes a transmission circuit 41 that transmits a data signal, a reception circuit 42 that receives the data signal and generates a clock signal, and a data transmission line provided between the transmission circuit 41 and the reception circuit 42. Data line 43. The transmission circuit 41 transmits the first data input signal B1, the second data input signal B2, and the third data input signal B3 to the reception circuit 42 via the data line 43. The receiving circuit 42 is supplied from a clock generator 422, a clock generator 422, 423, and 424 to which a clock oscillated and output by the clock oscillator 421 is supplied in common and data input signals B1, B2, and B3 are separately input. The first data input signal B1, the second data input signal B2, and the third data input signal B3 are received, and the first data output signal B7, the second data output signal B8, and the third data output are received. The signal B9, the first generated clock signal B10, the second generated clock signal B11, and the third generated clock signal B12 are output.

  In the embodiment shown in FIG. 1, the fastest clock selection unit 111 of the transmission circuit 11 selects the clock signal that is input to the clock generation units 121, 122, and 123 in the reception circuit 12 and serves as a basis for generating the generated clock signal. In the embodiment shown in FIG. 10, instead of the fastest clock signal, it is installed in the receiving circuit 42 and has the same frequency as the fastest clock signal (however, the fastest clock signal The clock signal B13 output from the clock oscillator 421 that oscillates a clock signal having a frequency equal to or higher than the frequency is used.

  The clock generators 422, 423, and 424 are commonly supplied with the clock signal B13 output from the clock oscillator 421, and the received data input signals B1, B2, and B3 are input separately. The configuration shown in FIG. The generated clock signals B10, B11, and B12 are output with the same configuration as in FIG.

  The embodiment of FIG. 10 has the same features as those of the embodiment of FIG. 1, and further has no fastest clock selection means in the transmission circuit 41. Therefore, the configuration of the transmission circuit is the same as that of the embodiment of FIG. In addition to the simplification, the clock oscillator 421 in the receiving circuit 42 is provided, so that the clock line can be completely eliminated.

  Note that the present invention is not limited to the above embodiment, and in each embodiment of FIG. 1, the number of data input signals and the number of clock input signals is three, but each of them is N (N is two or more). (In this case, the receiving circuit requires N clock generating means and outputs N data output signals and N generated clock signals). In the embodiment of FIG. 10, the number of data lines may be N (in this case, the receiving circuit requires N clock generating means).

  Further, by providing a scramble / descramble circuit (inputting the pre-descrambled data to the clock generation means) to the data line of the transmission / reception circuit, a generated clock signal that does not cause an error even if the same signal continues is provided. Can be generated.

It is a system configuration figure of one embodiment of the invention. It is a block diagram of an example of the fastest clock selection means in FIG. It is a block diagram of an example of the clock generation means in FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 3 is a timing chart for explaining the operation of the fastest clock selection means in FIG. 2. 4 is a timing chart for explaining the operation of the clock generation means 121 of FIG. 3. 2 is a timing chart for explaining the operation of the clock generation means 122 of FIG. 2 is a timing chart for explaining the operation of the clock generation means 123 of FIG. 3 is a timing chart showing comparison of data on the transmission side and the reception side in FIG. 1. It is a system configuration | structure figure of other embodiment of this invention. It is a system configuration diagram of a conventional example. It is a system configuration diagram of another conventional example. It is a block diagram explaining the subject of patent document 1. FIG. It is a signal waveform diagram explaining an example of the multiplexing method of a clock and data.

Explanation of symbols

11, 41 Transmission circuit 12, 42 Reception circuit 13, 43 Data line 14 Clock line 21, 22, 23 Ternary counter 24 Clock selector 31 Phase detection means 32 Inversion circuit 33 Clock selector 34 Noise removal means 111 Fastest clock selection means 121, 122, 123, 422, 423, 424 Clock generation means 421 Clock oscillator

Claims (10)

A data transmission / reception system in which N data signals synchronized with N clock signals having different frequencies (N is a natural number of 2 or more) are transmitted separately from a transmission circuit to a reception circuit via N data lines. There,
The transmission circuit transmits the N data signals that are asynchronous with each other, and selects a clock signal having the highest frequency among the N clock signals input from the outside to supply the fastest clock to the reception circuit. It is configured to output as a signal,
The receiving circuit is
Data receiving means for receiving the N data signals transmitted from the transmitting circuit;
Clock receiving means for receiving the fastest clock signal transmitted from the transmission circuit;
Controlling the phase of the fastest clock signal received based on the phase shift amount of the rising or falling edge of the fastest clock signal received by the clock receiving means at the logic change timing of the data signal received by the data receiving means. A data transmission / reception system comprising: N clock generation means for generating a generation clock signal having a pseudo frequency of the input data signal for retiming the input data signal. A data transmission / reception system in which N data signals synchronized with N clock signals having different frequencies (N is a natural number of 2 or more) are transmitted separately from a transmission circuit to a reception circuit via N data lines. There,
The transmission circuit includes:
Data output means for outputting the N data signals in an asynchronous relationship to the N data lines;
A fastest clock selecting means for selecting a clock signal having the highest frequency among the N clock signals inputted from the outside and outputting it as the fastest clock signal to the receiving circuit via one clock line;
The receiving circuit is
Data receiving means for receiving the N data signals via the N data lines;
Clock receiving means for receiving the fastest clock signal via the one clock line;
Provided for each of the N data signals received by the data receiving means, and detecting a phase difference between the received input data signal and the fastest clock signal received by the clock receiving means to obtain a phase information signal Generating and selecting the normal phase or the reverse phase of the received fastest clock signal according to the logic level of the phase information signal, thereby mimicking the input data signal for retiming the input data signal A data transmission / reception system comprising: N clock generation means for generating a frequency generation clock signal. The fastest clock selection means includes:
The N clock signals input from the outside are separately supplied, and N M-ary (M is a natural number of 3 or more) counters for counting the input clock signals;
Each of the M M-counter counter values and the N clock signals are received as inputs, and the currently selected clock signal is counted among the N clock signals input. The input clock signal of the M-ary counter that indicates a specific count value other than the predetermined value among the other (N-1) M-ary counters at the timing when the count value of the hexadecimal counter reaches a predetermined value is used as the fastest clock signal. The data transmission / reception system according to claim 2, further comprising selection means for selecting. The clock generation means includes
Phase detection means for detecting a phase difference between the received data signal and the received fastest clock signal to generate a phase information signal;
Inverting means for inverting the polarity of the fastest clock signal;
Fastest clock selection means for selecting the received fastest clock signal or the fastest clock signal inverted by the inverting means according to the logic level of the phase information signal;
The clock signal output from the fastest clock selection means is received as an input, and a pulse whose pulse width is determined to be not the clock of the fastest clock signal is removed (for example, ¼ clock length or less). The data transmission / reception system according to claim 2, further comprising: a noise removing unit that outputs the generated clock signal. A data transmission / reception system in which N data signals synchronized with N clock signals having different frequencies (N is a natural number of 2 or more) are transmitted separately from a transmission circuit to a reception circuit via N data lines. There,
The transmission circuit includes data output means for outputting the N data signals in an asynchronous relationship to the N data lines;
The receiving circuit is
Data receiving means for receiving the N data signals via the N data lines;
A fastest clock generating means for generating a fastest clock signal having a frequency equal to or higher than a frequency of a clock signal having the highest frequency among the N clock signals;
A phase information signal is provided for each of the N data signals received by the data receiving means and detects a phase difference between the received input data signal and the fastest clock signal generated by the fastest clock generating means. The pseudo frequency of the input data signal for retiming the input data signal by selecting the positive phase or the reverse phase of the fastest clock signal according to the logic level of the phase information signal A data transmission / reception system comprising: N clock generation means for generating the generated clock signal. In a transmission circuit used in a data transmission / reception system for transmitting N data signals synchronized with each of N clock signals of different frequencies (N is a natural number of 2 or more) to the reception circuit,
Data output means for transmitting the N data signals in an asynchronous relationship with each other;
And a fastest clock selecting means for selecting a clock signal having the highest frequency among the N clock signals inputted from the outside and outputting it as the fastest clock signal to the receiving circuit. The fastest clock selection means includes:
The N clock signals input from the outside are separately supplied, and N M-ary (M is a natural number of 3 or more) counters for counting the input clock signals;
Each of the M M-counter counter values and the N clock signals are received as inputs, and the currently selected clock signal is counted among the N clock signals input. The input clock signal of the M-ary counter that indicates a specific count value other than the predetermined value among the other (N-1) M-ary counters at the timing when the count value of the hexadecimal counter reaches a predetermined value is used as the fastest clock signal. The transmission circuit according to claim 6, further comprising selection means for selecting. N data signals transmitted from the transmission circuit and synchronized with N clock signals of different frequencies (N is a natural number of 2 or more) and a clock signal having the highest frequency among the N clock signals A receiving circuit used in a data transmission / reception system for receiving the fastest clock signal,
Data receiving means for receiving the N data signals transmitted from the transmitting circuit;
Clock receiving means for receiving the fastest clock signal transmitted from the transmission circuit;
Provided for each of the N data signals received by the data receiving means, and detecting a phase difference between the received input data signal and the fastest clock signal received by the clock receiving means to obtain a phase information signal Generating and selecting the normal phase or the reverse phase of the received fastest clock signal according to the logic level of the phase information signal, thereby mimicking the input data signal for retiming the input data signal A receiving circuit comprising: N clock generating means for generating a frequency generation clock signal. The clock generation means includes
Phase detection means for detecting a phase difference between the received data signal and the received fastest clock signal to generate a phase information signal;
Inverting means for inverting the polarity of the fastest clock signal;
Clock selection means for selecting the received fastest clock signal or the fastest clock signal inverted by the inverting means according to the logic level of the phase information signal;
The clock signal output from the clock selection means is received as an input, and a pulse whose pulse width is determined to be not the clock of the fastest clock signal is removed to remove a pulse having a certain width or less (for example, ¼ clock length or less). 9. The receiving circuit according to claim 8, further comprising: a noise removing unit that outputs the generated clock signal. A receiving circuit used in a data transmission / reception system for receiving N data signals transmitted from a transmitting circuit and synchronized with N clock signals of different frequencies (N is a natural number of 2 or more).
Data receiving means for receiving the N data signals;
A fastest clock generating means for generating a fastest clock signal having a frequency equal to or higher than a frequency of a clock signal having the highest frequency among the N clock signals;
A phase information signal is provided for each of the N data signals received by the data receiving means and detects a phase difference between the received input data signal and the fastest clock signal generated by the fastest clock generating means. The pseudo frequency of the input data signal for retiming the input data signal by selecting the positive phase or the reverse phase of the fastest clock signal according to the logic level of the phase information signal And N clock generating means for generating the generated clock signal.

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