JP2015012400A - Image processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce influence of an error in a synchronization signal caused by noise or the like on image quality on the reception side, when the synchronization signal is transmitted together with image data by serial communication.SOLUTION: An internal synchronization signal generation part 12 generates an internal synchronization signal having the same pulse period as a prescribed pulse period of an external synchronization signal. A data reception processing part 13 extracts image data and the external synchronization signal from a received transmission signal, and sequentially writes the image data into a line memory for each line on the basis of the internal synchronization signal. A line data reading part 14 sequentially reads out the image data from the line memory for each line on the basis of the internal synchronization signal. When an error detection part 17 detects that a pulse period of the internal synchronization signal and that of the external synchronization signal are not the same, the error detection part 17 causes image data written in a line memory in the pulse period of the internal synchronization signal to be discarded.

Description

  The present invention relates to an image processing apparatus.

  For example, there is a technique for transmitting image data by high-speed serial communication such as LVDS (Low Voltage Differential Signaling).

  When receiving image data by such high-speed serial communication, on the receiving side, for example, one line of pixel data is written to the line memory one pixel at a time using an external clock, and a synchronization signal is generated inside the receiving side. The line memory in which the image data is written is switched among the two line memories in accordance with the generated synchronization signal (see, for example, Patent Document 1).

JP 2012-56161 A

  For example, in a high-speed serial communication technology such as LVDS, it is possible to transmit a synchronization signal together with image data using a serial communication cable. The synchronization signal is a signal that designates synchronization timing with a synchronization pulse.

  When transmitting a synchronization signal together with image data, if noise such as electrostatic noise occurs in the serial communication cable during transmission, an erroneous pulse due to noise is detected in the synchronization signal on the receiving side, and an incorrect synchronization timing is detected. The sync pulse may be lost due to noise and the sync timing may not be detected correctly.

  If the synchronization signal is not correctly detected in this way, the start and end of the image data for one line is not set correctly, and the image data cannot be written accurately to the line memory line by line.

  For example, when an erroneous synchronization timing due to noise is detected, the number of lines of the image increases, and not only the image of the line in which the noise is generated is disturbed, but also the image is disturbed in the subsequent lines.

  Further, for example, when the synchronization pulse disappears due to noise, the number of lines of the image is reduced, and not only the image of the line where the noise is generated is disturbed, but also the image is disturbed in the subsequent lines.

  Such noise can be reduced by installing a shield on the serial communication cable, but this increases the cost and is not preferable.

  In addition, after converting the received serial data to parallel data on the receiving side, a digital filter may be applied to the parallel data to remove such noise. Therefore, it is difficult to selectively remove noise with a digital filter.

  The present invention has been made in view of the above problems, and when transmitting a synchronization signal together with image data by serial communication, the receiving side writes the image data into the line memory line by line according to the synchronization signal. An object of the present invention is to obtain an image processing apparatus that reduces the influence on the image quality of the error of the synchronization signal due to noise or the like.

  An image processing apparatus according to the present invention includes a receiving circuit that receives a transmission signal including image data and an external synchronization signal through serial communication, and an internal synchronization signal that generates an internal synchronization signal having the same pulse period as a specified pulse period of the external synchronization signal. Synchronizing signal generating unit, extracting the image data and the external synchronizing signal from the received transmission signal, sequentially switching the line memory for writing the image data for each line based on the internal synchronizing signal, A data reception processing unit that writes the image data to the line memory and a line memory that reads the image data for each line based on the internal synchronization signal are sequentially switched, and a line that reads the image data from the line memory. A data reading unit; and a pulse period detecting unit for detecting a pulse period of the external synchronization signal; When detecting that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, error detection for discarding the image data written in the line memory in the pulse period of the internal synchronization signal A part.

  According to the present invention, when a synchronization signal is transmitted together with image data by serial communication, noise or the like is caused when writing the image data to the line memory line by line according to the synchronization signal transmitted together with the image data. The influence of the error of the synchronization signal on the image quality is reduced.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a transmission signal. FIG. 3 is a flowchart for explaining the operation of the error detection unit 17 in FIG. FIG. 4 is a timing chart illustrating each signal when no error is detected, count values of the counters C1, C2, and C3, and writing and reading of image data to and from the line memories LM1 and LM2. FIG. 5 illustrates each signal when the noise pulse is superimposed on the external synchronization signal and an error is detected, the count values of the counters C1, C2, and C3, and the writing and reading of the image data to and from the line memories LM1 and LM2. It is a timing chart to do. FIG. 6 shows each signal when the synchronization pulse of the external synchronization signal disappears due to a noise pulse and an error is detected, the count values of the counters C1, C2, and C3, and the writing of image data to the line memories LM1 and LM2. It is a timing chart explaining reading. FIG. 7 shows each signal when an error is detected due to a phase shift between the internal synchronization signal and the external synchronization signal, count values of the counters C1, C2, and C3, and image data for the line memories LM1 and LM2. 6 is a timing chart for explaining writing and reading of data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. The image processing apparatus shown in FIG. 1 is an image reading apparatus that optically reads a document image line by line, generates image data of the document image, and outputs it.

  The image processing apparatus shown in FIG. 1 includes a CCD (Charge Coupled Device) 1, an analog front end (AFE) 2, a transmission circuit 3, a serial transmission path 4, and a data processing apparatus 5.

  The CCD 1 is an image sensor that optically reads, for example, a document image and outputs an analog signal corresponding to the image.

  The AFE 2 is a circuit that performs sampling, A / D (Analog to Digital) conversion, and the like on an analog signal output from the CCD 1 and outputs a digital signal corresponding to the analog electric signal.

  The transmission circuit 3 is a circuit that sends a transmission signal obtained from a digital signal to a serial transmission line 4 such as a twisted pair cable by a predetermined high-speed serial communication method such as LVDS. The transmission circuit 3 includes a serializer.

  The transmission circuit 3 transmits a transmission signal including image data and an external synchronization signal by serial communication. The external synchronization signal is a signal for dividing the image data for each line by a synchronization pulse. The transmission signal is time-divided into a plurality of time slots in synchronization with the clock, and the external synchronization signal is transmitted in one of the plurality of time slots. The external synchronization signal has a low level synchronization pulse.

  FIG. 2 is a diagram illustrating an example of a transmission signal. For example, as shown in FIG. 2, the transmission signal is divided into seven time slots, one of which is used for transmission of the external synchronization signal. One time slot has a time length of a clock cycle length CL.

  The data processing device 5 is connected to the transmission circuit 3 through the serial transmission path 4, receives the transmission signal transmitted from the transmission circuit 3, and outputs image data obtained from the transmission signal line by line.

  The data processing device 5 includes a reception circuit 11, an internal synchronization signal generation unit 12, a data reception processing unit 13, a line data reading unit 14, a clock generation unit 15, a pulse period detection unit 16, an error detection unit 17, and line memories LM1 and LM2. , And counters C1, C2, C3.

  The receiving circuit 11 receives a transmission signal including image data and an external synchronization signal by serial communication. In this embodiment, the receiving circuit 11 includes a deserializer.

  Note that the external synchronization signal included in the transmission signal by the transmission circuit 3 has a synchronization pulse at a predetermined specified pulse period. However, in the serial transmission path 4, the noise pulse is externally synchronized at a timing different from the synchronization pulse. The sync pulse may be superposed on the signal, or the sync pulse may disappear from the external sync signal due to the noise pulse.

  The internal synchronization signal generator 12 generates an internal synchronization signal having the same pulse period as the specified pulse period of the external synchronization signal (that is, the period of the external synchronization signal on the transmission circuit 3 side).

  The data reception processing unit 13 extracts the image data and the external synchronization signal from the received transmission signal, and extracts the image data for each line based on the internal synchronization signal having the same pulse period as the specified pulse period of the external synchronization signal. The line memory to be written is sequentially switched (here, the line memories LM1 and LM2 are alternately switched), and the image data is written to the line memories LM1 and LM2.

  The line data reading unit 14 sequentially switches the line memories LM1 and LM2 for reading out image data for each line based on an internal synchronization signal having the same pulse period as the prescribed pulse period of the external synchronization signal. Read from the line memories LM1, LM2. That is, the line data reading unit 14 reads the image data from the line memories LM1 and LM2 that are not written by the data reception processing unit 13 line by line based on the internal synchronization signal, and sends the image data to a subsequent image processing unit (not shown). Output.

  The clock generation unit 15 generates a clock from the received transmission signal. That is, the clock generation unit 15 generates a clock having the above-described cycle length CL.

  The pulse period detector 16 detects the pulse period of the external synchronization signal (here, the time from the rising edge of the pulse to the rising edge of the next pulse).

  When the error detection unit 17 detects that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, the error detection unit 17 stores the line synchronization (line memory LM1 or line memory LM2) in the pulse period of the internal synchronization signal. Discard the written image data.

  In this embodiment, when the error detection unit 17 detects that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, the data reception processing unit 13 switches the line memories LM1 and LM2. By prohibiting and overwriting the subsequent image data in the line memory (line memory LM1 or line memory LM2), the image data written in the line memory in the pulse cycle of the internal synchronization signal is discarded.

  In addition, the error detection unit 17 continues in a predetermined number of cycles (three cycles in this embodiment) of the internal synchronization signal, and the timing of the synchronization pulse of the internal synchronization signal and the timing of the pulse of the external synchronization signal are not the same. When it is detected that there is no signal, the timing of the synchronization pulse of the internal synchronization signal is synchronized with the timing of the pulse of the external synchronization signal.

  The line memories LM1 and LM2 are memories having a storage area for storing image data for at least one line.

  The counter C1 counts up to a predetermined count value (a value corresponding to the above-described prescribed pulse period) with the clock generated by the clock generation unit 15 and resets the counter.

  The counter C2 is incremented by the clock generated by the clock generator 15 and reset by the pulse of the external synchronization signal. Note that the pulse of the external synchronization signal is a synchronization pulse or a noise pulse.

  In this embodiment, the internal synchronization signal generator 12 generates a synchronization pulse of the internal synchronization signal when the count value of the counter C1 is a predetermined count value. Then, when the count value of the counter C1 and the count value of the counter C2 are not the same, the error detection unit 17 determines that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, and the internal synchronization The image data written in the line memory (line memory LM1 or line memory LM2) in the pulse cycle of the signal is discarded.

  Further, in this embodiment, the error detection unit 17 determines that the timing of the synchronization pulse of the internal synchronization signal and the timing of the pulse of the external synchronization signal are not the same in a predetermined number of cycles of the internal synchronization signal. When detected, the count value of the second counter is copied to the first counter, and the timing of the synchronization pulse of the internal synchronization signal is synchronized with the timing of the pulse of the external synchronization signal.

  The counter C3 counts the number of times that the error detection unit 17 has continuously detected that the timing of the synchronization pulse of the internal synchronization signal and the timing of the pulse of the external synchronization signal are not the same.

  The data processing device 5 is realized by, for example, an ASIC (Application Specific Integrated Circuit).

  Next, the operation of the image processing apparatus will be described.

  In this image processing apparatus, a receiving circuit 11 receives a transmission signal, a data reception processing unit 13 alternately writes image data obtained from the transmission signal in the line memories LM1 and LM2, and a line data reading unit 14 Image data is alternately read out from the memories LM1 and LM2 line by line.

  On the other hand, the internal synchronization signal generation unit 12 generates the internal synchronization signal, the pulse cycle detection unit 16 detects the pulse cycle of the external synchronization signal obtained from the transmission signal, and the error detection unit 17 detects the internal synchronization signal. Based on the pulse period and the pulse period of the external synchronization signal, an error in the transmission signal is detected as follows, switching of the line memories LM1 and LM2 is prohibited, and the image data of the line in which the error has occurred is discarded.

  Note that reading of image data from the line memories LM1 and LM2 is executed in accordance with the internal synchronization signal, so in the image data read from the line memories LM1 and LM2, increase / decrease of lines due to an error in the external synchronization signal occurs. do not do.

  FIG. 3 is a flowchart for explaining the operation of the error detection unit 17 in FIG.

  The error detection unit 17 determines whether either the current count value of the counter C1 or the current count value of the counter C2 is zero for each clock generated by the clock generation unit 15 (step S1).

  If any of the counters C1 and C2 is zero, the error detection unit 17 determines whether or not both are equal (step S2).

  If there is no error in the external synchronization signal, the pulse period of the internal synchronization signal and the pulse period of the external synchronization signal are the same, and if the pulse period of the internal synchronization signal and the pulse period of the external synchronization signal are the same, the counter C1 The count value is equal to the count value of the counter C2.

  For this reason, the error detection unit 17 sets the error detection signal to a low level (step S3). Further, the error detection unit 17 resets the counter C3 (that is, sets the counter value to zero) (step S4).

  In this embodiment, the error detection unit 17 sets an error detection signal that sets a low level when switching between the line memories LM1 and LM2 is permitted and sets a high level when switching between the line memories LM1 and LM2 is prohibited. The data reception processing unit 13 and the line data reading unit 14 supply the data reception processing unit 13 and the line data reading unit 14 when the internal synchronization signal is at a low level based on the level of the error detection signal. It is determined whether or not the line memories LM1 and LM2 to be written and read are switched.

  As described above, when an error does not occur in the external synchronization signal continuously, the error detection unit 17 continuously permits the switching of the line memories LM1 and LM2 in the data reception processing unit 13 and the line data reading unit 14. To do.

  FIG. 4 is a timing chart illustrating each signal when no error is detected, count values of the counters C1, C2, and C3, and writing and reading of image data to and from the line memories LM1 and LM2.

  In FIG. 4, “reception data” is image data of each line obtained by the data reception processing unit 13, and “write enable signal” is supplied to the line memories LM1 and LM2.

  In the example shown in FIG. 4, when the pulse period of the external synchronization signal is set to 10 times the cycle length CL of the clock and the count value of the counter C1 is 9, a synchronization pulse is generated in the internal synchronization signal. The

  When no error occurs in the external sync signal, no pulse is generated in the external sync signal except for the timing of the sync pulse of the internal sync signal, so the pulse cycle of the external sync signal is the same as the pulse cycle of the internal sync signal Thus, the error detection signal continues to be at a low level, and switching of the line memories LM1 and LM2 is continuously permitted. Therefore, image data is written to the line memories LM1 and LM2 alternately line by line, and image data is read from the line memories LM1 and LM2 alternately line by line.

  On the other hand, when the error detection unit 17 determines in step S2 that the current count value of the counter C1 is not equal to the current count value of the counter C2, the error detection unit 17 sets the error detection signal to a high level. (Step S6). Thereby, switching of the line memories LM1 and LM2 in the data reception processing unit 13 and the line data reading unit 14 is prohibited. At this time, if the value of the counter C1 is zero (step S6), the count value of the counter C3 is increased by 1 (step S7).

  Then, the error detection unit 17 determines whether or not the count value of the counter C3 is equal to or greater than a predetermined value (3 in this case) (step S8).

  The count value of the counter C3 indicates the number of times that the count values of the counters C1 and C2 are continuously determined to be not equal. Normally, errors due to noise such as electrostatic noise are unlikely to occur continuously for a long time, and therefore, it is rarely determined that the count values of the counters C1 and C2 are not equal for three lines or more.

  Therefore, when it is determined in step S2 that the current count value of the counter C1 is not equal to the current count value of the counter C2 due to noise, the count value of the counter C3 is 2 or less, and the error detection unit 17 In step S9, it is determined that the count value of the counter C3 is not 3 or more. That is, before the count value of the counter C3 becomes 3 or more, the count values of the counters C1 and C2 become equal, and the counter C3 is reset in step S3.

  FIG. 5 illustrates each signal when the noise pulse is superimposed on the external synchronization signal and an error is detected, the count values of the counters C1, C2, and C3, and the writing and reading of the image data to and from the line memories LM1 and LM2. It is a timing chart to do.

  As shown in FIG. 5, when a noise pulse is superimposed on the external synchronization signal, the count values of the counters C1 and C2 are different at the timing T1, so that the error detection signal is changed to a high level, and the line memories LM1 and LM2 Switching is prohibited. Therefore, data writing is continuously executed to the line memory LM1, and data is sequentially overwritten.

  Thereafter, when the error disappears (timing T2), the error detection signal is changed to the low level, and switching of the line memories LM1 and LM2 is permitted in the next cycle (at timing T3).

  By doing so, the image data for one line (that is, the image data having no error) written in the first period (period T2 to T3) after the error disappears is switched between the line memories LM1 and LM2. Read when resumed.

  FIG. 6 shows each signal when the synchronization pulse of the external synchronization signal disappears due to a noise pulse and an error is detected, the count values of the counters C1, C2, and C3, and the writing of image data to the line memories LM1 and LM2. It is a timing chart explaining reading.

  As shown in FIG. 6, when the synchronization pulse between the first line and the second line disappears in the external synchronization signal, the count values of the counters C1 and C2 are different at the timing T4 of the synchronization pulse of the internal synchronization signal. The error detection signal is changed to high level, and switching of the line memories LM1 and LM2 is prohibited. Therefore, data writing is continuously executed to the line memory LM2, and data is sequentially overwritten.

  Thereafter, when the error disappears (timing T5), the error detection signal is changed to the low level, and switching of the line memories LM1 and LM2 is permitted in the next cycle (at timing T6).

  By doing so, the image data for one line (that is, image data without error) written in the first period (period T5 to T6) after the error disappears is switched between the line memories LM1 and LM2. Read when resumed.

  Returning to FIG. 3, on the other hand, it is considered that the count value of the above-mentioned counter C3 being 3 or more is due to a phase shift between the external synchronization signal and the internal synchronization signal, and in step S8, the error detection unit 17 When it is determined that the count value of C3 is 3 or more, the count value of the counter C2 is set in the counter C1 (step S9). However, the synchronization pulse of the internal synchronization signal at this time is masked. Thus, since the count value of the counter C1 is synchronized with the count value of the counter C2, it is determined that the count values of the counters C1 and C2 are equal at the determination timing of the next step S1 (if there is no error due to noise). (Step S2).

  In this way, even if a phase difference occurs between the external synchronization signal and the internal synchronization signal, synchronization between the two is automatically ensured. Further, since the phase of the internal synchronization signal is matched to the phase of the external synchronization signal, the line memories LM1 and LM2 are switched substantially in synchronization with the external synchronization signal without error.

  FIG. 7 shows each signal when an error is detected due to a phase shift between the internal synchronization signal and the external synchronization signal, count values of the counters C1, C2, and C3, and image data for the line memories LM1 and LM2. 6 is a timing chart for explaining writing and reading of data.

  As shown in FIG. 7, after an error is detected at timing T7, if the error is detected continuously for three cycles, the count value of the counter C3 becomes 3, and the internal value when the count value of the counter C3 is 3 is shown. At the timing T8 of the synchronization pulse of the synchronization signal, the count value of the counter C2 is set to the counter C1 (however, this synchronization pulse itself is masked and not generated). As a result, the error detection signal is set to the low level at the next synchronization pulse (timing T9) of the internal synchronization signal, and switching of the line memories LM1 and LM2 is resumed at the next cycle (at timing T10).

  By doing so, the image data for one line (that is, the synchronized image data) written in the first period (period T9 to T10) while ensuring synchronization is stored in the line memories LM1 and LM2. Read when switching is resumed.

  In this case, as shown in FIG. 7, the write enable signal is set to the low level from the time when the count value of the counter C2 is set to the counter C1 until the next synchronization pulse (that is, during the period from timing T8 to T9). The writing to the line memories LM1 and LM2 is prevented from occurring.

  As described above, according to the above-described embodiment, the reception circuit 11 receives a transmission signal including image data and an external synchronization signal by serial communication, and the internal synchronization signal generation unit 12 has a specified pulse period of the external synchronization signal. The data reception processing unit 13 extracts the image data and the external synchronization signal from the received transmission signal, and writes the image data for each line based on the internal synchronization signal. The line memories LM1 and LM2 are switched in order, and the image data is written into the line memories LM1 and LM2. When the pulse period detection unit 16 detects the pulse period of the external synchronization signal and the error detection unit 17 detects that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, The image data written in the line memory (line memory LM1 or line memory LM2) in the pulse period of the synchronization signal is discarded.

  As a result, when the synchronization signal is transmitted together with the image data by serial communication, due to noise or the like when the image data is written to the line memories LM1 and LM2 line by line according to the synchronization signal transmitted together with the image data. The influence of the error of the synchronization signal on the image quality is reduced.

  The above-described embodiments are preferred examples of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. is there.

  The present invention is applicable to, for example, an image reading apparatus.

DESCRIPTION OF SYMBOLS 11 Reception circuit 12 Internal synchronous signal generation part 13 Data reception process part 14 Line data reading part 15 Clock generation part 16 Pulse period detection part 17 Error detection part C1 counter (an example of 1st counter)
C2 counter (example of second counter)
LM1, LM2 line memory

Claims (6)

A receiving circuit for receiving transmission signals including image data and an external synchronization signal by serial communication;
An internal synchronization signal generating unit that generates an internal synchronization signal having the same pulse period as the specified pulse period of the external synchronization signal;
The image data and the external synchronization signal are extracted from the received transmission signal, a line memory in which the image data is written is sequentially switched for each line based on the internal synchronization signal, and the image data is converted to the line A data reception processing unit for writing to the memory;
A line data reading unit for sequentially switching a line memory for reading out the image data for each line based on the internal synchronization signal, and reading out the image data from the line memory;
A pulse period detector for detecting a pulse period of the external synchronization signal;
When detecting that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, error detection for discarding the image data written in the line memory in the pulse period of the internal synchronization signal And
An image processing apparatus comprising: A clock generator for generating a clock from the transmission signal;
A first counter that counts up to a predetermined count value with the clock and resets;
A second counter that counts up with the clock and resets with a pulse of the external synchronization signal;
The internal synchronization signal generation unit generates a synchronization pulse of the internal synchronization signal when the count value of the first counter is the predetermined count value,
The error detection unit determines that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same when the count value of the first counter and the count value of the second counter are not the same. And discarding the image data written in the line memory in the pulse period of the internal synchronization signal,
The image processing apparatus according to claim 1.   When the error detection unit detects that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same, the error detection unit prohibits switching of the line memory by the data reception processing unit, The image processing apparatus according to claim 1, wherein the image data written in the line memory is discarded in the pulse cycle of the internal synchronization signal by overwriting the image data in the line memory.   When the error detection unit detects that the timing of the synchronization pulse of the internal synchronization signal is not the same as the timing of the pulse of the external synchronization signal continuously in a predetermined number of cycles of the internal synchronization signal, 2. The image processing apparatus according to claim 1, wherein the timing of the synchronization pulse of the internal synchronization signal is synchronized with the timing of the pulse of the external synchronization signal. A clock generator for generating a clock from the transmission signal;
A first counter that counts up to a predetermined count value with the clock and resets;
A second counter that counts up with the clock and resets with a pulse of the external synchronization signal;
The internal synchronization signal generation unit generates a synchronization pulse of the internal synchronization signal when the count value of the first counter is the predetermined count value,
The error detection unit determines that the pulse period of the external synchronization signal and the pulse period of the internal synchronization signal are not the same when the count value of the first counter and the count value of the second counter are not the same. The image data written in the line memory in the pulse period of the internal synchronization signal is discarded,
Further, when the error detection unit detects that the timing of the synchronization pulse of the internal synchronization signal and the timing of the pulse of the external synchronization signal are not the same continuously in a predetermined number of cycles of the internal synchronization signal Copying the count value of the second counter to the first counter to synchronize the timing of the synchronization pulse of the internal synchronization signal with the timing of the pulse of the external synchronization signal;
The image processing apparatus according to claim 4. The transmission signal is time-divided into a plurality of time slots in synchronization with the clock,
The external synchronization signal is transmitted in one of the plurality of time slots;
The image processing apparatus according to claim 1, wherein:

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