JP2008203459A - Driving method of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel driving method which can improve the display performance of brightness gradient when displaying dark images. <P>SOLUTION: This driving method carries out a resetting step of dividing one field period of video signals into two or more subfields and of initializing the pixel cells in the first subfield. The resetting step sequentially carries out a first step of applying to one of the pair of the line electrodes a first pulse negative with respect to the other line electrode and the column electrodes, a second step of applying to it a second pulse positive with respect to the column electrodes, and a third step of applying to it a third pulse negative with respect to the other line electrode and the column electrodes. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  At present, an AC type (AC discharge type) plasma display panel (hereinafter referred to as PDP) has been commercialized as a thin display device. In the PDP, two substrates, that is, a front transparent substrate and a rear substrate are arranged to face each other with a predetermined gap. On the inner surface of the front transparent substrate (surface facing the rear substrate) as a display surface, a plurality of row electrode pairs that are paired with each other and extend in the horizontal direction of the screen are formed. Furthermore, a dielectric layer covering each row electrode pair is formed on the inner surface of the front transparent substrate. On the other hand, on the back substrate side, a plurality of column electrodes extending in the vertical direction of the screen are formed so as to cross the row electrode pairs. When viewed from the display surface side, pixel cells corresponding to the pixels are formed at the intersections between the row electrode pairs and the column electrodes.

  In order to obtain halftone display luminance corresponding to the input video signal, gradation driving using the subfield method is performed on such a PDP.

  In gradation driving based on the subfield method, display driving is performed on a video signal for one field in each of a plurality of subfields to which the number of times (or periods) of light emission is assigned. In each subfield, an address process and a sustain process are executed sequentially. In the address process, a selective discharge is selectively generated between the row electrode and the column electrode in each pixel cell in accordance with the input video signal to form (or erase) a predetermined amount of wall charges. In the sustain process, only the pixel cells in which a predetermined amount of wall charges are formed are repeatedly discharged, and the light emission state associated with the discharge is maintained. Further, a reset process is executed prior to the address process in at least the first subfield. In such a reset process, the amount of wall charges remaining in all the pixel cells is initialized by causing a reset discharge between the paired row electrodes in all the pixel cells.

  Here, the reset discharge is a relatively strong discharge and has nothing to do with the content of the image to be displayed, so there is a problem that the light emission accompanying this discharge reduces the contrast of the image. .

Therefore, the discharge delay time is reduced by attaching a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak within a wavelength of 200 to 300 nm to the surface of the dielectric layer covering the row electrode pair. A shortened PDP and its driving method have been proposed (see, for example, Patent Document 1). According to such a PDP, the priming effect after the discharge continues for a relatively long time, so that a weak discharge can be stably generated. Therefore, a weak reset discharge is generated between adjacent row electrodes by applying to the row electrodes of the PDP as described above a reset pulse having a pulse waveform in which the voltage value gradually reaches the peak voltage value over time. I tried to make it. At this time, the light emission luminance associated with the discharge is reduced due to the weakening of the reset discharge, so that the contrast of the image can be increased.
JP 2006-54160 A

  However, even with such a driving method, the so-called dark contrast when displaying a dark image cannot be sufficiently increased, and a dark image cannot be provided in a high quality state.

  The problems to be solved by the present invention include the above-mentioned drawbacks as an example, and it is an object of the present invention to provide a method for driving a plasma display panel that can enhance the ability to express luminance gradations when displaying a dark image. It is an object of the invention.

  According to a first aspect of the present invention, there is provided a method for driving a plasma display panel, wherein a first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of devices are formed on the first substrate. A plasma display panel in which a pixel cell including a phosphor layer is formed at each intersection of a row electrode pair and a plurality of column electrodes formed on the second substrate is provided for each pixel based on a video signal. A driving method of a plasma display panel driven according to data, wherein the phosphor layer includes a phosphor material and a secondary electron emission material, and one field display period in the video signal is divided into a plurality of subfields A first reset process for initializing the pixel cell is performed in the first subfield of each of the plurality of subfields, and the pixel data in all the subfields of the plurality of subfields. An address process for setting the pixel cell to a lighting mode or a non-lighting mode by selectively discharging the pixel cell according to the data, and a sustaining discharge process for sustaining the pixel cell set to the lighting mode. In the first reset process, a first pulse on the cathode side with respect to the other row electrode and the column electrode of the row electrode pair is applied to one row electrode of the row electrode pair. A first step, a second step of applying a second pulse on the anode side with respect to the column electrode to the one row electrode, and the other row electrode and the column electrode to the one row electrode. On the other hand, a third step of applying a third pulse on the cathode side is sequentially executed.

  According to a thirty-third aspect of the present invention, there is provided a plasma display panel driving method in which a first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of devices are formed on the first substrate. Driving a plasma display panel in which pixel cells are formed at each intersection of a pair of row electrodes and a plurality of column electrodes formed on the second substrate according to pixel data for each pixel based on a video signal A method of driving a plasma display panel, comprising: performing a reset process for initializing the pixel cell in a first subfield when a one-field display period in the video signal is divided into a plurality of subfields, By selectively discharging the pixel cells according to the pixel data in all subfields of a plurality of subfields, An address process for setting the element cell to the lighting mode or the non-lighting mode and a sustain discharge process for causing the pixel cell set to the lighting mode to perform a sustain discharge are sequentially performed, and the reset process is performed for the row electrode pair. A first step of applying, to one row electrode, a first pulse on the cathode side of the other row electrode and the column electrode of the row electrode pair, and the one row electrode to the column electrode A second step of applying a second pulse on the anode side, and a third step of applying a third pulse on the cathode side with respect to the other row electrode and the column electrode to the one row electrode, The second step is characterized in that a positive potential is applied to each of the one row electrode and the other row electrode in the second step.

  According to a thirty-first aspect of the present invention, there is provided a plasma display panel driving method in which a first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of devices are formed on the first substrate. Driving a plasma display panel in which pixel cells are formed at each intersection of a pair of row electrodes and a plurality of column electrodes formed on the second substrate according to pixel data for each pixel based on a video signal A method of driving a plasma display panel, comprising: performing a reset process for initializing the pixel cell in a first subfield when a one-field display period in the video signal is divided into a plurality of subfields, By selectively discharging the pixel cells according to the pixel data in all subfields of a plurality of subfields, An address process for setting the element cell to the lighting mode or the non-lighting mode and a sustain discharge process for causing the pixel cell set to the lighting mode to perform a sustain discharge are sequentially performed, and the reset process is performed for the row electrode pair. A first step of applying, to one row electrode, a first pulse on the cathode side of the other row electrode and the column electrode of the row electrode pair, and the one row electrode to the column electrode A second step of applying a second pulse on the anode side, and a third step of applying a third pulse on the cathode side with respect to the other row electrode and the column electrode to the one row electrode, In the first step, the first pulse having a negative potential is applied to the one row electrode, and the first base pulse having a positive potential is applied to the other row electrode. That features It is.

  In the plasma display panel driving method according to the first, thirty and thirty-first aspects of the present invention, in the first step of the reset process of the first subfield, the row electrode is connected to one row electrode of the row electrode pair of each pixel cell. A first pulse on the cathode side is applied to the other row electrode and column electrode of the pair, and is weak between one row electrode and the other row electrode and between one row electrode and the column electrode. By causing discharge, the amount of positive wall charges increases near one of the row electrodes, and the negative wall charge increases near the column electrodes. A column in which current flows from one row electrode to the column electrode by applying a second pulse on the anode side with respect to the column electrode to one row electrode in the next second step due to this wall charge state A reset discharge called a side cathode discharge is likely to occur, that is, the discharge probability of the reset discharge is further increased, so that the black luminance is further lowered and the dark contrast is improved. In the third step of the reset process, a third pulse on the cathode side with respect to the other row electrode and the column electrode is applied to one of the row electrodes. Wall charges formed in the vicinity of each row electrode are erased, all the pixel cells are initialized to the extinguishing mode, and a weak discharge is generated between one row electrode and the column electrode. Due to the discharge, a part of the positive wall charges formed in the vicinity of the column electrode is erased, and the amount is adjusted so as to cause an address discharge in the address process.

  In the plasma display panel driving method according to the first aspect of the present invention, a pixel cell including a phosphor material and a secondary electron emission material is formed at each intersection of a plurality of column electrodes and a plurality of row electrode pairs. When the plasma display panel is driven and the reset discharge is performed, the cations in the discharge gas collide with the secondary electron emission material when heading toward the column electrode, and the secondary electrons are emitted into the discharge space. Due to the priming action by the secondary electrons, the discharge start voltage of the pixel cell is lowered, and a relatively weak reset discharge can be generated. Therefore, since the emission luminance associated with the discharge decreases due to weakening of the reset discharge, display with improved dark contrast becomes possible. Further, since this reset discharge is generated between one of the row electrode pairs formed on the front transparent substrate side and the column electrodes formed on the rear substrate side, the reset discharge is formed on the front transparent substrate side. Compared with the case where it occurs between the existing row electrodes, less discharge light is emitted to the outside from the front transparent substrate side. Therefore, the dark contrast can be further improved.

  In the driving method of the plasma display panel according to the thirty-third aspect, in the second step, a positive potential is applied to each of the one row electrode and the other row electrode, whereby one row electrode and the other row electrode are applied. It is possible to reliably cause the reset discharge while preventing the discharge between the electrodes.

  In the plasma display panel driving method according to the thirty-first aspect, in the first step, a first pulse having a negative potential is applied to one row electrode, and a positive potential is applied to the other row electrode. By applying the first base pulse, it is possible to adjust the amount of wall charges generated by the minute discharge to an appropriate amount, and to stabilize the subsequent reset discharge.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, an X electrode driver 51, a Y electrode driver 53, an address driver 55, and a drive control circuit 56.

The PDP 50 includes column electrodes D _{1 to} D _m arranged to extend in the vertical direction (vertical direction) of the two-dimensional display screen, and row electrodes X ₁ to X _m arranged to extend in the horizontal direction (horizontal direction). X _n and row electrodes _Y 1 to Y _n are formed. In this case, row electrode pairs (Y ₁ , X ₁ ), (Y ₂ , X ₂ ), (Y ₃ , X ₃ ),..., (Y _n , X _n ) that are paired with each other adjacent to each other. Are responsible for the first display line to the nth display line in the PDP 50, respectively. Each intersection of each display line and the column electrodes D ₁ to D _m, respectively (region surrounded by one-dot chain line in FIG. 1), the pixel cell PC serving as pixels are formed. That is, the PDP 50 includes pixel cells PC _{1,1 to} PC _{1, m} belonging to the first display line, pixel cells PC _{2,1 to} PC _{2, m} belonging to the second display line,. Each of the pixel cells PC _{n, 1 to} PC _{n, m} belonging to the line is arranged in a matrix.

  FIG. 2 is a front view schematically showing the internal structure of the PDP 50 as viewed from the display surface side. In FIG. 2, the crossing portions of three column electrodes D adjacent to each other and two display lines adjacent to each other are extracted and shown. 3 is a view showing a cross section of the PDP 50 taken along the line VV of FIG. 2, and FIG. 4 is a view showing a cross section of the PDP 50 taken along the line WW of FIG.

  As shown in FIG. 2, each row electrode X is provided in contact with a bus electrode Xb extending in the horizontal direction of the two-dimensional display screen and a position corresponding to each pixel cell PC on the bus electrode Xb. And a transparent electrode Xa having a letter shape. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the two-dimensional display screen, and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each pixel cell PC on the bus electrode Yb. Is composed of. The transparent electrodes Xa and Ya are made of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in FIG. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb are arranged on the back side of the front transparent substrate 10 whose front side is the display surface of the PDP 50. Is formed. At this time, the transparent electrodes Xa and Ya in each row electrode pair (X, Y) extend to the paired row electrode side, and the top sides of the wide portions pass through the discharge gap g1 having a predetermined width. Facing each other. Further, on the back side of the front transparent substrate 10, a horizontal extension of the two-dimensional display screen extends between the row electrode pair (X, Y) and the row electrode pair (X, Y) adjacent to the row electrode pair. A black or dark light absorbing layer (light shielding layer) 11 is formed. Further, a dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pair (X, Y). As shown in FIG. 3, on the back side of the dielectric layer 12 (the surface opposite to the surface in contact with the row electrode pair), the light absorbing layer 11 and bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are provided. A raised dielectric layer 12A is formed in a portion corresponding to the region where the and are formed.

  A magnesium oxide layer 13 is formed on the surfaces of the dielectric layer 12 and the raised dielectric layer 12A. The magnesium oxide layer 13 is excited by electron beam irradiation, and is a magnesium oxide crystal (as a secondary electron emission material) that emits CL (cathode luminescence) light having a peak within a wavelength of 200 to 300 nm, particularly 230 to 250 nm. Hereinafter, it is referred to as a CL light emitting MgO crystal). This CL light-emitting MgO crystal is obtained by vapor-phase oxidation of magnesium vapor generated by heating magnesium. For example, a multi-crystal structure in which cubic crystals are fitted to each other, or a cubic single crystal structure is obtained. Have. The average particle diameter of the CL luminescent MgO crystal is 2000 angstroms or more (measurement result by BET method).

  In order to form a vapor phase magnesium oxide single crystal having a large average particle diameter of 2000 angstroms or more, it is necessary to increase the heating temperature for generating magnesium vapor. For this reason, the length of the flame in which magnesium reacts with oxygen becomes longer, and the temperature difference between the flame and the surroundings becomes larger. Many of them having an energy level corresponding to the peak wavelength (for example, around 235 nm and within 230 to 250 nm) are formed.

  Compared with a general gas phase oxidation method, the amount of magnesium evaporated per unit time is increased to increase the reaction area between magnesium and oxygen, and the gas generated by reacting with more oxygen is generated. The phase method magnesium oxide single crystal has an energy level corresponding to the above-described peak wavelength of CL emission.

  The magnesium oxide layer 13 is formed by adhering such CL light-emitting MgO crystal to the surface of the dielectric layer 12 by spraying, electrostatic coating, or the like. Note that the magnesium oxide layer 13 may be formed by forming a thin film magnesium oxide layer on the surface of the dielectric layer 12 by vapor deposition or sputtering, and attaching a CL light emitting MgO crystal thereon.

  On the other hand, on the rear substrate 14 arranged in parallel with the front transparent substrate 10, each column electrode D is connected to the row electrode pair (X, Y) at a position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). , Y). On the back substrate 14, a white column electrode protective layer 15 that covers the column electrode D is further formed. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 includes a horizontal wall 16A extending in the horizontal direction of the two-dimensional display screen at a position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and intermediate portions between the column electrodes D adjacent to each other. A ladder wall is formed by the vertical wall 16B extending in the vertical direction of the two-dimensional display screen at the position. Further, a ladder-shaped partition wall 16 as shown in FIG. 2 is formed for each display line of the PDP 50. A gap SL as shown in FIG. 2 exists between the partition walls 16 adjacent to each other. Further, the ladder-shaped partition 16 partitions the pixel cell PC including the independent discharge space S and the transparent electrodes Xa and Ya. In the discharge space S, a discharge gas containing xenon gas is enclosed. A phosphor layer 17 is formed on the side surface of the horizontal wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protection layer 15 in each pixel cell PC so as to cover all of these surfaces. The phosphor layer 17 is actually composed of three types: a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light.

  The phosphor layer 17 contains MgO crystal (including CL light-emitting MgO crystal) as a secondary electron emission material in the form shown in FIG. 5, for example. At this time, the MgO crystal is exposed from the phosphor layer 17 so as to be in contact with the discharge gas at least on the surface of the phosphor layer 17, that is, on the surface in contact with the discharge space S.

  Here, between the discharge space S and the gap SL of each pixel cell PC, as shown in FIG. 3, the magnesium oxide layer 13 is closed to each other by contacting the lateral wall 16A. Further, as shown in FIG. 4, since the vertical wall 16B is not in contact with the magnesium oxide layer 13, there is a gap r therebetween. In other words, the discharge spaces S of the pixel cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through the gap r.

First, the drive control circuit 56 converts the input video signal into 8-bit pixel data that expresses all luminance levels in 256 gradations for each pixel, and performs error diffusion processing and dither processing on the pixel data. A multi-gradation process consisting of That is, first, in the error diffusion process, the upper 6 bits of the pixel data is set as display data, the remaining lower 2 bits are set as error data, and the error data in the pixel data corresponding to each peripheral pixel is weighted and added. By reflecting it in the display data, 6-bit error diffusion pixel data is obtained. According to such error diffusion processing, the luminance of the lower 2 bits in the original pixel is pseudo-expressed by the peripheral pixels, and therefore, the display data for 6 bits, which is less than 8 bits, and the pixel data for 8 bits. It is possible to express the same luminance gradation. Next, the drive control circuit 56 performs dither processing on the 6-bit error diffusion processing pixel data obtained by this error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. As a result, dither-added pixel data is obtained. According to the addition of the dither coefficients, when viewed in units of pixels as described above, it is possible to express the luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control circuit 56 converts the upper 4 bits of the dither added pixel data, as shown in FIG. 6, the overall brightness level to multi-gradation pixel data PD _S of four bits representing at 15 gradations. Then, the drive control circuit 56 converts the multi-grayscale pixel data PD _S to the pixel drive data GD of 14 bits in accordance with data conversion table as shown in FIG. The drive control circuit 56 associates the first to fourteenth bits in the pixel drive data GD with each of the subfields SF1 to SF14 (described later), and uses the bit digit corresponding to the subfield SF as a pixel drive data bit. One display line (m) is supplied to the address driver 55.

Further, the drive control circuit 56 supplies various control signals to drive the PDP 50 having the above structure to the panel driver including the X electrode driver 51, the Y electrode driver 53, and the address driver 55 according to the light emission drive sequence as shown in FIG. To do. That is, the drive control circuit 56 performs the reset process (first reset process) R, the selective write address process _WW, and the sustain (in the first subfield SF1 within one field (one frame) display period as shown in FIG. Sustain discharge) Various control signals to be sequentially driven in accordance with the respective steps I are supplied to the panel driver. Subfields each SF2～SF14, supplies various control signals for sequentially performing the drive in accordance with the selective erase address process W _D and sustain process I respectively to the panel driver. Only in the last subfield SF14 within one field display period, after the sustain process I is executed, the drive control circuit 56 supplies various control signals to be sequentially executed in accordance with the erase process E to the panel driver.

  The panel drivers, that is, the X electrode driver 51, the Y electrode driver 53, and the address driver 55 generate various drive pulses as shown in FIG. 8 in response to the various control signals supplied from the drive control circuit 56, and the columns of the PDP 50. Supply to electrode D and row electrodes X and Y.

  FIG. 8 shows only the operations in the first subfield SF1, the subsequent subfield SF2, and the last subfield SF14 in the subfields SF1 to SF14 shown in FIG. is there.

  The reset process R of the subfield SF1 includes a first step S1, a second step S2, and a third step S3. The first step S1, the second step S2, and the third step S3 are consecutive in that order.

First, in the first step S1 of the reset process R of the subfield SF1, the Y electrode driver 53 causes the negative wall charge adjustment pulse CP ′ to change to a peak potential (arrival potential) Vc by gradually changing the potential with time. applying a (first pulse) to all the row electrodes _Y 1 to Y _n. Over the application period Te of the wall charge adjustment pulse CP ′, the X electrode driver 51 applies a base pulse BP ′ (first base pulse) having a positive positive potential Va to all the row electrodes X _{1 to} X _n. Apply to. During this time, the address driver 55 sets the column electrodes _D 1 to D _m to a ground potential (0 volt). That is, each of the row electrodes Y _{1 to} Y _n is a negative electrode with respect to the row electrodes X _{1 to} X _n and the column electrodes D _{1 to} D _m . Therefore, in all the pixel cells PC, a discharge current flows from the row electrode X to the row electrode Y, and a discharge current flows from the column electrode D to the row electrode Y. Since the wall charge adjustment pulse CP ′ is a slowly varying long time constant pulse, a weak discharge is generated between the row electrode X and the row electrode Y and between the column electrode D and the row electrode Y, respectively.

In the second step S2 of the reset process R, the Y electrode driver 53 has a positive polarity reset pulse RP _Y1 (the first pulse having a waveform in which the potential transition at the leading edge with the passage of time is gentler than a sustain pulse described later. 2 pulse) is applied to all the row electrodes _Y 1 to Y _n. The peak potential (attainment potential) Vd of the reset pulse RP _Y1 is higher than the peak potential of the sustain pulse. During this time, the address driver 55 sets the column electrodes _D 1 to D _m to a ground potential (0 volt). In response to the application of the reset pulse RP _Y1, a first reset discharge is generated between the row electrode Y and the column electrode D in each of all the pixel cells PC. That is, in the second step S2 of the reset process R, a voltage is applied between both electrodes so that the row electrode Y is on the anode side and the column electrode D is on the cathode side, so that the row electrode Y is directed toward the column electrode D. A discharge through which a current flows (hereinafter referred to as column side cathode discharge) is generated as a first reset discharge. In response to the first reset discharge, negative wall charges are formed in the vicinity of the row electrodes Y in all the pixel cells PC, and positive wall charges are formed in the vicinity of the column electrodes D.

In a second step S2 of the reset stage R, X electrode driver 51, the same polarity as the reset pulse RP _Y1, and, prevent surface discharge between the row electrodes X and Y due to the application of the reset pulse RP _Y1 applying the reset pulse RP _X having a peak potential capable of all of the row electrodes _X 1 to X _n respectively.

Next, in the third step S3 of the reset process R of the subfield SF1, the Y electrode driver 53 applies a negative polarity reset pulse RP _Y2 (third pulse) in which the potential transition at the leading edge with time elapses gradually. occurred, applies it to all the row electrodes _Y 1 to Y _n. The pulse width (application period) of the reset pulse RP _Y2 is Tf. Further, in the third step S3 of the reset process R, the X electrode driver 51 applies a base pulse BP ″ (second base pulse) having a constant positive potential Vb to each of all the row electrodes X _{1 to} X _n. The potentials Va and Vb of the base pulses BP ′ and BP ″ have a relationship of Vb> Va. In response to the application of the negative reset pulse RP _Y2 and the positive base pulse BP ″, a second reset discharge is generated between the row electrodes X and Y in all the pixel cells PC. The reset pulse RP _Y2 and The peak potential of each base pulse BP ″ is determined in consideration of wall charges formed in the vicinity of the row electrodes X and Y in response to the weak discharge in the first step S1 and the first reset discharge in the second step S2. This is the lowest potential that can reliably cause the second reset discharge between the row electrodes X and Y. Negative peak potential in the reset pulse RP _Y2 is set to a higher potential, that is close to 0 volt potential than the peak potential of the negative polarity writing scan pulse SP _W, which will be described later. That is, when the peak potential of the reset pulse RP _Y2 thus lower than the peak potential of the write scan pulse SP _W, the occurrence strong discharge between the row electrodes Y and column electrodes D, are formed near the column electrode D wall charge erases much, is because the address discharge in the selective write address stage W _W becomes unstable. By the second reset discharge generated in the third step S3 of the reset process R, the wall charges formed in the vicinity of the row electrodes X and Y in each pixel cell PC are erased, and all the pixel cells PC are turned off. Initialized to mode. Further, in response to the application of the reset pulse RP _Y2, a weak discharge is generated between the row electrode Y and the column electrode D in all the pixel cells PC, and the discharge is formed in the vicinity of the column electrode D. some of the positive wall charges are erased, is adjusted to an amount capable of occur correctly selective write address discharge in the selective write address process W _W to be described later.

Next, in the selective write address process _{W W} of the subfield SF1, Y electrode driver 53, the base pulse BP having a predetermined negative base potential as shown in FIG. 8 ^- the row electrodes _Y 1 to Y _n at the same time applied and while, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. X electrode driver 51, the base pulse BP ⁺ applied to the row electrodes _X 1 to X _n at the third step S3 of the reset process R in the continuing row electrodes _X 1 to X _n, respectively In this selective write address process _{W W} Apply. Incidentally, the base pulse BP ^- and the base pulse BP ⁺ is the potentials, so that the voltage between the row electrodes X and Y during the non-application period of the write scan pulse SP _W is lower than the discharge start voltage of the pixel cell PC Is set to an appropriate potential.

Further, in the selective write address stage W _W, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 that should set the pixel cell PC to the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of a low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, it is between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode selective write address discharge Is born. Further, immediately after the selective write address discharge, a weak discharge is also generated between the row electrodes X and Y in the pixel cell PC. That is, after the write scan pulse SP _W is applied, the row electrodes X and Y between the base pulse BP to ^- but and voltage corresponding to the base pulse BP ⁺ is applied, the voltage discharge of the pixel cell PC Since the voltage is set lower than the start voltage, the discharge is not generated in the pixel cell PC only by applying the voltage. However, when the selective write address discharge is caused, is induced in the selective write address discharge, the base pulse BP ^- and only the voltage applied based on the base pulse BP ^+, discharge between the row electrodes X and Y It is born. By this discharge and the selective write address discharge, the pixel cell PC has a positive wall charge in the vicinity of the row electrode Y, a negative wall charge in the vicinity of the row electrode X, and a negative wall charge in the vicinity of the column electrode D. Are formed, that is, the lighting mode is set. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP is applied a low voltage to be set to off-mode (0 volt) described above Such selective write address discharge does not occur, and therefore no discharge occurs between the row electrodes X and Y. Therefore, the pixel cell PC maintains the state immediately before that, that is, the extinguished mode state initialized in the reset process R.

Next, in the sustain process I of the subfield SF1, the Y electrode driver 53 generates a sustain pulse IP having a positive polarity peak potential for one pulse and applies it to each of the row electrodes Y _{1 to} Y _n simultaneously. During this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the ground potential (0 volt) state, and the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volt) state. Set. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the pixel cell PC set in the lighting mode as described above. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, whereby one display light emission corresponding to the luminance weight of the subfield SF 1 is performed. . Further, in response to the application of the sustain pulse IP, a discharge is also generated between the row electrode Y and the column electrode D in the pixel cell PC set in the lighting mode. By this discharge and the sustain discharge, negative wall charges are formed in the vicinity of the row electrode Y in the pixel cell PC, and positive wall charges are formed in the vicinity of the row electrode X and the column electrode D, respectively. After the application of the sustain pulse IP, the Y electrode driver 53 applies the wall charge adjustment pulse CP having a negative peak potential with a gentle potential transition at the leading edge with time as shown in FIG. It applied to the Y ₁ to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the pixel cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed inside the pixel cell PC is erased. . Thus, the amount of wall charges within the pixel cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

Next, in subfields SF2~SF14 each selective erase address process _{W D,} Y electrode driver 53, while applying the base pulse BP ⁺ to the row electrodes _Y 1 to Y _n, each having a predetermined base potential of positive polarity, an erase scan pulse SP _D with a negative peak potential of the as shown in FIG. 8 successively alternatively applied to the row electrodes Y ₁ to Y _n, respectively. Peak potential of the base pulse BP ⁺ is over during execution of this selective erase address process W _D, is set to a potential capable of preventing erroneous discharge between the row electrodes X and Y. Further, over the running period of the selective erase address process _{W D,} X electrode driver 51 sets the row electrodes _X 1 to X _n respectively ground potential (0 volt).

In this selective erase address process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF to the pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the address driver 55 converts a pixel drive data bit having a logic level 1 to change the pixel cell PC from the lighting mode to the extinguishing mode, and converts it into a pixel data pulse DP having a positive peak potential. To do. On the other hand, when a pixel driving data bit having a logic level 0 to maintain the current state of the pixel cell PC is supplied, it is converted into a pixel data pulse DP of a low voltage (0 volts). The address driver 55 applies the pixel data pulse DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erasing scan pulse SP _D by one display line (m). At this time, simultaneously with the erase scanning pulse SP _D, selective erase address discharge between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP is applied is caused. By this selective erasure address discharge, the pixel cell PC is in a state in which positive wall charges are formed in the vicinity of the row electrodes Y and X and negative wall charges are formed in the vicinity of the column electrodes D, that is, the extinction mode. Set to On the other hand, simultaneously with the erase scanning pulse SP _D, as mentioned above selective erase address discharge between the column electrode D and the row electrodes Y of the pixel data pulse DP pixel cell PC which is applied a low voltage (0 volts) occurs Not. Therefore, this pixel cell PC maintains the state (lighting mode, extinguishing mode) until just before that.

Next, in the sustain process I of each of the subfields SF2 to SF14, the number of times corresponding to the luminance weight of the subfield is alternately performed by the X electrode driver 51 and the Y electrode driver 53 as shown in FIG. (even number) fraction by repeatedly applying a sustain pulse IP having a peak potential of positive polarity to the row electrodes _X 1 to X _n and _Y 1 to Y _n, respectively. Each time the sustain pulse IP is applied, a sustain discharge is generated between the row electrodes X and Y in the pixel cell PC set in the lighting mode. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, so that display light emission is performed for the number of times corresponding to the luminance weight of the subfield SF. . At this time, in the vicinity of the row electrode Y in the pixel cell PC in which the sustain discharge is generated according to the sustain pulse IP finally applied in the sustain process I of each of the subfields SF2 to SF14, Positive wall charges are formed in the vicinity of X and the column electrode D. After the final sustain pulse IP is applied, the Y electrode driver 53 performs a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge as time passes as shown in FIG. applied to the electrodes _Y 1 to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the pixel cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed inside the pixel cell PC is erased. . Thus, the amount of wall charges within the pixel cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

In the final erase step E of the final subfield SF14, the Y electrode driver 53 applies an erase pulse EP having a negative peak potential to all the row electrodes Y _{1 to} Y _n . In response to the application of the erase pulse EP, an erase discharge is generated only in the pixel cell PC in the lighting mode state. The pixel cell PC which has been in the lighting mode state due to the erasing discharge is changed to the light-off mode state.

The above driving is executed based on 15 types of pixel driving data GD as shown in FIG. According to such driving, as shown in FIG. 6, a write address discharge is first generated in each pixel cell PC in the first subfield SF1 except when the luminance level 0 is expressed (first gradation) ( This pixel cell PC is set to the lighting mode. Thereafter, the selective erasure address discharge is generated only by the selective erasure address process W _{O in} one of the subfields SF2 to SF14 (indicated by a black circle), and then the pixel cell PC is set to the off mode. . In other words, each pixel cell PC is set to the lighting mode in each of the continuous subfields corresponding to the intermediate luminance to be expressed, and the light emission associated with the sustain discharge is repeated for the number of times assigned to each of these subfields. Occurs (indicated by white circles). At this time, a luminance corresponding to the total number of sustain discharges generated in one field (or one frame) display period is visually recognized. Therefore, according to the 15 types of light emission patterns by the 1st to 15th gradation driving as shown in FIG. 6, the intermediate for 15 gradations corresponding to the total number of sustain discharges generated in each of the subfields indicated by white circles. Luminance is expressed.

  According to such driving, since the areas where the light emission patterns (lighted state, unlit state) are mutually inverted are not mixed in one screen within one field display period, the pseudo contour generated in such a state is prevented. Is done.

  In the drive shown in FIG. 8, in the first step S <b> 1 of the reset process R of the first subfield SF <b> 1, a weak discharge with the negative polarity (cathode side) of the row electrode Y is generated. Compared with before discharge, the amount of positive wall charges increases in the vicinity of the row electrode Y. In addition, by generating a weak discharge in which the column electrode D has a positive polarity (anode side), negative wall charges increase in the vicinity of the column electrode D after the discharge compared to before the discharge. Due to this wall charge state, a first reset discharge called column-side cathode discharge in which current flows from the row electrode Y to the column electrode D with the column electrode D as the cathode side in the next step S2 is likely to occur. That is, since the discharge probability of the first reset discharge in step S2 is further increased, the black luminance is further decreased and the dark contrast is improved. Moreover, by generating discharge in step S1, the number of priming particles increases, and the discharge probability of the first reset discharge in step S2 further increases due to this priming effect. That is, the reset discharge in step S2 is stabilized by the two actions of the wall charge action and the priming action, so that the discharge probability increases, the black luminance decreases, and the dark contrast increases.

  As described above, the wall charge adjustment pulse CP ′ in step S1 is a pulse with a long time constant, and between the row electrode Y and the row electrode X and between the row electrode Y and the column electrode D, as compared with the reset discharge. Therefore, the discharge is smaller than that of the reset discharge. Therefore, the dark discharge in step S1 hardly affects the dark contrast.

If the discharge intensity at step S1 is greater than the discharge intensity at step S3, unnecessary wall charges may remain in the vicinity of each electrode after the discharge at step S3. In this case, this unwanted wall charges, write miss pixel cells occurs generated by the address discharge of the selective write address process W _W subsequent to the step S3. From the above points, it is preferable that the discharge intensity in step S1 is weaker than the discharge intensity in step S3.

  The following methods (1) to (3) are employed as a method of weakening the discharge intensity in step S1 than the discharge intensity in step S3.

(1) The positive potential Va of the base pulse BP ′ in step S1 is set lower than the potential Vb of the base pulse BP ″ in step S3. For example, the base pulse BP ⁺ having a lower potential than the base pulse BP ″ The same potential as the potential.

(2) a negative target potential Vc of the wall charge adjusting pulse CP 'at step S1, is set higher than the ultimate potential Vd of the second reset pulse RP _Y2 in step S3.

(3) the pulse width Te of the wall charge adjusting pulse CP 'at step S1, is set to be shorter than the pulse width Tf of the second reset pulse RP _Y2 in step S3.

  By any one of these methods (1) to (3) or a combination of two or more of (1) to (3), the discharge intensity at step S1 is weaker than the discharge intensity at step S3. can do.

  At the time of the first reset discharge in step S2, when the cations in the discharge gas move to the column electrode D, the MgO crystal as the secondary electron emission material contained in the phosphor layer 17 as shown in FIG. Collisions cause secondary electrons to be emitted from this MgO crystal. In particular, in the PDP 50 of the plasma display device shown in FIG. 1, by exposing the MgO crystal body to the discharge space as shown in FIG. 5, the probability of collision with cations is increased, and the secondary electrons are efficiently put into the discharge space. It is trying to release. In this case, the discharge start voltage of the pixel cell PC is lowered by the priming action by such secondary electrons, and therefore it is possible to cause a relatively weak reset discharge. Therefore, since the emission luminance associated with the discharge decreases due to weakening of the reset discharge, display with improved dark contrast becomes possible.

  Further, in the drive shown in FIG. 8, the first reset discharge is generated between the row electrode Y formed on the front transparent substrate 10 side and the column electrode D formed on the back substrate 14 side as shown in FIG. I am letting. Therefore, compared with the case where reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, less discharge light is emitted to the outside from the front transparent substrate 10 side. The dark contrast can be improved.

  In the driving shown in FIGS. 7 and 8, first, in the first subfield SF1, after generating reset discharge to initialize all the pixel cells PC to the extinguishing mode state, the pixel cells PC in the extinguishing mode state are changed. A selective write address discharge to be shifted to the lighting mode state is generated. Then, a selective erasure address method of causing a selective erasure address discharge in which one of the subfields SF2 to SF14 subsequent to SF1 is to cause the pixel cell PC in the lighting mode state to transition to the extinguishing mode state is generated. The adopted drive is carried out. Therefore, when black display (luminance level 0) is performed by such driving, the discharge generated through one field display period is only the reset discharge in the first subfield SF1. In other words, when a reset discharge that initializes all the pixel cells PC to the lighting mode state is generated in the first subfield SF1 and then a drive for generating a selective erasure address discharge that should be changed to the light-off mode state is performed. In comparison, the number of discharges generated through one field display period is reduced. Therefore, according to the driving shown in FIGS. 7 and 8, the contrast when displaying a dark image, so-called dark contrast, can be improved.

Further, in the driving shown in FIG. 8, in the sustain process I of the subfield SF1 having the smallest luminance weight, the sustain reproduction is caused only once, and the display reproduction at the time of low gradation expressing low luminance is performed. Increases sex. Further, in the sustain process I of the subfield SF1, the sustain pulse IP applied to cause the sustain discharge is only once. Therefore, after the end of the sustain discharge generated in response to this one sustain pulse IP, a negative wall charge is formed in the vicinity of the row electrode Y, and a positive wall charge is formed in the vicinity of the column electrode D. It becomes. Thus, in the selective erase address process W _D of the next subfield SF2, discharges with the column electrodes D as an anode side between the column electrode D and the row electrodes Y (hereinafter, referred to as a column-side anode discharge) the selective erase address discharge Can be generated. On the other hand, in the sustain process I of each of the subsequent subfields SF2 to SF14, the number of times the sustain pulse IP is applied is an even number. Therefore, immediately after the end of each sustain step I, negative wall charges are formed in the vicinity of the row electrode Y, and positive wall charges are formed in the vicinity of the column electrode D. In that selective erase address process W _D, it is possible to train side anode discharge. Therefore, only a positive pulse is applied to the column electrode D, and the cost of the address driver 55 can be prevented.

  In the PDP 50 shown in FIG. 1, not only in the magnesium oxide layer 13 formed on the front transparent substrate 10 side in each pixel cell PC but also in the phosphor layer 17 formed on the back substrate 14 side. In addition, a CL light emitting MgO crystal as a secondary electron emission material is included.

  Below, the effect by having employ | adopted this structure is demonstrated, referring FIG.9 and FIG.10.

FIG. 9 shows a reset pulse as shown in FIG. 8 in a so-called conventional PDP in which only the magnesium oxide layer 13 in the magnesium oxide layer 13 and the phosphor layer 17 as described above contains a CL light-emitting MgO crystal. It is a figure showing transition of the discharge intensity in the column side cathode discharge which arises when RP _Y1 is applied.

On the other hand, FIG. 10 shows the column side generated when the reset pulse RP _Y1 is applied to the PDP 50 according to the present invention in which both the magnesium oxide layer 13 and the phosphor layer 17 contain a CL light-emitting MgO crystal. It is a figure showing transition of the discharge intensity in cathode discharge.

As shown in FIG. 9, according to the conventional PDP, a relatively strong column-side cathode discharge continues for 1 [ms] or more in response to the application of the reset pulse RP _Y1 , but according to the PDP 50 according to the present invention. Then, as shown in FIG. 10, the column side cathode discharge ends within about 0.04 [ms]. That is, the discharge delay time in the column side cathode discharge can be greatly shortened as compared with the conventional PDP.

Therefore, when the column side cathode discharge is caused by applying the reset pulse RP _Y1 having a waveform with a slow potential transition in the rising section as shown in FIG. 8 to the row electrode Y of the PDP 50, the potential of the reset pulse RP _Y1 is changed. Before reaching the peak potential, the discharge ends. Therefore, the column-side cathode discharge ends when the voltage applied between the row electrode and the column electrode is low, so that the discharge intensity is significantly lower than in the case of FIG. 9, as shown in FIG. .

That is, in the above embodiment, a reset pulse RP _Y1 having a waveform with a slow potential transition at the time of rising, for example, as shown in FIG. 8 is applied not only to the magnesium oxide layer 13 but also to the phosphor layer 17 as a CL emission MgO crystal. Is applied to the PDP 50 containing the above, thereby causing column-side cathode discharge with low discharge intensity to occur. Therefore, since the column side cathode discharge with extremely low discharge intensity can be generated as the reset discharge, it is possible to increase the image contrast, particularly the dark contrast when displaying a dark image.

The rising waveform of the reset pulse RP _Y1 applied to the row electrode Y to cause the reset discharge as the column side cathode discharge is not limited to a constant slope as shown in FIG. For example, as shown in FIG. 11, the inclination may gradually change with time.

FIG. 12 shows another light emission drive sequence that employs the selective erase address method for driving the PDP 50. The drive control circuit 56 sends various control signals for driving the PDP 50 having the configuration shown in FIG. 1 according to the light emission drive sequence as shown in FIG. 12 to the panel driver including the X electrode driver 51, the Y electrode driver 53, and the address driver 55. To supply. That is, the drive control circuit 56 performs the first reset process R1, the first selective write address process W1 _W, and the minute light emission process LL in the first subfield SF1 within one field (one frame) display period as shown in FIG. Various control signals to be sequentially driven according to each are supplied to the panel driver. In SF2 subsequent to such sub-field SF1, and supplies the second reset step R2, a second selective write addressing step W2 _W and various control signals for sequentially performing the drive in accordance with the sustain stage I each panel driver. Subfields each SF3～SF14, supplies various control signals for sequentially performing the drive in accordance with the selective erase address process W _D and sustain process I respectively to the panel driver. Only in the last subfield SF14 in one field display period, after the sustain process I is executed, the drive control circuit 56 supplies various control signals to be sequentially executed in accordance with the erase process E to the panel driver. To do.

Further, the drive control circuit 56 converts the upper 4 bits of the dither addition pixel data obtained by the above-described dither processing into 4-bit multi-gradation that represents the total luminance level in 16 gradations as shown in FIG. converting the pixel data PD _S. Then, the drive control circuit 56 converts the multi-grayscale pixel data PD _S pixel driving data GD of 14 bits in accordance with data conversion table as shown in FIG. 13, the first to fourteenth bits in the pixel drive data GD Corresponding to each of the subfields SF1 to SF14, the bit digit corresponding to the subfield SF is supplied to the address driver 55 by one display line (m) as pixel drive data bits.

  The panel drivers, that is, the X electrode driver 51, the Y electrode driver 53, and the address driver 55, generate various drive pulses as shown in FIG. 14 in response to various control signals supplied from the drive control circuit 56, thereby generating a column of the PDP 50. Supply to electrode D and row electrodes X and Y.

  In FIG. 14, only the operations in SF1 to SF3 and the last subfield SF14 in the subfields SF1 to SF14 shown in FIG. 12 are extracted and shown. Further, in FIG. 14, the same reference numerals are used for the same pulses as the various drive pulses generated when the selective erase address method as shown in FIG. 8 is adopted.

  The first reset process R1 of the subfield SF1 includes a first step S1, a second step S2, and a third step S3. The first step S1, the second step S2, and the third step S3 are consecutive in that order.

First, in the first step S1 of the reset step R of the subfield SF1, the Y electrode driver 53 causes the negative wall charge adjustment pulse CP ′ (first pulse) in which the potential gradually changes with time and becomes the peak potential Vc. ) is applied to all the row electrodes _Y 1 to Y _n a. Over the application period Te of the wall charge adjustment pulse CP ′, the X electrode driver 51 applies a base pulse BP ′ (first base pulse) having a positive positive potential Va to all the row electrodes X _{1 to} X _n. Apply to. During this time, the address driver 55 sets the column electrodes _D 1 to D _m to a ground potential (0 volt). That is, each of the row electrodes Y _{1 to} Y _n is a negative electrode with respect to the row electrodes X _{1 to} X _n and the column electrodes D _{1 to} D _m . Therefore, in all the pixel cells PC, a discharge current flows from the row electrode X to the row electrode Y, and a discharge current flows from the column electrode D to the row electrode Y. Since the wall charge adjustment pulse CP ′ is a slowly varying long time constant pulse, a weak discharge is generated between the row electrode X and the row electrode Y and between the column electrode D and the row electrode Y, respectively.

In the second step S2 of the first reset step R1 of the subfield SF1, the Y electrode driver 53 has a slower potential transition at the leading edge with the passage of time than the sustain pulse IP generated in the sustain step I. A positive polarity reset pulse RP1 _Y1 (second pulse) having a waveform is applied to all the row electrodes Y _{1 to} Y _n . During this time, X-electrode driver 51 is the reset pulse RP1 _Y1 the same polarity, and the reset pulse RP1 having a peak potential capable of preventing surface discharge between the row electrodes X and Y due to the application of the reset pulse RP1 _Y1 It is applied to all the row electrodes _X 1 to X _n respectively _X. During this time, if no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 supplies all the row electrodes X _{1 to} X _n to the ground potential (0 volt) instead of applying the reset pulse RP1 _X. You may make it set to. Here, in the second step S2 of the first reset step R1, a weak first reset is performed between the row electrode Y and the column electrode D in each of all the pixel cells PC in response to the application of the reset pulse RP1 _Y1 as described above. Discharge occurs. That is, in the second step S2 of the first reset process R1, a voltage is applied between both electrodes so that the row electrode Y is on the anode side and the column electrode D is on the cathode side, so that the row electrode Y is changed to the column electrode D. A column-side cathode discharge in which a current flows in the direction is generated as a first reset discharge. In response to the first reset discharge, negative wall charges are formed in the vicinity of the row electrodes Y in all the pixel cells PC, and positive wall charges are formed in the vicinity of the column electrodes D.

Next, in the third step S3 of the first reset step R1 of the subfield SF1, the Y electrode driver 53 causes the negative polarity reset pulse RP1 _Y2 (third pulse) in which the potential transition at the leading edge with time elapses gradually. ) generates and applies it to all the row electrodes _Y 1 to Y _n. The peak potential of the reset pulse RP1 _Y2 is Vd, and its pulse width (application time) is Tf. The During this time, the X electrode driver 51 applies a base pulse BP ″ (second base pulse) having a positive constant potential Vb to each of all the row electrodes X _{1 to} X _n . The base pulses BP ′ and BP ″ The potentials Va and Vb have a relationship of Vb> Va. In response to the application of the negative reset pulse RP _Y2 and the positive base pulse BP ″, a second reset discharge is generated between the row electrodes X and Y in all the pixel cells PC. The wall charges formed in the vicinity of each of the row electrodes X and Y in each pixel cell PC are erased, and all the pixel cells PC are initialized to the extinguishing mode, and the reset pulse RP1 _Y2 is applied. Accordingly, a weak discharge is generated between the row electrode Y and the column electrode D in all the pixel cells PC, and this weak discharge causes one of the positive wall charges formed near the column electrode D. The portion is erased and adjusted so that the selective write address discharge can be correctly generated in the first selective write address process W1 _W to be described later.

Next, in the first selective write address process W1 _W of the subfield SF1, the Y electrode driver 53 applies a base pulse BP ⁻ having a predetermined negative base potential as shown in FIG. 14 to the row electrodes Y _{1 to} Y _n . while applying simultaneously, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. During this time, the address driver 55 first converts the pixel drive data bit corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 that should set the pixel cell PC to the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of a low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, the selective write address discharge between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode Is born. During this time, a voltage corresponding to the write scan pulse SP _W also between the row electrodes X and Y is to be applied, all at this stage of the pixel cell PC OFF mode, that is, a state in which the wall charge is erased because, the discharge does not occur between such write scan pulse SP _W row electrodes X and Y only applied.

Therefore, in the first selective write address process W1 _W of the subfield SF1, between the column electrode D and the row electrode Y in the pixel cell PC according to the application of the write scan pulse SP _W and the high voltage pixel data pulse DP. Only the selective write address discharge is generated. Thus, although no wall charge exists near the row electrode X in the pixel cell PC, positive wall charge is formed near the row electrode Y, and negative wall charge is formed near the column electrode D. The lighting mode is set. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP is applied a low voltage to be set to off-mode (0 volt) described above Such selective write address discharge is not caused. Therefore, the pixel cell PC is in the extinguishing mode initialized in the first reset process R1, that is, in a state where no discharge occurs between the row electrode Y and the column electrode D and between the row electrodes X and Y. To maintain.

Next, in the minute light emission process LL of the subfield SF1, the Y electrode driver 53 simultaneously applies minute light emission pulses LP having a predetermined positive peak potential as shown in FIG. 14 to the row electrodes Y _{1 to} Y _n . In response to the application of the minute light emission pulse LP, a discharge (hereinafter referred to as a minute light emission discharge) is generated between the column electrode D and the row electrode Y in the pixel cell PC set in the lighting mode. That is, in the minute light emission process LL, although a discharge is generated between the row electrode Y and the column electrode D in the pixel cell PC, a potential that does not cause a discharge between the row electrodes X and Y is applied to the row electrode Y. By applying this, a minute light emission discharge is caused only between the column electrode D and the row electrode Y in the pixel cell PC set in the lighting mode. In this case, the peak potential of the minute light emission pulse LP is a potential lower than the peak potential of the sustain pulses IP applied in the subfield SF2 subsequent sustain process I to be described later, for example, in the selective erase address process W _D to be described later This is the same as the base potential applied to the row electrode Y.

Further, as shown in FIG. 14, the rate of change with time in the rising period of the potential in the minute light emission pulse LP is higher than the rate of change in the rising period of the reset pulse (RP1 _Y1 , RP2 _Y1 ). By making the potential transition at the leading edge of the minute light emission pulse LP steeper than the potential transition at the leading edge of the reset pulse, the first reset discharge generated in the first reset process R1 and the second reset process R2 is performed. It causes a strong discharge. Here, the discharge is a column-side cathode discharge as described above, and is a discharge generated by a minute light emission pulse LP having a pulse voltage lower than that of the sustain pulse IP. The light emission luminance associated with the discharge is lower than the sustain discharge generated between Y. That is, in the minute light emission process LL, although the discharge is accompanied by light emission having a higher luminance level than the first reset discharge, the discharge has a lower luminance level associated with the discharge than the sustain discharge, that is, a minute amount that can be used for display. A discharge accompanied by light emission is generated as a minute light emission discharge. At this time, in the first selective write address process W1 _W performed immediately before the minute light emission process LL, a selective write address discharge is generated between the column electrode D and the row electrode Y in the pixel cell PC. Therefore, in the subfield SF1, the luminance corresponding to the gradation that is higher by one level than the luminance level 0 is expressed by the light emission accompanying the selective write address discharge and the light emission accompanying the minute light emission discharge.

  After the minute light emission discharge, a negative wall charge is formed in the vicinity of the row electrode Y, and a positive wall charge is formed in the vicinity of the column electrode D.

Next, in the first half of the second reset step R2 of the subfield SF2, the Y electrode driver 53 has a positive polarity reset having a waveform in which the potential transition at the leading edge with the passage of time is gentler than the sustain pulse. pulse _{RP2 Y1} applied to all the row electrodes _Y 1 to Y _n. The peak potential of the reset pulse RP2 _Y1 is higher than the peak potential of the reset pulse RP1 _Y1 . During this time, the address driver 55 sets the column electrodes D _{1 to} D _m to a ground potential (0 volt) state, and the X electrode driver 51 is a surface between the row electrodes X and Y accompanying the application of the reset pulse RP2 _Y1. A positive reset pulse RP2 _X having a peak potential capable of preventing discharge is applied to each of all the row electrodes X _{1 to} X _n . If the is no surface discharge between the row electrodes X and Y, X electrode driver 51, instead of applying the reset pulse RP2 _X, sets all of the row electrodes X ₁ to X _n to the ground potential (0 volt) You may make it do. In response to the application of the reset pulse RP2 _Y1 , the minute light emission process is performed between the row electrode Y and the column electrode D in the pixel cell PC in which the column side cathode discharge is not generated in the minute light emission process LL in each pixel cell PC. A first reset discharge that is weaker than the column-side cathode discharge at LL occurs. That is, in the first half of the second reset process R2, by applying a voltage between both electrodes so that the row electrode Y is on the anode side and the column electrode D is on the cathode side, the row electrode Y is directed toward the column electrode D. The column side cathode discharge through which current flows is generated as the first reset discharge. On the other hand, in the pixel cell PC in which the minute light emission discharge has already occurred in the minute light emission process LL, no discharge is generated even if the reset pulse RP2 _Y1 is applied. Therefore, immediately after the end of the first half of the second reset process R2, negative wall charges are formed in the vicinity of the row electrodes Y in all the pixel cells PC, and positive wall charges are formed in the vicinity of the column electrodes D. Become.

Next, in the second half of the second reset step R2 of the subfield SF2, the Y electrode driver 53 applies a negative polarity reset pulse RP2 _Y2 having a gentle potential transition at the leading edge with the passage of time to the row electrodes Y ₁ to Y ₂ . It is applied to the Y _n. Furthermore, in the second half of the second resetting step R2, X electrode driver 51, applies a base pulse BP ⁺ to the row electrodes X ₁ to X _n each having a predetermined base potential of positive polarity. In response to the application of the negative reset pulse RP2 _Y2 and the positive base pulse BP ^+, a second reset discharge is generated between the row electrodes X and Y in all the pixel cells PC. The peak potentials of the reset pulse RP2 _Y2 and the base pulse BP ⁺ are surely determined between the row electrodes X and Y in consideration of wall charges formed in the vicinity of the row electrodes X and Y by the first reset discharge. 2 The lowest potential that can cause a reset discharge. Negative peak potential in the reset pulse RP2 _Y2 is set higher potential, the potential close to that is 0 volts than the peak potential of negative polarity write scan pulse SP _W. That is, when the peak potential of the reset pulse RP2 _Y2 would be lower than the peak potential of the write scan pulse SP _W, the occurrence strong discharge between the row electrodes Y and column electrodes D, are formed near the column electrode D wall charges erases greatly, because the address discharge in the second selective write addressing step W2 _W becomes unstable. Here, the wall charges formed in the vicinity of the row electrodes X and Y in each pixel cell PC are erased by the second reset discharge generated in the second half of the second reset step R2, and all the pixel cells are erased. The PC is initialized to the off mode. Further, in response to the application of the reset pulse RP2 _Y2, a weak discharge is generated between the row electrode Y and the column electrode D in all the pixel cells PC, and the positive electrode formed in the vicinity of the column electrode D by the discharge. erases a portion of sexual wall charges are adjusted to an amount that can correctly to rise to selective write address discharge in the second selective write addressing step W2 _W.

Next, in the second selective write addressing step W2 _W of the subfield SF2, Y electrode driver 53, the base pulse BP having a predetermined base potential of negative polarity as shown in FIG. 14 ^- to the row electrodes _Y 1 to Y _n while applying simultaneously, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. X electrode driver 51 continues the row electrodes _X 1 to X _n be the base pulse BP ⁺ applied to the row electrodes _X 1 to X _n in the second half portion in the second selective write addressing step W2 _W of the second reset step R2 Apply to each. Base pulse BP ^- and the base pulse BP ⁺ is each potential, the potential at which the voltage between the row electrodes X and Y during the non-application period of the write scan pulse SP _W is lower than the discharge start voltage of the pixel cell PC Is set. Further, in the second selective write address process W2 _W, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF2 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 that should set the pixel cell PC to the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of a low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, it is between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode selective write address discharge Is born. Further, immediately after the selective write address discharge, a weak discharge is also generated between the row electrodes X and Y in the pixel cell PC. That is, after the write scan pulse SP _W is applied, the row electrodes X and Y between the base pulse BP to ^- but and voltage corresponding to the base pulse BP ⁺ is applied, the voltage discharge of the pixel cell PC Since the voltage is set lower than the start voltage, the discharge is not generated in the pixel cell PC only by applying the voltage. However, when the selective write address discharge is caused, is induced in the selective write address discharge, the base pulse BP ^- and the discharge between the row electrodes X and Y only voltage applied based on the base pulse BP ⁺ is occurring It is done. Such a discharge is not generated in the first selective write address process W1 _W in which the base pulse BP ⁺ is not applied to the row electrode X. By this discharge and selective write address discharge, the pixel cell PC has positive wall charges in the vicinity of the row electrode Y, negative wall charges in the vicinity of the row electrode X, and negative wall charges in the vicinity of the column electrode D. Each formed state, that is, the lighting mode is set. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrode Y within the pixel cell PC in which the pixel data pulse DP is applied a low voltage to be set to off-mode (0 volt) described above Such selective write address discharge does not occur, and therefore no discharge occurs between the row electrodes X and Y. Therefore, the pixel cell PC maintains the state immediately before that, that is, the extinguished mode state initialized in the second reset step R2.

Next, in the sustain process I of the subfield SF2, the Y electrode driver 53 generates a sustain pulse IP having a positive peak potential for one pulse and applies it to each of the row electrodes Y _{1 to} Y _n simultaneously. During this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the ground potential (0 volt) state, and the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volt) state. Set. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the pixel cell PC set in the lighting mode as described above. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, whereby one display light emission corresponding to the luminance weight of the subfield SF2 is performed. . Further, in response to the application of the sustain pulse IP, a discharge is also generated between the row electrode Y and the column electrode D in the pixel cell PC set in the lighting mode. By this discharge and the sustain discharge, negative wall charges are formed in the vicinity of the row electrode Y in the pixel cell PC, and positive wall charges are formed in the vicinity of the row electrode X and the column electrode D, respectively. After the application of the sustain pulse IP, the Y electrode driver 53 applies the wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge with time as shown in FIG. It applied to the Y ₁ to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the pixel cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed inside the pixel cell PC is erased. . Thus, the amount of wall charges within the pixel cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

Next, in subfields SF3~SF14 each selective erase address process W _O, Y electrode driver 53, while applying the base pulse BP ⁺ to the row electrodes _Y 1 to Y _n, each having a predetermined base potential of positive polarity, an erase scan pulse SP _D with a negative peak potential of the as shown in FIG. 14 successively alternatively applied to the row electrodes Y ₁ to Y _n, respectively. The peak potential of the base pulse BP ⁺ is set to a potential that can prevent erroneous discharge between the row electrodes X and Y during the execution period of the selective erase address process W _O. Further, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 volt) during the execution period of the selective erasure address process W _O. In this selective erase address process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF to the pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the address driver 55 converts a pixel drive data bit having a logic level 1 to change the pixel cell PC from the lighting mode to the extinguishing mode, and converts it into a pixel data pulse DP having a positive peak potential. To do.

On the other hand, when a pixel driving data bit having a logic level 0 to maintain the current state of the pixel cell PC is supplied, it is converted into a pixel data pulse DP of a low voltage (0 volts). The address driver 55 applies the pixel data pulse DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erasing scan pulse SP _D by one display line (m). At this time, simultaneously with the erase scanning pulse SP _D, selective erase address discharge between the column electrode D and the row electrodes Y in the high-voltage pixel cell PC in which the pixel data pulse DP is applied is caused. By this selective erasure address discharge, the pixel cell PC is in a state in which positive wall charges are formed in the vicinity of the row electrodes Y and X and negative wall charges are formed in the vicinity of the column electrodes D, that is, the extinction mode. Set to On the other hand, simultaneously with the erase scanning pulse SP _D, as mentioned above selective erase address discharge between the column electrode D and the row electrodes Y of the pixel data pulse DP pixel cell PC which is applied a low voltage (0 volts) occurs Not. Therefore, this pixel cell PC maintains the state (lighting mode, extinguishing mode) until just before that.

Next, in the sustain process I of each of the subfields SF3 to SF14, the X electrode driver 51 and the Y electrode driver 53 perform the number of times corresponding to the luminance weight of the subfield alternately with the row electrodes X and Y as shown in FIG. (even number) fraction by repeatedly applying a sustain pulse IP having a peak potential of positive polarity to the row electrodes _X 1 to X _n and _Y 1 to Y _n, respectively. Each time the sustain pulse IP is applied, a sustain discharge is generated between the row electrodes X and Y in the pixel cell PC set in the lighting mode. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, so that display light emission is performed for the number of times corresponding to the luminance weight of the subfield SF. . At this time, in the vicinity of the row electrode Y in the pixel cell PC in which the sustain discharge is generated according to the sustain pulse IP finally applied in the sustain process I of each of the subfields SF2 to SF14, Positive wall charges are formed in the vicinity of X and the column electrode D. After the final sustain pulse IP is applied, the Y electrode driver 53 performs a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge with time as shown in FIG. applied to the electrodes _Y 1 to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the pixel cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed inside the pixel cell PC is erased. . Thus, the amount of wall charges within the pixel cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

Then, after the end of the sustain process I in the final subfield SF14, the erase process E is executed. In the erasing step E, the Y electrode driver 53 applies an erasing pulse EP having a negative peak potential to all the row electrodes Y _{1 to} Y _n . In response to the application of the erase pulse EP, an erase discharge is generated only in the pixel cell PC in the lighting mode state. The pixel cell PC which has been in the lighting mode state due to the erasing discharge is changed to the light-off mode state.

  The above driving is executed based on 16 kinds of pixel driving data GD as shown in FIG.

  First, as shown in FIG. 13, in the second gradation representing the luminance by one level higher than the first gradation representing the black display (luminance level 0), only the pixel SF1 in the subfields SF1 to SF14 is used. A selective write address discharge for setting the PC in the lighting mode is generated, and the pixel cell PC set in the lighting mode is caused to emit a small amount of light (indicated by a square). At this time, the luminance level at the time of light emission accompanying the selective write address discharge and the minute light emission discharge is lower than the luminance level at the time of light emission accompanying one sustain discharge. Therefore, when the luminance level visually recognized by the sustain discharge is “1”, the luminance corresponding to the luminance level “α” lower than the luminance level “1” is expressed in the second gradation.

  Next, in the third gradation that represents one level higher than the second gradation, the selective write address discharge for setting the pixel cell PC to the lighting mode only with SF2 of the subfields SF1 to SF14. Is generated (indicated by a double circle), and a selective erasure address discharge for causing the pixel cell PC to transition to the extinguishing mode is generated in the next subfield SF3 (indicated by a black circle). Therefore, in the third gradation, light emission associated with one sustain discharge is performed only in the sustain process I of SF2 of the subfields SF1 to SF14, and the luminance corresponding to the luminance level “1” is expressed.

  Next, in the fourth gradation representing the brightness higher by one level than the third gradation, first, in the subfield SF1, a selective write address discharge for setting the pixel cell PC to the lighting mode is generated, The pixel cell PC set in this lighting mode is subjected to minute light emission discharge (indicated by □). Further, in the fourth gradation, a selective write address discharge for causing the pixel cell PC to be set to the lighting mode is generated only by SF2 of the subfields SF1 to SF14 (indicated by a double circle), and the following In the subfield SF3, a selective erasure address discharge for causing the pixel cell PC to transition to the extinguishing mode is generated (indicated by a black circle). Therefore, in the fourth gradation, the light emission of the luminance level “α” is performed in the subfield SF1, and the sustain discharge accompanied by the light emission of the luminance level “1” is performed only once in the SF2. The luminance corresponding to “α” + “1” is expressed.

  In each of the fifth to sixteenth gradations, a selective write address discharge for causing the pixel cell PC to be set in the lighting mode is generated in the subfield SF1, and the pixel cell PC set in this lighting mode is caused to emit a small amount of light ( □) Then, a selective erasure address discharge for causing the pixel cell PC to transition to the extinguishing mode is caused only in one subfield corresponding to the gradation (indicated by a black circle). Therefore, in each of the fifth to sixteenth gradations, the minute light emission discharge is generated in the subfield SF1, the sustain discharge for one time is generated in SF2, and then the number corresponding to the gradation is continuous. In each of the subfields (indicated by white circles), the sustain discharge is generated for the number of times assigned to the subfield. Thereby, in each of the fifth to 16th gradations, the brightness corresponding to the brightness level “α” + “the total number of sustain discharges generated in one field (or one frame) display period” is visually recognized.

  That is, according to the driving as shown in FIG. 13, the luminance range from “0” to “255 + α” can be expressed in 16 levels as shown in FIG.

  According to such driving, since the areas where the light emission patterns (lighted state, unlit state) are mutually inverted within one field display period are not mixed in one screen, the pseudo contour generated in such a state is not present. Is prevented.

  In the drive shown in FIG. 14, in the first step S1 of the first reset step R of the first subfield SF1, a weak discharge is generated with the row electrode Y having a negative polarity (cathode side). Later, the amount of positive wall charges increases in the vicinity of the row electrode Y compared to before the discharge. In addition, by generating a weak discharge in which the column electrode D has a positive polarity (anode side), negative wall charges increase in the vicinity of the column electrode D after the discharge compared to before the discharge. Due to this wall charge state, a first reset discharge called column-side cathode discharge in which current flows from the row electrode Y to the column electrode D with the column electrode D as the cathode side in the next step S2 is likely to occur. That is, since the discharge probability of the first reset discharge in step S2 is further increased, the black luminance is further decreased and the dark contrast is improved. Moreover, by generating discharge in step S1, the number of priming particles increases, and the discharge probability of the first reset discharge in step S2 further increases due to this priming effect. That is, the reset discharge in step S2 is stabilized by the two actions of the wall charge action and the priming action, so that the discharge probability increases, the black luminance decreases, and the dark contrast increases.

  As described above, the wall charge adjustment pulse CP ′ in step S1 is a pulse with a long time constant, and between the row electrode Y and the row electrode X and between the row electrode Y and the column electrode D, as compared with the reset discharge. Therefore, the discharge is smaller than that of the reset discharge. Therefore, the dark discharge in step S1 hardly affects the dark contrast.

If the discharge intensity at step S1 is greater than the discharge intensity at step S3, unnecessary wall charges may remain in the vicinity of each electrode after the discharge at step S3. In this case, this unwanted wall charges, write miss pixel cells occurs generated by the address discharge of the selective write address process W _W subsequent to the step S3. From the above points, it is preferable that the discharge intensity in step S1 is weaker than the discharge intensity in step S3.

  The following methods (1) to (3) are employed as a method of weakening the discharge intensity in step S1 than the discharge intensity in step S3.

(1) The positive potential Va of the base pulse BP ′ in step S1 is set lower than the potential Vb of the base pulse BP ″ in step S3. For example, the base pulse BP ⁺ having a lower potential than the base pulse BP ″ The same potential as the potential.

(2) a negative target potential Vc of the wall charge adjusting pulse CP 'at step S1, is set higher than the ultimate potential Vd of the second reset pulse RP _Y2 in step S3.

(3) the pulse width Te of the wall charge adjusting pulse CP 'at step S1, is set to be shorter than the pulse width Tf of the second reset pulse RP _Y2 in step S3.

  By any one of these methods (1) to (3) or a combination of two or more of (1) to (3), the discharge intensity at step S1 is weaker than the discharge intensity at step S3. can do.

  Further, in the drive shown in FIG. 14, in each of the first reset step R1 of the subfield SF1 and the second reset step R2 of SF2, a voltage with the column electrode D as the cathode side and the row electrode Y as the anode side is set between the two electrodes. As a result, a column side cathode discharge in which a current flows from the row electrode Y to the column electrode D is generated as a first reset discharge. Therefore, at the time of the first reset discharge, when the cations in the discharge gas head toward the column electrode D, the MgO crystal as the secondary electron emission material contained in the phosphor layer 17 as shown in FIG. Collisions cause secondary electrons to be emitted from the MgO crystal. In particular, in the PDP 50 of the plasma display device shown in FIG. 1, by exposing the MgO crystal body to the discharge space as shown in FIG. 5, the probability of collision with cations is increased, and the secondary electrons are efficiently put into the discharge space. It is trying to release. Then, since the discharge start voltage of the pixel cell PC is lowered by the priming action by the secondary electrons, it is possible to cause a relatively weak reset discharge. Therefore, since the emission luminance associated with the discharge is reduced due to weakening of the reset discharge, it is possible to perform display with improved contrast when displaying a dark image, so-called dark contrast.

  Further, in the drive shown in FIG. 14, a first reset discharge is generated between the row electrode Y formed on the front transparent substrate 10 side and the column electrode D formed on the back substrate 14 side as shown in FIG. I am letting. Therefore, compared with the case where reset discharge is caused between the row electrodes X and Y formed on the front transparent substrate 10 side, less discharge light is emitted to the outside from the front transparent substrate 10 side. The dark contrast can be improved.

  In the driving shown in FIG. 12 to FIG. 14, in the first subfield SF <b> 1, after a reset discharge that should initialize all the pixel cells PC to the light-off mode state is generated, the pixel cells PC in the light-off mode state are turned on. A selective write address discharge to be changed to the state is generated. Then, a selective erasure address method of causing a selective erasure address discharge in which one of the subfields SF3 to SF14 following SF2 is to cause the pixel cell PC in the lighting mode state to transition to the light-off mode state is generated. The adopted drive is carried out. Therefore, when black display (luminance level 0) is performed by driving according to the first gradation as shown in FIG. 6, the discharge generated during the one-field display period is only the reset discharge in the first subfield SF1. Therefore, as compared with the case where the drive for generating the selective erasure address discharge for causing the reset discharge for initializing all the pixel cells PC to the lighting mode state in the subfield SF1 and then shifting the pixel cell PC to the lighting mode state is adopted. Since the number of discharges that occur during one field display period is reduced, dark contrast can be improved.

  In the driving shown in FIGS. 12 to 14, in the subfield SF1 having the smallest luminance weight, a minute light-emitting discharge is generated instead of the sustain discharge as the discharge contributing to the display image. At this time, since the minute light emission discharge is a discharge generated between the column electrode D and the row electrode Y, the luminance level at the time of light emission accompanying the discharge is higher than that of the sustain discharge generated between the row electrodes X and Y. Low. Therefore, when the brightness is expressed by one level higher than the black display (luminance level 0) by the minute light emission discharge (second gradation), the luminance of the brightness level 0 is compared to the case where this is expressed by the sustain discharge. The difference is small. Therefore, the gradation expression ability when expressing a low luminance image is enhanced. Further, in the second gradation, since the reset discharge is not generated in the second reset process R2 of SF2 following the subfield SF1, a decrease in dark contrast due to the reset discharge is suppressed.

In the drive shown in FIG. 14, the peak potential of the reset pulse RP1 _Y1 applied to the row electrode Y to cause the first reset discharge in the first reset step R1 of the subfield SF1 is changed to the second potential in the second reset step R2 of SF2. The reset pulse RP2 applied to the row electrode Y to cause one reset discharge is set lower than the peak potential of the _Y1 . As a result, in the first reset step R1 of the subfield SF1, the light emission when all the pixel cells PC are reset and discharged at the same time is weakened, and the decrease in dark contrast is suppressed.

Further, in the driving shown in FIGS. 12 to 14, in the sustain process I of the subfield SF2 in which the luminance weight is the second smallest, the sustain discharge is caused only once to express the low luminance image. The gradation expression ability is enhanced. In the sustain process I of the subfield SF2, since the sustain pulse IP applied to generate the sustain discharge is only once, the vicinity of the row electrode Y after the end of the sustain discharge generated according to the sustain pulse IP for one time. In this state, negative wall charges are formed, and positive wall charges are formed in the vicinity of the column electrodes D. Thus, in the selective erase address process W _D of the next subfield SF3, discharges with the column electrodes D as an anode side between the column electrode D and the row electrodes Y (hereinafter, referred to as a column-side anode discharge) the selective erase address discharge Can be generated. On the other hand, in the sustain process I of each of the subsequent subfields SF3 to SF14, the number of times the sustain pulse IP is applied is an even number. Therefore, immediately after the end of each sustain step I, negative wall charges are formed in the vicinity of the row electrode Y, and positive wall charges are formed in the vicinity of the column electrode D. In that selective erase address process W _D, it is possible to train side anode discharge. Therefore, only a positive pulse is applied to the column electrode D, and the cost of the address driver 55 is suppressed.

  In the driving shown in FIG. 12 to FIG. 14, the light emission minute emission discharge accompanied by the light emission of the luminance level α is generated in the subfield SF1 also in the gradation after the fourth gradation. The minute light emission discharge may not be generated in the gradation after the gradation. In short, since light emission associated with minute light emission discharge has extremely low luminance (brightness level α), when used in combination with sustain discharge with light emission higher than this, that is, in the gradation after the third gradation, This is because it is not necessary to cause the minute light emission discharge when the increase in luminance at the level α cannot be visually recognized.

In the embodiment shown in FIG. 14, the minute light emission pulse LP and the reset pulse RP2 _Y1 are connected and applied to the row electrode Y. However, as shown in FIG. You may make it apply to the row electrode Y sequentially.

  Further, in the reset process R shown in FIG. 14, the reset discharge is generated simultaneously for all the pixel cells. However, the reset discharge is performed for each pixel cell block composed of a plurality of pixel cells. You may be made to carry out dispersion | distribution in time.

  In FIG. 5, MgO crystal is included in the phosphor layer 17 provided on the back substrate 14 side of the PDP 50. However, as shown in FIG. A secondary electron emission layer 18 made of a secondary electron emission material is provided so as to cover the surface of the body particle layer 17a, and the laminated phosphor particle layer 17a and secondary electron emission layer 18 are used as the phosphor layer 17. May be. At this time, the secondary electron emission layer 18 is formed by laying a crystal made of a secondary electron emission material (for example, MgO crystal including a CL emission MgO crystal) on the surface of the phosphor particle layer 17a. Alternatively, the secondary electron emission material may be formed by forming a thin film.

It is a figure which shows schematic structure of the plasma display apparatus to which this invention is applied. It is a front view which shows typically the internal structure of PDP in the apparatus of FIG. It is a figure which shows the cross section on the VV line | wire shown by FIG. It is a figure which shows the cross section on the WW line shown by FIG. It is a figure which represents typically the MgO crystal | crystallization contained in the fluorescent substance layer of each pixel cell of PDP of FIG. It is a figure which shows the light emission pattern for every gradation. It is a figure which shows an example of the light emission drive sequence at the time of employ | adopting the selective erase address method as a light emission drive system in the apparatus of FIG. It is a figure which shows the various drive pulses applied to PDP according to the light emission drive sequence of FIG. It is a figure showing transition of the discharge intensity in the column side cathode discharge produced when a reset pulse is applied with respect to the conventional PDP. It is a figure showing transition of the discharge intensity in the column side cathode discharge which arises when a reset pulse is applied with respect to PDP which has the structure of FIG. It is a figure showing the other waveform of a reset pulse. It is a figure which shows the other example of the light emission drive sequence at the time of employ | adopting the selective writing address method as a light emission drive system in the apparatus of FIG. It is a figure which shows the light emission pattern for every gradation in the light emission drive sequence of FIG. It is a figure which shows the various drive pulses applied to PDP according to the light emission drive sequence of FIG. It is a figure which shows the modification of the micro light emission pulse of FIG. 14, and a reset pulse. It is a figure which shows the other structural example of the fluorescent substance layer of each pixel cell of PDP of FIG.

Explanation of main part codes

13 Magnesium oxide layer 17 Phosphor layer 50 PDP
51 X electrode driver 53 Y electrode driver 55 Address driver
56 Drive control circuit

Claims (31)

A first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of row electrode pairs formed on the first substrate and a plurality formed on the second substrate. A plasma display panel driving method for driving a plasma display panel in which a pixel cell including a phosphor layer is formed at each intersection with a column electrode according to pixel data for each pixel based on a video signal. ,
The phosphor layer includes a phosphor material and a secondary electron emission material,
Performing a first reset process for initializing the pixel cells in a first subfield when a one-field display period in the video signal is divided into a plurality of subfields;
An address process for setting the pixel cell to a lighting mode or a non-lighting mode by selectively discharging the pixel cell according to the pixel data in all the subfields of the plurality of subfields, and the lighting mode. A sustain discharge process for causing the set pixel cells to perform a sustain discharge is sequentially executed,
The first reset step includes applying a first pulse on the cathode side to the other row electrode and the column electrode of the row electrode pair to one row electrode of the row electrode pair;
A second step of applying, to the one row electrode, a second pulse on the anode side with respect to the column electrode;
3. A plasma display panel driving method, comprising: sequentially performing a third step of applying, to the one row electrode, a third pulse on the cathode side with respect to the other row electrode and the column electrode.   2. The method of driving a plasma display panel according to claim 1, wherein in the first step, a first base pulse having a positive potential is applied to the other row electrode.   In the third step, a second base pulse having a positive potential is applied to the other row electrode, and the potential of the first base pulse is lower than the potential of the second base pulse. The method of driving a plasma display panel according to claim 2.   The arrival potential of the first pulse and the arrival potential of the third pulse are both negative, and the arrival potential of the first pulse is higher than the arrival potential of the third pulse. The method for driving a plasma display panel according to claim 1.   2. The method of driving a plasma display panel according to claim 1, wherein a pulse width of the first pulse is shorter than a pulse width of the third pulse.   2. The method of driving a plasma display panel according to claim 1, wherein the first pulse and the third pulse are applied in such a manner that the potential applied to the one row electrode is gradually decreased with time. .   2. The driving of a plasma display panel according to claim 1, wherein a second reset process for initializing the pixel cell is further performed at a head portion of a second subfield subsequent to the head subfield. Method.   In the first reset process, the one row electrode and the column electrode are applied by applying a voltage between the one row electrode and the column electrode, with the one row electrode serving as the anode side and the column electrode serving as the cathode side. 2. The method of driving a plasma display panel according to claim 1, wherein a reset discharge is generated between the two.   In the second reset process, the one row electrode and the column electrode are applied by applying a voltage between the one row electrode and the column electrode, with the one row electrode serving as the anode side and the column electrode serving as the cathode side. 8. The method of driving a plasma display panel according to claim 7, wherein a reset discharge is generated between the two.   10. The plasma display panel according to claim 8, wherein a potential for preventing a discharge between the other row electrode and the one row electrode is applied to the other row electrode during the reset discharge. Driving method.   10. The method of driving a plasma display panel according to claim 8, wherein a positive potential is applied to each of the one row electrode and the other row electrode during the reset discharge.   In the first subfield, the sustain discharge pulse is applied only once to the one row electrode subsequent to the address process, so that only the pixel cell set in the lighting mode is sustain-discharged only once. 2. The method of driving a plasma display panel according to claim 1, wherein a sustain discharge process is performed.   In the second subfield, subsequent to the addressing process, by applying a sustain discharge pulse only to the one row electrode only once, only the pixel cell set in the lighting mode is only applied once. 8. The method of driving a plasma display panel according to claim 7, wherein a sustain discharge process for sustain discharge is performed.   2. The method of driving a plasma display panel according to claim 1, wherein the pixel cell is initialized only in the first subfield of each of the subfields within one field display period.   8. The driving of a plasma display panel according to claim 7, wherein the pixel cell is initialized only in the first subfield and the second subfield in each of the subfields in one field display period. Method.   In the addressing process of the first subfield, the pixel cell is set to the lighting mode by selectively discharging and writing the pixel cell according to the pixel data, and follows the first subfield. 2. The plasma according to claim 1, wherein the pixel cell is set in the extinguishing mode by selectively erasing and discharging the pixel cell in accordance with the pixel data in an address process of all subfields. Display panel drive method.   In the addressing process of the first subfield and the second subfield, the pixel cell is set to the lighting mode by selectively writing and discharging the pixel cell according to the pixel data; In the address process of all the subfields subsequent to the second subfield, the pixel cells are selectively erased and discharged according to the pixel data to set the pixel cells to the extinguishing mode. The method for driving a plasma display panel according to claim 7.   During the reset discharge, a voltage that causes the reset discharge is generated between the column electrode and the one row electrode by gradually increasing the potential applied to the one row electrode with time. The method for driving a plasma display panel according to claim 8 or 9.   The negative base potential is applied to the one row electrode and the positive base potential is applied to the other row electrode of the row electrode pair in the address process of the first subfield. Item 8. A method for driving a plasma display panel according to Item 1.   In the address process of the second subfield, a negative base potential is applied to the one row electrode, and a positive base potential is applied to the other row electrode of the row electrode pair, The method for driving a plasma display panel according to claim 7.   Immediately after the addressing process in the first subfield, a voltage is applied between the one row electrode and the column electrode, with one row electrode of the row electrode pair serving as the anode side and the column electrode serving as the cathode side. To execute a micro light emission process for generating a micro light emission discharge between the column electrode and the one row electrode in the pixel cell set in the lighting mode in the address process in the head subfield. The method for driving a plasma display panel according to claim 9.   22. The method of driving a plasma display panel according to claim 21, wherein the minute light emission discharge is a discharge accompanied by light emission corresponding to a gradation having a luminance higher by one level than a luminance level of zero.   In the second reset process of the second subfield, the reset discharge is generated by gradually increasing the potential applied to the one row electrode with time so as to generate the minute light emission discharge. The method of driving a plasma display panel according to claim 21.   The rate of change over time in the rising section of the potential applied to the one row electrode to cause the minute light emission discharge in the minute light emission stroke is applied to the one row electrode to cause the reset discharge. 22. The method of driving a plasma display panel according to claim 21, wherein the rate of change is higher than the rate of change with time in the potential rising section. In each subfield subsequent to the second subfield, only the pixel cell in the lighting mode is maintained by alternately applying a sustain pulse to each of the one row electrode and the other row electrode. Execute the sustain discharge process to discharge,
The method of driving a plasma display panel according to claim 21, wherein a potential applied to the one row electrode to cause the minute light emission discharge in the minute light emission process is lower than a peak potential of the sustain pulse.   2. The method of driving a plasma display panel according to claim 1, wherein the secondary electron emission material is made of magnesium oxide.   27. The driving method of a plasma display panel according to claim 26, wherein the magnesium oxide includes a magnesium oxide crystal that emits cathode luminescence light having a peak in a wavelength range of 200 to 300 nm when excited by an electron beam.   28. The driving method of the plasma display panel according to claim 27, wherein the magnesium oxide crystal is generated by a gas phase oxidation method.   2. The method of driving a plasma display panel according to claim 1, wherein the particles made of the secondary electron emission material are in contact with the discharge gas in the discharge space. A first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of row electrode pairs formed on the first substrate and a plurality formed on the second substrate. A plasma display panel driving method for driving a plasma display panel in which a pixel cell is formed at each intersection with the column electrode according to pixel data for each pixel based on a video signal,
Performing a reset process for initializing the pixel cell in a first subfield when a one-field display period in the video signal is divided into a plurality of subfields;
An address process for setting the pixel cell to a lighting mode or a non-lighting mode by selectively discharging the pixel cell according to the pixel data in all the subfields of the plurality of subfields, and the lighting mode. A sustain discharge process for causing the set pixel cells to perform a sustain discharge is sequentially executed,
The reset process includes a first step of applying, to one row electrode of the row electrode pair, a first pulse on the cathode side with respect to the other row electrode and the column electrode of the row electrode pair;
A second step of applying, to the one row electrode, a second pulse on the anode side with respect to the column electrode;
A third step of sequentially applying, to the one row electrode, a third pulse on the cathode side with respect to the other row electrode and the column electrode,
In the second step, a positive potential is applied to each of the one row electrode and the other row electrode, and the driving method of the plasma display panel. A first substrate and a second substrate are arranged to face each other across a discharge space in which a discharge gas is sealed, and a plurality of row electrode pairs formed on the first substrate and a plurality formed on the second substrate. A plasma display panel driving method for driving a plasma display panel in which a pixel cell is formed at each intersection with the column electrode according to pixel data for each pixel based on a video signal,
Performing a reset process for initializing the pixel cell in a first subfield when a one-field display period in the video signal is divided into a plurality of subfields;
An address process for setting the pixel cell to a lighting mode or a non-lighting mode by selectively discharging the pixel cell according to the pixel data in all the subfields of the plurality of subfields, and the lighting mode. A sustain discharge process for causing the set pixel cells to perform a sustain discharge is sequentially executed,
The reset process includes a first step of applying, to one row electrode of the row electrode pair, a first pulse on the cathode side with respect to the other row electrode and the column electrode of the row electrode pair;
A second step of applying, to the one row electrode, a second pulse on the anode side with respect to the column electrode;
A third step of sequentially applying, to the one row electrode, a third pulse on the cathode side with respect to the other row electrode and the column electrode,
In the first step, the first pulse having a negative potential is applied to the one row electrode, and the first base pulse having a positive potential is applied to the other row electrode. To drive a plasma display panel.

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