JP2008130159A - Error correction apparatus and recording/reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when an error detection correction circuit reads data from an ECC block memory to detect and correct an error, the correction efficiency of the circuit is deteriorated if a past synchronization signal detection result or BIS data remains without being overwritten by new demodulation data in the ECF block memory. <P>SOLUTION: An FF data overwriting circuit 23 writes a byte FFh in the predetermined address of an area of the ECC block memory 21. Demodulation data is written in the ECC block memory 21 at a subsequent timing. In this case, data obtained by applying error detection and correction to previous demodulation data and the FFh data written by the FF data overwriting circuit 23 are overwritten. However, when the data to be transferred are partially lost and stored in a position different from the original position of the ECC block memory 21, the previous FFh data remains without being overwritten, and thus erasure correction is carried out by error correction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an error correction apparatus and a recording / reproducing apparatus, and more particularly to an error correcting apparatus that corrects a code error of a signal to which an error correcting code based on a Reed-Solomon code is added, and a recording / reproducing apparatus that records and reproduces the error correction code. .

  In an optical disc having a high recording density, for example, a Blu-ray Disc, an error correction block (ECC block) called a picket code (Picket Code) is used in order to improve correction capability for a burst error of a reproduction signal due to a very thin cover layer. ) (See Non-Patent Document 1, for example). That is, the ECC block is configured in units of 64 kbytes of user data, and the user data is protected by a Reed-Solomon code composed of 304 code words. Each code word of the Reed-Solomon code is 216. Information symbols (in the case of Blu-ray Disc C, one symbol is 1 byte) and 32 parity symbols, and as shown in FIG. 6, constitutes an ECC block of 152 bytes wide and 496 bytes long. . One code word is composed of data every other line in the vertical direction.

  In this one ECC block, the above four Picket Code columns are arranged at equal intervals, and the Picket code in the right three columns is protected by error correction coding by a burst indicator subcode (BIS). . The BIS code word is 62 symbols including 30 information symbols and 32 parity symbols, and three codek sequences each of which 24 code words are composed of 496 bytes (in FIG. Are interleaved and stored in columns B0, B1, and B2.

  That is, as shown in FIG. 6, the main signal is subjected to the error correction code by the Reed-Solomon code in the vertical direction of the ECC block configuration, and the BIS having information different from the main signal is also subjected to the error correction code by the Reed-Solomon code, It is embedded in the main signal constituting the ECC block as information for notifying an error position called Picket at a predetermined interval. Further, a synchronization signal Sync indicating a synchronization position is inserted at the beginning of each row in the horizontal direction of the ECC block (data recording method of the optical disk).

  FIG. 7 is a block diagram showing an example of a conventional error correction apparatus and an outline of a peripheral circuit. The reproduction signal of the format shown in FIG. 6 reproduced from the recording medium is detected by the synchronization detection circuit 11 and demodulated by the demodulation circuit 12 based on the timing of the synchronization signal Sync. The demodulated data obtained by the demodulation circuit 12 is written in the ECC block memory 13 in units of ECC blocks. The demodulated data written in the ECC block memory 13 is once read and supplied to the error detection and correction circuit 14, where error detection and error correction are performed.

  In the above error correction, for example, when the synchronization signal SY0 and the picket code B0 shown in FIG. 8 are known to be errors, 38 bytes of data D0 to data D37 between the synchronization signal SY0 and the picket code B0 are regarded as errors. Correct the deemed disappearance. The data error-corrected by the error detection / correction circuit 14 is written into the ECC block memory 13 again.

  Thereafter, the demodulated data read from the ECC block memory 13 is supplied to the subsequent signal processing circuit 15 where subsequent signal processing such as descrambling / deinterleaving is performed and then output as reproduction data. The circuit section from the demodulating circuit 12 to the subsequent signal processing circuit 15 constitutes a memory access block 16. The timing generation circuit 17 generates processing timing signals for the circuits 12, 14, and 15 in the memory access block 16 and supplies them to the circuits 12, 14, and 15.

  As described above, the reproduction signal in the above format uses the synchronization signal and the picket code as an index (pointer) indicating the position of the burst error, and regards a place where the synchronization signal and the picket code are continuously erroneous as a burst error, Perform erasure correction. This makes it possible to correct a burst error that greatly exceeds the correction capability obtained from the distance of the Reed-Solomon code applied in the vertical direction of the main data.

  In general, in order to read out desired data, address information is included at regular intervals of information data. As described above, the reproduction circuit detects the synchronization signal and the leading address of the ECC block from the signal reproduced from the recording medium by the synchronization detection circuit 11, and demodulates the subsequent information data in units of ECC blocks after the demodulation of the information data. Is temporarily stored, the information data in the ECC block memory 13 is read out, and error correction processing is performed by the error detection and correction circuit 14. As described above, error correction using the picket code is performed based on the detection result of the synchronization signal Sync. In order to use it as an index representing the position of the error, the ECC block memory 13 is sent with the availability of the detection result of the synchronization signal from the synchronization detection circuit 11 and held together with the information data.

Edited by Hiroki Eda et al., “Next-generation optical disc dismantling new book”, Nikkei BP, 2003, 72 pages

  By the way, the ECC block memory 13 stores the demodulated information data in units of ECC blocks. At this time, each data constituting the ECC block is stored in the ECC block unit in the ECC block memory 13. It needs to be stored at a fixed location. Since the data is stored at the determined position, the error detection and correction circuit 14 can correctly read the data.

  However, if the reproduction signal is disturbed due to dirt or scratches on the surface of the optical disk, an error may occur in the detection of the synchronization signal Sync in the synchronization detection circuit 11 or the demodulation in the demodulation circuit 12. In that case, a part of data to be transferred from the demodulation circuit 12 to the ECC block memory 13 may be lost, and the data may be stored in a position different from the original position in the ECC block memory 13. That is, there are cases where data for several rows in the ECC block of FIG. 6 cannot be stored in the ECC block memory 13 or cannot be stored in units of address units. Furthermore, in FIG. 6, the data of address unit 1 may be stored at the location of address unit 0.

  On the other hand, the information transferred in the past and the detection result of the synchronization signal may remain on the ECC block memory 13. Alternatively, when reproduction is performed after recording with the same apparatus, data used for recording may remain in the ECC block memory 13.

  In these cases, when the error detection / correction circuit 14 reads out the data from the ECC block memory 13 and processes the data, the detection result of the past synchronization signal and the BIS data are used. Therefore, the detection result of the synchronization signal that should be treated as an error or the BIS data is handled as an error-free one. As a result, an erasure (pointer) to be added to data between an erroneous synchronization signal and an erroneous picket code byte cannot be added. That is, the correction ability is reduced.

  The present invention has been made in view of the above points, and provides an error correction apparatus and a recording / reproducing apparatus that do not deteriorate the correction capability even when a reproduction signal is disturbed due to dirt or scratches on the surface of an optical disk. With the goal.

In order to achieve the above object, the error correction apparatus according to the first aspect of the present invention provides L information blocks (L is equal to or greater than 2) obtained by dividing the first information data into predetermined bytes. A natural number), a synchronization signal arranged at the head of the information transmission direction of each L information block, and second information data respectively inserted between the L information blocks The block is configured by arranging M rows (M is a natural number of 2 or more), and the first error correction code by the first Reed-Solomon code is added to the first information data, and the second A recording medium in which an error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added to the information data independently of the first information data is recorded. Play from A error correction device for performing error correction on regulating the error correction block,
Extracts the sync signal from the signal reproduced from the recording medium, and detects whether the sync signal is normally detected, and operates based on the timing of the sync signal extracted by the sync signal detection means A demodulating means for demodulating the signal reproduced from the recording medium to obtain an error correction block, and for outputting error data indicating whether the demodulated error correction block and the synchronization signal are normally detected; and a storage means The error correction of the second information data is performed using the second error correction code in the demodulated error correction block read out from, and two adjacent second information data determined to have an error by the error correction If it is determined that the second information data immediately before or immediately after the synchronization signal indicated by the availability data or not correctly detected by the availability data is in error, Error correction using the first error correction code in the demodulated error correction block with the first information data constituting the information block between the initial signal and the second information data determined to be error as erasure Or predetermined information in each information block immediately before and immediately after the synchronization signal indicating that it was not normally detected by one second information data or availability data determined to have an error by error correction. Error correction means for correcting the error by using the first error correction code by erasing the first information data between positions, and storing means each time the error correction processing of the error correction block after demodulation by the error correction means is completed The second error correction added to the availability data indicating whether or not the synchronization signal of the error correction block for which the error correction has been completed is normally detected, the second information data, and the second information data. The storage area of the code, and having a overwriting means for overwriting a predetermined data.

  In the present invention, it is added to the availability data, the second information data, and the second information data indicating whether or not the synchronization signal of the error correction block whose error correction has been completed by the overwriting means has been normally detected. In addition, since the storage area of the second error correction code is overwritten with predetermined data, when a part of the demodulated data to be demodulated thereafter is lost, a part of the storage area of the storage means In this case, the predetermined data that was previously overwritten by the overwriting means remains as it is without being overwritten by the demodulated data of this time. As a result, after the demodulated data is written, the error correction means and the second information The predetermined data is read out as data and the second error correction code, and error detection and correction becomes possible.

  In order to achieve the above object, an error correction apparatus according to a second invention is an error correction apparatus that performs error correction on an error correction block similar to that of the first invention, and is reproduced from a recording medium. The signal is demodulated to obtain an error correction block, and the demodulated error correction block and availability data indicating whether or not the synchronization signal is normally detected, and each of the synchronization blocks constituting the error correction block are synchronized after demodulation. Demodulation means for outputting synchronous block update data having a predetermined value indicating a block, and error-correcting blocks and propriety data after demodulation output from the demodulating means and synchronous block update data having a predetermined value Error correction of the second information data using the storage means for storing the correction block unit and the second error correction code in the demodulated error correction block read from the storage means And when the synchronization block update data read from the storage means is not a predetermined value, the first block constituting the information block between the synchronization signal included in the synchronization block indicated by the synchronization block update data and the second information data Error data is corrected using the first error correction code in the demodulated error correction block as erasure, and when the synchronization block update data has a predetermined value, in the synchronization block indicated by the synchronization block update data The second information data between two adjacent second information data determined to have an error by error correction, or immediately before or immediately after the synchronization signal indicating that the data is not normally detected by the availability data is an error. If it is determined that there is an information block that forms an information block between the synchronization signal and the second information data determined to be in error The information data is lost and error correction is performed using the first error correction code, or it is not normally detected by one second information data or pass / fail data determined to have an error by error correction. Error correction means for performing error correction using the first error correction code by erasing first information data between predetermined positions in each information block immediately before and immediately after the indicated synchronization signal; and error correction means And overwriting means for overwriting the storage area of the synchronous block update data of the error correction block for which the error correction of the storage means has been completed, every time the error correction processing of the error correction block after demodulation is completed by And

  In this invention, since the storage area of the synchronous block update data of the error correction block for which the error correction of the storage means has been completed by the overwriting means is overwritten with the predetermined data, a part of the demodulated data demodulated thereafter is missing. In such a case, a part of the storage area of the storage means is not overwritten with the demodulated data of this time, but the predetermined data overwritten by the overwriting means last time remains as it is, and as a result, the demodulated data After the writing, the above-mentioned predetermined data is read out as the synchronous block update data from the storage means by the error correction means, and error detection and correction becomes possible.

  In order to achieve the above object, the recording / reproducing apparatus of the third invention modulates an error correction block having the same configuration as the error correction block to be error-corrected in the first invention and records it on the recording medium. And a recording / reproducing apparatus that obtains an error correction block by demodulating a signal reproduced from a recording medium, the synchronization signal detecting means, the demodulating means, the storage means, and the error correcting means similar to the first invention, In addition, the first error correction code is added to the first information data input from the outside at the time of recording, and the second information data input from the outside or generated internally is second. Error correction coding means for adding the error correction code and storing it in the storage means, first and second information data stored in the error correction coding means from the storage means, and the first and second error correction codes, Read out the signal An error correction block for recording is constructed by adding a synchronization signal, and then the modulation / recording means that modulates the error correction block and records it on a recording medium, and error correction coding from the storage means by the modulation / recording means Each time the reading of the first and second information data and the first and second error correction codes stored by the means is completed, whether or not the error correction block corresponding to the read signal is reproduced is stored. A first storage area of the storage means, and a second storage area of the storage means for storing the second information data and the second error correction code added to the second information data at the time of reproduction, Each has overwriting means for overwriting with predetermined data.

  In the present invention, the overwrite means at the time of recording stores the first storage area of the storage means for storing the availability data at the time of reproduction of the error correction block to be recorded, the second information data and the second information data at the time of reproduction. Since the second storage area of the storage means in which the added second error correction code is stored is overwritten with predetermined data, the recording medium immediately after the error correction block is recorded on the recording medium. When the recorded information at another location is reproduced, the demodulated data caused by the disturbance of the reproduced signal for some reason when error correction of the reproduced signal is performed using the same storage means as at the time of recording. Due to missing or the like, the predetermined data overwritten by the overwriting unit at the time of recording remains in the storage unit as it is. As a result, after the demodulated data is written, the above-mentioned predetermined data is read out from the storage means by the error correction means as the availability data, the second information data, or the second error correction code, and error detection and correction becomes possible.

  In order to achieve the above object, the recording / reproducing apparatus of the fourth invention modulates an error correction block having the same structure as the error correction block to be error corrected in the second invention and records it on the recording medium. And a recording / reproducing apparatus for obtaining an error correction block by demodulating a signal reproduced from a recording medium, the same synchronization signal detecting means, demodulating means, storage means, error correcting means as in the second invention, In addition, the first error correction code is added to the first information data input from the outside at the time of recording, and the second information data input from the outside or generated internally is second. Error correction coding means for adding the error correction code and storing it in the storage means, first and second information data stored in the error correction coding means from the storage means, and the first and second error correction codes, Read out the signal An error correction block for recording is constructed by adding a synchronization signal, and then the modulation / recording means that modulates the error correction block and records it on a recording medium, and error correction coding from the storage means by the modulation / recording means Each time reading of the first and second information data and the first and second error correction codes stored by the means is completed, synchronous block update data is stored during reproduction of the error correction block corresponding to the read signal. And overwriting means for overwriting the storage area with predetermined data.

  In the present invention, every time reading of the first and second information data and the first and second error correction codes stored in the error correction coding means from the storage means by the modulation / recording means is completed by the overwriting means. In addition, by overwriting the storage area for storing the synchronous block update data during reproduction of the error correction block corresponding to the read signal with predetermined data, it has the same features as the third invention.

  According to the error correction apparatus of the present invention, the availability data, the second information data, and the second information indicating whether or not the synchronization signal of the error correction block for which the error correction of the storage means has been completed by the overwriting means has been normally detected. A storage area for the second error correction code added to the data or a storage area for synchronization block update data having a predetermined value indicating that each of the synchronization blocks constituting the error correction block is a demodulated synchronization block Is overwritten with predetermined data, and if some of the demodulated data to be demodulated thereafter is lost, etc., the error correction means writes the possibility data or the second information data from the storage means after writing the demodulated data. The predetermined data overwritten by the above-described overwriting means is read as the second error correction code or the synchronous block update data. Therefore, erasure correction can be performed, thereby making it possible to lower the probability that the reproduced data is lost.

  Further, according to the recording / reproducing apparatus of the present invention, the error correction block in which recording on the recording medium of the storage means in which the data subjected to error detection / correction encoding at the time of recording is stored in units of error correction blocks is synchronized. Overwrite the storage area where the data indicating whether or not the signal is detected and the storage area of the second information data and the second error correction code are overwritten with predetermined data, or the storage area of the synchronous block update data is predetermined When the same storage means is shared for recording and reproduction, even if a part of the demodulated data is missing, erasure correction can be performed. The probability that the reproduction data is lost can be lowered.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a block diagram of a main part of a first embodiment of an error correction apparatus according to the present invention. In this embodiment, as shown in FIG. 1, an ECC block memory 21 includes an ECC block memory 13, an error detection / correction circuit 14 and a subsequent signal processing circuit 15 in the memory access block 16 shown in FIG. , An error detection and correction circuit 22, an FF data overwrite circuit 23, and a subsequent signal processing circuit 24.

  In the ECC block memory 21, the demodulated data obtained by demodulating by the demodulating circuit 12 shown in FIG. 7 is written in units of the ECC block. The ECC block memory 21 is divided into a plurality of areas A to W as shown in FIG. Each area A to W stores demodulated data in units of 1 · ECC block. Further, the availability of the detection result of each synchronization signal is stored at a predetermined address in the same area. Here, the predetermined address is an address obtained by adding the start address of each area and a predetermined relative address. The same applies to the following. Here, when the synchronization signal Sync is detected without error, byte 00h is stored, and in other cases, byte FFh is stored. Here, an area in which demodulated data for 1 · ECC block is stored is an area A.

  The error detection / correction circuit 22 performs error detection / correction on the demodulated data read from the ECC block memory 21 in the same manner as the error detection / correction circuit 14 shown in FIG. The demodulated data that has been error-corrected by the error detection and correction circuit 22 is written into the ECC block memory 21 again. At this time, the area where the data after error correction is written is the same area (area A) as the area where the demodulated data is written by the demodulation circuit 12.

  Here, since the present embodiment is an error correction apparatus that corrects an error with respect to a reproduction signal of an ECC block having the format shown in FIG. 6, first, details of the format of the ECC block shown in FIG. 6 will be described. . FIG. 3 shows an example of a method for generating an ECC block. In FIG. 3, user data 31 of 32 × 2048 bytes, which is first information data such as video or music information, is added with a 4-byte error detection code EDC generated every 2048 bytes, and is 32 × 2052 bytes. After that, the data frame 33 is scrambled into a scrambled data frame 34 by a predetermined method.

  Subsequently, the scrambled data frame 34 is made into a data block 35 of 216 bytes (216 rows) in the row (horizontal) direction and 304 bytes (304 columns) in the column (vertical) direction, and further RS (248, 216, 33). An LDC block 37 having 304 columns and 248 rows is generated by performing error correction coding of a long distance code (LDC) with the Reed-Solomon code 36. The LDC block 37 is composed of 304 code words, and one code word is composed of 216 information symbols (in the case of Blu-ray Disc, one symbol is 1 byte) and 32 parity symbols. .

  The LDC block 37 is interleaved every 2 × 2 in the column direction of the block to form an LDC cluster 38 of 152 bytes horizontally and 496 bytes vertically (152 columns and 496 rows). On the other hand, BIS is error-correction-encoded with Reed-Solomon codes of RS (62, 30, 33), and 24 code words are arranged as pickets in the ECC block as described above. An ECC cluster 39 is generated.

  In this ECC cluster 39, as shown in FIG. 6, BIS is inserted every 38 bytes (38 columns) in the horizontal direction with respect to data bytes of 152 columns and 496 rows consisting of D0 to D75391 consisting of main data and parity. This is the configuration. Further, the synchronization signal Sync is added to the head of each row, and an ECC block is configured as a set of synchronization blocks composed of 155 bytes + Sync.

  Further, as shown in FIG. 6, the BIS includes address information of 9 bytes from the head of each address unit. The address information is uniformly arranged at a constant address unit interval of 4805 (= (38 × 4 + 3) × 31) bytes (not including Sync) before modulation (after demodulation). The address information is error correction encoded with Reed-Solomon code of RS (9, 5, 5). The ECC block is recorded in the horizontal direction and from top to bottom in FIG.

  Next, the operation of the embodiment of FIG. 1 will be described. The error detection / correction circuit 22 detects and corrects the data of the ECC block of the format shown in FIG. 6 read from the ECC block memory 21. First, whether or not the detection result of the synchronization signal Sync is detected is read by 496, which is the number of synchronization signals existing in one ECC block. As described above, when the synchronization signal Sync is detected without error, the byte 00h is stored, and in other cases, the byte FFh is stored. Therefore, whether the detection result of the synchronization signal Sync is detected is stored. When the address data is sequentially read and FFh is read, the position is stored in the error detection and correction circuit 22.

  Next, error detection correction of the Reed-Solomon code of RS (62, 30, 33) is performed for each BIS codeword. The BIS error byte position calculated at this time is stored in the error detection and correction circuit 22.

  The error detection and correction circuit 22 calculates the disappearance for the main data from the stored error position of the sync signal Sync and the position of the error byte of the BIS. That is, as shown in FIG. 8, the main data sandwiched between the erroneous sync signal Sync (or BIS byte) and the erroneous BIS byte (or sync signal Sync) in the order of recording data. Adds erasures to the data (corrects erasures). Using this erasure, the Reed-Solomon code error detection correction of each code word RS (248, 216, 33) of the main data is performed.

  The BIS and main data data subjected to error detection and correction by the error detection and correction circuit 22 are written again in the same area (area A) of the ECC block memory 21 as the area where the demodulated data is written by the demodulation circuit 12.

  When the data for 1 · ECC block is read from the ECC block memory 21, subjected to error detection and correction, and written to the ECC block memory 21 again, the subsequent signal processing circuit 24 stores the data in the area of the ECC block memory 21. Read from A. Then, after subsequent signal processing such as descrambling and deinterleaving is performed, it is output to the outside as reproduction data.

  When the subsequent signal processing circuit 24 has read the data for 1 · ECC block from the ECC block memory 21 and output the data as reproduction data to the outside, the FF data overwrite circuit 23 receives the data for 1 · ECC block. Is written in a predetermined address (storage area) of the area (area A) of the ECC block memory 21 in which is stored. Specifically, it is an address where the burst indicator subcode (BIS) is stored and whether the detection result of the synchronization signal Sync is available.

  The demodulated data obtained by demodulating by the demodulating circuit 12 at a later timing is written into the previously used area (area A) in the ECC block memory 21. At this time, data obtained by error detection correction of the previous demodulated data and FFh data written by the FF data overwrite circuit 23 are overwritten. However, when the reproduction signal is disturbed due to dirt or scratches on the optical disk surface, a part of data to be transferred from the demodulation circuit to the ECC block memory 21 is lost, and the original data in the ECC block memory 21 is lost. The data may be stored at a position different from the position. In that case, the previous data remains in a part of the area A without being overwritten.

  At a later timing, when the demodulating circuit 12 has written the data for 1 · ECC block into the area A in the ECC block memory 21, the error detection and correction circuit 22 reads out the demodulated data from the area A to detect an error. Make corrections.

  As in the previous case, first, 496 pieces of readability of the detection result of the synchronization signal Sync are read. At this time, if the previous data has not been overwritten by the data written this time, the FFh written by the FF data overwrite circuit 23 last time is read out. Therefore, the position where the FFh is read is stored in the error detection / correction circuit 22 assuming that the synchronization signal Sync is incorrect.

  Next, each code word of BIS is read from the area A in the ECC block memory 21 and error detection correction of the Reed-Solomon code of RS (62, 30, 33) is performed. At this time, if the previous data has not been overwritten by the data written this time, the FFh written by the FF data overwrite circuit 23 last time is read out. The FFh data is determined to be an error as a result of error detection and correction of the Reed-Solomon code. Therefore, the position is stored in the error detection / correction circuit 22 as the position of the BIS error byte.

  Next, each code word of the main data is read from the area A in the ECC block memory 21, and error detection correction of the Reed-Solomon code of RS (248, 216, 33) is performed. At that time, the erasure is added from the error position of the synchronization signal Sync and the position of the error byte of the BIS stored previously. At this time, if the previous data is not overwritten, the data as the previous data is mixed with a part of the data read as the main data. According to the present embodiment, error detection and correction is performed on such data as it was last time with erasure added.

  When the erasure is correctly added, the correction capability limit value of the erasure correction is the minimum intersymbol distance −1 (= number of parity). In this example, the minimum intersymbol distance of the Reed-Solomon code is “33”. Therefore, 32 erasure corrections are possible. On the other hand, when no erasure is added, the correction capability limit value is (minimum inter-code distance −1) / 2, and up to 16 corrections can be made.

  Here, it is assumed that there is 30 bytes of data in the main data code word that is left over without being overwritten due to disturbance of the reproduction signal. Further, if the detection result of the synchronization signal Sync and the BIS demodulated data are also written from the demodulator circuit last time or the BIS is error-detected and corrected, it is conventionally determined that there is no error. In that case, no erasure is added to the 30 bytes of the main data. Therefore, the limit of the correction capability when no erasure is added is exceeded, and it is determined as an uncorrectable codeword, and all of the data is lost.

  On the other hand, in the present embodiment, as described above, with respect to the detection result of the synchronization signal Sync and the BIS data, all data at byte positions not overwritten with the demodulated data are FFh, and it is determined that there is an error. As a result, since erasure is added to the corresponding main data, the erasure is added to the 30 bytes. If erasure correction is performed using this, a 30-byte error can be corrected, and all data can be obtained.

  In the present embodiment, the data to be overwritten by the FF data overwrite circuit 23 is FFh. However, the present invention is not limited to this. For example, it is assumed that the byte 00h is stored when the synchronization signal Sync is detected without error, and a byte other than 00h is stored in the other byte of the detection result of the synchronization signal Sync. Assuming that the error detection and correction circuit 22 handles the data, the data to be overwritten by the FF data overwriting circuit 23 may be any value other than 00h.

(Second Embodiment)
Next, a second embodiment of the error correction apparatus of the present invention will be described. FIG. 4 shows a block diagram of a main part of a second embodiment of the error correction apparatus according to the present invention. In the figure, the same components as those in FIG. In the present embodiment, the ECC block memory 21 has a relatively large capacity and is also a so-called track buffer. The track buffer is a buffer for data transfer between the optical disc recording / reproducing device and an external device. During reproduction, reproduction data from the optical disk is temporarily stored so that data can be transferred continuously in response to a request from an external device. During recording, data from an external device is temporarily stored so that it can be recorded on an optical disk at an appropriate timing. The ECC block memory 21 of the present embodiment is divided into areas in units of ECC blocks as shown in FIG.

  In the ECC block memory 21, the demodulated data obtained by demodulating by the demodulating circuit 12 shown in FIG. 7 is written in units of the ECC block. Here, it is assumed that data is written in the area A. Further, the availability of the detection result of each synchronization signal is stored at a predetermined address in the same area A. Here, when the synchronization signal Sync is detected without error, byte 00h is stored, and in other cases, byte FFh is stored.

  The error detection / correction circuit 22 performs error detection / correction on the demodulated data read from the ECC block memory 21 as in the first embodiment. First, 496 pieces of readability of the detection result of the synchronization signal Sync is read. As described above, when the synchronization signal Sync is detected without error, the byte 00h is stored, and in other cases, the byte FFh is stored. Therefore, whether the detection result of the synchronization signal Sync is detected is stored. When the address data is sequentially read and FFh is read, the position is stored in the error detection and correction circuit 22. Next, error detection correction of the Reed-Solomon code of RS (62, 30, 33) is performed for each BIS codeword. The BIS error byte position calculated at this time is stored in the error detection and correction circuit 22.

  The error detection and correction circuit 22 calculates the erasure with respect to the main data from the stored error position of the synchronization signal Sync and the position of the error byte of the BIS as in the first embodiment. Next, main data is read and error detection and correction are performed. In the present embodiment, the main data after error detection and correction is stored in the internal memory 26. The error detection and correction of the main data is performed using the previously calculated erasure.

  The main data stored in the internal memory 26 is read by the descrambling circuit 25, descrambled, and written back to the ECC block memory 21. At this time, the area to be written back is written back to another area (area G) instead of the area A written by the demodulation circuit 12. When the data is written back, an address is generated so as to release the interleaving, and data is written back to the address. More specifically, an address is generated so that the interleaving is solved as a relative address in the area, and the start address of each area is added to the address.

  The data for 1 · ECC block is read from the ECC block memory 21 to perform error detection and correction. When the descramble circuit 25 finishes writing the descrambled data to the ECC block memory 21, the FF data overwrite circuit 23 The byte FFh is written to a predetermined address in the area (area A) of the ECC block memory 21 in which data for 1 · ECC block is stored. Specifically, it is an address where the burst indicator subcode (BIS) is stored and whether the detection result of the synchronization signal Sync is available. The data written back to the area G by the descrambling circuit 25 is read at a predetermined timing and output to an external device.

  In the area A, data for 1 · ECC block is stored by the demodulation circuit 12 at a later timing. At this time, the previous demodulated data and the FFh data written by the FF data overwrite circuit 23 are overwritten. However, when the reproduction signal is disturbed due to dirt or scratches on the optical disk surface, a part of data to be transferred from the demodulation circuit to the ECC block memory 21 is lost, and the original data in the ECC block memory 21 is lost. The data may be stored at a position different from the position. In that case, the previous data remains in a part of the area A of the ECC block memory 21 without being overwritten.

  The error detection and correction circuit 22 reads the data in the area A of the ECC block memory 21 such that a part of the data remains without being overwritten, and performs error detection and correction. According to the present embodiment, as in the first embodiment, among the data that remains without being overwritten, the FF data overwrite circuit is used for the byte indicating whether or not the detection result of the synchronization signal Sync is possible and the BIS byte. FFh written in 23 remains. Therefore, since these bytes can be handled as errors, erasure can be added to the main data. As a result, the error correction capability of main data can be improved.

  In the present embodiment, the data written by the FF data overwrite circuit 23 is FFh. However, the present invention is not limited to this. For example, it is assumed that the byte 00h is stored when the synchronization signal Sync is detected without error, and a byte other than 00h is stored in the other byte of the detection result of the synchronization signal Sync. Assuming that the error detection and correction circuit 22 handles the data, the data written by the FF data overwrite circuit 23 may be any value other than 00h.

  In this embodiment, the descrambling process is performed when the descrambling circuit 25 writes data back to the ECC block memory 21. However, the error detection / correction circuit 22 performs the descrambling process from the ECC block memory 21. You may make it carry out when reading data. An address of the ECC block memory 21 is generated so as to release interleaving (scramble), and data at the address is read out. Alternatively, the descrambling process may be performed at both the address generated by the error detection / correction circuit 22 and the address generated by the descrambling circuit 25. Furthermore, the descrambling process may be performed not when reading or writing data from the ECC block memory 21 but when writing or reading data to or from the internal memory 26.

(Third embodiment)
Next, a third embodiment of the error correction apparatus of the present invention will be described. Also in the case of this embodiment, a block diagram of the main part can be shown as shown in FIG. In the present embodiment, the FF data overwriting circuit 23 of FIG. 4 indicates that each synchronization block of the error correction block for which error correction has been completed among the data stored in the ECC block memory 21 is demodulated data. It is characterized in that the data shown (hereinafter referred to as synchronous block update data) is overwritten with FFh.

  Further, the error detection and correction circuit 22 reads out the synchronization block update data indicating that each synchronization block is data after demodulation from the ECC block memory 21, and the value of the synchronization block update data is the value after the synchronization block is demodulated. When the value is not 00h indicating data, a means for confirming that the synchronization signal of the synchronization block has not been correctly detected and that the BIS or the error correction code added thereto is an error is provided.

  In the present embodiment, the ECC block memory 21 has a relatively large capacity and is also a so-called track buffer. The ECC block memory 21 of the present embodiment is divided into areas in units of ECC blocks as shown in FIG.

  In the ECC block memory 21, the demodulated data obtained by demodulating by the demodulating circuit 12 shown in FIG. 7 is written in units of the ECC block. Here, it is assumed that data is written in the area A. Further, the availability of the detection result of each synchronization signal is stored at a predetermined address in the same area A. Here, when the synchronization signal Sync is detected without error, byte 00h is stored, and in other cases, byte FFh is stored. The above is the same as in the second embodiment, but in this embodiment, synchronization block update data 00h indicating that each synchronization block has been written from the demodulation circuit is stored in another predetermined address. .

  The error detection / correction circuit 22 of the present embodiment performs error detection / correction of the demodulated data read from the ECC block memory 21 as in the first embodiment. In this case, in the present embodiment, first, 496 pieces of synchronous block update data corresponding to all synchronous blocks of 1 · ECC block are read. At this time, when a value other than 00h is read, the position is stored in the error detection and correction circuit 22.

  Next, whether or not the detection result of the synchronization signal Sync is detected is read for 496 pieces. As described above, when the synchronization signal Sync is detected without error, the byte 00h is stored, and in other cases, the byte FFh is stored. Therefore, whether the detection result of the synchronization signal Sync is detected is stored. The data at the address is sequentially read out, and when other than 00h is read out, the position is stored in the error detection / correction circuit 22. If the synchronization block update data is other than 00h, the synchronization signal Sync of the synchronization block is assumed to be incorrect regardless of the read value, and the position is stored in the error detection / correction circuit 22.

  Next, error detection correction of the Reed-Solomon code of RS (62, 30, 33) is performed for each BIS codeword. The BIS error byte position calculated at this time is stored in the error detection and correction circuit 22. If the synchronous block update data is other than 00h, the BIS data byte belonging to the synchronous block is replaced with FFh, and error detection and correction are performed. As will be described later, the address where the synchronous block update data of the ECC block memory 21 is stored is overwritten with the FF data (FFh), but the FF data (FFh) is stored for the address where the BIS is stored. This is because no overwriting is performed.

  The error detection and correction circuit 22 calculates the erasure with respect to the main data from the stored error position of the synchronization signal Sync and the position of the error byte of the BIS as in the first embodiment. Next, main data is read and error detection and correction are performed. In the present embodiment, the main data after error detection and correction is stored in the internal memory 26. The error detection and correction of the main data is performed using the previously calculated erasure.

  The main data stored in the internal memory 26 is read and descrambled by the descrambling circuit 25 and written back to the ECC block memory 21. At this time, the area to be written back is written back to another area (area G) instead of the area A written by the demodulation circuit 12. When data is written back, an address is generated so as to release interleaving (scramble), and data is written back to the address. More specifically, an address is generated so as to be scrambled as a relative address in the area, and the start address of each area is added to the address.

  The data for 1 · ECC block is read from the ECC block memory 21 to perform error detection and correction. When the descramble circuit 25 finishes writing the descrambled data to the ECC block memory 21, the FF data overwrite circuit 23 The byte FFh is written to a predetermined address in the area (area A) of the ECC block memory 21 in which data for 1 · ECC block is stored. Specifically, the address overwritten with the FF data is the address where the synchronous block update data is stored, and the FF data is not overwritten with respect to the address where the BIS is stored. Therefore, the present embodiment has a feature that the amount of data to be overwritten is smaller than that of the second embodiment.

  The data written back to the area G by the descrambling circuit 25 is read at a predetermined timing and output to an external device. In the area A, data for 1 · ECC block is stored by the demodulation circuit 12 at a later timing. At this time, the previous demodulated data and the FFh data written by the FF data overwrite circuit 23 are overwritten. However, when the reproduction signal is disturbed due to dirt or scratches on the optical disk surface, a part of the data to be transferred from the demodulation circuit to the ECC block memory 21 is lost or the original position in the ECC block memory 21 is lost. Data may be stored in a different location. In that case, the previous data remains in a part of the area A without being overwritten.

  The error detection and correction circuit 22 reads the data in the area A of the ECC block memory 21 such that a part of the data remains without being overwritten, and performs error detection and correction. According to the present embodiment, as in the first embodiment, among the data remaining without being overwritten, the FFh written by the FF data overwrite circuit 23 remains for the bytes of the synchronous block update data. Yes. Therefore, since the bytes of the synchronization signal Sync and the BIS data related to the synchronization block update data can be handled as errors, erasure can be added to the main data. As a result, the error correction capability of main data can be improved.

  In the present embodiment, the data written by the FF data overwrite circuit 23 is FFh. However, the present invention is not limited to this. The byte of the synchronous block update data may be an arbitrary value other than 00h because 00h is written when it is written from the demodulation circuit. Furthermore, if the predetermined value is written when the byte of the synchronous block update data is written from the demodulation circuit, the data overwritten by the FF data overwriting circuit 23 is data other than the predetermined value. May be.

  In this embodiment, the byte of the synchronization block update data and the byte indicating whether the detection result of the synchronization signal Sync is acceptable are different from each other. However, these bytes may be the same byte. The byte indicating whether or not the detection result of the synchronization signal Sync is valid is written with 00h when the synchronization signal Sync is detected without error and 01h in other cases. This byte is also synchronous block update data.

  The error detection / correction circuit 22 reads out the detection result byte (also serves as the synchronization block update data) of the synchronization signal Sync from the ECC block memory 21, and if the value is 00h, the associated synchronization block is read from the demodulation circuit. It is determined that the signal has been written and the synchronization signal Sync is detected without error. If the value is 01h, it is determined that the associated synchronization block has been written from the demodulation circuit, but the synchronization signal Sync has an error.

  If the value of the byte indicating whether or not the detection result of the synchronization signal Sync is acceptable (also serving as synchronization block update data) is a value other than these, it is determined that the associated synchronization block has not been written from the demodulation circuit, and the synchronization signal Sync is determined. Is replaced with an error, and the byte of the BIS data belonging to the synchronous block is replaced with FFh. Further, the FF data overwrite circuit 23 overwrites FFh at an address where a byte indicating whether or not the detection result of the synchronization signal Sync is possible (also serving as synchronization block update data) is stored.

(Recording and playback device)
Next, an embodiment of the recording / reproducing apparatus of the present invention will be described. FIG. 5 shows a block diagram of an embodiment of the main part of the recording system of the recording / reproducing apparatus according to the present invention. In the figure, the same components as in FIG. The components used for the main part of the playback system of the recording / playback apparatus are the same as in FIG. 4 and operate in the same way as in the second embodiment. In FIG. 5, the ECC block memory 21 has a relatively large capacity and is a so-called track buffer. Further, the ECC block memory 21 is divided into areas in units of ECC blocks as shown in FIG.

  Although the present embodiment relates to an operation at the time of recording, the ECC block memory 21 is commonly used for recording and reproduction. At the time of recording, data to be recorded from the external device is stored in the ECC block memory 21. Main data corresponding to 1 · ECC block is written in, for example, the area G in FIG. 1. When the main data corresponding to the ECC block has been written, the scramble circuit 27 in FIG. 5 reads the data from the area G of the ECC block memory 21. The read data is added with an error detection code EDC, further scrambled, and stored in the internal memory 26.

  The error detection / correction encoding circuit 28 reads data from the internal memory 26, performs error correction encoding, and stores the encoded data in an area (for example, area A) other than the area G of the ECC block memory 21. At this time, an address is generated so as to realize interleaving, and data is written to the address. More specifically, an address is generated so as to realize interleaving as a relative address in the area, and the start address of each area is added to the address.

  Next, the error detection / correction encoding circuit 28 encodes the BIS data and writes the encoded data at a predetermined address in the area A of the ECC block memory 21. The arrangement of the data in the area A at this time is the same as the arrangement when the demodulation circuit writes in the ECC block memory 21 in the second embodiment.

  As described above, when the encoded data of the 1 ECC block main data and the BIS data are stored at predetermined addresses in the area A of the ECC block memory 21, the modulation circuit (not shown) read out. Then, a synchronizing signal Sync is added to the head, recording modulation is performed, and recording is performed on an optical disc (not shown).

  When the modulation circuit reads data for 1 · ECC block and records it on the optical disk, the FF data overwrite circuit 29 writes the byte FFh to a predetermined address (storage area) in the area A of the ECC block memory 21. Specifically, it is an address where the BIS data is stored and whether the detection result of the synchronization signal Sync is possible. At the time of recording, since the synchronization signal Sync is not detected, it is not necessary to store the availability of the detection result. The address where the availability of the detection result of the synchronization signal Sync is to be stored is an address in the area A where the demodulation circuit stores the availability of the detection result of the synchronization signal Sync during reproduction.

  Depending on the situation of recording / reproducing data on an optical disc, data at another location may be reproduced immediately after the data is recorded at a location on the optical disc. In such a case, the area A of the ECC block memory 21 used at the time of recording may be used as an area where the demodulation circuit writes the demodulated data at the time of reproduction.

  When the demodulated data is written in the area A, if the reproduction signal is disturbed due to dirt or scratches on the optical disk surface, a part of the data to be transferred from the demodulator circuit to the ECC block memory 21 may be lost. The data may be stored in a position different from the original position in the ECC block memory 21. In that case, data at the time of recording remains in a part of the area A without being overwritten.

  Similar to the second embodiment, a reproduction system error detection and correction circuit (not shown) reads data in the area A of the ECC block memory 21 such that a part of the data remains without being overwritten. , Perform error detection and correction. According to the present embodiment, as in the second embodiment, among the data that remains without being overwritten, the FF data overwriting circuit is used for the byte indicating whether or not the detection result of the synchronization signal Sync is possible and the BIS byte. FFh written in 29 remains. Therefore, since these bytes can be handled as errors, erasure can be added to the main data. As a result, the error correction capability of the main data can be improved.

  In the present embodiment, the data arrangement in which the error detection / correction coding circuit 28 has written the data after error detection / correction coding in the ECC block memory 21 and the arrangement in which the demodulation circuit has written in the ECC block memory 21 Although similar, it need not be the same. When the arrangement is different, the byte FFh may be written in the address where the demodulating circuit should write the data indicating whether the detection result of the sync is possible and the address where the BIS data should be written.

  In the present embodiment, the data written by the FF data overwrite circuit 29 is FFh. However, the present invention is not limited to this. Further, in this embodiment, the interleaving process is performed when the error detection / correction coding circuit 28 writes data back to the ECC block memory 21. However, the interleaving process is performed by the scramble circuit 27 from the ECC block memory 21. It may be performed when reading out.

  An address of the ECC block memory 21 is generated so as to realize interleaving, and data at the address is read out. Alternatively, the interleaving process may be performed on both the address generated by the error detection / correction coding circuit 28 and the address generated by the scramble circuit 27. Further, the interleaving process may be performed not when reading or writing data from the ECC block memory 21 but when writing or reading data to or from the internal memory 26.

  Further, in FIG. 5, the reproduction system error detection and correction circuit (not shown) reads the data in the ECC block memory 21 such that a part of the data remains without being overwritten, and the first or third data is read out. It is also possible to perform error detection and correction similar to the embodiment.

  Furthermore, in the above embodiment, it is explained that the erasure correction of the data constituting the information block is performed between the synchronization signal determined to be an error and the BIS determined to have an error by the error correction immediately before or immediately after that. However, the present invention is not limited to this. For example, when two adjacent BISs are determined to have an error by error correction, the erasure correction of the data constituting the information block between the two BISs is performed. It is also possible to perform.

  Further, in the present invention, when one BIS is determined to have an error by error correction, the data of the BIS is determined from data at a predetermined position (for example, data at an intermediate position) in the information block immediately before the BIS. It is also possible to perform erasure correction up to data at a predetermined position in the immediately following information block (for example, data at an intermediate position). In this case, for example, when it is determined that B0 in FIG. 8 has an error, erasure correction is performed, for example, in D19 to D57. The same applies to the case where only the synchronization signal is determined to have an error and the BIS adjacent thereto is determined to have no error. Note that the above erasure correction can be performed independently or simultaneously.

It is a block diagram of the principal part of 1st Embodiment of the error correction apparatus of this invention. It is a block diagram of the area | region of the ECC block memory of this invention. It is a figure which shows the production | generation method of an example of an ECC block. It is a block diagram of the principal part of the 2nd, 3rd embodiment of the error correction apparatus of this invention. 1 is a block diagram of an embodiment of a main part of a recording system of a recording / reproducing apparatus of the present invention. It is an example of an error correction block (ECC block) configuration. It is a block diagram which shows an example of the conventional error correction apparatus, and the outline of a peripheral circuit. It is a figure which shows the error part of an example of an error correction block (ECC block) structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Synchronization detection circuit 12 Demodulation circuit 13, 21 ECC block memory 14, 22 Error detection correction circuit 15, 24 Subsequent signal processing circuit 16 Memory access block 17 Timing generation circuit 23, 29 FF data overwrite circuit 25 Descramble circuit 26 Internal memory 27 Scramble circuit 28 Error detection and correction coding circuit 31 User data 32 ADD EDC
33 Data frame 34 Scrambled data frame 35 Data block 36 LDC encoding 37 LDC block 38 LDC cluster 39 ECC cluster

Claims (4)

L pieces of information blocks (L is a natural number of 2 or more) obtained by dividing the first information data into predetermined bytes and the information blocks for each of the L pieces of information blocks. M rows (M is a natural number greater than or equal to 2) M blocks (M is a natural number greater than or equal to 2) A first error correction code based on a first Reed-Solomon code is added to the first information data, and the first information data is added to the first information data. The error correction block reproduced and demodulated from the recording medium on which the error correction block having the second Reed-Solomon code added with the second error correction code independently of the information data is modulated and recorded. An error correction device which performs error correction on the click,
A synchronization signal detecting means for extracting the synchronization signal from the signal reproduced from the recording medium and detecting whether or not the synchronization signal is normally detected;
It operates based on the timing of the synchronization signal extracted by the synchronization signal detection means, demodulates the signal reproduced from the recording medium to obtain the error correction block, and the demodulated error correction block and the synchronization Demodulation means for outputting availability data indicating whether or not the signal has been detected normally;
Storage means for storing the error-corrected block and the propriety data after demodulation output from the demodulating means in units of the error-correcting blocks;
Error correction of the second information data is performed using the second error correction code in the demodulated error correction block read from the storage means, and adjacently determined to have an error by the error correction When it is determined that the second information data between the two pieces of the second information data or immediately before or after the synchronization signal indicating that the data is not normally detected by the availability data is an error. The first information data constituting the information block between the synchronization signal and the second information data determined to be the error is regarded as an erasure, and the first error data in the demodulated error correction block Error correction is performed using an error correction code, or it is normally detected by the second information data or the availability data determined to have an error by the error correction. An error in which error correction is performed using the first error correction code by erasing the first information data between predetermined positions in each information block immediately before and immediately after the synchronization signal indicating that there is no synchronization signal. Correction means;
The availability indicating whether or not the synchronization signal of the error correction block that has finished the error correction of the storage means is normally detected every time the error correction processing of the error correction block after demodulation by the error correction means is completed. And an overwriting means for overwriting a storage area of the second error correction code added to the data, the second information data and the second information data with predetermined data. Correction device. L pieces of information blocks (L is a natural number of 2 or more) obtained by dividing the first information data into predetermined bytes and the information blocks for each of the L pieces of information blocks. M rows (M is a natural number greater than or equal to 2) M blocks (M is a natural number greater than or equal to 2) A first error correction code based on a first Reed-Solomon code is added to the first information data, and the first information data is added to the first information data. The error correction block reproduced and demodulated from the recording medium on which the error correction block having the second Reed-Solomon code added with the second error correction code independently of the information data is modulated and recorded. An error correction device which performs error correction on the click,
A synchronization signal detecting means for extracting the synchronization signal from the signal reproduced from the recording medium and detecting whether or not the synchronization signal is normally detected;
It operates based on the timing of the synchronization signal extracted by the synchronization signal detection means, demodulates the signal reproduced from the recording medium to obtain the error correction block, and the demodulated error correction block and the synchronization Outputs whether or not the signal is normally detected, and whether or not each of the synchronization blocks constituting the error correction block is a demodulated synchronization block having a predetermined value indicating synchronization block update data. Demodulation means;
Storage means for storing the error correction block and the propriety data after demodulation output from the demodulation means and the synchronization block update data of the predetermined value in units of the error correction blocks;
The second information data is corrected using the second error correction code in the demodulated error correction block read from the storage means, and the synchronous block update data read from the storage means When it is not the predetermined value, the first information data constituting the information block between the synchronization signal included in the synchronization block indicated by the synchronization block update data and the second information data is regarded as erasure. Error correction is performed using the first error correction code in the demodulated error correction block, and the error is detected in the synchronization block indicated by the synchronization block update data when the synchronization block update data is the predetermined value. It is normally detected between two adjacent second information data determined to have an error by correction or by the availability data. If it is determined that the second information data immediately before or immediately after the synchronization signal indicating that the error has not been made is an error, the synchronization information and the second information data determined to be the error The first information data constituting the information block during the period is erased and error correction is performed using the first error correction code, or one of the second information determined to have an error by the error correction The first information data between the predetermined positions in each information block immediately before and immediately after the synchronization signal indicated that the information data is not normally detected by the information data or the availability data is regarded as erasure. Error correction means for performing error correction using the error correction code of
Each time the error correction processing of the error correction block after demodulation by the error correction means is completed, the storage area of the synchronous block update data of the error correction block of the error correction block of the storage means is overwritten with predetermined data And an overwriting means for performing error correction. L pieces of information blocks (L is a natural number of 2 or more) obtained by dividing the first information data into predetermined bytes and the information blocks for each of the L pieces of information blocks. M rows (M is a natural number greater than or equal to 2) M blocks (M is a natural number greater than or equal to 2) A first error correction code based on a first Reed-Solomon code is added to the first information data, and the first information data is added to the first information data. An error correction block to which the second error correction code based on the second Reed-Solomon code is added is formed independently of the information data, the error correction block is modulated, recorded on the recording medium, and reproduced from the recording medium The The signal is demodulated to a recording and reproducing apparatus for obtaining the error correction block,
A synchronization signal detecting means for extracting the synchronization signal from the signal reproduced from the recording medium and detecting whether or not the synchronization signal is normally detected;
It operates based on the timing of the synchronization signal extracted by the synchronization signal detection means, demodulates the signal reproduced from the recording medium to obtain the error correction block, and the demodulated error correction block and the synchronization Demodulation means for outputting availability data indicating whether or not the signal has been detected normally;
Storage means for storing at least the demodulated error correction block and the availability data output from the demodulation means in units of the error correction block;
The second information data is corrected using the second error correction code in the demodulated error correction block read from the storage means at the time of reproduction, and it is determined that there is an error by the error correction. It is determined that the second information data immediately before or immediately after the synchronization signal between the two adjacent second information data or immediately before or after the synchronization signal indicated by the availability data is incorrect. In the case, the first information data constituting the information block between the synchronization signal and the second information data determined to be the error is regarded as an erasure, and the first error correction block in the demodulated error correction block Error correction is performed using one error correction code, or one of the second information data determined to have an error by the error correction or normality by the availability data Error correction using the first error correction code is performed by erasing the first information data between predetermined positions in each information block immediately before and immediately after the synchronization signal indicating that it has not been detected. Error correction means to perform;
The first error correction code is added to the first information data input from the outside during recording, and the second error is added to the second information data input from the outside or generated internally. Error correction coding means for adding a correction code and storing it in the storage means;
Read the first and second information data and the first and second error correction codes stored by the error correction encoding means from the storage means, add the synchronization signal to the read signal and record Modulation / recording means for modulating the error correction block after recording the error correction block for recording on the recording medium;
Each time the reading of the first and second information data and the first and second error correction codes stored by the error correction encoding means from the storage means by the modulation / recording means is completed, The error correction block corresponding to the read signal is added to the first storage area of the storage means for storing the availability data at the time of reproduction, and to the second information data and the second information data at the time of reproduction. A recording / reproducing apparatus comprising: overwriting means for overwriting a second storage area of the storage means in which the second error correction code is stored with predetermined data, respectively. L pieces of information blocks (L is a natural number of 2 or more) obtained by dividing the first information data into predetermined bytes and the information blocks for each of the L pieces of information blocks. M rows (M is a natural number greater than or equal to 2) M blocks (M is a natural number greater than or equal to 2) A first error correction code based on a first Reed-Solomon code is added to the first information data, and the first information data is added to the first information data. An error correction block to which the second error correction code based on the second Reed-Solomon code is added is formed independently of the information data, the error correction block is modulated, recorded on the recording medium, and reproduced from the recording medium The The signal is demodulated to a recording and reproducing apparatus for obtaining the error correction block,
A synchronization signal detecting means for extracting the synchronization signal from the signal reproduced from the recording medium and detecting whether or not the synchronization signal is normally detected;
It operates based on the timing of the synchronization signal extracted by the synchronization signal detection means, demodulates the signal reproduced from the recording medium to obtain the error correction block, and the demodulated error correction block and the synchronization Outputs whether or not the signal is normally detected, and whether or not each of the synchronization blocks constituting the error correction block is a demodulated synchronization block having a predetermined value indicating synchronization block update data. Demodulation means;
Storage means for storing at least the error correction block and the propriety data after the demodulation output from the demodulation means and the synchronization block update data of the predetermined value in units of the error correction block;
Performing error correction of the second information data using the second error correction code in the demodulated error correction block read from the storage means at the time of reproduction, and updating the synchronous block read from the storage means When the data is not the predetermined value, the first information data constituting the information block between the synchronization signal included in the synchronization block indicated by the synchronization block update data and the second information data is lost. As described above, error correction is performed using the first error correction code in the demodulated error correction block, and when the synchronous block update data is the predetermined value, the synchronous block indicated by the synchronous block update data Between two adjacent second information data determined to have an error by the error correction, or by the availability data When it is determined that the second information data immediately before or after the synchronization signal indicating that it has not always been detected is an error, the synchronization signal and the second information data determined to be the error The first information data constituting the information block between the information data is erased and error correction is performed using the first error correction code, or one of the errors determined by the error correction is an error The first information data between the predetermined positions in each information block immediately before and immediately after the synchronization signal, which is indicated as not being normally detected by the second information data or the availability data, is defined as the erasure. Error correcting means for performing error correction using the first error correcting code;
The first error correction code is added to the first information data input from the outside during recording, and the second error is added to the second information data input from the outside or generated internally. Error correction coding means for adding a correction code and storing it in the storage means;
Read the first and second information data and the first and second error correction codes stored by the error correction encoding means from the storage means, add the synchronization signal to the read signal and record Modulation / recording means for modulating the error correction block after recording the error correction block for recording on the recording medium;
Each time the reading of the first and second information data and the first and second error correction codes stored by the error correction encoding means from the storage means by the modulation / recording means is completed, A recording / reproducing apparatus comprising: overwriting means for overwriting a storage area in which the synchronous block update data is stored during reproduction of the error correction block corresponding to the read signal with predetermined data.

Images