JP2008078526A - Nitride semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device whose leakage current is reduced to attain a high voltage resistance, the dispersion of frequency can be controlled, and the threshold voltage is easily controlled and its manufacturing method. <P>SOLUTION: The nitride semiconductor device includes a first nitride semiconductor layer which is composed of a group III-V nitride semiconductor layer laminated on a substrate, a second nitride semiconductor layer which is composed of a group III-V nitride semiconductor layer laminated at a temperature lower than a film-forming temperature of the first nitride semiconductor layer on the first nitride semiconductor layer and is formed in a fine crystal structure without aluminum, a group III-V nitride semiconductor layer which is laminated on the second nitride semiconductor layer in a control electrode forming area, a third nitride semiconductor layer which has a p-type conductivity, and a control electrode which ohmically contacts with the third nitride semiconductor layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device using a nitride semiconductor as an active layer and a method for manufacturing the same, and in particular, controls such as a high electron mobility transistor (HEMT) and a field effect transistor (Field Effect Transistor). The present invention relates to a normally-off type nitride semiconductor device having electrodes and a method for manufacturing the same.

FIG. 7 shows a cross-sectional view of a conventional nitride semiconductor device made of a group III-V nitride semiconductor. The nitride semiconductor device shown in FIG. 7 has a so-called HEMT structure, on a substrate 101 made of a sapphire substrate, a buffer layer 102 made of gallium nitride (GaN), a channel layer 103 made of gallium nitride, and n-type nitride. A carrier supply layer 104 made of aluminum gallium (AlGaN) and a Schottky layer 105 made of non-doped aluminum gallium nitride are sequentially stacked. In the vicinity of the heterojunction interface made up of the channel layer 103 and the carrier supply layer 104, a potential well is formed. A two-dimensional electron gas layer having a very high electron mobility is formed. In this nitride semiconductor device, a recess structure 108 is provided in a part of the Schottky layer 105, and by controlling the voltage applied to the gate electrode 106 (control electrode) in Schottky contact in the recess structure 108, the source electrode 107a and Carriers (two-dimensional electron gas) flowing between the drain electrodes 107b are controlled. Further, by providing the recess structure 108, a normally-off operation is enabled. For this type of semiconductor device, various structures as disclosed in Non-Patent Document 1, for example, have been proposed.
T. Kawasaki and two others, “Normally-off AlGaN / GaN HENT with Recessed Gate for High Power Applications”, Extended Abstracts of the 2005 International Conference on SOLID STATE DEVICES AND MATERIALS, KOBE, 2005, Japan Society of Applied Physics September 13, 2005, p. 206-207

  The breakdown voltage of such a conventional nitride semiconductor device is greatly influenced by the Schottky characteristics formed by the contact between the gate metal and the nitride semiconductor layer. In general, Schottky characteristics of a gate metal formed on a nitride semiconductor layer, for example, an aluminum gallium nitride layer or a gallium nitride layer, show a high gate leakage current, which triggers impact ionization and is a nitride of a high power device. There is a problem that the high breakdown voltage performance of the wide gap material cannot be fully obtained by lowering the off breakdown voltage (drain breakdown voltage when the FET is off), which is an important parameter of the semiconductor device, from the expected value. It was.

  In addition, in a semiconductor device in which a gate electrode is formed on a nitride semiconductor layer such as an aluminum gallium nitride layer or a gallium nitride layer, the surface potential fluctuates due to electrons trapped in the surface level of the nitride semiconductor layer, and current-voltage There was a problem that frequency dispersion of characteristics occurred.

  Further, in a normally-off nitride semiconductor device including a recess-structured gate electrode, the recess structure is formed by dry etching the Schottky layer 105 having a thickness of about 25 nm to a thickness of about 10 nm. However, the controllability is insufficient and it is difficult to control the threshold voltage (Vth). In addition, there is a problem that gate leakage current increases due to damage caused by dry etching. Furthermore, since the Schottky barrier is about 1.0 eV, the positive voltage that can be applied to the gate electrode is as small as about 1.5 V. Therefore, the threshold voltage (Vth) of the normally-off FET is set to the value of silicon MOSFEET or IGBT. As described above, there is a problem that it is difficult to obtain a large value exceeding 1 V, and a sufficient drain current cannot be obtained.

  The present invention significantly reduces the leakage current of a control electrode formed in a nitride semiconductor layer, and can achieve high breakdown voltage by suppressing impact ionization in the nitride semiconductor layer. And it aims at providing the manufacturing method. It is another object of the present invention to provide a nitride semiconductor device capable of suppressing frequency dispersion and realizing a normally-off operation with good reproducibility and a method for manufacturing the same. Still another object of the present invention is to provide a nitride semiconductor device that can easily control the threshold voltage and a method for manufacturing the same.

  In order to achieve the above object, the invention according to claim 1 of the present application provides at least one group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least one of the group consisting of nitrogen, phosphorus and arsenic. In a nitride semiconductor device comprising a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, a first nitride semiconductor layer comprising the group III-V nitride semiconductor layer stacked on a substrate And a III-V group nitride semiconductor layer laminated on the first nitride semiconductor layer at a temperature lower than the film formation temperature of the first nitride semiconductor layer, and does not contain aluminum And a group III-V nitride semiconductor layer stacked on the second nitride semiconductor layer in the control electrode formation region, and has a p-type conductivity. Nitride semiconductor When, is characterized in that a control electrode in ohmic contact with the third nitride semiconductor layer.

  The invention according to claim 2 of the present application is the nitride semiconductor device according to claim 1, wherein the third nitride semiconductor layer is exposed by removing the second nitride semiconductor layer only in the control electrode formation region. It is laminated on the first nitride semiconductor layer or on the first nitride semiconductor layer from which a part of the surface is further removed.

  The invention according to claim 3 of the present application is the nitride semiconductor device according to claim 1 or 2, wherein the energy of the first nitride semiconductor layer is between the substrate and the first nitride semiconductor layer. A fourth nitride semiconductor layer comprising the group III-V nitride semiconductor layer having an energy gap smaller than the gap is provided.

  The invention according to claim 4 of the present application is the nitride semiconductor device according to any one of claims 1 to 3, further comprising an ohmic electrode in ohmic contact with the second nitride semiconductor layer. .

  The invention according to claim 5 of the present application is a group III element comprising at least one group selected from the group consisting of gallium, aluminum, boron and indium, and a group V element including at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic. And forming a first nitride semiconductor layer made of the group III-V nitride semiconductor layer on a substrate in a method for manufacturing a nitride semiconductor device made of a group III-V nitride semiconductor layer comprising: And a group III-V nitride semiconductor layer comprising aluminum at a temperature lower than a film forming temperature for forming the first nitride semiconductor layer on the first nitride semiconductor layer. Forming a second nitride semiconductor layer having no microcrystalline structure, forming a mask film having an opening in a control electrode formation region on the second nitride semiconductor layer, and using the mask film The second A part of the surface is formed on the nitride semiconductor layer, on the first nitride semiconductor layer exposed by removing the second nitride semiconductor layer in the opening using the mask film, or on the surface of the nitride semiconductor layer. Selectively forming a third nitride semiconductor layer made of the III-V nitride semiconductor layer and having p-type conductivity on the removed first nitride semiconductor layer; And a step of forming a control electrode in ohmic contact with the third nitride semiconductor layer on the third nitride semiconductor layer.

  The invention according to claim 6 of the present application is the method for manufacturing a nitride semiconductor device according to claim 5, wherein an energy gap of the first nitride semiconductor layer is provided between the substrate and the first nitride semiconductor layer. Forming a fourth nitride semiconductor layer made of the group III-V nitride semiconductor layer having a smaller energy gap.

  The invention according to claim 7 of the present application includes the step of forming an ohmic electrode in ohmic contact on the second nitride semiconductor layer in the method of manufacturing a nitride semiconductor device according to claim 5 or 6. It is a feature.

  The nitride semiconductor device of the present invention includes a p-type conductive nitride semiconductor layer (third nitride semiconductor layer) and a control electrode that is in ohmic contact with the control electrode that does not contain at least aluminum and has a high insulating property. Since the structure is in contact with the nitride semiconductor layer (second nitride semiconductor layer) having a crystal structure, leakage current can be reduced.

  When the control electrode of the present invention is a gate electrode such as an FET or HEMT, the gate leakage current is reduced. Further, by suppressing collision ionization in the channel, a high breakdown voltage can be realized. In addition, since a nitride semiconductor layer having a highly insulating microcrystalline structure is provided between the gate and drain electrodes, suppression of electrons trapped in the surface level between the gate and drain electrodes or surface state density The current collapse phenomenon is suppressed and the high frequency characteristics are improved. Furthermore, the structure is in ohmic contact with the microcrystalline nitride semiconductor layer, an ohmic electrode with low contact resistance can be formed, and low on-resistance can be realized.

  In addition, according to the present invention, the diffusion potential becomes large (specifically, when the control electrode is formed on p-type GaN, the diffusion potential is 3 V or more), which is easier than the conventional Schottky junction control electrode. It was also confirmed that the Mary-off operation can be realized, and that a high drain current can be obtained despite the normally-off operation.

  In addition, the nitride semiconductor device of the present invention removes a part of the nitride semiconductor layer (second nitride semiconductor layer) having a microcrystalline structure that does not contain at least aluminum and has high insulating properties, and performs p-type conductivity. Even when a structure in which the nitride semiconductor layer (third nitride semiconductor layer) and the control electrode in ohmic contact with the nitride semiconductor layer have a structure in which the nitride semiconductor layer (first nitride semiconductor layer) is in direct contact with the lower nitride semiconductor layer (first nitride semiconductor layer), Leakage current can be reduced.

  Even when the control electrode of the present invention is a gate electrode such as FET or HEMT, the gate leakage current is reduced. Further, by suppressing collision ionization in the channel, a high breakdown voltage can be realized. In addition, since a nitride semiconductor layer having a highly insulating microcrystalline structure is provided between the gate and drain electrodes, suppression of electrons trapped in the surface level between the gate and drain electrodes or surface state density The current collapse phenomenon is suppressed and the high frequency characteristics are improved. Furthermore, the structure is in ohmic contact with the nitride semiconductor layer having a microcrystalline structure, an ohmic electrode having a low contact resistance can be formed, and a low on-resistance can be realized.

  In addition, according to the present invention, the diffusion potential becomes large (specifically, when the control electrode is formed on p-type GaN, the diffusion potential is 3 V or more), which is easier than the conventional Schottky junction control electrode. It was also confirmed that the Mary-off operation can be realized, and that a high drain current can be obtained despite the normally-off operation.

In particular, when the third nitride semiconductor layer is in contact with the first nitride semiconductor layer, the threshold voltage can be set to a large value of 1 V or more, which is suitable as a noise-resistant switching transistor.

  Furthermore, the method for manufacturing a nitride semiconductor device of the present invention can be formed in accordance with a normal manufacturing process of a semiconductor device, and it is possible to manufacture a nitride semiconductor device having good controllability and excellent characteristics with good yield. it can.

  Hereinafter, the nitride semiconductor device and the manufacturing method thereof according to the present invention will be described in detail with reference to a HEMT that is a group III-V nitride semiconductor device.

  FIG. 1 is a cross-sectional view of a HEMT according to a first embodiment of the present invention, and FIG. 2 is an explanatory view of the manufacturing method. Hereinafter, it demonstrates according to a manufacturing process. First, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm and a barrier layer (carrier supply to be described later) are formed by MOCVD (metal organic chemical vapor deposition). Channel layer 13 (fourth nitride semiconductor layer) made of non-doped gallium nitride (GaN) having an energy gap smaller than the energy gap of layer 2) and a two-dimensional electron gas serving as a carrier at the interface with the channel layer 13 A barrier layer 14 (first nitride semiconductor layer) made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 25 nm and forming a layer is sequentially grown at a substrate temperature of 1080 ° C. Thereafter, the substrate temperature is set to 550 ° C., and a cap layer 15 (second nitride semiconductor layer) made of non-doped gallium nitride having a microcrystalline structure with a thickness of 10 nm is grown (FIG. 2a).

A dielectric film 16 made of a silicon oxide (SiO ₂ ) film is formed on the cap layer 15 by plasma CVD or the like, and the dielectric film 16 is removed by dry etching so as to open the gate electrode formation region, thereby forming the recess 16a. Form. Using this dielectric film 16 (mask film) as a mask, p-type gallium nitride doped with 5 × 10 ¹⁹ / cm ³ of magnesium (Mg) as a p-type impurity with a growth temperature of 1080 ° C. and a thickness of 50 nm is formed by MOCVD. A layer 17 (third nitride semiconductor layer) is selectively grown only in the recess 16a (FIG. 2b).

  Using an ordinary lithography technique, a photoresist opening is formed on the recess 16a to deposit a metal such as a nickel (Ni) / gold (Au) laminate, and the gate is formed on the p-type gallium nitride 17 by a lift-off method. The electrode 18 is formed. Thereafter, heat treatment is performed to bring the gate electrode 18 into ohmic contact with the p-type gallium nitride layer 17 (FIG. 2c). The dielectric film 16 formed on the cap layer 15 is removed by etching, and the source electrode 19a made of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) is formed on the exposed cap layer 15 and the drain. The electrode 19b is formed. Thereafter, heat treatment is performed to form an ohmic contact with the cap layer 15 to form the nitride semiconductor device having the structure shown in FIG. 1 (FIG. 2d).

The cap layer 15 is formed at a temperature lower by about 500 ° C. than the film formation temperature of the barrier layer 14 by MOCVD, thereby forming a microcrystalline structure and forming a highly insulating nitride semiconductor layer. Specifically, the specific resistance is a high resistance of 10 ⁹ Ωcm or more.

  FIG. 3 shows current-voltage characteristics between the gate and source electrodes of the nitride semiconductor device formed in this way. In FIG. 3, the horizontal axis represents the gate-source voltage Vgs (V), and the vertical axis represents the gate current Ig (A). For comparison, the current-voltage characteristics when the cap layer 15 is a nitride semiconductor layer made of non-doped aluminum gallium nitride formed at the same temperature and film formation conditions as the barrier layer 14 and a gate electrode having the same structure is formed. It is shown as a conventional example. When both are compared, it can be seen that the nitride semiconductor device of this example has a better insulating characteristic, and therefore the gate current (gate leakage current) is reduced by two orders of magnitude or more. As the gate leakage current is reduced, collision ionization in the channel can be suppressed, and as a result, the off breakdown voltage is improved from the conventional 90V to 150V. It has been reported that the off breakdown voltage of a nitride semiconductor HEMT is not due to thermal runaway but due to impact ionization and is largely governed by the tunnel current flowing into the channel from the Schottky electrode (International Conference on Nitride Semiconductor, Nara, 2003, Tu-P2.067).

  FIG. 4 shows the drain current-voltage characteristics. The drain sweep voltage is 0V to 20V, the gate voltage is changed from 0V to + 3V in step 1V, and a normally-off operation can be confirmed. Also, the current collapse is significantly suppressed compared to the conventional structure even in pulse IV measurement in which the measurement period is 10 ms, the gate voltage is applied with a pulse width of 300 μsec, and the drain voltage is stepped up from 0 V to 40 V. Was confirmed. Furthermore, it has been confirmed that an ohmic electrode having a low contact resistance can be formed because the structure is in ohmic contact with the nitride semiconductor layer having a microcrystalline structure.

  Next, a second embodiment will be described with reference to FIG. As in the first embodiment, a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 100 nm is formed on a substrate 11 made of silicon carbide (SiC) by MOCVD (metal organic chemical vapor deposition). Channel layer 13 (fourth nitride semiconductor layer) made of non-doped gallium nitride (GaN) having an energy gap smaller than that of a barrier layer, which will be described later, and having a thickness of 2 μm, and a two-dimensional carrier serving as an interface with the channel layer 13 A barrier layer 14 (first nitride semiconductor layer) made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 10 nm and forming an electron gas layer is sequentially stacked and grown at a substrate temperature of 1080 ° C. Thereafter, the substrate temperature is set to 550 ° C., and a cap layer 15 (second nitride semiconductor layer) made of non-doped gallium nitride having a microcrystalline structure with a thickness of 10 nm is grown (FIG. 5a).

A dielectric film 16 made of a silicon oxide (SiO ₂ ) film is formed on the cap layer 15 by plasma CVD or the like, and the dielectric film 16 is removed by dry etching so as to open the gate electrode formation region, thereby forming the recess 16a. Form. Using this dielectric film 16 (mask film) as a mask, the cap layer 15 is removed by etching to expose the barrier layer 14. After that, using the dielectric film 16 as a mask, a p-type gallium nitride layer 17 doped with 5 × 10 ¹⁹ / cm ³ of magnesium (Mg) as a p-type impurity having a growth temperature of 1080 ° C. and a thickness of 50 nm is formed by MOCVD. A third nitride semiconductor layer) is selectively grown only in the recess 16a (FIG. 5b).

  Using an ordinary lithography technique, a photoresist opening is formed on the recess 16a to deposit a metal such as a nickel (Ni) / gold (Au) laminate, and the gate is formed on the p-type gallium nitride 17 by a lift-off method. The electrode 18 is formed. Thereafter, heat treatment is performed to bring the gate electrode 18 into ohmic contact with the p-type gallium nitride layer 17 (FIG. 5c). The dielectric film 16 formed on the cap layer 15 is removed by etching, and the source electrode 19a made of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) is formed on the exposed cap layer 15 and the drain. The electrode 19b is formed. Thereafter, heat treatment is performed to form an ohmic contact with the cap layer 15, whereby the nitride semiconductor device of this example can be formed (FIG. 5d).

  Also in this example, like the first example, it was confirmed that normally-off operation and current collapse were suppressed. It was also confirmed that the microcrystalline structure was in ohmic contact with the nitride semiconductor layer and an ohmic electrode with low contact resistance could be formed.

  Next, a third embodiment will be described. In the above-described embodiment, the case where the gate electrode 18 is formed on the barrier layer 14 by removing the cap layer 15 or only the cap layer 15 has been described. However, in the embodiment, as shown in FIG. 6, a part of the barrier layer 14 exposed by removing the cap layer 15 is further etched to form a recess structure, and a p-type gallium nitride layer 17 is grown on the barrier layer 14. It can also be a structure. In the manufacturing process of the nitride semiconductor device having such a structure, the dielectric film 16 is used as a mask, and the cap layer 15 is removed by etching to expose the barrier layer 14 as in the second embodiment. A step of etching and removing the exposed barrier layer 14 to a predetermined depth may be added. Thereafter, as in the second embodiment, the p-type gallium nitride layer 17 having a thickness of 50 nm is selectively grown by MOCVD at a growth temperature of 1080 ° C. using the dielectric film 16 as a mask. Further, a photoresist opening is formed on the recess 16a, a metal made of a nickel (Ni) / gold (Au) laminate or the like is deposited, and a gate electrode 18 is formed on the p-type gallium nitride 17 by a lift-off method. The control electrode can be formed by performing heat treatment and making ohmic contact.

  Also in the present example, as in the first and second examples described above, it was confirmed that normally-off operation and current collapse were suppressed. In addition, it was confirmed that an ohmic electrode having a low contact resistance can be formed because the structure is in ohmic contact with the nitride semiconductor layer having a microcrystalline structure. Furthermore, in this example, it was confirmed that by introducing a recess structure, a threshold voltage exceeding 1 V can be easily realized as compared with a Schottky FET.

  Further, by adopting a recess structure, a threshold voltage (Vth) of 1 V or more can be easily realized because the diffusion potential of the gate electrode 18 formed on the p-type gallium nitride 17 is 3 V or more. Since the two-dimensional electron gas concentration is sufficient, the high frequency characteristics and on-resistance can be improved by reducing the gate-source resistance. In addition, since the diffusion potential of the gate electrode of the present invention is 3 V or more, compared to the conventional Schottky gate height of about 1.0 V, the controllability of the required recess amount is eased.

  As mentioned above, although the Example of this invention was described, this invention is not limited to these, A various change is possible. For example, the types of the control electrode and ohmic electrode, the thickness of the cap layer and the barrier layer, and the impurity concentration can be appropriately selected and set. Instead of the nitride semiconductor device having the HEMT structure, a nitride semiconductor layer to which an impurity is added is used as an active layer (a channel layer, which corresponds to the first nitride semiconductor layer), and the above-described cap layer 15 ( An FET structure having a structure in which a second nitride semiconductor layer is formed) is also possible. The nitride semiconductor layer is not limited to a GaN / AlGaN system, and can be formed of a layer made of GaN, InN, AlN, or a mixed crystal compound thereof. A sapphire substrate may be used instead of the silicon carbide (SiC) substrate used in the above embodiment. In that case, it is preferable to use gallium nitride (GaN) grown at a low temperature as the buffer layer 12. A silicon substrate (Si) may be used instead of the silicon carbide (SiC) substrate.

  Although the second nitride semiconductor layer has been described as having a microcrystalline structure, this is an aggregate of microcrystalline grains or a rearranged structure thereof. The growth temperature, the atmospheric gas composition during growth, the growth of the substrate to be grown. The size and arrangement of crystal grains vary depending on the type and the like, and can be obtained by controlling the growth temperature within a range where desired insulating characteristics (acceptable gate leakage current) can be obtained. The growth temperature of the second nitride semiconductor layer is preferably set to a temperature lower by about 400 ° C. than the growth temperature of the first nitride semiconductor layer, which is suitable for forming a HEMT or FET control electrode.

1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention. It is explanatory drawing of the manufacturing method of the nitride semiconductor device which is the 1st Example of this invention. It is a figure which shows the current-voltage characteristic between gate-source explaining the effect of this invention. It is a figure which shows the drain current-voltage characteristic explaining the effect of this invention. It is explanatory drawing of the manufacturing method of the nitride semiconductor device which is the 2nd Example of this invention. It is sectional drawing of the nitride semiconductor device which is the 3rd Example of this invention. It is sectional drawing of this kind of conventional nitride semiconductor device.

Explanation of symbols

11; substrate, 12; buffer layer, 13; channel layer, 14; barrier layer, 15; cap layer, 16; dielectric film, 16a; recess, 17; p-type gallium nitride layer, 18; Electrode, 19b; drain electrode

Claims (7)

Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device comprising a semiconductor layer,
A first nitride semiconductor layer comprising the group III-V nitride semiconductor layer stacked on a substrate, and a temperature lower than a film forming temperature of the first nitride semiconductor layer on the first nitride semiconductor layer; And a second nitride semiconductor layer having a microcrystalline structure that does not include aluminum, and the second nitride semiconductor layer in the control electrode formation region. And a third nitride semiconductor layer having p-type conductivity and a control electrode in ohmic contact with the third nitride semiconductor layer. A nitride semiconductor device.   2. The nitride semiconductor device according to claim 1, wherein the third nitride semiconductor layer is formed on the first nitride semiconductor layer exposed by removing the second nitride semiconductor layer only in the control electrode formation region. Alternatively, the nitride semiconductor device is further laminated on the first nitride semiconductor layer from which a part of the surface is removed.   3. The nitride semiconductor device according to claim 1, wherein an energy gap between the substrate and the first nitride semiconductor layer is smaller than an energy gap of the first nitride semiconductor layer. A nitride semiconductor device comprising a fourth nitride semiconductor layer made of a group III-V nitride semiconductor layer.   4. The nitride semiconductor device according to claim 1, further comprising an ohmic electrode that is in ohmic contact with the second nitride semiconductor layer. Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a method for manufacturing a nitride semiconductor device comprising a semiconductor layer,
Forming a first nitride semiconductor layer comprising the III-V nitride semiconductor layer on a substrate;
On the first nitride semiconductor layer, a fine material which is made of the III-V nitride semiconductor layer and does not contain aluminum at a temperature lower than the film formation temperature when forming the first nitride semiconductor layer. Forming a second nitride semiconductor layer having a crystal structure;
Forming a mask film having an opening in the control electrode formation region on the second nitride semiconductor layer;
The first nitride semiconductor layer exposed on the second nitride semiconductor layer using the mask film or by removing the second nitride semiconductor layer in the opening using the mask film A third nitride semiconductor layer made of the III-V nitride semiconductor layer and having p-type conductivity is formed on the first nitride semiconductor layer from which a part of the surface is further removed. Selectively forming, and
Forming a control electrode in ohmic contact with the third nitride semiconductor layer on the third nitride semiconductor layer.   6. The method for manufacturing a nitride semiconductor device according to claim 5, wherein the III and the first nitride semiconductor layer have an energy gap smaller than that of the first nitride semiconductor layer. A method for manufacturing a nitride semiconductor device, comprising a step of forming a fourth nitride semiconductor layer made of a group V nitride semiconductor layer.   7. The method of manufacturing a nitride semiconductor device according to claim 5, further comprising a step of forming an ohmic electrode in ohmic contact with the second nitride semiconductor layer. Method.

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