JP2008035197A - Clocking circuit, video processor and clock adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clocking circuit capable of accurately generating clocks, even in the case of continuously receiving a plurality of transport packets to which time information is added, and a clock adjustment method, and to provide a video processor capable of accurately decoding the transport packets, even when the plurality of transport packets to which the time information has been added are received continuously. <P>SOLUTION: The plurality of transport packets to which the time information is added are received continuously. Then, the transport packet containing the clock adjustment value for adjusting the frequency of the clock is detected, and a comparison processing of comparing the clock adjustment value with a changed counter value is performed. A clock generation means adjusts the frequency of the clock to be generated by using the result of the comparison processing at a timing controlled by a timing control means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock circuit, a video processing device, and a clock adjustment method, and more particularly, to a clock circuit, a video processing device, and a clock adjustment method for processing a transport packet used for content distribution.

  In recent years, a technology based on a transport stream protocol capable of transmitting a plurality of contents (for example, programs) at a time is rapidly spreading. As a representative transport stream, there is MPEG (Moving Picture Experts Group) 2-TS (Transport Stream). At present, communication protocols using MPEG2-TS are used in digital broadcasting, VOD (Video On Demand) services, and the like.

  FIG. 5 is a diagram for explaining a transport stream. The transport stream shown in FIG. 5 is, for example, an MPEG2 transport stream.

  Referring to FIG. 5, the transport stream is composed of a plurality of transport packets. Hereinafter, the transport packet is also referred to as a TS packet. The size of each of the plurality of TS packets is 188 or 204 bytes. Each of the plurality of TS packets includes adaptation field control. The adaptation field control is information indicating whether or not the adaptation field is included in the corresponding TS packet. Therefore, depending on the information of the adaptation field control, some TS packets do not include the adaptation field.

  The adaptation field indicates additional information of the corresponding TS packet. The adaptation field includes a PCR (Program Clock Reference) flag. The PCR flag is information indicating whether or not a PCR as an optional field is included in the corresponding adaptation field. When the PCR flag indicates “1”, it indicates that the adaptation field includes PCR as an optional field. When the PCR flag indicates “0”, it indicates that the adaptation field does not include PCR as an optional field. Therefore, depending on the information of the PCR flag, there is also an adaptation field that does not include PCR as an optional field.

  The PCR is a value of time information for reproducing the system clock of the encoding device that generated the transport stream by the decoding device that receives the transport stream. The PCR is also a clock adjustment value for adjusting the frequency of the system clock of the encoding device that generated the transport stream and the frequency of the system clock generated by the decoding device that receives the transport stream.

  Note that the frequency of the system clock of the encoding device that generated the transport stream is strictly different from the system clock of the decoding device that receives the transport stream. Therefore, in order for the decoding device to decode the same number of frames as the number of frames generated by the encoding device, it is necessary for the decoding device to reproduce and match the system clock of the encoding device. Therefore, when transmitting a transport stream, the encoding device sets a counter value counted by the system clock of the encoding device in a TS packet at a predetermined time interval among a plurality of TS packets included in the transport stream to be transmitted. Add as PCR. Using this PCR, the decoding device reproduces the system clock of the encoding device.

International Publication No. WO 01/004893 pamphlet (Patent Document 1) discloses a technique for continuously recording a transport stream (hereinafter also referred to as first prior art). In the following, a device capable of recording a transport stream is also referred to as a video processing device.
International Publication No. WO01 / 004893 Pamphlet

  FIG. 6 is a block diagram showing an example of an internal configuration of a conventional video processing apparatus 10000. Referring to FIG. 6, video processing apparatus 10000 includes communication unit 1200, control unit 1400, storage unit 1500, and decode circuit 1600.

  The communication unit 1200 has a function of receiving a transport stream from a network such as the Internet. The communication unit 1200 transmits the received transport stream to the control unit 1400.

  The control unit 1400 has a function of performing various processes. The control unit 1400 may be any of a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and other circuits having arithmetic functions.

  The storage unit 1500 has a function of storing data in a nonvolatile manner. The storage unit 1500 is accessed by the control unit 1400. The storage unit 1500 is a hard disk capable of storing a large amount of data. Note that the storage unit 1500 is not limited to a hard disk, and may be any medium (for example, a flash memory) that can hold data in a nonvolatile manner even when power is not supplied.

  The control unit 1400 performs processing for storing the received transport stream in the storage unit 1500. In addition, the control unit 1400 performs a process of reading the transport stream stored in the storage unit 1500 and transmitting it to the decoding circuit 1600.

  The decode circuit 1600 decodes the received transport stream, generates a video signal and an audio signal, and transmits them to an external display device.

  Decode circuit 1600 includes a clock circuit 1700 and a decode unit 1800. The clock circuit 1700 receives a plurality of TS packets including the PCR included in the transport stream, and generates a system clock SCK having the same frequency as the system clock frequency of the encoder based on the PCR value. The system clock SCK thus transmitted is transmitted to the decoding unit 1800. The frequency of the system clock SCK generated by the clock circuit 1700 is adjusted based on the received PCR value. In addition, the clock circuit 1700 transmits the received transport stream to the decoding unit 1800.

  The decoding unit 1800 operates at the frequency of the received system clock SCK. In addition, the decoding unit 1800 decodes the received transport stream, generates a video signal and an audio signal, and transmits them to, for example, an external display device. The display device displays video based on the received video signal and outputs audio based on the received audio signal.

  When the conventional video processing apparatus 10000 as described above stores, for example, one program data in the storage unit 1500 instead of all of the plurality of programs among the plurality of programs included in the transport stream, the storage unit In order to normally reproduce the program data stored in the 1500, a time stamp is added to the TS packet stored in the storage unit 1500.

  Here, it is assumed that the video processing apparatus 10000 stores in the storage unit 1500 a transport stream including a plurality of TS packets corresponding to one program in the transport stream STM illustrated in FIG. 7, for example. In FIG. 7, the horizontal axis indicates the time at which the control unit 1400 in the video processing apparatus 10000 receives the corresponding TS packet. For example, it is indicated that the TS packet T30 is received by the control unit 1400 at time t7.

  The transport stream STM includes a plurality of TS packets corresponding to each of the programs A, B, and C. For example, TS packets corresponding to the program A are TS packets T10, T20, T30, and T40. Among a plurality of TS packets in the transport stream STM, a TS packet described as “(PCR)” indicates that the corresponding TS packet includes a PCR value.

  When the control unit 1400 stores the TS packet corresponding to the program A among the plurality of TS packets in the transport stream STM in the storage unit 1500, when the control unit 1400 stores the TS packet in the storage unit 1500, A counter value corresponding to the time when the TS packet is received is added as a time stamp. The counter value added to the TS packet is a value to be incremented, for example, in the range of “0” to “2 to the power of 2” every time the control unit 1400 receives a 27 MHz clock (not shown).

  For example, when the control unit 1400 stores the TS packet T20 in the storage unit 1500, the control unit 1400 adds a time stamp indicating a counter value corresponding to the time t4 when the TS packet T20 is received to the TS packet T20. Thus, the data is stored in the storage unit 1500 as the TS packet T20A.

  The control unit 1400 causes the storage unit 1500 to store a plurality of TS packets corresponding to the program A, so that the transport stream STA shown in FIG. As shown in FIG. 8, in the TS packet T10A included in the transport stream STA, a 4-byte time stamp is added to the TS packet. The time stamp indicates a counter value corresponding to the time t1. The TS packet T10A includes a PCR. Note that time stamps are added to all TS packets included in the transport stream STA, similarly to the TS packet T10A.

  Referring to FIG. 7, at time tn (n: natural number) described in the upper part of transport stream STA, a time stamp indicating a counter value corresponding to time tn is added to the corresponding TS packet. Indicates. For example, a time stamp indicating a counter value corresponding to the time t10 is added to the TS packet T40A.

  The storage unit 1500 continuously stores a plurality of TS packets corresponding to the program A in the transport stream STM as indicated by the transport stream STA. That is, a plurality of non-continuous packets on the time axis are stored in the storage unit 1500 so as to be continuous on the time axis. Hereinafter, the TS packet stored in the storage unit 1500 is also referred to as a stored TS packet.

  Here, when decoding the transport stream STA stored in the storage unit 1500, when the control unit 1400 transmits a plurality of storage TS packets included in the transport stream STA to the clock circuit 1700 without a time interval, The clock circuit 1700 has a problem that it cannot accurately generate the system clock SCK having the same frequency as the system clock of the encoding device.

  Because, for example, the TS packet T40A included in the transport stream STA includes a PCR for adjusting the frequency of the system clock, so that the TS packet T40A includes a control unit like the transport stream STM illustrated in FIG. This is because the transmission of the TS packet T10A to the clock circuit 1700 by the time 1400 needs to be transmitted to the clock circuit 1700 at the time when the difference between the time t10 and the time t1 has elapsed.

  That is, the TS packets T10A and T40A including the PCR need to be input to the clock circuit 1700 at time intervals corresponding to the TS packets T10 and T40 included in the transport stream STM. For this purpose, for example, a circuit for controlling the timing for transmitting a plurality of TS packets included in the transport stream STA to the clock circuit 1700 is required.

  That is, the clock circuit 1700 cannot generate the system clock SCK having the same frequency as the system clock of the encoding device when receiving a plurality of continuous transport packets to which time stamps are added. To do. The first prior art does not disclose a specific circuit or method for the above timing control.

  When the clock circuit 1700 cannot accurately generate the system clock SCK having the same frequency as the system clock of the encoding device, the decoding unit 1800 that operates based on the system clock SCK output from the clock circuit 1700 This causes a problem that the transport stream cannot be decoded normally.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to accurately generate a clock even when a plurality of transport packets to which time information is added are continuously received. It is to provide a clock circuit that is capable of.

  Another object of the present invention is to provide a video processing apparatus capable of accurately decoding transport packets even when a plurality of transport packets to which time information is added are continuously received.

  Still another object of the present invention is to provide a clock adjustment method capable of accurately generating a clock even when a plurality of transport packets to which time information is added are continuously received.

  In order to solve the above-described problem, a clock circuit according to an aspect of the present invention includes a clock generation unit that generates a clock, a counter unit that changes the value of the counter based on the clock generated by the clock generation unit, Receiving means for continuously receiving a plurality of transport packets to which time information is added, and detection for detecting a transport packet including a clock adjustment value for adjusting a clock frequency among the plurality of received transport packets. Means for comparing the clock adjustment value included in the transport packet detected by the detecting means with the counter value changed by the counter means, and the clock generating means Timing control means for controlling the timing of use, and a clock Forming means at a timing controlled by the timing control means, using the results of the comparison process, to adjust the frequency of the generated clock.

  According to the present invention, a plurality of transport packets to which time information is added are continuously received. Then, a transport packet including a clock adjustment value for adjusting the clock frequency is detected, and a comparison process is performed for comparing the clock adjustment value with the changed counter value. The clock generation means adjusts the frequency of the generated clock using the result of the comparison process at the timing controlled by the timing control means.

  Therefore, even when a plurality of transport packets to which time information is added are continuously received, the clock frequency can be adjusted with accurate timing. That is, even when a plurality of transport packets to which time information is added are continuously received, the clock can be generated accurately.

Preferably, the result of the comparison process is a difference between the clock adjustment value and the counter value.
According to the present invention, even when a plurality of transport packets to which time information is added are continuously received, the clock can be generated accurately.

  Preferably, the timing control means includes a comparison counter means for changing the value of the comparison counter for controlling the timing at which the clock generation means uses the result of the comparison processing at every predetermined time, and the transport detected by the detection means. Comparison timing control means for controlling the timing at which the clock generation means uses the result of the comparison processing by comparing the value indicated by the time information added to the packet with the value of the comparison counter changed by the comparison counter means; including.

  According to the present invention, the clock generation means compares the value indicated by the time information added to the transport packet detected by the detection means with the value of the comparison counter changed by the comparison counter means. Control when to use the result. Therefore, there is an effect that the clock can be generated accurately.

  A video processing apparatus according to another aspect of the present invention includes a clock circuit and decoding means for successively decoding a plurality of transport packets to which time information is added based on a clock generated by the clock circuit.

  According to the present invention, the decoding means continuously decodes a plurality of transport packets to which time information is added based on an accurate clock generated by the clock circuit. Therefore, even when a plurality of transport packets to which time information is added are continuously received, the transport packet can be accurately decoded.

  According to still another aspect of the present invention, there is provided a clock adjustment method performed by a clock circuit provided with a clock generation unit for generating a clock, the clock adjustment method including a counter based on a clock generated by the clock generation unit A counter step for changing the value of the reception, a reception step for continuously receiving a plurality of transport packets to which time information is added, and a clock adjustment value for adjusting a clock frequency among the plurality of received transport packets A detection step for detecting a transport packet including a comparison step for performing a comparison process for comparing a clock adjustment value included in the transport packet detected in the detection step with a counter value changed in the counter step; The clock generator uses the result of the comparison process. Comprising a timing control step of controlling the timing, at the timing controlled by the timing control step, using the results of the comparison process, an adjustment step of adjusting the frequency of the clock by the clock generation unit generates.

  According to the present invention, a plurality of transport packets to which time information is added are continuously received. Then, a transport packet including a clock adjustment value for adjusting the clock frequency is detected, and a comparison process is performed for comparing the clock adjustment value with the changed counter value. The clock generation unit that generates the clock adjusts the frequency of the generated clock using the result of the comparison process at the timing controlled by the timing control step.

  Therefore, even when a plurality of transport packets to which time information is added are continuously received, the clock frequency can be adjusted with accurate timing. That is, even when a plurality of transport packets to which time information is added are continuously received, the clock can be generated accurately.

  The clock circuit according to the present invention continuously receives a plurality of transport packets to which time information is added. Then, a transport packet including a clock adjustment value for adjusting the clock frequency is detected, and a comparison process is performed for comparing the clock adjustment value with the changed counter value. The clock generation means adjusts the frequency of the generated clock using the result of the comparison process at the timing controlled by the timing control means.

  Therefore, even when a plurality of transport packets to which time information is added are continuously received, the clock frequency can be adjusted with accurate timing. That is, even when a plurality of transport packets to which time information is added are continuously received, the clock can be generated accurately.

  In the video processing apparatus according to the present invention, the decoding means continuously decodes a plurality of transport packets to which time information is added based on an accurate clock generated by the clock circuit. Therefore, even when a plurality of transport packets to which time information is added are continuously received, the transport packet can be accurately decoded.

  The clock adjustment method according to the present invention continuously receives a plurality of transport packets to which time information is added. Then, a transport packet including a clock adjustment value for adjusting the clock frequency is detected, and a comparison process is performed for comparing the clock adjustment value with the changed counter value. The clock generation unit that generates the clock adjusts the frequency of the generated clock using the result of the comparison process at the timing controlled by the timing control step.

  Therefore, even when a plurality of transport packets to which time information is added are continuously received, the clock frequency can be adjusted with accurate timing. That is, even when a plurality of transport packets to which time information is added are continuously received, the clock can be generated accurately.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  FIG. 1 is a block diagram showing an example of the internal configuration of the video processing apparatus 1000 in the present embodiment. Referring to FIG. 1, video processing apparatus 1000 is different from video processing apparatus 10000 in FIG. 6 in that a decoding circuit 1600A is provided instead of decoding circuit 1600. Other than that, it is the same as the video processing apparatus 10000, and therefore, detailed description will not be repeated. The video processing apparatus 1000 is an HDD (Hard Disk Drive) recorder, for example. The video processing apparatus 1000 is not limited to an HDD recorder, and may be any apparatus that can record video.

  The decode circuit 1600A differs from the decode circuit 1600 in that it includes a clock circuit 1700A instead of the clock circuit 1700. Other than that, it is the same as that of the decoding circuit 1600, and therefore detailed description will not be repeated.

  The decode circuit 1600A receives a transport stream from the control unit 1400, decodes the received transport stream, generates a video signal and an audio signal, and transmits the video signal and an audio signal to an external display device. The decode circuit 1600A is a one-chip microprocessor. Note that the decode circuit 1600A is not limited to a one-chip microprocessor, and may be a circuit composed of a plurality of circuits.

  FIG. 2 is a block diagram illustrating an example of an internal configuration of the clock circuit 1700A in the present embodiment. Referring to FIG. 2, clock circuit 1700A includes a buffer 1710, a detection unit 1720, and a switch control unit 1730. In the following description, the binary high voltage state (power supply voltage Vcc) and low voltage state of the signal and signal line are also referred to as “H level” and “L level”, respectively.

  The buffer 1710 is a FIFO (First-In First-Out) buffer that temporarily stores a plurality of TS packets. Further, the buffer 1710 operates in accordance with the control signal SWSG transmitted from the switch control unit 1730. Specifically, when control signal SWSG is at the H level, buffer 1710 enters a packet transmission state, and transmits a plurality of TS packets stored in buffer 1710 to detection unit 1720. Further, when the control signal SWSG is at the L level, the buffer 1710 enters a packet transmission stop state and stops the process of transmitting a plurality of TS packets stored in the buffer 1710. Note that when the buffer 1710 newly receives a TS packet during a period in which the buffer 1710 is in a packet transmission stop state, the buffer 1710 stores the newly received TS packet.

  The detection unit 1720 transmits a control signal DTSG for controlling the switch control unit 1730 to the switch control unit 1730. In addition, the detection unit 1720 detects a TS packet including the above-described PCR (hereinafter also referred to as a PCR inclusion TS packet). As described above, the PCR is a value of time information for reproducing the system clock of the encoding device that generated the transport stream by the clock circuit 1700A that receives the transport stream. The PCR is also a clock adjustment value for adjusting the frequency of the system clock of the encoding device that has generated the transport stream and the frequency of the system clock SCK generated by the clock circuit 1700A that receives the transport stream.

  When detecting the PCR inclusion TS packet, the detection unit 1720 sets the control signal DTSG to the H level.

  The switch control unit 1730 transmits a control signal SWSG for controlling the buffer 1710 to the buffer 1710. Control signal DTSG is set to H level in the initial state. Therefore, the buffer 1710 is in a packet transmission state in the initial state. When the switch control unit 1730 receives the control signal DTSG at the H level, the switch control unit 1730 sets the control signal SWSG to the L level to place the buffer 1710 in a packet transmission stop state.

  Clock circuit 1700A further includes a buffer 1740, a counter 1750, a clock generation circuit 1752, and a comparison circuit 1760.

  The buffer 1740 temporarily stores one PCR inclusion TS packet. In addition, when detecting the PCR inclusion TS packet, the detection unit 1720 stores the detected PCR inclusion TS packet in the buffer 1740. FIG. 2 shows a state in which the PCR inclusion TS packet is stored in the buffer 1740.

  The detection unit 1720 stores the detected PCR inclusion TS packet in the buffer 1740, and then transmits the PCR inclusion TS packet to the decoding unit 1800. If the received TS packet is not a PCR inclusion TS packet, the detection unit 1720 transmits the received TS packet to the decoding unit 1800.

  The clock generation circuit 1752 transmits a clock having a frequency of 27 MHz to the counter 1750. Note that the frequency of the clock transmitted by the clock generation circuit 1752 is not limited to 27 MHz, and may be another value.

  The counter 1750 updates a comparison counter CPCT for counting a value to be compared with the time stamp value added to the PCR inclusion TS packet stored in the buffer 1740. Specifically, the counter 1750 increments the value of the comparison counter CPCT by “1” every time a clock is received from the clock generation circuit 1752. The value of the comparison counter CPCT is, for example, a value in the range of “0” to “2 raised to the 42nd power”. Therefore, when the value of the comparison counter CPCT is “2 to the power of 42”, when the value is incremented by “1”, the value of the comparison counter CPCT becomes “0”.

  When detecting the PCR inclusion TS packet for the first time, the detection unit 1720 sets the value of the time stamp added to the detected PCR inclusion TS packet as the initial value of the comparison counter CPCT.

  The comparison circuit 1760 compares the value of the time stamp added to the PCR inclusion TS packet stored in the buffer 1740 with the value of the comparison counter CPCT. Comparison circuit 1760 transmits comparison signal CPSG to switch control unit 1730. The comparison circuit 1760 sets the comparison signal CPSG to the H level when the value of the time stamp added to the PCR inclusion TS packet stored in the buffer 1740 matches the value of the comparison counter CPCT. Upon receiving the H level comparison signal CPSG, the switch control unit 1730 sets the control signal DTSG to the H level to place the buffer 1710 in the packet transmission state.

  The clock circuit 1700A further includes an STC (System Time Clock) counter 1771, a comparison circuit 1772, a latch circuit 1773, a DAC (Digital Analog Converter) 1774, an LPF (Low Pass Filter) 1775, and a VCO (Voltage Control Oscillator). ) 1776.

  The STC counter 1771 updates the value of the system clock counter SYCT for counting the system clock SCK output from the VCO 1776 described later. Specifically, the STC counter 1771 increments the value of the system clock counter SYCT by “1” every time it receives the system clock SCK from the VCO 1776. The value of the system clock counter SYCT is, for example, a value in the range of “0” to “2 to the 42nd power”. Therefore, when the value of the system clock counter SYCT is “2 to the power of 42”, when the system clock counter SYCT is incremented by “1”, the value of the system clock counter SYCT becomes “0”. Also, the STC counter 1771 transmits the value of the system clock counter SYCT to the comparison circuit 1772.

  Further, when detecting the PCR inclusion TS packet for the first time, the detection unit 1720 sets the PCR value included in the detected PCR inclusion TS packet to the initial value of the system clock counter SYCT.

  The comparison circuit 1772 performs comparison processing for comparing the value of the PCR included in the PCR inclusion TS packet stored in the buffer 1740 with the value of the system clock counter SYCT received from the STC counter 1771. In the comparison processing, the comparison circuit 1772 calculates the difference value between the PCR value and the system clock counter SYCT value by subtracting the system clock counter SYCT value from the PCR value. The difference value is “0”, a positive value, or a negative value. Then, the comparison circuit 1772 transmits the calculated difference value to the latch circuit 1773.

  Comparison circuit 1760 described above further transmits comparison signal CPSG to latch circuit 1773.

  The latch circuit 1773 temporarily stores the difference value transmitted from the comparison circuit 1772 when the comparison signal CPSG of H level is received. The latch circuit 1773 transmits the stored difference value to the DAC 1774.

  The DAC 1774 converts the analog signal with a voltage corresponding to the received difference value. If the received difference value is “0”, the DAC 1774 generates an analog signal of 1V, for example. If the received difference value is a positive value, the DAC 1774 generates an analog signal having a voltage greater than 1V, for example. If the received difference value is a negative value, the DAC 1774 generates, for example, an analog signal having a voltage of less than 1V. Then, the DAC 1774 transmits the generated analog signal to the LPF 1775.

  The LPF 1775 transmits only the low frequency component of the received analog signal to the VCO 1776. Note that the voltage of the received analog signal may change. In this case, when the voltage of the received analog signal changes, for example, in the order of 1.1, 1.0, and 0.9 V in a short time (for example, 0.5 seconds), the LPF 1775 transmits to the VCO 1776. The voltage of the analog signal is 1.1V, 1.0V, 0.9V average and 1.0V. That is, the LPF 1775 performs a process of averaging the change in the voltage of the received analog signal in a short time.

  The VCO 1776 generates a system clock SCK having a frequency corresponding to the voltage of the received analog signal. For example, when receiving an analog signal of 1V, the VCO 1776 generates a system clock SCK having a frequency of 27 MHz. In this case, when receiving an analog signal having a voltage higher than 1V, the VCO 1776 generates a system clock SCK having a frequency higher than 27 MHz. In addition, when receiving an analog signal having a voltage lower than 1 V, the VCO 1776 generates a system clock SCK having a frequency lower than 27 MHz.

  The VCO 1776 transmits the generated system clock SCK to the decoding unit 1800 and the STC counter 1771. As a result, the decoding unit 1800 operates at the frequency of the received system clock SCK. Further, as described above, the STC counter 1771 increments the value of the system clock counter SYCT by “1” every time the system clock SCK is received.

  FIG. 3 is an operation waveform diagram as an example for explaining the operation of the clock circuit 1700A. 3 shows the transport stream STM and the transport stream STA of FIG. 7 described above for the sake of explanation.

  In FIG. 3, “STA” indicates the state of a plurality of TS packets included in the transport stream STA over time. “TMSTP” indicates the value of the time stamp added to the PCR-containing TS packet stored in the buffer 1740. “CPCT” indicates the value of the comparison counter CPCT. “CPSG” indicates the voltage level of the comparison signal CPSG. The “latch circuit” indicates a value stored in the latch circuit 1773. “SWSG” indicates the voltage level of the control signal SWSG.

  Next, the operation of the video processing apparatus 1000 will be described with reference to FIGS. It is assumed that the above-described transport stream STA is stored in the storage unit 1500 of the video processing apparatus 1000. When the video processing apparatus 1000 performs the decoding process on the transport stream STA, first, the control unit 1400 reads the transport stream STA and transmits it to the clock circuit 1700A. It is assumed that the data capacity of the transport stream STA is less than or equal to the data capacity that can be stored in the buffer 1710.

  The TS packet T10A included in the transport stream STA has a time stamp indicating a counter value corresponding to the time t1. As an example, the value of the time stamp added to the TS packet T10A is “110”. The TS packet T10A includes a PCR. Here, it is assumed that the value of PCR is “210” as an example.

  First, the transport stream STA is transmitted to the buffer 1710. Since the buffer 1710 in the initial state is in a packet transmission state, the buffer 1710 first transmits the first TS packet T10A included in the received transport stream STA to the detection unit 1720.

  The detection unit 1720 receives the TS packet T10A at time t1. As described above, when detecting unit 1720 detects the PCR inclusion TS packet, it sets control signal DTSG to the H level. Since the TS packet T10A is a PCR-included TS packet, when receiving the TS packet T10A, the detection unit 1720 sets the control signal DTSG to the H level, assuming that the PCR-included TS packet is detected. Accordingly, the switch control unit 1730 receives the control signal DTSG at the H level, and the switch control unit 1730 sets the control signal SWSG to the L level, thereby putting the buffer 1710 in a packet transmission stop state. As a result, TS packets after the TS packet T10A are held in the buffer 1710.

  Further, as described above, when detecting unit 1720 detects the PCR-containing TS packet, detection unit 1720 stores the detected PCR-containing TS packet in buffer 1740. Since the TS packet T10A is a PCR inclusion TS packet, the detection unit 1720 stores the TS packet T10A in the buffer 1740 when the TS packet T10A is received. Then, the detection unit 1720 transmits the TS packet T10A to the decoding unit 1800.

  A time stamp indicating a counter value “110” corresponding to the time t1 is added to the TS packet T10A as the PCR inclusion TS packet stored in the buffer 1740.

  Further, since the detection unit 1720 detects the PCR inclusion TS packet for the first time by receiving the TS packet T10A, the value of the time stamp (“110”) added to the TS packet T10A is compared with the comparison counter CPCT. Set to the initial value of. The counter 1750 increments the value of the comparison counter CPCT by “1” every time a 27 MHz clock is received from the clock generation circuit 1752.

  As described above, the comparison circuit 1760 compares the value of the time stamp added to the PCR inclusion TS packet stored in the buffer 1740 with the value of the comparison counter CPCT. Further, when the time stamp value added to the PCR-containing TS packet stored in the buffer 1740 matches the comparison circuit 1760, the comparison circuit 1760 sets the comparison signal CPSG to the H level. Therefore, comparison circuit 1760 sets comparison signal CPSG to the H level. As a result, the switch control unit 1730 receives the H level comparison signal CPSG, and sets the control signal SWSG to the H level, thereby setting the buffer 1710 to the packet transmission state. Therefore, the buffer 1710 starts processing for transmitting TS packets after the TS packet T10A (TS packets T20A, T30A, T40A,...) To the detection unit 1720.

  Further, as described above, when detecting unit 1720 detects a PCR inclusion TS packet for the first time, it sets the PCR value included in the detected PCR inclusion TS packet as the initial value of system clock counter SYCT. Therefore, the detection unit 1720 detects the PCR-included TS packet for the first time by receiving the TS packet T10A, so the PCR value (“210”) included in the TS packet T10A is set to the system clock counter SYCT. Set to the initial value.

  Further, the comparison circuit 1772 compares the PCR value (“210”) included in the TS packet T10A stored in the buffer 1740 with the value of the system clock counter SYCT (“210”) received from the STC counter 1771. The comparison process is performed. Then, the comparison circuit 1772 subtracts the value of the system clock counter SYCT (“210”) from the value of PCR (“210”), thereby obtaining a difference value between the PCR value and the value of the system clock counter SYCT. calculate. In this case, the calculated difference value is “0”. Then, the comparison circuit 1772 transmits the calculated difference value “0” to the latch circuit 1773.

  Further, since the comparison signal CPSG is set to the H level by the processing of the comparison circuit 1760, the latch circuit 1773 stores the received difference value “0”.

  The latch circuit 1773 transmits the stored difference value “0” to the DAC 1774. The DAC 1774 converts the analog signal with a voltage corresponding to the received difference value. Here, when the difference value is “0”, the DAC 1774 generates an analog signal of 1V. Then, the DAC 1774 transmits the generated 1V analog signal to the LPF 1775.

  The 1V analog signal is transmitted to the VCO 1776 via the LPF 1775 described above.

  As described above, the VCO 1776 generates the system clock SCK having a frequency corresponding to the voltage of the received analog signal. For example, it is assumed that the VCO 1776 generates a system clock SCK having a frequency of 27 MHz when an analog signal of 1 V is received. Therefore, the VCO 1776 that has received the analog signal of 1V generates a system clock SCK having a frequency of 27 MHz. The VCO 1776 transmits the generated system clock SCK to the decoding unit 1800 and the STC counter 1771. The STC counter 1771 increments the value of the system clock counter SYCT by “1” every time it receives the system clock SCK.

  As described above, the buffer 1710 in the packet transmission state transmits TS packets after the TS packet T10A (TS packets T20A, T30A, T40A,...) To the detection unit 1720. Here, the TS packet T40A has a time stamp indicating a counter value corresponding to the time t10. As an example, the value of the time stamp added to the TS packet T40A is “210”.

  Further, it is assumed that the TS packet T40A is a packet generated by a coding device that operates with a system clock of 27.1 MHz, in which the frequency of the system clock is changed from 27 MHz, for example. The TS packet T40A includes a PCR. Here, the value of PCR is assumed to be “320” as an example. Further, it is assumed that the PCR value is a value for adjusting (changing) the frequency of the system clock SCK at time t10 as shown in the transport stream STM of FIG.

  When receiving the TS packets T20A and T30A, the detection unit 1720 transmits the received TS packets T20A and T30A to the decoding unit 1800. Then, when the detection unit 1720 receives the TS packet T40A as the PCR inclusion TS packet at time t4, the detection unit 1720 sets the control signal DTSG to the H level because it detects the PCR inclusion TS packet. Accordingly, the switch control unit 1730 receives the control signal DTSG at the H level, and the switch control unit 1730 sets the control signal SWSG to the L level, thereby putting the buffer 1710 in a packet transmission stop state. As a result, TS packets after the TS packet T40A are held in the buffer 1710.

  In addition, when detecting the TS packet T40A as the PCR inclusion TS packet, the detection unit 1720 stores the TS packet T40A in the buffer 1740. Then, the detection unit 1720 transmits the TS packet T40A to the decoding unit 1800.

  A time stamp indicating a counter value “210” corresponding to time t10 is added to the TS packet T40A as the PCR inclusion TS packet stored in the buffer 1740.

The comparison circuit 1760 compares the time stamp value (“210”) added to the TS packet T40A stored in the buffer 1740 with the value of the comparison counter CPCT. The value of the comparison counter CPCT is “110” at time t1.
Is set, the value of the comparison counter CPCT is incremented by “1” every time a 27 MHz clock is received from the clock generation circuit 1752. Then, it is assumed that the value of the comparison counter CPCT becomes “210” at time t10.

  Therefore, comparison circuit 1760 sets comparison signal CPSG to the H level when the value of the time stamp (“210”) added to TS packet T40A matches the value of comparison counter CPCT. As a result, the switch control unit 1730 receives the H level comparison signal CPSG, and sets the control signal SWSG to the H level, thereby setting the buffer 1710 to the packet transmission state. Therefore, the buffer 1710 starts a process of transmitting TS packets after the TS packet T40A (TS packet T50A,...) To the detection unit 1720.

  When the switch control unit 1730 receives the H level comparison signal CPSG, the value of the system clock counter SYCT at the time when the control signal SWSG is set to the H level is changed from the initial value “210” to, for example, “310”. Suppose that it is increasing. The value of the system clock counter SYCT is changed by incrementing the value of the system clock counter SYCT by “1” every time the STC counter 1771 receives the system clock SCK.

  Then, the comparison circuit 1772 compares the PCR value (“320”) included in the TS packet T40A stored in the buffer 1740 with the value of the system clock counter SYCT (“310”) received from the STC counter 1771. The comparison process is performed. Then, the comparison circuit 1772 subtracts the value of the system clock counter SYCT (“310”) from the value of PCR (“320”), thereby obtaining the difference value between the PCR value and the value of the system clock counter SYCT. calculate. In this case, the calculated difference value is “10”. Then, the comparison circuit 1772 transmits the calculated difference value “10” to the latch circuit 1773.

  Further, since the comparison signal CPSG is set to the H level by the processing of the comparison circuit 1760 described above, the latch circuit 1773 stores the received difference value “10”.

  The latch circuit 1773 transmits the stored difference value “10” to the DAC 1774. Here, when the difference value is “10”, the DAC 1774 generates an analog signal of 1.1V. Then, the DAC 1774 transmits the generated 1.1 V analog signal to the LPF 1775.

  The 1.1V analog signal is transmitted to the VCO 1776 via the LPF 1775 described above.

  The VCO 1776 that has received the 1.1V analog signal generates a system clock SCK having a frequency of 27.1 MHz, for example. The VCO 1776 transmits the generated system clock SCK to the decoding unit 1800 and the STC counter 1771. That is, the frequency of the system clock SCK is adjusted (changed) from 27 MHz to 27.1 MHz at approximately time t10, which is the timing at which the frequency of the system clock SCK should be adjusted.

  As a result, the decoding unit 1800 operates at the frequency (27.1 MHz) of the received system clock SCK. Then, the decoding unit 1800 operating with the system clock SCK of 27.1 MHz can normally decode the received TS packet. The STC counter 1771 increments the value of the system clock counter SYCT by “1” every time it receives the system clock SCK.

Thereafter, the processing described above is repeated in the same manner.
FIG. 4 is a diagram showing a flowchart of clock adjustment processing and count processing performed in the clock circuit 1700A.

The count processing is processing performed by the STC counter 1771.
In step S210, when the STC counter 1771 receives the system clock SCK from the VCO 1776, the value of the system clock counter SYCT is incremented by “1”. Thereafter, the process of step S210 is repeated again. That is, the STC counter 1771 increments the value of the system clock counter SYCT by “1” every time the system clock SCK is received from the VCO 1776.

In the clock adjustment process, first, the process of step S110 is performed.
In step S110, when the buffer 1710 is in a packet transmission state, the detection unit 1720 receives a TS packet. Here, it is assumed that the TS packet received by the detection unit 1720 is one TS packet among a plurality of continuous TS packets to which a time stamp is added. As an example, it is assumed that the TS packet received by the detection unit 1720 is the TS packet T40A in FIG. Then, it progresses to step S111.

  In step S111, the detection unit 1720 determines whether a PCR inclusion TS packet has been detected. That is, the detection unit 1720 determines whether or not the received TS packet is a PCR inclusion TS packet. If YES in step S111, the process proceeds to step S112. On the other hand, if NO at step S111, the process at step S110 is performed again. In this case, in step S110, a packet next to the received packet is received. Here, assuming that the TS packet T40A as the PCR inclusion TS packet is received, the process proceeds to step S112.

  In step S112, the detection unit 1720 stores the received PCR inclusion TS packet in the buffer 1740. Thereafter, the process proceeds to step S113.

  In step S113, a comparison process is performed. In the comparison processing, the comparison circuit 1772 performs comparison processing for comparing the value of the PCR included in the TS packet stored in the buffer 1740 with the value of the system clock counter SYCT received from the STC counter 1771. Then, the comparison circuit 1772 calculates a difference value between the value of the PCR and the value of the system clock counter SYCT by subtracting the value of the system clock counter SYCT from the value of PCR. Then, the comparison circuit 1772 transmits the calculated difference value to the latch circuit 1773. Thereafter, the process proceeds to step S114.

  In step S114, it is determined whether a predetermined condition is satisfied. Here, the predetermined condition is a condition that the value of the PCR compared with the value of the system clock counter SYCT compared in the comparison process in step S113 does not match. That is, the predetermined condition is a condition that the difference value between the value of the PCR and the value of the system clock counter SYCT is not “0”. If YES in step S114, the process proceeds to step S115. On the other hand, if NO at step S114, the process at step S110 is performed again. Here, assuming that the difference value is not “0”, the process proceeds to step S115.

  In step S115, comparison circuit 1760 determines whether or not the current time is a time for changing the frequency of system clock counter SYCT. Specifically, the comparison circuit 1760 compares the time stamp value added to the PCR inclusion TS packet stored in the buffer 1740 with the value of the comparison counter CPCT, and compares the time stamp value with the comparison counter CPCT. It is determined whether or not the value matches. If YES in step S115, the process proceeds to step S116. On the other hand, if NO at step S115, the process at step S115 is performed again.

  Note that it is assumed that the latch circuit 1773, the DAC 1774, and the LPF 1775 are performing the above-described process based on the difference value before the process of step S116 is performed.

  In step S116, the VCO 1776 adjusts (changes) the frequency of the generated system clock SCK by the latch circuit 1773, the DAC 1774, and the LPF 1775 based on the difference value subjected to the above-described processing. Thereafter, the process of step S110 is performed again.

  As described above, in the present embodiment, when a plurality of TS packets to which time stamps as time information are added are continuously received, a PCR-containing TS packet including a PCR is detected. Then, the timing at which the frequency of the system clock SCK should be adjusted by controlling the timing at which the frequency of the system clock SCK is adjusted (changed) using the value of the PCR included in the detected PCR inclusion TS packet. Thus, the frequency of the system clock SCK is adjusted (changed).

  Therefore, even when a plurality of TS packets to which time information is added are continuously received, the frequency of the system clock SCK can be adjusted (changed) at an accurate timing. That is, there is an effect that the system clock SCK can be generated accurately.

  In addition, since the decoding unit 1800 operates based on the system clock SCK generated correctly, there is an effect that the received TS packet can be accurately decoded.

  That is, the decoding circuit 1600A in the present embodiment has an effect that the TS packet can be accurately decoded even when a plurality of TS packets to which time information is added are continuously received.

  That is, in this embodiment, video processing apparatus 1000 including decoding circuit 1600A can accurately decode TS packets even when a plurality of TS packets to which time information is added are continuously received. Play.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows an example of the internal structure of the video processing apparatus in this Embodiment. It is a block diagram which shows an example of the internal structure of the clock circuit in this Embodiment. It is an operation waveform diagram as an example for explaining the operation of the clock circuit. It is a figure which shows the flowchart of the clock adjustment process performed in a clock circuit, and a count process. It is a figure for demonstrating a transport stream. It is a block diagram which shows an example of the internal structure of the conventional video processing apparatus. It is a figure for demonstrating a transport stream. It is a figure which shows the transport packet to which the time stamp was added.

Explanation of symbols

  1000 video processing device, 1200 communication unit, 1400 control unit, 1500 storage unit, 1600A decoding circuit, 1700A clock circuit, 1710 buffer, 1720 detection unit, 1730 switch control unit, 1740 buffer, 1750 counter, 1752 clock generation circuit, 1760 comparison Circuit, 1771 STC counter, 1772 comparison circuit, 1773 latch circuit, 1774 DAC, 1775 LPF, 1776 VCO, 1800 decoding unit.

Claims (5)

Clock generation means for generating a clock;
Counter means for changing the value of the counter based on the clock generated by the clock generation means;
Receiving means for continuously receiving a plurality of transport packets to which time information is added;
Detecting means for detecting a transport packet including a clock adjustment value for adjusting a clock frequency among the plurality of received transport packets;
Comparison means for performing comparison processing for comparing the clock adjustment value included in the transport packet detected by the detection means and the value of the counter changed by the counter means;
Timing control means for controlling the timing at which the clock generation means uses the result of the comparison process;
A clock circuit configured to adjust a frequency of a clock to be generated using a result of the comparison process at a timing controlled by the timing control unit;   The clock circuit according to claim 1, wherein a result of the comparison processing is a difference between the clock adjustment value and a value of the counter. The timing control means includes
Comparison counter means for changing a value of a comparison counter for controlling the timing at which the clock generation means uses the result of the comparison processing, every predetermined time;
The clock generation means compares the value indicated by the time information added to the transport packet detected by the detection means with the value of the comparison counter changed by the comparison counter means, so that the clock generation means The clock circuit according to claim 1, further comprising a comparison timing control unit that controls a timing of using the clock. A clock circuit according to any one of claims 1 to 3;
A video processing apparatus comprising: decoding means for successively decoding a plurality of transport packets to which time information is added based on a clock generated by the clock circuit. A clock adjustment method performed by a clock circuit provided with a clock generation unit for generating a clock,
The clock adjustment method includes:
A counter step of changing the value of the counter based on the clock generated by the clock generation unit;
A reception step of continuously receiving a plurality of transport packets to which time information is added;
A detection step of detecting a transport packet including a clock adjustment value for adjusting a clock frequency among the plurality of received transport packets;
A comparison step for performing a comparison process for comparing the clock adjustment value included in the transport packet detected by the detection step with the value of the counter changed by the counter step;
A timing control step for controlling the timing at which the clock generation unit uses the result of the comparison process;
A clock adjustment method comprising: an adjustment step of adjusting a frequency of a clock generated by the clock generation unit using a result of the comparison process at a timing controlled by the timing control step.

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