JP2008028274A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for easily determining a leak current that is caused by a crack formed on an insulating film underneath electrode pads. <P>SOLUTION: A probe is put simultaneously to a signal electrode pad 2, and an inspection electrode pad 3 which is an isolated pattern formed on a corner of a semiconductor chip, to measure a leak current between the inspection electrode pad 3 and a circle-around power interconnect 7 that runs underneath a plurality of signal electrode pads 2 and the inspection electrode 3 via insulating films 4 and 6. If a leak current larger than a rating current is measured between the inspection electrode pad 3 and the circle-around power interconnect 7, a leak current is measured between the inspection electrode pad 3 and the signal electrode pad 2 (2A) adjacent thereto. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to a method for detecting a leakage defect caused by a crack generated in an insulating film directly under an electrode pad.

  In a semiconductor device including a wiring layer passing directly under all electrode pads through an insulating film, and at least one of the electrode pads is electrically connected to the wiring layer, the first electrode pad and the wiring connected to the wiring layer Japanese Unexamined Patent Application Publication No. 2005-251829 (Patent Document 1) discloses a semiconductor device inspection method for measuring a leakage current between second electrode pads not connected to a layer.

  In addition, one or more electrode pads for inspection, inspection electrode pads, and wirings electrically connected to the inspection electrode pads provided in the wiring layer region immediately below all the electrode pads for inspection In preparation for the scribe region, a probe is brought into contact with the electrode pad for inspection and the electrode pad for inspection, and the destruction of the electrode pad under inspection due to the contact is detected by conduction between the electrode pad for inspection and the electrode pad for inspection through the wiring. A method is disclosed in Japanese Patent Application Laid-Open No. 2006-5180.

  In addition, the first region where pressurization during probe inspection with the probe needle is permitted has a dual-purpose pad used for both probe inspection and assembly, and the second region where pressurization during probe inspection with the probe needle is prohibited Japanese Unexamined Patent Application Publication No. 2005-303279 (Patent Document 3) discloses a semiconductor device having an assembly pad that is not used for probe inspection in a region.

Further, in the state where the bonding wire is connected to the pad, the presence or absence of a crack under the pad of the semiconductor chip is detected by detecting the electrical conduction state between the heater block on which the semiconductor chip is placed and the bonding wire. A method is disclosed in Japanese Patent Application Laid-Open No. 2000-1000085 (Patent Document 4).
JP 2005-251829 A (paragraph [0005], FIG. 1) JP 2006-5180 (paragraphs [0026] to [0027], FIG. Japanese Patent Laying-Open No. 2005-303279 (paragraph [0024], FIG. 1) Japanese Unexamined Patent Publication No. 2000-1000085 (paragraph [0014], FIG. 1)

  In recent years, with the demand for increasing the number of pins or reducing the area of a semiconductor chip, a method of arranging electrode pads on a wiring layer or an active element has been adopted. However, there are various technical problems described below with respect to the method of arranging such electrode pads.

  For example, in the probe inspection process, when a single mechanism is used to apply probes (probes) to a plurality of electrode pads on a semiconductor chip, the needle pressure is increased to ensure the minimum needle pressure for all probes. Must be set to In general, there are a plurality of test items (for example, a memory test, a high temperature test, a low temperature test, etc.) in the probe inspection, and the measurement devices are different from each other. Furthermore, stress may be applied to the electrode pad even in an assembly process in which bump electrodes are formed or wire bonding is performed.

  As described above, in the probe inspection process, the assembly process, and the like, when stress is applied to the electrode pad, the stress is applied to the insulating film immediately below the electrode pad, and cracks may occur in the electrode pad and the insulating film. If a potential difference is generated between the electrode pad and the wiring layer or the active element in a state where the crack is generated, a leak current flows through the crack, so that the semiconductor device does not exhibit normal operation. However, it is difficult to determine whether or not there is a leakage current due to a crack generated in the insulating film immediately below the electrode pad, and a new method that can detect the leakage current from the probe inspection process to the assembly process is desired. ing.

  An object of the present invention is to provide a technique that can easily determine a leakage current caused by a crack generated in an insulating film immediately below an electrode pad.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a method of manufacturing a semiconductor device including an inspection process for detecting a leakage failure caused by a crack generated in an insulating film directly under an electrode pad for a signal electrically connected to an internal circuit. A probe is simultaneously applied to the electrode pad and the inspection electrode pad which is an isolated pattern formed in the corner portion of the semiconductor chip, and an insulating film is formed immediately below the inspection electrode pad, the plurality of signal electrode pads and the inspection electrode pad. Measure the leakage current between the power supply circuit wiring and the inspection electrode pad and the power supply circuit wiring. The leakage current between the signal electrode pads is measured.

  The present invention is a method of manufacturing a semiconductor device including an inspection process for detecting a leakage defect caused by a crack generated in an insulating film immediately below an electrode pad for a signal electrically connected to an internal circuit. A plurality of signal electrode pads formed on the semiconductor chip, and an inspection electrode pad which is an isolated pattern formed at a corner portion of the semiconductor chip, and formed on the mounting substrate. A plurality of electrodes are connected to each other, a semiconductor chip is sealed with a resin and assembled into a package product, and then the first electrode on the mounting substrate connected to the inspection electrode pad, the plurality of signal electrode pads, and the inspection The leakage current between the first electrode and the second electrode is measured between the second electrode on the mounting substrate connected to the power supply circuit wiring that passes through the insulating film directly under the electrode pad for use. Rule Or if the leakage current is measured in is to measure the leakage current between the first electrode and a predetermined third electrode connected mounted on the substrate signal electrode pads.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It is possible to easily detect a leakage current caused by a crack generated in an insulating film immediately below the electrode pad from the probe inspection process to the assembly process.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable, unless otherwise specified and clearly considered essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings. In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer, but not only to this, but also to form an SOI (Silicon On Insulator) wafer and an integrated circuit thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A semiconductor device having an inspection electrode pad according to an embodiment of the present invention will be described with reference to FIGS. 1, FIG. 2, and FIG. 3 are top views of a semiconductor device showing a first example, a second example, and a third example of the arrangement of a plurality of signal electrode pads and test electrode pads, respectively. FIG. FIG. 5 is a schematic cross-sectional view of the main part taken along the line BB ′ of FIG. 4.

  As shown in FIG. 1, on the upper surface of the semiconductor device 1, for example, a plurality of signal electrode pads (open squares) 2 are arranged at predetermined intervals along the outer periphery thereof. The signal electrode pad 2 is electrically connected to the internal circuit of the semiconductor device 1 via a wiring layer, and supplies power or a signal from the outside of the semiconductor device 1 to the internal circuit of the semiconductor device 1 or the semiconductor device. 1 is an external connection electrode provided for taking out an electrical signal of one internal circuit to the outside of the semiconductor device 1.

  Further, a plurality of inspection electrode pads (black-filled squares) 3 are arranged at the corner portion of the semiconductor device 1. The inspection electrode pad 3 is an isolated pattern that is not connected to the internal circuit of the semiconductor device 1 and the signal electrode pad 2. In this embodiment, the inspection electrode pads 3 are arranged at both ends of a plurality of signal electrode pads 2 arranged in a row (for example, in FIG. 1, the number of vertical rows is 15 and the number of horizontal rows is 14). Each of the four corners has two inspection electrode pads 3. The signal electrode pad 2 and the inspection electrode pad 3 are made of, for example, a metal material such as aluminum, and the dimensions thereof are, for example, 55 μm × 70 μm. Further, a ring-shaped power circuit wiring 7 described later is formed directly below the signal electrode pad 2 and the inspection electrode pad 3 via an insulating film.

  Note that the number and arrangement of the inspection electrode pads 3 are not limited to this. For example, as shown in FIG. 2, one inspection electrode pad 3 may be provided in each of four corner portions. As shown in FIG. 3, one inspection electrode pad 3 may be provided only in two corner portions.

  As shown in FIGS. 4 and 5, a buffer layer 5 is provided directly below the signal electrode pad 2 and the inspection electrode pad 3 via an insulating film 4. The buffer layer 5 has a function to disperse the stress generated when the probe is applied to the signal electrode pad 2 and prevent the insulating film 6 and the wiring layer of the internal circuit from being cracked. Yes. The buffer layer 5 is made of a metal material such as copper or aluminum. The size of the buffer layer 5 is not particularly limited, but is set to be the same as the size of the signal electrode pad 2 or smaller than the size of the signal electrode pad 2. The buffer layer 5 is an isolated pattern that is not connected to the internal circuit of the semiconductor device 1, the signal electrode pad 2, the inspection electrode pad 3, or the like.

  Further, immediately below the buffer layer 5, a power supply wiring 7 having a ring shape in plan view is provided via an insulating film 6. The power circuit wiring 7 is electrically connected to at least one of the signal electrode pads 2 through, for example, a plug formed in the insulating films 4 and 6. The power circuit wiring 7 is made of a metal material such as copper or aluminum. In FIG. 5, reference numerals 8a and 8b denote a wiring layer and a semiconductor element constituting the internal circuit, respectively.

  Next, a method for detecting a leakage failure caused by a crack generated in an insulating film immediately below an electrode pad according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5, and FIGS. 6 and 7. FIG. 6 is a process diagram of a procedure for detecting a leakage failure caused by a crack generated in an insulating film immediately below the electrode pad, and FIG. 7 is an arrangement of pins provided on the back surface of a surface mount package (BGA (Ball Grid Array)). It is a top view which shows an example.

  First, an integrated circuit is formed on the main surface of a semiconductor wafer. An integrated circuit is formed in units of semiconductor chips in a manufacturing process called a preprocess or a diffusion process.

  Next, a characteristic test of the integrated circuit is performed for each semiconductor chip to determine whether each semiconductor chip is good or defective. The integrated circuit characteristic test is, for example, a memory test, a high temperature test, a low temperature test, or the like, and is performed on a plurality of test items. In the present embodiment, as shown in FIG. 6, three characteristic tests are performed: a first probe test (step S1), a second probe test (step S2), and a third probe test (step S3). The case is illustrated. Further, different measurement devices are used in each characteristic test, but a probe card in which probes are arranged in accordance with all electrode pads is used. The dimension of the tip of the probe is, for example, 8 μm × 8 μm.

  In the first probe test (step S1), the probe is brought into contact with the signal electrode pad 2 used for measurement and the inspection electrode pad 3 disposed at the corner of the semiconductor chip. Then, the probe pressure is gradually applied up to the pressure at the time of measurement.

  Probe stress may be excessively applied to the signal electrode pad 2 due to factors such as probe pressure variation, probe card pressure variation, and probe pressure misconfiguration. When an excessive stress is applied from the probe to the signal electrode pad 2 in the depth direction of the semiconductor chip, the stress is applied to the insulating film 4 immediately below the signal electrode pad 2 through the signal electrode pad 2. Cracks may occur in the insulating film 4 immediately below the signal electrode pad 2, the buffer layer 5 disposed to disperse the stress, and the insulating film 6 immediately below the buffer layer 5. If a potential difference occurs between the signal electrode pad 2 and the wiring layer or semiconductor element constituting the integrated circuit in a state where the crack is generated, a leakage current flows between the two through the crack, so that the semiconductor device operates normally. Disappear. Depending on the type of probe card, such excessive probe stress tends to increase at the corner of the semiconductor chip, and is placed at the corner of the semiconductor chip before cracking occurs directly under the signal electrode pad 2. Cracks are likely to occur immediately below the inspection electrode pad 3. When the stress becomes strong at the corner of the chip, the inspection electrode pad 3 is an isolated pattern and can be treated as a good product without any problem even if cracks occur, and thus has an effect of reducing the defect rate.

  Therefore, the probe failure is detected by measuring the leakage current between the inspection electrode pad 3 arranged at the corner portion of the semiconductor chip and the power supply wiring 7 (first leakage current measurement). In the case where a leak current exceeding the standard is not measured between the inspection electrode pad 3 and the power supply circuit wiring 7 (OK display), it is assumed that conduction is not recognized between the test electrode pad 3 and the power supply circuit wiring 7. A first characteristic test is performed.

  However, when a leak current exceeding the standard is measured between the inspection electrode pad 3 and the power supply circuit wiring 7 (NG display), conduction is recognized between the test electrode pad 3 and the power supply circuit wiring 7. Next, the leakage current between the inspection electrode pad 3 and the signal electrode pad 2 (2A) adjacent thereto is measured (second leakage current measurement).

  If a leak current exceeding the standard is not measured between the inspection electrode pad 3 and the signal electrode pad 2 (2A), there is a problem with the probe, but there is a crack directly under the signal electrode pad 2 (2A). It is estimated that the semiconductor chip is not generated, and the semiconductor chip is determined to be good. In some cases, leakage current between the test electrode pad 3 and the signal electrode pad 2 (2B) adjacent to the signal electrode pad 2 (2A), the test electrode pad 3 and the signal electrode pad 2 (2B) The leakage current between the inspection electrode pad 3 and the plurality of signal electrode pads 2 is measured one after another, such as the leakage current between the signal electrode pad 2 (2C) adjacent to (2). When a leak current exceeding the standard is not measured between the inspection electrode pad 3 and all the signal electrode pads 2, there is a problem with the probe, but no crack is generated immediately below the signal electrode pad 2. It is estimated that the semiconductor chip is good. Note that it is not always necessary to measure the leakage current between the test electrode pad 3 and all the signal electrode pads 2, and between the test electrode pad 3 and a predetermined signal electrode pad 2 determined in advance. The leakage current may be measured. Thereafter, the conditions of the first probe test (step S1) are reviewed, and the defect of the probe is corrected.

  When a leak current exceeding the standard is measured between the inspection electrode pad 3 and the signal electrode pad 2 (2A), the signal electrode pad 2 (2A) may be caused by a defect in the probe or a manufacturing method in the previous process. ) Is estimated to have cracks, and the semiconductor chip is determined to be defective. In some cases, leakage current between the test electrode pad 3 and the signal electrode pad 2 (2B) adjacent to the signal electrode pad 2 (2A), the test electrode pad 3 and the signal electrode pad 2 (2B) The leakage current between the inspection electrode pad 3 and the plurality of signal electrode pads 2 is measured one after another, such as the leakage current between the signal electrode pad 2 (2C) adjacent to (2). If a leakage current exceeding the standard is measured between the inspection electrode pad 3 and some or all of the signal electrode pads 2, the signal electrode pad 2 may be damaged due to a defect in the probe or a manufacturing method in the previous process. It is estimated that a crack has occurred directly below, and the semiconductor chip is determined to be defective. Thereafter, the conditions of the first probe test (step S1) or the manufacturing process of the previous step are reviewed.

  Next, in the same manner as the first probe test (step S1), the second probe test (step S2) and the semiconductor chip determined to be good in the first probe test (step S1) A third probe test (step S3) is performed. The semiconductor wafer that has obtained a predetermined yield in the probe inspection (steps S1, S2, and S3) of the first, second, and third probe tests is sent to a manufacturing process called a post-process.

  Here, first, the back surface of the semiconductor wafer is ground so that the semiconductor wafer has a predetermined thickness, and then the semiconductor wafer is diced to separate the semiconductor wafer into semiconductor chips. Subsequently, the semiconductor chip finally determined to be good by the first, second and third probe tests (steps S1, S2 and S3) is picked up, and the semiconductor chip is mounted on the mounting substrate.

  Next, the plurality of signal electrode pads 2 and the inspection electrode pad 3 formed on the semiconductor chip are connected to the plurality of electrodes formed on the mounting substrate using wires or bump electrodes, respectively. At this time, the inspection electrode pad 3 is connected to an electrode on the mounting board connected to a pin not normally used such as an index pin, a corner pin, or a non-connecting pin of the mounting board. For example, the surface mount package 9 shown in FIG. 7 can be connected to the non-connect pin 10. The signal electrode pad 2 is connected to an electrode on the mounting substrate connected to the pin 11.

  Next, by encapsulating the semiconductor chip with a mold resin, the semiconductor chip is assembled into a package product, and then a product name or the like is imprinted on the mold resin, so that each semiconductor product is separated from the mounting substrate. After that, the finished semiconductor product is selected according to the product standard, and the semiconductor product is completed through an inspection process.

  Also in this inspection process, the fourth probe test (step S4) is performed in the same manner as the first probe test (step S1) described above, thereby detecting cracks that occur immediately below the signal electrode pad 2 during assembly. can do. In other words, by measuring the leakage current between the first electrode on the mounting substrate connected to the inspection electrode pad 3 and the second electrode on the mounting substrate connected to the power circuit wiring 7, Is detected (first leakage current measurement). When a leak current exceeding the standard is not measured between the first electrode and the second electrode (OK display), the final characteristic test is performed as it is. However, when a leak current exceeding the standard is measured between the first electrode and the second electrode (NG display), the third electrode connected to the first electrode and the predetermined signal electrode pad 3 is used. The leakage current between the electrodes is measured (second leakage current measurement). When the leak current exceeding the standard is not measured between the first electrode and the third electrode, the semiconductor product is determined to be good and the final characteristic test is performed, but the leak current exceeding the standard is measured. The semiconductor product is determined to be defective, and the manufacturing process of the assembly process is reviewed.

  In this embodiment, the buffer layer 5 is provided directly below the signal electrode pad 2 and the inspection electrode pad 3 via the insulating film 4. However, without providing the buffer layer 5, the signal electrode pad 2 and A power supply surrounding wiring 7 may be provided directly below the inspection electrode pad 3 through only the insulating film 4.

  In the present embodiment, the planar shape of the power circuit wiring 7 is a ring shape. However, the plurality of signal electrode pads 2 and the signal electrode pads 2 directly below the plurality of signal electrode pads 2 that require measurement of leakage current are used. The power supply wiring 7 may be provided immediately below the inspection electrode pad 3 arranged at the corner of the semiconductor chip at the end of the semiconductor chip. For example, a ring shape with a part cut off, a straight line along one side of the semiconductor chip, etc. There may be.

  As described above, according to the present embodiment, it is possible to easily detect a leakage current caused by a crack generated in the insulating films 4 and 6 immediately below the signal electrode pad 2 from the probe inspection process to the assembly process.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a method for manufacturing a semiconductor device in which an electrode pad is disposed above a wiring layer or a semiconductor element.

1 is a top view of a semiconductor device showing a first example of an arrangement of signal electrode pads and inspection power supply pads according to an embodiment of the present invention; It is a top view of the semiconductor device which shows the 2nd example of arrangement | positioning of the signal electrode pad and test | inspection power supply pad by one embodiment of this invention. It is a top view of the semiconductor device which shows the 3rd example of arrangement | positioning of the electrode pad for signals and the power pad for a test | inspection by one embodiment of this invention. FIG. 2 is a top view of a semiconductor device in which an area A in FIG. 1 is enlarged. It is a schematic diagram of the principal part cross section in the BB 'line | wire of FIG. It is process drawing which shows the detection procedure of the leakage current resulting from the crack which arose in the insulating film directly under the electrode pad by one embodiment of this invention. It is a top view which shows the pin arrangement | positioning provided in the back surface of the surface mount type package by one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2,2A, 2B, 2C Signal electrode pad 3 Inspection electrode pad 4 Insulating film 5 Buffer layer 6 Insulating film 7 Power supply surrounding wiring 8a Wiring layer 8b Semiconductor element 9 Surface mount package 10 Non-connect pin 11 Pin

Claims (6)

A manufacturing method of a semiconductor device including an inspection process for detecting a leakage defect caused by a crack generated in an insulating film immediately below an electrode pad for a signal electrically connected to an internal circuit,
(A) a step of simultaneously applying a probe to each of a plurality of signal electrode pads and an inspection electrode pad formed in a corner portion of a semiconductor chip;
(B) measuring a leakage current between the inspection electrode pad and a plurality of signal electrode pads and a power supply wiring that passes directly under the inspection electrode pad through the insulating film; ,
The method of manufacturing a semiconductor device, wherein the inspection electrode pad is an isolated pattern that is not electrically connected to the internal circuit, the plurality of signal electrode pads, and the power circuit wiring. A manufacturing method of a semiconductor device including an inspection process for detecting a leakage defect caused by a crack generated in an insulating film immediately below an electrode pad for a signal electrically connected to an internal circuit,
(A) a step of simultaneously applying a probe to each of a plurality of signal electrode pads and an inspection electrode pad formed in a corner portion of a semiconductor chip;
(B) a step of measuring a leakage current between the inspection electrode pad and a plurality of signal electrode pads and a power supply wiring that passes directly under the inspection electrode pad through the insulating film;
(C) In the step (b), when a leak current exceeding a standard is measured between the inspection electrode pad and the power supply circuit wiring, the inspection electrode pad and the inspection electrode pad are adjacent to each other. Measuring a leakage current between the signal electrode pads,
The method of manufacturing a semiconductor device, wherein the inspection electrode pad is an isolated pattern that is not electrically connected to the internal circuit, the plurality of signal electrode pads, and the power circuit wiring. A manufacturing method of a semiconductor device including an inspection process for detecting a leakage defect caused by a crack generated in an insulating film immediately below an electrode pad for a signal electrically connected to an internal circuit,
(A) A semiconductor chip separated is mounted on a mounting substrate, a plurality of signal electrode pads formed on the semiconductor chip, an inspection electrode pad formed on a corner portion of the semiconductor chip, and the mounting Connecting each of a plurality of electrodes formed on the substrate;
(B) a step of resin-sealing the semiconductor chip and assembling it into a package product;
(C) a first electrode on the mounting substrate connected to the inspection electrode pad, and a power supply wiring that passes directly below the plurality of signal electrode pads and the inspection electrode pad via the insulating film Measuring a leakage current between the connected second electrodes on the mounting substrate,
The method of manufacturing a semiconductor device, wherein the inspection electrode pad is an isolated pattern that is not electrically connected to the internal circuit, the plurality of signal electrode pads, and the power circuit wiring. A manufacturing method of a semiconductor device including an inspection process for detecting a leakage defect caused by a crack generated in an insulating film immediately below an electrode pad for a signal electrically connected to an internal circuit,
(A) A semiconductor chip separated is mounted on a mounting substrate, a plurality of signal electrode pads formed on the semiconductor chip, an inspection electrode pad formed on a corner portion of the semiconductor chip, and the mounting Connecting each of a plurality of electrodes formed on the substrate;
(B) a step of resin-sealing the semiconductor chip and assembling it into a package product;
(C) a first electrode on the mounting substrate connected to the inspection electrode pad, and a power supply wiring that passes directly below the plurality of signal electrode pads and the inspection electrode pad via the insulating film Measuring a leakage current between the connected second electrodes on the mounting substrate;
(D) In the step (c), when a leak current exceeding the standard is measured between the first electrode and the second electrode, the first electrode and a predetermined signal electrode pad Measuring a leakage current between the connected third electrodes on the mounting substrate,
The method of manufacturing a semiconductor device, wherein the inspection electrode pad is an isolated pattern that is not electrically connected to the internal circuit, the plurality of signal electrode pads, and the power circuit wiring.   5. The semiconductor device manufacturing method according to claim 1, wherein an isolated buffer layer is formed between the plurality of signal electrode pads, the inspection electrode pad, and the power supply wiring. A method for manufacturing a semiconductor device, wherein:   5. The method of manufacturing a semiconductor device according to claim 1, wherein a planar shape of the power supply circuit wiring is a ring shape. 6.