JP2008010049A - Information reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a PLL center frequency is changed to be within a capturable range, the value of the PLL center frequency is discretely changed because a control value is a digital value, and as a result, it takes time until the PLL is locked, and pulling time including frequency control is prolonged. <P>SOLUTION: In a response control circuit 10, a target value from an adder 9 is compared with a reference value output after response control, a value obtained by subtracting a predetermined value from the reference value after the response control is outputted when the target value is smaller than the reference value after the response control, a value obtained by adding a predetermined value to the reference value after the response control is outputted when the target value is larger than the reference value after the response control, and the reference value after the response control is outputted when the target value is equal to the reference value after the response control. This operation is repeated until a detected status indicating that a phase synchronous loop is locked is entered from a Sync detection circuit 6. Based on the reference value after the response control, the center frequency of a DPLL is continuously and gradually changed slowly. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information reproducing apparatus, and more particularly, optically digitally from an optical disk, which is a disk-shaped recording medium on which a digital information signal modulated by a modulation method in which a maximum value and a minimum value of an inversion interval are defined is recorded together with a synchronization signal. The present invention relates to an information reproducing apparatus for reproducing an information signal.

  In an information reproducing apparatus for optically reproducing a digital information signal recorded on an optical disk and modulated by a modulation method in which the maximum value and minimum value of the inversion interval are defined, the signal read from the optical disk is converted into a phase-locked loop (PLL). ; Phase Locked Loop) circuit, a clock synchronized with the read signal is extracted by the PLL circuit, and the rotation speed of the optical disk is controlled using the clock, and at the same time, reproduction data of the digital information signal is obtained. .

  The PLL circuit inputs the read signal as an input signal to the phase comparator and supplies the output oscillation frequency of the voltage controlled oscillator (VCO) to the loop filter directly or through a frequency divider having a predetermined frequency division ratio. Further, the output signal of the loop filter is input to the phase comparator, the phase difference from the read signal is detected by the phase comparator, and the phase error signal corresponding to the phase difference is supplied to the VCO as a voltage control signal. A feedback loop circuit that variably controls the output oscillation frequency of the VCO so that the phase difference becomes a predetermined value, and outputs the clock from the VCO.

  In this PLL circuit, when the frequency difference between the two signals to be phase-compared by the phase comparator is not within the frequency pull-in range (capture range), the VCO is not controlled by the phase comparator in a direction to reduce the phase difference. In addition, there is a characteristic that the unlocked state is maintained without being locked indefinitely, and the input signal from the outside (read signal in the above case) is centered on a predetermined frequency (clock frequency in the above case). When the frequency is within a predetermined frequency range (lock range), the phase lock state is maintained in which the output oscillation frequency of the VCO is variably controlled following the phase error of the input signal.

  On the other hand, in recent years, an increase in capacity has been increasingly demanded without changing the disk size of the optical disk, and accordingly, recording marks are recorded by high-density recording that further narrows the recording track pitch of the optical disk. The spatial frequency of the shortest mark length is close to the optical limit, and the read signal level of the recording mark with the shortest mark length is minimal. In this state, the lock range of the PLL circuit is narrowed, and the PLL circuit is weak against disturbance, and the capture range of the PLL circuit is also narrowed. In particular, the phenomenon that the capture range becomes narrow is fatal, and even if the frequency of the read signal from the optical disk approaches the frequency at which the PLL circuit should perform the original pull-in operation, it cannot be pulled in. For this reason, the optical disk reproduction system is not established.

  Therefore, it is conceivable to control the rotational speed of the spindle motor that rotates the optical disc and the center frequency of the PLL circuit to compensate for a narrow chapter challenge or lock range. At this time, one of the information used as information is a synchronization signal inserted during recording at a constant interval, and is a synchronization signal in a signal read from the optical disk (a constant pattern of 11T (T is the period of the channel clock; the same applies hereinafter)) In the prior art, an information reproducing apparatus that detects the maximum reversal interval of the above and controls the number of revolutions of the spindle motor has been disclosed (for example, see Patent Document 1). As described above, if the read signal level of the shortest recording mark does not become minimum, the information reproducing apparatus described in Patent Document 1 operates normally and the effect can be expected.

JP-A-8-138328

  However, in the above-described high-density optical disc, the read signal level at the minimum inversion interval is minimized, and erroneous detection beyond the maximum inversion interval is likely to occur. Therefore, the information reproducing apparatus described in Patent Document 1 cannot perform correct control. There is a problem. Therefore, it is conceivable to control the center frequency of the PLL circuit using the maximum inversion interval of the synchronization signal. However, when the PLL circuit is a digital PLL (DPLL), the value to be controlled becomes discrete, so that a phenomenon that the DPLL cannot capture occurs.

  In other words, considering the case where the center frequency of the DPLL (hereinafter referred to as the PLL center frequency) is controlled based on the maximum inversion interval of the synchronization signal by a signal supplied to the timing adjuster inside the DPLL, the result of counting the interval of the synchronization signal However, it can be obtained only at the interval of the synchronization signal. This is illustrated in FIG. FIG. 8A shows a diagram in which the horizontal axis represents time and the vertical axis represents the PLL center frequency. As shown in FIG. 5A, the DPLL control value is changed from the initial value so that the PLL center frequency is within the captureable range I. However, since the control value is a digital value, The value changes discretely. As a result, as shown in FIG. 8B, it takes time from the initial state to the lock determination indicating that the PLL center frequency is within the captureable range I, and during that time, the DPLL cannot be pulled in. For this reason, the pull-in time including the frequency control becomes longer, and the system is adversely affected.

  The present invention has been made in view of the above points, and when controlling the PLL center frequency, it is not possible to discretely change the information, but by gradually changing the information, information can be reproduced quickly. An object is to provide an apparatus.

  In order to achieve the above object, the present invention provides a digital information signal generated based on a modulation method in which the maximum value and minimum value of the inversion interval are defined, and digital information inserted into the digital information signal at regular intervals. An information reproducing apparatus for reproducing a recording medium on which a synchronization signal having a special pattern in which an inversion interval is set larger than a maximum inversion interval of a signal is recorded, a reading unit for reading a recording signal of the recording medium, and a reading unit Measuring means for sequentially measuring the inversion interval of the read signal from the predetermined period, and estimating the maximum value among the inversion intervals obtained by measuring by the measuring means as the synchronization signal, and based on the estimated position information of the synchronization signal Interval detection means for detecting the appearance interval of the synchronization signal, a read signal is inputted, a clock synchronized with the phase of the read signal is generated, and a desired bit rate is generated A phase-locked loop circuit that generates digital data sampled with a bit clock, a decoding means that decodes the digital data, and a reference that determines the center frequency of the phase-locked loop circuit based on the appearance interval of the synchronizing signal detected by the interval detecting means An addition means for calculating a target value by adding to the reference value as a correction amount for the value, and a post-response control reference value that changes continuously and gently following the target value, and the reference after the response control Response control means for controlling the center frequency of the phase-locked loop circuit according to the value.

  In the present invention, the center frequency of the phase locked loop circuit is controlled by the reference value after response control that changes continuously and gently following the target value. Can be changed gradually and continuously rather than discretely.

  In order to achieve the above object, the present invention provides a digital information signal generated based on a modulation method in which the maximum value and minimum value of the inversion interval are defined, and a digital information signal inserted into the digital information signal at a constant period. An information reproducing apparatus for reproducing a recording medium on which a synchronization signal having a special pattern in which an inversion interval is set larger than a maximum inversion interval of an information signal is recorded, and a reading unit that reads the recording signal of the recording medium, Measuring means for sequentially measuring the inversion interval of the read signal from the means for a predetermined period, and estimating the maximum value among the inversion intervals obtained by measuring by the measuring means as the synchronization signal, and based on the estimated position information of the synchronization signal An interval detection means for detecting the appearance interval of the synchronization signal, an A / D conversion means for converting the read signal into a digital signal by the system clock, and an A / D conversion means. ATC / AGC means for performing automatic gain control for making the amplitude constant for the input digital signal or read signal, and automatic threshold control for appropriately direct current controlling the threshold of the binary comparison, and A / D conversion A digital phase-locked loop circuit for generating digital data resampled with a bit clock of a desired bit rate for the digital signals processed by each of the means and the ATC / AGC means, and a decoding means for decoding the digital data, Addition means for calculating the target value by adding the appearance interval of the synchronization signal detected by the interval detection means to the reference value as a correction amount for the reference value that determines the center frequency of the digital phase locked loop circuit, and following the target value Then, a reference value after response control that changes continuously and gently is generated, and the reference value after response control is generated. And having a response control means for controlling the center frequency of the digital phase locked loop circuit.

  In order to achieve the above object, the present invention further includes detection means for detecting that the phase locked loop circuit is in a locked state based on the decoded data of the decoding means, and the response control means includes a target value. Is compared with the reference value after response control, and when the target value is smaller than the reference value after response control, a value obtained by subtracting a predetermined value from the reference value after response control is output. When the value is greater than the reference value after control, a value obtained by adding a predetermined value to the reference value after response control is output. When the target value is the same as the reference value after response control, a reference value after response control is output. The operation of temporarily calculating and outputting the reference value after response control after the output value of the calculation means and the comparison calculation means is repeated until the detection status indicating that the phase locked loop circuit is locked is input from the detection means. Characterized by comprising holding means To.

  According to the present invention, the center frequency of the phase-locked loop circuit is controlled by the reference value after response control that changes continuously and gently following the target value. Since it is not changed discretely but gradually changed continuously, the center frequency of the phase-locked loop circuit can be reliably pulled into the captureable range in a short time.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of an information reproducing apparatus according to the present invention. In the optical disk to be reproduced in the present embodiment, a special pattern synchronization signal is added to a digital information signal (for example, a run length limit code) generated based on a modulation method in which the maximum value and minimum value of the inversion interval are defined. A signal inserted at a constant period is recorded at high density as a pit string in which recording marks having a plurality of types of mark lengths are appropriately combined with spaces. However, the inversion interval of the synchronization signal is the digital information described above. For example, two or more inversion intervals larger than the maximum inversion interval of the digital information signal are continuous.

  A read signal (reproduced signal) optically read from the optical disk by an optical head (not shown) having a known configuration is supplied to the A / D converter 1 shown in FIG. After being sampled and converted into a digital signal, automatic threshold control (ATC) in which the ATC / AGC circuit 2 appropriately controls the threshold of the binary comparison is controlled by direct current (DC) and automatic gain control in which the amplitude is controlled to be constant (AGC) is performed.

  The output signal of the ATC / AGC circuit 2 is supplied to a DPLL (Digital PLL) 3 and a synchronization signal interval detection circuit 7 described later. The DPLL 3 is a digital PLL circuit in which a loop is completed in its own block, and an input signal sampled with a fixed system clock by the A / D converter 1 is regenerated with a bit clock having a desired bit rate. The sampled digital data is generated and supplied to the equalizer (EQ) circuit 4 at the subsequent stage. Here, “resampling” refers to obtaining sampling data at the timing of the bit clock by performing a thinning interpolation operation from a digital signal obtained by A / D conversion at the timing of the system clock. The position where the A / D converter 1 is provided may be anywhere on the input side of the DPLL 3.

  The EQ circuit 4 gives a partial response (PR) characteristic to the digital data output from the DPLL 3 to generate an equalized reproduction waveform and supplies it to the Viterbi decoding circuit 5. The circuit configuration of the Viterbi Viterbi decoding circuit 5 is known. For example, a branch metric calculation circuit that calculates a branch metric from sample values of the equalized reproduction waveform, and a path metric is calculated by accumulating the branch metrics for each clock. A path metric calculation circuit and a path memory for storing a signal for selecting a most probable data series having a minimum path metric. The path memory stores a plurality of candidate series, and outputs the candidate series selected according to the selection signal from the path metric calculation circuit as binary data that is a decoded data series. The decoded data obtained by Viterbi decoding by the Viterbi decoding circuit 5 is supplied to the Sync detection circuit 6, where Sync (synchronization signal) is detected. This Sync (synchronization signal) is not a special pattern synchronization signal, but a fixed pattern synchronization signal included in the digital information signal recorded on the optical disc at a constant period. The sync detection circuit 6 supplies a synchronization detection status signal to the response control circuit 10 when the sync (synchronization signal) can be detected stably.

  In this embodiment, in the information reproducing apparatus that performs the reproducing operation described above, the synchronization signal interval detecting circuit 7, the frequency correcting circuit 8, the adder 9, and the response control circuit 10 are provided, and the output signal of the response control circuit 10 is the DPLL 3 It is characterized by controlling the center frequency of the. FIG. 2 is a diagram showing the configuration of the DPLL 3 together with the blocks 2, 7, 8, 9, and 10 of the main part of the present embodiment. The same components as those in FIG.

  As shown in FIG. 2, the DPLL 3 is a loop feedback loop circuit composed of an interpolator 31, a phase detector 32, a loop filter 33, an adder 34, and a timing adjuster 35. The interpolator 31 is an ATC / AGC. The digital signal output from the circuit 2 and the signal from the timing adjuster 35 are received as input signals, and the data value of the phase point data is estimated by interpolation from the data point phase information input from the timing adjuster 35 and the bit clock. Output. The output data value of the interpolator 31 is supplied to the EQ circuit 4 in FIG. 1 as a resampling signal and also to the phase detector 32.

  The phase detector 32 detects the zero cross point from the resampling signal, and outputs the phase error using the data value at the zero cross point. For example, a phase error can be obtained by detecting the zero cross point from the data Di-1 one bit before and the data Di at the present time and multiplying the polarity of Di-1 by (Di-1 + Di) / 2.

  The output phase error signal of the phase detector 232 is integrated by the loop filter 33, further added to the output signal of the adder 9 by the adder 34, and then supplied to the timing adjuster 35, where the output of the loop filter 33 is obtained. The next data point phase is estimated, and the data point phase information and the generated bit clock are supplied to the interpolator 31.

  On the other hand, in the digital signal output from the ATC / AGC circuit 2, the synchronization signal interval detection circuit 7 detects the interval between adjacent synchronization signals. The synchronization signal interval detection circuit 7 estimates a signal having a relatively long inversion interval as a synchronization signal and measures the appearance interval. One of the synchronization signal interval information detected by the synchronization signal interval detection circuit 7 is supplied to the spindle servo circuit and used for controlling the rotation speed of the optical disk, that is, the rotation of the spindle motor. The other of the synchronization signal interval information is supplied to the frequency correction circuit 8 and is supplied to the adder 9 as a correction amount for a reference value (supplied from a CPU (not shown)) that determines the center frequency of the DPLL 3 based on the deviation of the synchronization signal interval. The values are supplied and added to generate a target value. This target value is supplied to the response control circuit 10, and after controlling the response, it is supplied to the adder 34 in the DPLL 3 as a reference value after response control.

  Next, the synchronization signal interval detection circuit 7 will be described in more detail. FIG. 3 shows a block diagram of an embodiment of the synchronization signal interval detection circuit 7. As shown in the figure, the synchronization signal interval detection circuit 7 includes an inversion interval detection circuit 71, a maximum value detection circuit 72, a synchronization signal extraction circuit 73, and an interval detection circuit 74. The synchronization signal interval detection circuit 7 first measures (detects) an inversion interval corresponding to a predetermined threshold value of the digital signal (sampling data) output from the ATC / AGC circuit 2 in the inversion interval detection circuit 71. To do.

  Next, the maximum value detection circuit 72 sequentially calculates, for example, interval information for two consecutive inversion intervals from the inversion interval information of a predetermined period measured by the inversion interval detection circuit 71, and further, the plurality of interval information of these plural pieces of interval information. The maximum value is detected from the inside. The predetermined period is, for example, a one-period recording period of a special pattern synchronization signal (a recording period from a certain synchronization signal to the next adjacent synchronization signal).

  Next, the synchronization signal extraction circuit 73 extracts a probable value from the maximum values detected by the maximum value detection circuit 72. That is, as described above, the optical disk reproduced in the present embodiment records a synchronization signal that is longer than the maximum inversion interval of the digital information signal and has at least two known inversion intervals that are continuous. Therefore, the maximum value that is the same as or close to the interval of one period in total of two known consecutive inversion intervals is extracted as a probable one, that is, a synchronization signal.

  Based on the position of the synchronization signal extracted by the synchronization signal extraction circuit 73, the synchronization detection circuit 74 measures the appearance interval of adjacent synchronization signals with a predetermined clock, and generates synchronization signal interval information as a result. This synchronization signal interval information is supplied to the spindle servo circuit and frequency correction circuit 8.

  Next, the response control circuit 10 constituting the main part of the present embodiment will be described in detail. FIG. 4 shows a block diagram of an embodiment of the response control circuit 10. As shown in FIG. 4, the response control circuit 10 includes a comparison operation block 101 and a D latch circuit 102. The comparison operation block 101 receives the target value output from the adder 9 shown in FIGS. 1 and 2 and the reference value after response control output from the D latch circuit 102 as inputs, and according to the comparison result. The output value A is obtained based on the following logic. The above logic in the comparison operation block 101 is expressed as follows, assuming that the target value from the adder 9 is B and the post-response control reference value output from the D latch circuit 102 is An-1.

(1) When An-1> B, A = An-1-α
(2) When An-1 = B, A = A
(3) When An-1 <B, A = An-1 + α
Here, α is an arbitrary value.

  The output value A output from the comparison operation block 101 based on the above logic is supplied to the D latch circuit 102, sampled at every predetermined clock, temporarily held, and then used as a reference value An-1 after response control. Is output and supplied to the comparison operation block 101 and the adder 34 in the DPLL 3. With this configuration, the post-response control reference value An-1 follows the target value B and shows a gentle and continuous response with the inclination α. This will be described with reference to FIG.

  FIG. 5 shows a diagram in which the horizontal axis represents time and the vertical axis represents the PLL center frequency. As shown by the solid line II in the figure, when the post-response control reference value An-1 of the DPLL is changed from the initial value, the post-response control reference value An-1 is a value that changes continuously and gently. Therefore, the PLL center frequency can be changed continuously and gently so that the capture range III can be surely entered in a short time.

  FIG. 5 shows a state where the capture operation is not performed, but when the DPLL 3 is operated, the result is as shown in FIG. FIG. 6A shows a diagram in which the horizontal axis represents time and the vertical axis represents the PLL center frequency. As shown in FIG. 6A, when the reference value An-1 after response control of DPLL3 is changed from the initial value so that the PLL center frequency is within the captureable range III, the captureable range III is entered in a short time. DPLL3 locks. When the DPLL 3 is in the locked state, the synchronization detection status output from the sync detection circuit 6 becomes logic “1” indicating that the synchronization is detected, as shown in FIG.

  The synchronization detection status of logic “1” is inverted in polarity by the inverter 103 shown in FIG. 4 and then supplied to the enable terminal of the D latch circuit 102 to put the D latch circuit 102 in an operation holding state. As a result, the response control circuit 10 enters an operation holding state and stops the frequency control, so that a stable state can be maintained thereafter. As described above, according to the present embodiment, the response control post-response control reference value An-1 supplied from the response control circuit 10 to the DPLL 3 follows the target value B, and exhibits a gentle and continuous response with the inclination α. As a result, the pull-in time including frequency control can be greatly improved as compared with the conventional case.

  Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing another embodiment of the information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. In the embodiment of FIG. 7, automatic gain control (AGC) for controlling the amplitude to be constant is performed together with automatic threshold control (ATC) for appropriately direct current (DC) controlling the threshold of the binary comparison with respect to the read signal. The ATC / AGC circuit 11 is configured by an analog circuit, and the synchronization signal interval detection circuit 7 and the frequency correction circuit 8 are also configured by an analog circuit. The principle is the same as that of the embodiment of FIG.

  The A / D converter 12 in FIG. 7 samples the output signal of the ATC / AGC circuit 11 based on the clock output from the voltage controlled oscillator (VCO) 16. The output signal of the A / D converter 12 is waveform-equalized by the equalizer circuit 4 and then decoded by the Viterbi decoding circuit 5. Using the decoded output, the Sync detection circuit 6 detects a synchronization signal. The output signal of the A / D converter 12 is also supplied to the phase detection circuit 13.

  The phase detection circuit 13 performs phase comparison between the clock output from the VCO 16 and the output signal from the A / D converter 12 and outputs the phase error signal to the adder 14. The adder 14 supplies a signal obtained by adding the output signal of the frequency correction circuit 8 and the reference value to the above phase error signal to the response control circuit 15 as a target value. The response control circuit 15 performs the same operation as the response control circuit shown in FIG. 4, and applies the obtained reference value after response control to the VCO 16 as a control voltage. Of course, the reference value may be omitted (only the DC loop gain is increased). In the synchronization signal interval detection circuit 7, the function of FIG. 3 which is a main part of the present invention is configured by an analog circuit, and has the same effect as the embodiment of FIG.

  In addition, this invention is not limited to said embodiment, The computer program which implement | achieves the structure of FIGS. 2-4 by a computer is also included. This computer program may be recorded on a recording medium and taken into the computer from the recording medium, or distributed via a communication network and taken into the computer.

It is a block diagram of one embodiment of the present invention. It is a block diagram of an example of DPLL in FIG. FIG. 2 is a block diagram of an embodiment of a synchronization signal interval detection circuit that is a main part of FIG. 1. It is a block diagram of one Embodiment of the response control circuit which is the other principal part of FIG. It is FIG. (1) explaining operation | movement of the principal part of one embodiment of this invention. It is FIG. (2) explaining operation | movement of the principal part of one embodiment of this invention. It is a block diagram of other embodiments of the present invention. It is a figure explaining the subject of the conventional information reproducing | regenerating apparatus.

Explanation of symbols

1, 12 A / D converter 2, 11 ATC / AGC circuit 3 DPLL
4 Equalizer (EQ) Circuit 7 Synchronization Signal Interval Detection Circuit 8 Frequency Correction Circuit 9, 14, 34 Adder 10, 15 Response Control Circuit 13 Phase Detection Circuit 16 Voltage Control Oscillator (VCO)
Reference Signs List 31 Interpolator 32 Phase Detector 33 Loop Filter 35 Timing Adjuster 71 Inversion Interval Detection Circuit 72 Maximum Value Detection Circuit 73 Synchronization Signal Extraction Circuit 74 Interval Detection Circuit 101 Comparison Operation Block 102 D Latch Circuit 103 Inverter

Claims (3)

A digital information signal generated based on a modulation method in which the maximum value and minimum value of the inversion interval are defined, and the inversion interval is greater than the maximum inversion interval of the digital information signal inserted in the digital information signal at a constant period. An information reproducing apparatus for reproducing a recording medium on which a synchronization signal of a special pattern set to be large is recorded,
Reading means for reading a recording signal of the recording medium;
Measuring means for sequentially measuring the inversion interval of the read signal from the reading means for a predetermined period;
An interval detection unit that estimates the maximum value of the inversion intervals obtained by measurement by the measurement unit as the synchronization signal, and detects an appearance interval of the synchronization signal based on the estimated position information of the synchronization signal;
A phase-locked loop circuit that receives the read signal, generates a clock synchronized with the phase of the read signal, and generates digital data sampled with a bit clock of a desired bit rate;
Decoding means for decoding the digital data;
An addition unit for calculating a target value by adding the appearance interval of the synchronization signal detected by the interval detection unit to the reference value as a correction amount with respect to a reference value determining a center frequency of the phase-locked loop circuit;
Response control means for generating a reference value after response control that changes continuously and gently following the target value, and that controls the center frequency of the phase-locked loop circuit based on the reference value after response control. An information reproducing apparatus characterized by that. A digital information signal generated based on a modulation method in which the maximum value and minimum value of the inversion interval are defined, and the inversion interval is greater than the maximum inversion interval of the digital information signal inserted in the digital information signal at a constant period. An information reproducing apparatus for reproducing a recording medium on which a synchronization signal of a special pattern set to be large is recorded,
Reading means for reading a recording signal of the recording medium;
Measuring means for sequentially measuring the inversion interval of the read signal from the reading means for a predetermined period;
An interval detection unit that estimates the maximum value of the inversion intervals obtained by measurement by the measurement unit as the synchronization signal, and detects an appearance interval of the synchronization signal based on the estimated position information of the synchronization signal;
A / D conversion means for converting the read signal into a digital signal with a system clock;
An ATC / ATC that performs automatic gain control for making the amplitude constant and automatic threshold control for appropriately DC-controlling the threshold of the binary comparison with respect to the digital signal or the read signal output from the A / D conversion means. AGC means,
A digital phase-locked loop circuit for generating digital data resampled with a bit clock of a desired bit rate for the digital signals processed by each of the A / D conversion means and the ATC / AGC means;
Decoding means for decoding the digital data;
An adding means for calculating a target value by adding an appearance interval of the synchronizing signal detected by the interval detecting means to the reference value as a correction amount with respect to a reference value determining a center frequency of the digital phase locked loop circuit;
Response control means for generating a reference value after response control that changes continuously and gently following the target value, and controls the center frequency of the digital phase locked loop circuit based on the reference value after response control. An information reproducing apparatus comprising: Further comprising detection means for detecting that the phase-locked loop circuit is in a locked state based on the decoded data of the decoding means;
The response control means includes
When the target value is compared with the reference value after response control, and the target value is smaller than the reference value after response control, a value obtained by subtracting a predetermined value from the reference value after response control is subtracted. When the target value is larger than the reference value after response control, a value obtained by adding the predetermined value to the reference value after response control is output, and the target value is the same as the reference value after response control. Comparison operation means for outputting the reference value after the response control at the same time,
The operation of temporarily holding the output value of the comparison operation means and outputting it as the reference value after response control is repeated until a detection status indicating that the phase-locked loop circuit is locked is input from the detection means. The information reproducing apparatus according to claim 1, further comprising a holding unit.

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