JP2007529115A - Power semiconductor device and manufacturing method thereof - Google Patents

Abstract

  As with various embodiments for improved power devices, packaging methods and circuits incorporating the power devices for their manufacturing methods, use in a wide variety of power electronic applications are disclosed. One aspect of the present invention leads to different embodiments for power devices with improved voltage performance, fast switching speed and low on-resistance by combining many charge regulation methods and other methods to reduce parasitic capacitance. . Another aspect of the invention provides an improved termination structure for low voltage, medium voltage and high voltage devices. An improved method of power device manufacture is provided by another aspect of the present invention. Improvements have been shown for certain processing steps, such as, for example, forming trenches, forming dielectric layers inside trenches, forming mesa structures and reducing substrate thickness. According to another aspect of the invention, the charge regulation power device incorporates a temperature and current detector, such as a diode on the same chip. Other aspects of the present invention improve the equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device, and provide improvements for packaging of charge-regulated power devices.

Description

  The present invention relates to semiconductor devices, and in particular to various embodiments for improved power semiconductor devices such as transistors and diodes, and methods of manufacturing the same, including packages and circuits incorporating such devices.

  An important element in power electronics applications is the solid state switch. There is a need for a power switch that optimally meets the requirements of a particular application in order to power the converter in industrial applications, from ignition control in automotive applications to battery powered consumer electronic devices. Solid state switches, including, for example, power metal oxide semiconductor field effect transistors (power MOSFETs), insulated gate bipolar transistors (IGBTs) and various types of thyristors continue to evolve to meet this need. In the case of a power MOSFET, for example, a double diffusion structure (DMOS) with side channels (eg, US Pat. No. 4,682,405 by Blanchard et al.), A trench gate structure (eg US Pat. 429,481) and various techniques for charge balancing in the drift region of the transistor (eg, US Pat. No. 4,941,026 by Temple, US Pat. No. 5,216,275 by Chen and Neilson). U.S. Pat. No. 6,081,009) has been developed among many other technologies and will handle different, often competing demanded performance.

Some of the defining operating characteristics for a power switch are its on-resistance, breakdown voltage, and switching speed. Different emphasis is placed on each of these performance criteria, depending on the requirements of a particular application. For example, for power applications greater than about 300-400 volts, an IGBT exhibits an inherently low on-resistance compared to a power MOSFET, but its switching speed is slower due to its slower turn-off characteristics. Thus, for applications greater than 400 volts with low switching frequency that require low on-resistance, the IGBT is the preferred switch, while the power MOSFET is the device selected for relatively high frequency applications. There are often. If the frequency requirement of any application determines the type of switch used, the voltage requirement will determine the particular switch configuration. For example, in the case of a power MOSFET, improving the voltage performance of the transistor while maintaining a low R _DSon poses challenges due to the proportional relationship between the drain-source on-resistance R _DSon and the breakdown voltage. . Various charge control structures in the transistor drift region have been developed to address this challenge with different degrees of success.

  Device performance parameters are also affected by the manufacturing process and die packaging. Attempts have been made to address some of these challenges by developing a variety of improved processing and packaging technologies.

  Whether it is routers and hubs in consumer electronic devices or communication systems that are ultraportable, various applications for power switches continue to grow with the development of the electronics industry. Therefore, the power switch is still a semiconductor device with high development potential.

  The present invention provides various embodiments for power devices for various power electronics applications, as well as their manufacturing methods, packaging, and circuits incorporating such power devices. In general, one aspect of the present invention combines a number of charge conditioning techniques with other techniques that reduce parasitic capacitance to provide various implementations for power devices with improved voltage performance, fast switching speed, and low on-resistance. Find an example. Another aspect of the present invention provides an improved termination structure for low voltage, medium voltage and high voltage voltage devices. An improved manufacturing method for power devices is provided by another aspect of the present invention. Various embodiments of the present invention provide improvements to specific processing steps such as, for example, the formation of trenches, the formation of dielectric layers inside the trenches, the formation of mesa structures and the process of reducing substrate thickness. Yes. According to another aspect of the present invention, a charge tuned power device incorporates a temperature and current detector, such as a diode, on the same chip. Other aspects of the invention improve the equivalent series resistance (ESR) or gate resistance for power devices, incorporate additional circuitry on the same chip as the power device, and improve the packaging for charge-tuned power devices. give.

  These and other aspects of the invention are described in more detail below with reference to the accompanying drawings.

Detailed Description of the Invention

<Related patents>
This application is a continuation-in-part of the following commonly-assigned US patent applications.

  U.S. Patent No. 10 / 155,554 (Application Date: May 24, 2002) entitled "Electrolytic Effect Transistor and Method for Producing the Same" by Mo et al. (Attorney Docket No. 18865-17-2 / 17732) -722.001).

  US Patent Application No. 10,209,110 entitled "Dual Trench Power MOSFET" by Sapp (filing date: July 30, 2002) (Attorney Docket No. 18865-98 / 17732-55270).

  US patent application Ser. No. 09 / 981,583 entitled “Semiconductor Structure with Improved Small Forward Loss and High Device Capabilities” by Kocon (filing date: October 17, 2001) ( Agent reference number 18865-90 / 17732-51620).

  US Patent Application No. 10 / 640,742 entitled “Improved MOS Gate Method for Reduced Mirror Capacitance and Switching Loss” by Kocon et al. (Filing date: August 14, 2003) (Reference number 90065.000241 / 17732-66550).

  US patent application Ser. No. 09 / 774,780 entitled “Electrolytic Effect Transistor with Reduced Side Structure” by Marchant (filing date: Jan. 30, 2001) (Attorney Docket No. 18865-69 / 17732) 26400).

  US patent application Ser. No. 10 / 200,056 entitled “Vertical Charge Control Semiconductor Device with Low Output Capacitance” by Sapp et al. (Filing date: July 18, 2002) (Attorney Docket No. 18865-97) / 17732-26400).

  US Patent Application No. 10 / 288,982 (Filing date: November 5, 2002) titled “Blocking Low Voltage Drop Semiconductor Structure with High Drift Region” by Kocon et al. (Attorney Docket No. 18865-117) / 17732-66550).

  US patent application Ser. No. 10 / 442,670 entitled “Structure of Trench MOSFET with Self-Aligned Features and Method of Manufacturing the Same” by Herrick (filing date: May 20, 2003) Number 18865-131 / 17732-66850).

  US patent application Ser. No. 10 / 315,719 entitled “Method of Insulating Current Direction to Planar or Trench Striped Power Device While Maintaining Continuous Stripe Cell” (Filing Date: Dec. 10, 2002) (Agent reference number 90065.051802 / 17732-56400).

  US patent application Ser. No. 10 / 222,481, entitled “Method and Circuit for Reducing Loss in DC-DC Converters” by Elbanhawy (Filing Date: August 16, 2002) (Attorney Docket No. 18865) -91-1 / 17732-514300).

  US Patent Application No. 10 / 235,249 entitled “Semiconductor Device Unmolded Package” by Joshi (Filing Date: September 4, 2002) (Attorney Docket No. 18865-71-1 / 17732) 26390-3).

  US patent application Ser. No. 10 / 607,633 (Filing date: June 27, 2003) entitled “Flip Chip in Leaded Mold Package and Method of Manufacturing the Same” by Joshi et al. (Attorney Docket No. 18865) -42-1 / 17732-13420).

  This application claims the benefit of the following provisionally filed US patent application:

  US Patent Application No. 60 / 506,194 entitled "High Voltage Shielded Trench Gate LDMOS" by Wilson et al. (Filing date: September 26, 2003) (Attorney Docket No. 18865-135 / 17732-66940).

  US Patent Application No. 60 / 588,845 entitled “Storage Device with Charge Balance Structure and Method for Forming It” (Filing Date: July 15, 2004) (Attorney Docket No. 18865-164 / 17732) -67010).

  All the above patent applications are incorporated herein by reference in their entirety.

  The power switch can be implemented by any of a power MOSFET, IGBT, various types of thyristors, and the like. Many of the new techniques presented herein have been described in the context of power MOSFETs for purposes of illustration. However, the various embodiments of the invention described herein are not limited to MOSFETs, but include, for example, IGBTs, other types of bipolar switches, and various types of thyristors, as well as diodes. It should be understood that it can be applied to many other types of power switch technologies. Further, for purposes of explanation, various embodiments of the invention are shown to include specific p-type and n-type regions. It will be appreciated by those skilled in the art that the teachings herein are equally applicable to devices in which the conductivity of various regions is reversed.

  Referring to FIG. 1, a cross-sectional view of a portion of an exemplary n-type trench power MOSFET 100 is shown. The same applies to all other figures described herein, but the relative dimensions and sizes of the various elements and components shown in the figures accurately reflect the actual dimensions. It is not for illustrative purposes only. Trench MOSFET 100 includes a gate electrode formed inside trench 102. The trench 102 extends from the top surface of the substrate through a p-type well or body region 104 and terminates in an n-type drift or epitaxial region 106. The trench 102 is surrounded by a thin dielectric layer 108 and is substantially filled with a conductive material 110 such as doped polysilicon. N-type source region 112 is formed inside body region 104 adjacent to trench 102. The drain terminal for MOSFET 100 is formed on the back side of the substrate connected to the heavily doped n + substrate region. The structure shown in FIG. 1 is repeated many times on a common substrate, for example made of silicon, to form an array of transistors. The array can be configured in a variety of cellular or striped structures that are well known in the art. When the transistor is turned on, a conductive channel is formed vertically between the source region 112 and the drift region 106 along the wall of the gate trench 102.

  Due to its vertical gate structure, MOSFET 100 allows a higher recording density compared to planar gate devices. This high recording density results in a relatively low on-resistance. In order to improve the breakdown voltage performance of the transistor, a heavily doped p + body region 118 is formed inside the p-type well 104 at the interface between the heavily doped p + body region 118 and the p-type well 104. A staircase junction is formed. By controlling the depth of the heavily doped body region with respect to the depth of the trench and the depth of the well, the electric field generated when a voltage is applied is moved away from the trench. This increases the avalanche current associated with transistor performance. Variations on this improved structure and transistor, particularly the process of forming a step junction, are described in more detail in US Pat. No. 6,429,481 to Mo et al., The entire contents of which are incorporated herein by reference. Incorporated.

The vertical trench MOSFET 100 exhibits good on-resistance and improved durability, but has a relatively high input capacitance. The input capacitance to the trench MOSFET 100 has two components: a capacitance Cgs between the gate and the source and a capacitance Cgd between the gate and the drain. The capacitance Cgs between the gate and source arises from the overlap between the gate conductive material 110 and the source region 112 near the top surface of the trench. The capacitance formed between the gate and the inversion channel in the main body also contributes to Cgs. This is because in normal power switching applications, the body and source electrode of the transistor are both shorted. The capacitance Cgd between the gate and the drain results from the overlap between the gate conductive material 110 at the bottom of each trench and the drift region 106 connected to the drain. Capacitance Cgd or mirror capacitance between the gate and drain limits the transition time of transistor V _DS . Therefore, larger Cgs and Cgd result in significant switching losses. These switching losses become increasingly important as power management applications move toward higher switching frequencies.

One way to reduce the capacitance Cgs between the gate and source is to shorten the channel length of the transistor. If the channel length is shortened, Cgs which is a component directly between the gate and the channel decreases. The short channel length is also directly proportional to R _DSON and makes it possible to obtain the same device current capacity with a small gate trench. This will reduce both Cgs and Cgd by reducing the amount of overlap between the gate and source and between the gate and drain. However, the short channel length weakens the device and penetrates when a depletion layer is formed as a result of the reverse-biased body-drain junction being pushed deeply into the body region and approaching the source region. Reducing the doping concentration of the drift region so that the drift region maintains more depletion layers has the undesirable effect of increasing the on-resistance R _{DSON of the} transistor.

  An improvement to the transistor structure that allows a shorter channel length and is also effective in addressing the above drawbacks is to use an additional shield trench that is laterally spaced from the gate trench. Referring to FIG. 2A, an exemplary embodiment of a dual trench MOSFET 200 is shown. The term dual trench refers to a transistor having two different types of trenches, as opposed to the total number of similar trenches. In addition to the structural features common to the MOSFET of FIG. 1, the dual trench MOSFET 200 includes a shield and a wrench 220 that are interposed between adjacent gate trenches 202. In the exemplary embodiment shown in FIG. 2A, the shield trench 220 extends from the surface through the P + region 218, the body region 204 and into the drift region well below the depth of the gate trench 202. The trench 220 is surrounded by a dielectric material 222 and is substantially filled with a conductive material 224, such as doped polysilicon. The metal layer 216 electrically connects the conductive material 224 inside the trench 220 to the n + source region 212 and the high concentration p + body region 218. Accordingly, in this embodiment, trench 220 is referred to as a source shield trench. An example of this type of dual trench MOSFET, manufacturing method and circuit application for the MOSFET is more detailed in co-pending US patent application Ser. No. 10 / 209,110 entitled “Dual Trench Power MOSFET” by Steven Sapp. The entire contents of which are incorporated herein by reference.

  The effect of the deeper source shield trench 220 is to push deeply into the drift region 206 the depletion layer formed as a result of the reverse-biased body-drain junction. Thus, a wider depletion region can occur without increasing the electric field. This allows the drift region to be more highly doped without reducing the breakdown voltage. The highly doped drift region reduces the on-resistance of the transistor. Furthermore, by reducing the electric field in the vicinity of the body-drain junction, the channel length can be substantially shortened, the on-resistance of the transistor is reduced, and the capacitance Cgs between the gate and the source is substantially reduced. Reduction. Also, compared to the MOSFET of FIG. 1, the dual trench MOSFET makes it possible to obtain the same transistor current capacity with considerably fewer gate trenches. This significantly reduces the overlap capacitance between the gate and the source and the overlap capacitance between the gate and the drain. In the exemplary embodiment shown in FIG. 2A, the gate trench conductive layer 210 is embedded in the trench and is an interlayer dielectric film overlying the trench 102 in the MOSFET 100 shown in FIG. It should be noted that this would eliminate the need for a dome. Also, the use of the source shield trenches taught herein is not limited to trench gate MOSFETs, and the same advantage is that source shield trenches are planar MOSFETs (the gate is horizontal to the top surface of the substrate). It is also obtained when used in the above. An exemplary embodiment of a planar gate MOSFET with a source shield trench is shown in FIG. 2B.

  In order to further reduce the input capacitance, further structural improvements can be made, focusing on reducing the capacitance Cgd between the gate and drain. As described above, the capacitance Cgd between the gate and the drain is caused by the overlap between the gate and the drift region under the trench. One way to reduce this capacitance is to increase the thickness of the gate dielectric layer below the trench. Referring again to FIG. 2A, the gate trench 202 is shown having a thick dielectric layer 226 at the bottom of the trench. Below the trench, the gate trench 202 overlaps with the drift region 206 (the drain end of the transistor) compared to the dielectric layer along the sidewall of the gate trench. This reduces the capacitance Cgd between the gate and drain without degrading the forward conduction of the transistor. Creating a thick dielectric layer under the gate trench can be done in many different ways. One exemplary process for forming a thick dielectric layer is described in US Pat. No. 6,437,386 to Hurst et al., The entire contents of which are incorporated herein by reference. Another process for forming a thick dielectric layer at the bottom of the trench is described further below in connection with FIGS. Another way to minimize the capacitance between the gate and drain is to include the dielectric core of the die 2 located in the center inside the trench. The second dielectric core extends upward from a dielectric liner at the bottom of the trench. In one example, the second dielectric core may extend until it contacts the dielectric layer above the trench conductive material 210. This embodiment and its variations are described in more detail in Shenoy's own US Pat. No. 6,573,560.

  Another technique for reducing the capacitance Cgd between the gate and drain requires that the gate be shielded using one or more biased electrodes. According to this embodiment, one or more electrodes are formed inside the gate trench and under the conductive material that forms the gate electrode to shield the gate from the drift region and thereby between the gate and drain. Overlap capacity is substantially reduced. Referring to FIG. 3A, a portion of an exemplary embodiment of a shielded gate trench MOSFET 300A is shown. Trench 302 in MOSFET 300A includes a gate electrode 310 and, in this embodiment, two additional electrodes 311a, 311b below the gate electrode 310. The electrodes 311a and 311b shield since the gate electrode 310 substantially overlaps with the drift region 306, and eliminate the overlapping capacitance between the gate and the drain. The shield electrodes 311a and 311b are independently biased at an optimum potential. In one embodiment, one of the shield electrodes 311a or 311b can be biased at the same potential as the source end. Similar to the dual trench structure, biasing the shield electrode broadens the depletion region formed at the body-drain junction. This depletion layer further reduces Cgd. It should be understood that the number of shield electrodes 311 will vary depending on the switching application and in particular the voltage requirements of the application. Similarly, the size of the shield electrode in any trench can vary. For example, the shield electrode 311a can be larger than the shield electrode 311b. In one embodiment, the smallest shield electrode is closest to the bottom of the trench, and the remaining shield electrodes increase in size as they approach the gate electrode. The independently biased electrode inside the trench can also be used for vertical charge control, improving low forward voltage and high blocking capability. This aspect of the transistor structure, described further below in connection with high voltage devices, is self-patented by Kocon, entitled “Semiconductor Structure with Improved Low Forward Voltage Loss and High Blocking Capability”. Application 09 / 981,583 is also described in more detail. The entire contents of the patent application are incorporated herein by reference.

  FIG. 3B shows another embodiment for a shielded gate trench MOSFET 300B that combines the dual trench structure of FIG. 2A with the shielded gate structure of FIG. 3A. In the exemplary embodiment shown in FIG. 3B, gate trench 301 includes gate poly 310 over shield poly 311, similar to trench 302 of MOSFET 300A. However, MOSFET 300B includes a non-gate trench that can be deeper than gate trench 302 for vertical charge control. The charge control trench 301 may have a single layer of conductive material (eg, polysilicon) that connects to the source metal at the top of the trench, as in FIG. 2A, but the embodiment shown in FIG. A multiple stacked poly electrode 313 is used that is biased. The number of electrodes 313 stacked in the trench can vary depending on application requirements, as can the size of the electrodes 313 as shown in FIG. 3B. The electrodes may be independently connected or electrically connected. The number of charge control trenches in the device also depends on the application.

  Yet another technique for improving the switching speed of the power MOSFET reduces the capacitance Cgd between the gate and the drain by using a dual gate structure. According to this embodiment, the gate structure inside the trench receives a switching signal, performs a conventional gate function, shields the first part of the gate from the drift (drain) region and independently biases it. It is divided into two parts, a second part that can be applied. This greatly reduces the capacitance between the gate and drain of the MOSFET. FIG. 4A is a simplified partial view of an exemplary embodiment of a dual gate trench MOSFET 400A. As shown in FIG. 4A, the gate of MOSFET 400A has two portions G1 and G2. Unlike the shield electrodes (311a and 311b) in MOSFET 300A of FIG. 3A, the conductive material forming G2 in MOSFET 400A has an overlapping region 401 with a channel, and thus serves as the gate end. However, the second gate terminal G2 is biased independently of the first gate terminal G1, and does not receive the same signal that drives the switching transistor. In one embodiment, instead, G2 biases the MOSFET threshold voltage at a constant potential, inverting the channel in the overlap region 401. This ensures that a continuous channel is formed when transitioning from the second gate G2 to the first gate G1. In addition, the potential at G2 is higher than the source potential, and the charge transfer from the drift region to the second gate G2 further contributes to the reduction of Cgd, so that Cgd is reduced. In another embodiment, the second gate G2 is biased at a potential above the threshold voltage just prior to a switching event. In other embodiments, the potential at G2 can be made variable and optimally adjusted to minimize the helicopter of the capacitance Cgd between the gate and drain. The dual gate structure can be used in MOSFETs having a planar gate structure, as well as other types of trench gate power devices, including IGBTs and the like. A variation on dual gate trench MOS gate devices and methods of manufacturing such devices is described in Kocon et al., US Pat. / 640,742. The entire contents of the patent application are incorporated herein by reference.

  Another embodiment for an improved power MOSFET is shown in FIG. 4B. Here, the exemplary MOSFET 400B combines a planar dual gate structure with a trench electrode for vertical charge control. The first and second gate ends G1 and G2 function in a manner similar to the trench dual gate structure of FIG. 4A, but the deep trench 420 provides an electrode in the drift region to broaden the charge and increase the device breakdown voltage. Let In the embodiment shown, the shield or second gate G2 covers the top of the first gate G1 and extends to the P-type well 404 and the drift region 406. In another embodiment, the first gate G1 extends to the shield / second gate G2.

  Accordingly, the various techniques described, such as trench electrodes and gate shields for vertical charge control, can be combined to obtain power devices including lateral MOSFETs, vertical MOSFETs, IGBTs, diodes, and the like. The operating characteristics of the power device are optimized for any application. For example, the trench dual gate structure shown in FIG. 4A can be advantageously combined with a vertical charge control trench structure of the type shown in FIG. 3B or 4B. Such devices are filled with a single layer of conductive material (as seen in trench 420 in FIG. 4B) or with multiple stacked conductive electrodes (as seen in trench 301 in FIG. 3B). As well as the deep charge control trench, it includes an active trench having a dual gate structure as shown in FIG. 4A. For lateral devices where the drain end is coplanar with the source end in the substrate (ie, the current flows laterally), the charge control electrode forms a field plate instead of being stacked in a vertical trench And arranged in the horizontal direction. The positioning of the charge control electrode is generally parallel to the direction of current flow in the drift region.

  In one embodiment, dual gate and shield gate techniques are combined within the same trench, giving increased switching speed and blocking voltage. FIG. 4C shows the MOSFET 4C. In FIG. 4C, a trench 402C includes a first gate G1, a second gate G2, and a shield layer 411 stacked in one trench as shown. The trench 402C can be made deep and can include as many shield layers 411 as the application requires. High density is achieved by using the same trench for the charge control and shield electrodes. The reason is that the need for two trenches is eliminated and they are combined into one. It also allows better current spreading and improves device on-resistance.

  Thus, the described device uses a combination of shielded gates, dual gates, and other technologies to reduce parasitic capacitance. However, due to the effects at the helicopter, these techniques do not completely minimize the capacitance Cgd between the gate and drain. Referring to FIG. 4D, a partial cross-sectional view of an exemplary embodiment of MOSFET 400D having a deep body design is shown. According to this embodiment, the body structure is formed by a trench 418 that is etched through the center of the mesa formed between the gate trenches 402 and extends the same depth as the gate trench or deeper than the gate trench. The source metal layer may include a thin refractory metal at the metal-diffusion boundary (not shown). In this example, the body structure further includes a p + body implant 419 substantially surrounding the body trench 418. The p + implant layer 419 allows further shielding and changes the potential distribution within the device, particularly in the vicinity of the gate electrode. In another embodiment shown in FIG. 4E, the body trench 418 is filled with an epitaxial material using, for example, a selective epitaxial growth (SEG) method. Alternatively, the body trench 418E is filled with doped silicon. In either of these two embodiments, instead of embedding the p + shield junction 419, a dopant is diffused into the silicon from the body filled with a later temperature treatment to form the p + shield junction 419. Many of the variations or configurations for the body structure from which the trench is made are described in more detail in commonly assigned US Pat. Nos. 6,437,399 and 6,110,799 to Huang. The entire contents of the patent are incorporated herein by reference.

  In the embodiment shown in FIGS. 4D and 4E, the distance L between the gate trench 402 and the body trench 418 minimizes the capacitance of the helicopter between the gate and drain, as well as the relative depth of the two trenches. It is controlled to become. In embodiments using SEG or poly filled body trenches, the spacing between the outer edge of layer 419 and the gate trench walls is adjusted by changing the doping concentration of poly or SEG inside body trench 418. obtain. 4F and 4G show the effect of a trenched deep body with trenches formed on the distribution of potential lines inside the device near the gate electrode. For illustration purposes, FIGS. 4F and 4G use MOSFETs with a shielded gate structure. FIG. 4F shows a potential line for a reverse-biased shield gate MOSFET 400F having a deep body 418 with a trench formed therein. FIG. 4G shows potential lines for a reverse-biased shielded gate MOSFET 400G having a shallow body structure. The contour lines in each device indicate the potential distribution inside the device when reverse bias is applied (that is, in the blocking off state). White lines indicate well junctions and define the bottom of the channel located next to the gate electrode. As can be seen, there is a low potential and a low electric field surrounding the gate electrode for the deep body MOSFET 400F applied to the channel and formed with the trench of FIG. 4F. This potential reduction allows for a reduced channel length that reduces all gate charge to the device. For example, the depth of the gate trench 402 can be made shallower than the body trench 418 having a spacing L that can be, for example, 0.5 μm or less and about 0.5 μm or less. In one exemplary embodiment, the spacing L is less than 0.3 μm. Another advantage of this embodiment is that the gate-drain charge Qgd and Miller capacitance Cgd are reduced. The smaller these parameter values, the faster the device can be turned on and off. This improvement is achieved through reducing the potential present adjacent to the gate electrode. This improved structure has a fairly small potential that is turned on and off, and the induced capacitive current at the gate is quite small. This allows the gate to turn on and off faster.

  Deep body structures with trenches, as described in connection with FIGS. 4D and 4E, can be combined with other charge conditioning techniques, such as shielded gate or dual gate structures, for device switching. This will further improve the speed, on-resistance and blocking capability.

The improvements provided by the above power devices and variations thereof provide a robust switching element for relatively low voltage power electronic applications. Low voltage as used herein refers to a voltage range of, for example, about 30V to 40V or less, but this range can vary depending on the particular application. Applications that require device voltages that exceed this range require a type of structural improvement to the power transistor. Usually, the doping concentration in the drift region of the power transistor is reduced to maintain a higher voltage while the device is in the blocking state. However, the lower doped drift region results in an increase in the on-resistance R _DSOn of the transistor. High resistivity directly increases the power loss of the switch. This power loss becomes more important as recent advances in semiconductor manufacturing further increase the recording density of power devices.

  Attempts have been made to improve device on-resistance and power loss while maintaining a high blocking voltage. Many of these attempts use a variety of vertical charge control techniques to create large and flat electric fields in semiconductor devices. Many device structures of this type are disclosed by Kocon in his own US Pat. No. 6,713,813 entitled “Field Effect Transistor with Lateral Depletion Structure” by Korchant and Kocon. It has been proposed to include the device disclosed in U.S. Pat. No. 6,376,878. The entire contents of both these patents are incorporated herein by reference.

  FIG. 5A is a partial cross-sectional view of a portion of an exemplary power MOSFET 500A having a planar gate structure. MOSFET 500A appears to have a structure similar to planar MOSFET 200B of FIG. 2B, but differs in two important respects. Instead of filling the trenches 520 with conductive material, these trenches are filled with a dielectric such as silicon dioxide. The device includes discontinuous floating p-type regions 524 spaced adjacent to the outer sidewalls of trench 520. As described in connection with the dual trench MOSFET of FIG. 2A, the conductive material (eg, polysilicon) in the source trench 202 helps to improve the cell breakdown voltage by pushing the depletion region deep into the drift region. . Thus, removing other conductive material from these trenches results in a reduction in breakdown voltage if no other means of reducing the electric field is used. The floating p-type region 524 serves to reduce the electric field.

  Referring to MOSFET 500A shown in FIG. 5A, since the electric field increases as the drain voltage increases, the floating p region 524 obtains a corresponding potential determined by their position in the space charge region. These floating potentials in the p region 524 cause the electric field to spread deeply into the drift region, resulting in a more uniform electric field across the depth of the mesa region between the trenches 520. As a result, the breakdown voltage of the transistor is increased. The advantage of replacing the conductive material in the trench with an insulating material is that a larger space charge region appears across the insulator rather than the drift region, which can be silicon. The dielectric constant of the insulator is lower than that of silicon, for example, and the area of the depletion region in the trench is reduced, so that the output capacitance of the device is greatly reduced. This further enhances the switching characteristics of the transistor. The depth of the trench 520 filled with dielectric depends on the voltage requirements. The deeper the trench, the higher the blocking voltage. Another advantage of the vertical charge control technique is that it allows the transistor cells to be moved laterally for thermal isolation without significantly increasing capacitance. In another embodiment, instead of a floating p region, a p-type layer is placed on the outer sidewall of the dielectric filled trench to provide similar vertical charge adjustment. A simplified partial cross-sectional view of this embodiment is shown in FIG. 5B where the outer sidewalls of trench 520 are covered with a p-type layer or liner 526. In the exemplary embodiment shown in FIG. 5B, the gate is also formed with a trench, further improving the transconductance of the device. Another embodiment for an improved power device that utilizes a variation of this technology is US Pat. App. No. 1, filed by the same applicant entitled “Vertical Charge Control Semiconductor Device with Low Output Capacitance” by Sapp et al. 10 / 200,056 (Attorney Docket No. 18865-0097 / 17732-55280). The entire contents of the patent application are incorporated herein by reference.

As described above, the trench MOSFET 500B of FIG. 5B exhibits reduced output capacitance and improved breakdown voltage. However, since the active trench (gate trench 502) is disposed between the charge control trenches 520 filled with a dielectric, the channel width of the MOSFET 500B is not as thick as the conventional trench MOSFET structure. This can result in a higher on-resistance R _DSon . Referring to FIG. 5C, another embodiment is shown for a trench MOSFET 500C with vertical charge control that eliminates the second charge control trench. Trench 502C in MOSFET 500C includes a lower portion filled with dielectric that extends deeply into gate poly 510 and drift region 506. In one embodiment, trench 502C extends to a depth below about half the depth of drift region 506. A p-type liner 526C surrounds the outer sidewall along the lower portion of each trench, as shown. This single trench structure eliminates the second charge control trench, allowing additional channel width and lower R _DSon . The lower portion of the deeper trench 502C, surrounded by a p-type liner 526C on its outer wall, supports the main part of the electric field to reduce the output capacitance and the capacitance between the gate and drain. In another embodiment, p-type liner 526C is made in a plurality of discontinuous regions along the sides and bottom of trench 502C. Other embodiments are possible by combining a single trench charge control structure with the aforementioned shielded gate or dual gate technology, further reducing the parasitic capacitance of the device.

  Referring to FIG. 6, a simplified cross-sectional view of a power MOSFET 600 suitable for high voltage applications is shown. Such high voltage applications also require fast switching. MOSFET 600 combines vertical charge control to improve breakdown voltage with a shielded gate structure that improves switching speed. As shown in FIG. 6, the shield electrode 611 is disposed inside the gate trench 602 between the gate conductive material 610 and the lower portion of the trench. The electrode 611 shields the transistor gate from the underlying drain region (drift region 606), which significantly reduces the capacitance between the transistor gate and drain. As a result, the maximum switching frequency is increased. A dielectric-filled trench 620 with a doped liner 626 helps to create a large and flat electric field in the vertical direction and will improve the breakdown voltage of the device. In operation, the combination of a dielectric-filled trench 620 with a p-type liner 626 and a shield gate structure reduces parasitic capacitance and eliminates the drift region that disperses the electric field concentration at the edge of the gate electrode. To help. This type of device can be used in RF amplifiers or high frequency switching applications.

  FIG. 7 shows another embodiment for another power MOSFET suitable for high voltage, high frequency applications. In the simplified example shown in FIG. 7, MOSFET 700 combines vertical charge control to improve breakdown voltage with a dual gate structure that improves switching speed. Similar to the device shown in FIG. 6, vertical charge control is implemented through the use of a dielectric-filled trench 720 having a p-doped liner 726. The reduction of the parasitic capacitance is realized by using a dual gate structure in which the first gate electrode G1 is shielded from the drain (n drift region 706) by the second gate electrode G2. The second gate electrode G2 may be continuously biased or biased prior to a switching event to reverse the channel in region 701, and the continuous channel when the device is activated. Ensure a continuous flow of current through.

  In another embodiment, the shielded vertical charge control MOSFET uses a trench filled with a doped sidewall dielectric to provide an integrated Schottky diode. FIG. 8 shows an example of a shield gate MOSFET 800 according to this embodiment. In this example, the electrode 811 at the lower portion of the trench 802 shields the gate electrode 810 from the drift region 806 and reduces the parasitic capacitance between the gate and drain. A dielectric filled trench 820 with a p-doped liner on the outer sidewall provides vertical charge control. Schottky diode 828 is formed between two trenches 820A and 820B that form a mesa of width W. This Schottky diode structure is scattered throughout the trench MOSFET cell array and enhances the operating characteristics of the MOSFET switch. The forward voltage drop is reduced by utilizing the low barrier height of the Schottky structure 828. In addition, this diode has an inherent reverse regeneration speed advantage compared to the normal PN junction of a vertical power MOSFET. Doping the sidewalls of the trench 820 filled with dielectric, for example with boron, eliminates sidewall leakage paths due to phosphorous segregation. The trench process features can be used to optimize the operation of the Schottky diode 828. In one embodiment, for example, the width W is adjusted so that depletion in the drift region of the Schottky structure 828 is affected and controlled by the adjacent PN junction to increase the reverse voltage performance of the Schottky diode 828. . Examples of monolithically integrated trench MOSFETs and Schottky diodes can be found in commonly-assigned US Pat. No. 6,351,018. The entire contents of the patent are incorporated herein by reference.

  Schottky diodes formed between trenches filled with a dielectric include MOSFETs having a planar gate structure and trench gate MOSFETs with or without a shield electrode under the trench (with or without a thick dielectric), etc. It can be integrated with a variety of different types of MOSFETs, including: An exemplary embodiment for a dual gate trench MOSFET with an integrated Schottky diode is shown in FIG. 9A. The MOSFET 900A includes a gate trench 902, and the first gate G1 is formed on the second gate G2, reducing the parasitic capacitance and increasing the switching frequency. MOSFET 900A also includes a dielectric-filled trench 920 having a p-doped liner 926 formed along its outer sidewall for vertical charge control to increase the breakdown voltage of the device. One method of forming the liners of many of the foregoing embodiments (eg, FIGS. 6, 7, 8 and 9A) uses a plasma doping process. Schottky diode 928A is formed between two adjacent dielectric filled trenches as shown. In other variations, monolithically integrated Schottky diodes and trench MOSFETs are formed without having a trench filled with a dielectric. FIG. 9B is a cross-sectional view of an exemplary device 900B according to this embodiment. MOSFET 900B includes active trenches 902B, each active trench having an electrode 911 embedded under gate electrode 910. Schottky diode 928B is formed between two trenches 902L and 902R as shown. The charge adjustment effect of the biased electrode 911 makes it possible to increase the doping concentration of the drift region without compromising the reverse breakdown voltage. A higher doping concentration in the drift region reduces the forward voltage drop for this structure. In the case of the above-described trench MOSFET having a buried electrode, the depth of each trench can be changed in the same manner as the number of buried electrodes. In one variation shown in FIG. 9C, trench 902C has gate electrode 910S and one buried electrode 911 in Schottky cell 928C connected to the source electrode, as shown. The gate of the Schottky diode can be selectively connected to the MOSFET gate end. Figures 9D, 9E and 9F show exemplary layout variations for Schottky diodes interspersed within the active cell array of MOSFETs. 9D and 9E show the layout of the single mesa Schottky and double mesa Schottky, respectively, while FIG. 9F shows the layout where the Schottky region is perpendicular to the MOSFET trench. These and other variations of integrated Schottky diodes, including multiple Schottky to MOSFET regions, can be combined with any of the transistor structures described herein.

  In other embodiments, the power device's voltage blocking capability is achieved by continuously applying one or more diode structures embedded within a dielectric-edged trench and disposed parallel to the current flow in the device drift region. Increased by using. FIG. 10 provides a simplified cross-sectional view of an exemplary trench MOSFET 1000 according to this embodiment. Diode trenches 1020 are disposed on either side of the gate trench 1002 and extend into the drift region 1006. The diode trench 1020 includes one or more diode structures comprised of regions 1023 and 1025 of opposite conductivity that form one or more PN junctions within the trench. In one embodiment, the trench 1020 has one region that has the opposite polarity to the drift region such that a single PN junction is formed at the interface with the drift region. P-type and n-type doped polysilicon or silicon can be used to form regions 1023 and 1025, respectively. Other types of materials such as unitary silicon, gallium arsenide, silicon germanium, etc. may also be used to form regions 1023 and 1025. A thin dielectric layer 1021 extending along the sidewalls inside the trench insulates the diode in the trench from the drift region. As shown, since there is no dielectric layer along the bottom of the trench 1020, the lower region 1027 can be electrically connected to the underlying substrate. In one embodiment, similar considerations affecting the design and manufacture of gate oxide 1008 apply to designing and forming dielectric layer 1021. For example, the thickness of the dielectric layer 1021 is determined by factors such as voltage, and is maintained and stretched so that the electric field in the diode trench is induced in the drift region (ie, the extent to couple through the dielectric layer). Is needed.

  In operation, when MOSFET 1000 is biased in its blocking state, the PN junction inside diode trench 1020 is reverse biased with a peak electric field that occurs at each diode junction. Through the dielectric layer 1021, the electric field in the diode trench has a corresponding electric field in the drift region 1006. The induced electric field is manifested in the drift region in the form of an upswing spike and a general increase in the electric field curve in the drift region. This increase in the electric field results in a larger area under the electric field curve that results in a higher breakdown voltage. A variation in this example is US Pat. Application Serial No. 10 / 288,982 (Attorney Docket No. 18865) entitled “Drift Region High Blocking Low Forward Voltage Drop Semiconductor Structure” by Kocon et al. -117 / 17732-66560). The entirety of this patent application is incorporated herein by reference.

  Other embodiments are possible for power devices that combine diodes with trenches for charge regulation with techniques to reduce parasitic capacitance, such as shielded gate or dual gate structures. FIG. 11 illustrates one embodiment of a MOSFET 1100 according to one such embodiment. The MOSFET 1100 uses a shield electrode 1111 below the gate electrode 1110 inside the active trench 1102 to reduce the capacitance Cgd between the gate and drain, for example for the transistor described above in connection with MOSFET 300A in FIG. 3A. A different number of PN junctions are used in MOSFET 1100 when compared to MOSFET 1000. FIG. 12 is a cross-sectional view of MOSFET 1200 combining dual gate technology with a trench diode structure. Active trench 1202 in MOSFET 1200 includes a first gate G1 and a second gate G2, and operates in the same manner as the active trench in the dual gate MOSFET described in connection with FIG. 4B. The diode trench 1220 provides charge regulation and increases the blocking voltage of the device while the dual gate active trench structure improves the switching speed of the device.

  Yet another embodiment combines a trenched diode charge regulation technique with an integrated Schottky diode in a planar gate MOSFET 1300 as shown in FIG. Similar advantages can be obtained by combining the Schottky diode 1328 with the MOSFETs described in connection with the embodiments of FIGS. In this embodiment, the planar gate structure is shown for illustration, and the combination of the integrated Schottky diode and trench diode structure is any of other types of gate structures including trench gates, dual gates and shield gates. Can be used in MOSFETs having Any of the resulting embodiments can also be combined with the technique of the body in which the trench is formed, and as described in connection with MOSFET 400D or 400E of FIGS. 4D and 4E, fringing parasitic capacitance. capacitance) is further minimized. Other variations and equivalents are possible. For example, the number of heteropolar conducting regions inside the diode trench can vary as well as the depth of the diode trench. The polarity of the heteropolar conduction region can be reversed as is the case with the MOSFET. Also, any of the PN regions (such as 923, 925 or 1023, 1025) can be made as necessary by extending each region along the three dimensions to a silicon surface where electrical contact can be made to them, for example. Can be independently biased. Further, multiple diode trenches can be used when required by device size and application voltage requirements. The spacing and placement of the diode trenches can be implemented with various stripe or porous designs.

  In another embodiment, a class of transistors in accumulation mode is provided that utilizes various charge adjustment techniques for lower forward voltage loss and higher blocking capability. In a normal accumulation mode transistor, there is no blocking junction and the device is turned off by slightly inverting the channel region adjacent to the gate edge. When the transistor is turned on by applying a gate bias, a storage layer is formed in the channel region rather than an inversion layer. Since there is no inversion channel formation, the channel resistance is minimized. Further, there is no PN body diode in the accumulation mode transistor that minimizes loss. This loss occurs in certain circuit applications, such as synchronous rectifiers. The disadvantage of conventional accumulation mode devices is that when the device is in blocking mode, the drift region must be slightly doped to support the reverse bias voltage. A slightly doped drift region means higher on-resistance. The embodiments described herein overcome this limitation by utilizing various charge adjustment techniques in accumulation mode devices.

  Referring to FIG. 14, a simplified embodiment of an exemplary accumulation mode transistor 1400 is shown having alternating conduction regions arranged parallel to current flow. In this embodiment, the transistor 1400 includes an n-channel transistor having a gate end formed inside a trench 1402, an n-type channel region 1412 formed between the trenches, a columnar n-type portion 1403 having different polarity and p A drift region 1406 having a mold portion 1405 and an n-type drain region 1414. Unlike enhancement mode transistors, accumulation mode transistor 1400 does not include a blocking (p-type in this embodiment) well or body region inside the channel. Instead, a conductive channel is formed when the storage layer is formed in region 1412. Transistor 1400 is typically turned on or off depending on the doping concentration of region 1412 and the doping type of the gate electrode. Turns on when n-type region 1412 is completely used up and slightly inverted. The doping concentration in the heteropolar regions 1403 and 1405 is adjusted to maximize charge diffusion. Such charge diffusion allows the transistor to support higher voltages. By using a cylindrical heteropolar region parallel to the current flow, the electric field distribution is flattened without decreasing linearly away from the junction formed between regions 1412 and 1406. The charge diffusion effect of this structure allows the use of a highly doped drift region that reduces the on-resistance of the transistor. The doping concentration of various regions can vary. For example, n-type regions 1412 and 1403 can have the same or different doping concentrations. Those skilled in the art will recognize that improved p-type transistors can be obtained by reversing the polarity of the various regions of the device shown in FIG. Other variations of the cylindrical heteropolar region within the drift region are described in more detail in connection with the ultra high voltage device described further below.

  FIG. 15 is a schematic diagram of another accumulation mode device 1500 having a trench electrode for charge diffusion purposes. All regions 1512, 1506 and 1514 are of the same conductivity type, and in this example are n-type. For off-devices, the gate polysilicon is made p-type. The doping concentration of region 1512 is adjusted to form a blocking junction that is substantially emptied under an unbiased condition. In each trench 1502, one or more embedded electrodes 1511 are formed under the gate electrode 1510. All of the embedded electrodes are surrounded by a dielectric 1508. As described in connection with enhancement mode MOSFET 300A of FIG. 3A, buried electrodes 1511 function as field plates and can be biased to a potential that optimizes their charge diffusion function as needed. Since charge diffusion can be controlled independently by biasing the buried electrode 1511, the maximum electric field can be greatly increased. Similar to the buried electrodes used in MOSFET 300A, variations in structure are possible. For example, the depth of the trench 1502 and the size and number of buried electrodes 1511 can vary depending on the application. In a manner similar to that shown for the trench structure of MOSFET 300B in FIG. 3B, the charge diffusion electrode may be embedded inside a trench that is separate from the active trench that houses the gate electrode of the transistor. Such an embodiment is illustrated in FIG. In the example shown in FIG. 16, n-type region 1612 includes a more heavily doped n + source region 1603 that can be added as the situation demands. The heavily doped source region 1603 is formed as two regions extending along the upper end of the n-type region 1612 or adjacent to the trench wall along the upper end of the n-type region 1612 as shown. (Not shown in this figure). In some embodiments, it may be necessary to reduce the doping concentration of n-type region 1606 by including n + region 1603 to ensure that the transistor is properly turned off. This optional heavily doped source region can be used in the same manner for any of the storage transistors described herein.

  Another embodiment for an improved accumulation mode transistor uses a trench filled with a dielectric with a different polarity outer liner. FIG. 17 is a simplified cross-sectional view of a storage transistor 1700 according to this embodiment. A trench 1720 filled with dielectric extends downward from the surface of the silicon well into the drift region 1706. The trench 1720 is filled with a dielectric such as silicon dioxide. In this exemplary embodiment, transistor 1700 is an n-channel transistor having a gate structure with a trench formed. The p-type region 1726 covers the outer wall of the trench 1720 filled with dielectric, as shown. Similar to enhancement mode transistors 500A, 500B, and 500C described in connection with FIGS. 5A, 5B, and 5C, respectively, trench 1720 reduces the output capacitance of the transistor, while p-type liner 1726 does not operate in the drift region. Provides charge regulation and increases the blocking capability of the transistor. In another embodiment shown in FIG. 18, diametrically doped liners 1826N and 1826P are formed proximate to the opposite side of the dielectric filled trench 1820. That is, the dielectric filled trench 1820 has a p-type liner 1826P extending along one outer wall and an n-type liner 1826N extending along the other outer wall of the same trench. Other variations on this combination of storage transistors having trenches filled with dielectric are possible, as will be described in connection with the corresponding enhancement mode transistors. These include, for example, a storage transistor having a planar (as opposed to trench) gate structure and floating p-type region instead of a p-type liner, such as the device shown in FIG. 5A, and the device shown in FIG. 5B. A storage transistor with a p-type liner covering the bottom of the trench, such as a storage transistor having a p-type liner that covers only the outer wall and does not cover the bottom of the trench 1726, and especially the device shown in FIG. 5C. Including transistors.

  In another embodiment, the accumulation mode transistor uses one or more diodes formed sequentially within the trench for charge regulation purposes. A simplified cross-sectional view of an exemplary accumulation mode transistor 1900 according to this embodiment is shown in FIG. The diode trench 1920 is disposed on both sides of the gate trench 1902 and extends to the drift region. The diode trench 1920 has one or more diode structures composed of diametrically opposite conductivity type regions 1923 and 1925 that form one or more PN junctions within the trench. p-type and n-type doped polysilicon or silicon is used to form regions 1923 and 1925. A thin dielectric layer extending along the trench inner wall insulates the diode in the trench from the drift region. As shown, there is no dielectric layer along the bottom of the trench 1920, allowing the bottom region 1927 to make electrical contact with the underlying substrate. Other variations on this combination of storage transistors with trench diodes are possible, as described in connection with the corresponding enhancement mode transistors shown in FIGS. 10, 11, 12, 13 and variations thereof. It is.

  Any of the above-described accumulation mode transistors may use a heavily doped heteropolar region in the top (source) region. FIG. 20 is a simplified three-dimensional view of an exemplary accumulation mode transistor 2000 that illustrates this functionality in combination with other variations. In this embodiment, the charge adjustment diode in the accumulation mode transistor 2000 is formed in the same trench as the gate. Trench 2002 includes a gate electrode 2010, below which n-type 2023 and p-type 2025 silicon or polysilicon layers form a PN junction. A thin dielectric layer 2008 separates the diode structure from the gate end 2002 as well as the drift region. The heavily doped p + regions 2118 are formed at intervals along the length of the mesas formed between the trenches in the source region 2012, as shown. The heavily doped p + region 2118 reduces the area of the n− region 2012 and reduces device leakage. The p + region 2118 enables a p + contact that improves hole current flow in the avalanche and also improves device reliability. Variations of exemplary vertical MOS gate storage transistors are being considered to demonstrate the various functions and benefits of this type of device. Those skilled in the art will recognize that these are done in other types of devices including lateral MOS gate transistors, diodes, bipolar transistors, and the like. The charge diffusion electrode can be formed either inside the same trench as the gate or inside another trench. The various exemplary accumulation mode transistors described above end with a drift region, but can also end with a more heavily doped substrate connected to the drain. The various transistors can be formed in a stripe or cell structure comprising hexagonal or square transistor cells. Other variations and combinations described with other embodiments are possible, many of which are further described in previously referenced US patent application 60 / 506,194 and US patent application 60 / 588,845. ing. The entire contents of both of these patent applications are incorporated herein by reference.

  Another type of power switching device, designed for high voltage applications, uses vertical portions of alternating p-doped and n-doped silicon in the epitaxial region between the substrate and the well. Referring to FIG. 21, one example of a MOSFET 2100 that uses this type of structure is shown. In MOSFET 2100, region 2102, sometimes referred to as a voltage maintaining or blocking region, includes staggered n-type portion 2104 and p-type portion 2106. The effect of this structure is that when a voltage is applied to the device, the depletion region extends horizontally on each side of the 2104 and 2106 portions. The total vertical thickness of blocking layer 2102 is depleted before the horizontal electric field is high enough to cause avalanche breakdown. The reason is that the net quantity of charge in each vertical portion 2104 and 2106 is less than needed to cause a breakdown field. After the region is completely depleted in the horizontal direction, the electric field continues to form in the vertical direction until an avalanche field of about 20-30 V / μm is reached. This significantly increases the voltage blocking capability of the device and extends the voltage range of the device to over 400V. Different variations on this type of super junction device are described in more detail in Nielson's own US Pat. No. 6,081,009 and US Pat. No. 6,066,878. The entire contents of these US patent applications are incorporated herein by reference.

A variation of superjunction MOSFET 2100 uses floating p-type islands in the n-type blocking region. In contrast to the pillar approach, the use of floating p-type islands makes it possible to reduce the thickness of the charge adjustment layer that reduces R _DSon . In one embodiment, the p-type islands are spaced to maintain an electric field near the critical electric field instead of being uniformly spaced. FIG. 22 is a simplified cross-sectional view of MOSFET 2200 illustrating one example of a device according to this embodiment. In this example, the deeper floating region 2226 is spaced further away from the floating region above it. That is, the distance L3 is greater than the distance L2, and the distance L2 is greater than the distance L1. By manipulating the distance between the floating junctions in this manner, minority carriers are introduced in a more granular manner. The more granular the source of these carriers, the lower the R _DSon and the higher breakdown voltage can be caused. It will be appreciated by those skilled in the art that many variations are possible. For example, the number of floating regions 2226 in the vertical direction is not limited to four as shown, and the optimal number may vary. Also, the doping concentration in each floating region 2226 can vary. For example, in one embodiment, the doping concentration in each floating region 2226 gradually decreases as the region approaches the substrate 2114.

Further, many of the techniques for reducing parasitic capacitance to increase switching speed, including shielded gate and dual gate structures, as described in connection with low voltage and intermediate voltage devices, are shown in FIGS. Can be combined with the high voltage device described in FIG. FIG. 23 is a simplified cross-sectional view of a high voltage MOSFET 2300 in which a variation of the super junction structure is combined with a dual gate structure. The MOSFET 2300 has, for example, a planar dual gate structure composed of gate ends G1 and G2, similarly to the dual gate transistor shown in FIG. 4B. Gastric polarity (p-type in this example) region 2326 is disposed vertically to n-type drift region 2306 below p-well 2308. The size and spacing of the p-type regions 2326 vary in this example, so that the regions 2326 located closer to the p-well 2308 are in contact with each other, but the regions 2326 located further below are floating It is small in size as shown. FIG. 24 shows yet another embodiment for a high voltage MOSFET combining superjunction technology with a shielded gate structure. MOSFET 2400 is a trench gate device having a gate electrode 2410. For example, like the MOSFET 300A in FIG. 3A, the gate electrode 2410 is shielded from the drift region 2406 by the shield electrode 2411. MOSFET 2400 also includes a heteropolar floating region 242 disposed in drift region 2406 parallel to the current flow.
Termination Structure The various types of individual devices described above have a breakdown voltage limited by the cylindrical or spherical shape of the depletion region at the tip end. This cylindrical or spherical breakdown voltage is usually much lower than the parallel plane breakdown voltage BV _pp in the active area of the device, so that the edge of the device is a breakdown for the device that is close to the breakdown voltage of the active area. It needs to be terminated to achieve a voltage. Different techniques have been developed to spread the electric field and voltage uniformly over the end of the end, achieving a breakdown voltage close to BV _pp . These include field plates, field rings, junction termination extensions (JTE) and different combinations of these technologies. Already referenced, U.S. Pat. No. 6,429,481, by Mo et al., Describes a deep junction (deeper than a well) that has an overlying field oxide layer surrounding and overlying an active cell array. One example of an electric field termination structure with In the case of an n-channel transistor, for example, the termination structure includes a deep p + region that forms a PN junction with the n-type drift region.

In another embodiment, one or more ring-shaped trenches surrounding the periphery of the cell array serve to reduce the electric field and increase avalanche breakdown. FIG. 25A shows a typical trench layout for a trench transistor. The active trench 2502 is surrounded by a ring-shaped termination trench 2503. In this structure, a region 2506, indicated by a circle drawn with a dotted line at the mesa end, becomes depleted earlier than the other regions, and the increased electric field in this region reduces the breakdown voltage under reverse bias conditions. Bring. Thus, this type of layout is limited to low voltage devices (eg <30V). FIGS. 25B-25F illustrate a number of embodiments for termination structures with different trench layouts to reduce the high field region shown in FIG. 25A. As can be seen in the figure, in these embodiments, some or all of the trenches are isolated from the termination trench. Gap W _G between the end portion and the termination trench in the active trench serves to reduce the electric field congestion effect observed in the structure shown in FIG. 25A. In one exemplary embodiment, W _G is made approximately half the width of the mesa between the trenches. For high voltage devices, multiple termination trenches as shown in FIG. 25F are used, further increasing the breakdown voltage of the device. US Pat. No. 6,683,363, entitled “Trench Structure for Semiconductor Devices” by Challa, describes variations on some of these embodiments in more detail. The entire contents of the US patent are incorporated herein by reference.

  26A-26C show various trench termination structures for charge tuned trench MOSFETs. In the illustrated exemplary embodiment, MOSFET 2600A uses a shielded gate structure having a shielded poly electrode 2611 embedded under gate poly 2610 inside active trench 2602. In the embodiment shown in FIG. 26A, termination trench 2603A is covered with a relatively thick dielectric layer (oxide) 2605A and filled with a conductive material such as poly 2607A. The thickness of the oxide layer 2605A, the depth of the termination trench 2603A, and the spacing between the termination trench and the adjacent active trench (ie, the width of the last mesa) is determined by the device's reverse blocking voltage. In the embodiment shown in FIG. 26A, the trench is wide on the surface (T-trench structure), and the metal field plate 2609A is used over the termination region. In another embodiment (not shown), the field plate is formed on the surface and over the termination region (to the left of the termination trench in FIG. 26A) by extending poly 2607A inside termination trench 2603A. Can be formed from Many variations are possible. For example, a p + region (not shown) under a metal contact to silicon can be added for better ohmic contact. The p-well region 2604 and its respective contact in the last mesa adjacent to the termination trench 2603A can be removed depending on the situation. Also, the floating p-type region can be added to the left of the termination trench 2603A (ie, outside the active area).

  In another variation, instead of filling the termination trench 2603 with poly, the poly electrode is embedded in the lower portion of the trench inside the oxide filled trench. This embodiment is shown in FIG. 26B, where approximately half of the termination trench 2603B is filled with oxide 2605B and the lower half has a poly electrode 2607B embedded within the oxide. The depth of trench 2603B and the height of buried poly 2607B will vary based on device processing. In yet another embodiment shown in FIG. 26C, the termination trench 2603C is filled with a dielectric and no conductive material is embedded therein. For all three embodiments shown in FIGS. 26A, 26B, and 26C, the width of the last mesa separating the termination trench from the last active trench is a standard width formed between the two active trenches. Different from the width of any mesa and can be tailored to achieve the best charge adjustment in the termination region. All of the above-described variations related to the structure shown in FIG. 26A can be applied to the structure shown in FIGS. 26B and 26C. Furthermore, although termination structures are described herein for shielded gate devices, those skilled in the art will appreciate that similar structures can be implemented for all the various trench-based devices described above. Recognized by.

  For low voltage devices, the corner design for the trench termination ring may not be important. However, for high voltage devices, it is desirable that the corner roundness of the termination ring has a larger radius of curvature. The higher the device voltage requirement, the greater the radius of curvature at the corners of the termination trench. Also, the number of termination rings can increase as the device voltage increases. FIG. 27 illustrates an exemplary device that includes two termination trenches 2703-1 and 2703-2 having relatively large radii of curvature. The spacing between the trenches can be adjusted based on the voltage requirements of the device. In this embodiment, the distance S1 between the termination trenches 2703-1 and 2703-2 is approximately twice the distance between the first termination trench 2703-1 and the active trench.

  28A, 28B, 28C, and 28D show exemplary cross-sectional views for various termination regions having silicon pillar charge conditioning structures. In the embodiment shown in FIG. 28A, the field plate 2809A contacts all the rings of the p-type pillar 2803A. This allows for a wider mesa area due to lateral depletion by the field plate. The breakdown voltage usually depends on the thickness of the field oxide film, the number of rings, and the depth and interval of the termination pillar 2803A. Many different variations on this type of termination structure are possible. For example, FIG. 28B shows another embodiment, where a large field plate 2809B-1 covers all pillars 2803B except the last pillar. The last pillar is connected to another field plate 2809B-2. By grounding the large field plate 2809B-1, the mesa region between the p-type pillars is quickly depleted and the horizontal voltage drop is less noticeable, resulting in a lower breakdown voltage than the embodiment shown in FIG. 28A. It becomes. In another embodiment shown in FIG. 28C, the termination structure does not have a field plate on the central pillar. Since there are no field plates on the central pillar, they have a narrower mesa area to fully deplete. In one embodiment, optimum performance is provided by gradually decreasing the mesa toward the outer ring. The embodiment shown in FIG. 28D facilitates contact with the p-type pillars by providing a wide well region 2808D and increasing the spacing between field oxides as shown.

  In the case of ultra high voltage devices using various superjunction technologies of the type described above, the breakdown voltage is much higher than conventional BVpp. For superjunction devices, charge conditioning or superjunction structures (eg, heteropolar pillars or floating regions, buried electrodes, etc.) are also used in the termination region. A standard end termination structure in combination with a charge conditioning structure such as a field plate on the top surface at the edge of the device may also be used. In some embodiments, the standard end structure at the top surface can be removed by using a rapidly decreasing charge at the termination junction. For example, p-type pillars in the termination region can be formed with charges that decrease the farther away from the active area they cause net n-type regulation charge.

  In one embodiment, the spacing between p-type pillars in the termination region changes as the pillars move away from the active region. A simplified cross-sectional view of an exemplary embodiment of device 2900A according to this embodiment is shown in FIG. 29A. In the active area of device 2900A, a pillar 2926A of opposite conductivity, for example composed of a plurality of connected p-type spheres, is formed below the p-type well 2908A in the n-type drift region 2904A. As shown, p-type termination pillars TP1-TPn are formed at the end of the device below the termination region. Instead of having a uniform spacing in the active area, the center-to-center distance between the termination pillars T1 to TPn increases as the pillar moves away from the interface with the active area. That is, the distance D1 between TP2 and TP3 is shorter than the distance D2 between TP3 and TP4. The distance D2 is shorter than the distance D3 between TP4 and TP5.

Several variations of this type of superjunction termination structure are possible. For example, instead of forming the p-type termination pillars TP1 to TPn by changing the distance inside the voltage maintaining layer 2904A, the center-to-center distance is uniform, but the width of each termination pillar can be changed. FIG. 29B shows a simplified example of a termination structure according to this embodiment. In this example, the end pillar TP1 has a width TP1 larger than the width W2 of the end pillar TP2. W2 is made larger than the width W3 of the terminal pillar TP3. Regarding the distance between the different polarity charge adjustment regions in the termination region, even if the center-to-center distance between the trench pillars is the same in the device 2900B, the structure obtained in the device 2900B is the same as that in the device 2900A. In another exemplary embodiment shown in the simplified cross-sectional view in FIG. 29C, the width of each heteropolar pillar 2926C in the active region decreases from the top surface to the substrate, while the width of the termination pillars TP1 and TP2 is substantially Are the same. This makes it possible to achieve a desired breakdown voltage while utilizing a small area. It will be appreciated by those skilled in the art that the various termination structures described above can be combined in any desired manner. This includes, for example, that the center-to-center distance and / or full width of the termination pillars in device 2900C can vary as described in connection with the embodiment shown in FIGS. 29A and 29B.
Processing techniques Accordingly , many different devices have been described, including trench structures with multiple buried electrodes or diodes. In order to bias these trench electrodes, these devices allow electrical contacts to be made to each buried layer. Many methods for forming a trench structure with a buried electrode and many methods for making a contact to a buried poly layer inside a trench are described herein. In one embodiment, the contact to the trench poly layer is comprised at the end of the chip. FIG. 30A shows one example of an end contact for a trench device 3000 having two poly layers 3010 and 3020. FIG. 30A shows a cross-sectional view along the longitudinal axis of the trench. According to this embodiment where the trench terminates near the edge of the chip, the poly layers 3010 and 3020 are on the substrate surface for contact purposes. Openings 3012 and 3022 in dielectric layers 3030 and 3040 allow metal contact to the poly layer. 30B and 30F illustrate various processing steps including forming the end contact structure of FIG. 30A. In FIG. 30B, a dielectric (eg, silicon dioxide) layer 3001 is patterned on the top surface of the epitaxial layer 3006 and the exposed surface of the substrate is etched to form a trench 3002. Thereafter, a first oxide layer 3003 is formed over the top surface of the substrate and will include a trench as shown in FIG. 30C. Thereafter, a first layer of conductive material (eg, polysilicon) 3010 is formed on the surface of oxide layer 3003 as shown in FIG. 30D. Referring to FIG. 30E, the poly layer 3010 is etched from the inside of the trench, and another oxide layer 3030 is formed over the poly 3010. A similar process is performed to form a second oxide-poly-oxide sandwich as shown in FIG. 30F. Here, the top oxide layer 3040 is shown etched to create openings 3012 and 3022 for the metal contact layers relative to the poly layers 3010 and 3020, respectively. The last step can be repeated for additional poly layers. The poly layers can be joined by an overlying metal layer if desired.

  In other embodiments, contacts to multiple poly layers in any trench are made in the active area of the device instead of along the edge of the chip. FIG. 31A shows one example of an active area contact structure for multiple buried poly layers. In this example, the cross-sectional view along the longitudinal axis of the trench shows the poly layer 3110 providing the gate end and poly layers 3111a and 3111b providing two shield layers. Three separation lines 3112, 3122 and 3132 are shown as contact formations to the shield poly layer, but they are all connected and connected to the source end of the device or other contacting combinations, It can be used as required by a particular application. The advantage of this structure is the planar nature of the contact compared to the multi-layer end contact structure shown in FIG. 30A.

  31B-31M show one example of a process flow for forming an active area shield contact structure for a trench having two poly layers. After etching of trench 3102 in FIG. 31B, formation of shield oxide 3108 in FIG. 31C is continued. Thereafter, shield polysilicon 3111 is deposited and embedded in the trench as shown in FIG. 31D. The shield poly 3111 is further embedded in FIG. 31E except where shield contact on the substrate surface is required. In FIG. 31E, mask 3109 protects the poly inside the central trench from further etching. In one embodiment, this mask is applied at different locations across different trenches so that, for example, the shield poly is buried in other parts of the trench in three dimensions (not shown) for the central trench. In other embodiments, the shield poly 3111 inside one or more selected trenches in the active area is masked over the entire length of the trench. Thereafter, the shield oxide 3108 is etched as shown in FIG. 31F. Then, after the mask 3109 is removed as shown in FIG. 31G, a thin layer of gate oxide 3108a is formed over the top surface of the substrate. Next, gate poly deposition and recess (FIG. 31H), p-well implant and drive and n + source implant (FIG. 31J) are continued. FIGS. 31K, 31L and 31M show the steps of BPSG deposition, contact etching and high concentration p + body filling, respectively, followed by metallization. FIG. 31N shows a cross-sectional view of another embodiment for an active area shield contact structure, where shield poly 3111 forms a relatively broad platform on the top surface of the shield oxide. This facilitates contact with the shield poly, but introduces a structure that can further complicate the manufacturing process.

  A simplified comprehensive layout diagram of an exemplary trench device with active area shield contact is shown in FIG. 32A. The recess in the shield poly defined by the mask prevents the shield poly from being recessed at the position 3211C in the active region, as is the case with the periphery of the shield trench 3213. An improvement on this technique uses a dog-bone-like shape for the shielded poly indentation mask. The mask provides a wide area at the intersection including each trench 3202 for contact to the shield poly. This allows the shield poly in the masked area to be recessed, but removes the structure on the first surface of the mesa. A comprehensive layout diagram for another embodiment is shown in FIG. 32B, where the active area trench is connected to the peripheral trench. In this embodiment, the shield poly recess mask forms a shield poly recess over the length of the selected trench (in the example shown, the central trench) for active area shield trench contact to the source metal. Prevent you from doing. FIGS. 32C and 32D are simplified layout diagrams illustrating two different embodiments for making a contact in a peripheral trench in a trench device having an interrupted trench structure. In these figures, the active trench 3202 and the peripheral trench 3213 are shown as single lines for the purpose of illustration. In FIG. 32C, extensions or fingers from the peripheral gate polyrunner 3210 are alternated with respect to the peripheral shield polyfinger, with peripheral contacts spaced apart from the peripheral trench. Source and shield contact area 3215 is also in contact with the shield poly in the active region at location 3211C, as shown. The embodiment shown in FIG. 32D eliminates the offset between the active and peripheral trenches and avoids the possible limitations that result from trench pitch requirements. In this example, horizontal extensions from active trench 3202 and peripheral trench 3213 are aligned, and window 3217 in gate polyrunner 3210 allows contact to be made to the peripheral shield poly. The active area contact is made at location 3211C as in the previous example.

  Another example of contacting the trench shield poly layer in the active area is shown in FIG. 33A. In this embodiment, instead of making a recess in the shield poly, it extends vertically to the silicon substrate over the main part of the active trench. Referring to FIG. 33A, a shield poly 3311 divides the gate poly 3310 in two and extends vertically along the height of the trench 3302. The two gate polys are connected in three dimensions at the appropriate location inside the trench or they exit the trench. One advantage of this embodiment is the area saved by making the source poly contact inside the active trench instead of using silicon space that contributes to the poly contact in which the trench is formed. 33B-33M illustrate one example of a process flow for forming an active area shield contact structure of the type shown in FIG. 33A. The etching of trench 3302 in FIG. 33B is followed by the formation of shield oxide 3308 in FIG. 33C. Thereafter, shield polysilicon 3311 is deposited inside the trench as shown in FIG. 33D. The shield poly 3311 is etched and buried inside the trench as shown in FIG. 33E. The shield oxide 3308 is then etched as shown in FIG. 33F, leaving an exposed portion of shield polysilicon 3311 that forms two depressions on the interior side of the trench. Thereafter, a thin layer of gate oxide 3308a is formed over the top surface of the substrate, the sidewalls of the trench, and the depressions within the trench, as shown in FIG. 33G. Next, gate poly deposition and depression (FIG. 33H), p-well implantation and drive (FIG. 33I) and n + source implantation (FIG. 33J) are followed. 33K, 33L, and 33M show the steps of BPSG deposition, contact etching, and high concentration p + body embedment, respectively, and metallization continues. Variations in this process flow are possible. For example, the process of forming the gate poly 3310 by rearranging several processes may be performed before the process of forming the shield poly 3311.

Specific process methods, parameters and variations for performing many of the steps in the process flow described above are well known. For any application, specific process methods, chemistries and material types can be fine-tuned to increase device manufacturability and performance. Improvements can be made from the starting material, ie the substrate on which the epitaxial (epi) drift region is formed. In most power applications, it is desirable to reduce the on-resistance R _DSon of the transistor. The ideal on-resistance for power applications is a strong function of the critical field defined as the maximum electric field in the device under breakdown voltage. If the device has a higher critical field than silicon, provided that moderate mobility is maintained, the specific on-resistance of the transistor can be greatly reduced. Many of the characteristics of the power device, including the structures and processes described above, have been described in the context of a silicon substrate, but other embodiments using substrate materials other than silicon are possible. According to one embodiment, the power device described herein includes a band comprising, for example, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), diamond, and the like. Manufactured with a substrate made of a material with a wide gap. These wide bandgap materials exhibit a critical electric field that is higher than that for silicon, making it possible to greatly reduce the on-resistance of the transistor.

Another major factor for the on-resistance of the transistor is the drift region thickness and doping concentration. The drift region is usually formed by epitaxially grown silicon. In order to reduce R _DSon , it is desirable to minimize the thickness of this epi drift region. The thickness of the epi layer is partially influenced by the type of starting substrate. For example, red phosphorus doped substrates are commonly used as starting substrate materials for discrete semiconductor devices. However, phosphorus atoms have the property of quickly diffusing into silicon. Accordingly, the thickness of the epi region formed on the top surface of the substrate is determined to correspond to the upward diffusion of phosphorus atoms from the underlying heavily doped substrate.

  In order to minimize the thickness of the epi layer, according to one embodiment shown in FIG. 34, an epi spacer or buffer (or barrier) layer 3415 having a relatively low diffusivity dopant such as arsenic is A phosphorus substrate 3414 is formed. The combination of the phosphorus doped substrate and the arsenic doped buffer layer provides the basis for the subsequent formation of the epi drift region 3406. The arsenic dopant concentration in layer 3415 is determined by the breakdown voltage requirement of the device, and the thickness of the arsenic epilayer 3415 is determined by the specific amount of heat. A conventional epi layer 3406 is then deposited on top of the arsenic epi and its thickness is determined by device requirements. The much lower diffusion rate of arsenic allows the overall thickness of the drift region to be reduced, which will reduce the on-resistance of the transistor.

In another embodiment, a diffusion layer is used between the two layers to address upward diffusion of dopant species from the heavily doped substrate to the epi layer. According to one exemplary embodiment shown in FIG. 35, a barrier layer of, for example, silicon carbide Si _x C _1-x is epitaxially deposited on a substrate 3514 containing boron or phosphorus. Thereafter, an epi layer 3506 is deposited on the barrier layer 3515. Thickness and carbon composition can vary with the amount of heat in the manufacturing technique. The carbon dopant is first implanted into the substrate, and then the carbon atoms are activated by heat treatment to form a Si _x C _1-x compound on the surface of the substrate 3514.

Another aspect of certain transistor technologies that limit the ability to reduce the thickness of the epi is formed between the epi layer and the deep body used in the active region, sometimes in the termination region, and sometimes in the termination region Is a joint. The formation of this deep body region usually has an embedding step early in the process. Due to the subsequent large amount of heat required by the field oxide and the gate oxide, the junctions in the deep body and drift region are gradually changing. To avoid initial breakdown at the chip edge, a fairly thick drift region is required that provides a high on-resistance. In order to minimize the required epi thickness, diffusion barrier layers can also be used for deep body-epi junctions. According to the exemplary embodiment shown in FIG. 36, the carbon dopant is implanted through the deep body window and a deep body implant is performed. The subsequent thermal process activates the carbon atoms and forms a layer 3615 of Si _x C _1-x compound at the boundary of the deep body region 3630 at the p-well epi junction. The silicon carbide layer 3615 functions as a diffusion barrier that prevents boron diffusion. The resulting deep body junction becomes narrow and allows the thickness of the epi layer 3606 to be reduced. Yet another junction in a typical trench transistor that can benefit from a diffusion barrier is a well-drift region junction. A simplified example of an embodiment using such a barrier layer is shown in FIG. In the exemplary process flow for the structure of FIG. 31M, a p-well is formed between the two steps shown in FIGS. 31H and 31I. Carbon is first embedded before the well dopant (p-type for this exemplary n-channel embodiment) is embedded. The subsequent thermal process activates the carbon atoms and forms a Si _x C _1-x layer 3715 at the p-well and epi junction. Layer 3715 functions as a diffusion barrier to prevent boron diffusion and the depth of p-well 3704 can be maintained. This helps to reduce the channel length of the transistor without increasing the potential for reach-through. Reach-through occurs when the edge of the forward depletion boundary reaches the source junction as the drain-source voltage increases. By serving as a diffusion barrier, layer 3715 also prevents reach through.

  As described above, it is desirable to shorten the channel length of the transistor. The reason is that this results in a reduction in on-resistance. In another embodiment, the channel length of the transistor is minimized by forming a well region using epitaxially grown silicon. That is, instead of the conventional method of well formation including embedding in the drift epi layer (the diffusion step is then continued), the well region is formed on the top surface of the epi drift layer. There are advantages other than the short channel length that can be obtained from the formation of epi-wells. In a shielded gate trench transistor, for example, the distance that the gate electrode extends under the bottom of the well (the contact with the trench (overlap from the gate to the drain) is important in determining the gate charge Qgd. Directly affects the switching speed of the transistor, so it is desirable to be able to accurately minimize and control this distance, but, for example, as shown in FIG. This distance is difficult to control in a manufacturing process that is embedded and spreading.

  In order to better control the gate-drain overlap at the well corners, various methods have been proposed for forming trench devices with self-aligned wells. In one embodiment, a process flow that includes epi-well deposition allows the bottom of the body junction to self-align to the bottom of the gate. Referring to FIGS. 38A-38D, a simplified process flow is shown for one example of a self-aligned epi-well trench device having a buried electrode (or shield gate). The trench 3802 is etched into the first epi layer 3806 formed on the top surface of the substrate 3814. For an n-channel transistor, the substrate 3814 and the first epi layer 3806 are n-type material.

  FIG. 38A shows a layer of shield dielectric 3808S grown on top of the epi layer 3806 including the internal trench 3802. FIG. Thereafter, a conductive material 3811 such as polysilicon is deposited inside the trench 3802 and etched back below the epimesa as shown in FIG. 38B. Additional dielectric 3809S is deposited over the shield poly 3811. After etching back the dielectric to reveal mesas, a second epi layer 3804 is selectively grown on top of the first epi layer 3806, as shown in FIG. 38C. The mesa formed by the epi layer 3804 creates an upper trench portion over the first trench 3802 as shown. The second epi layer 3804 has a dopant having a polarity different from that of the first epi layer 3806 (for example, p-type). The dopant concentration in the second epi layer 3804 is set to a desired level with respect to the well region of the transistor. After a selective epi growth (SEG) step to form layer 3804, a layer of gate dielectric 3808G is formed on the top surface and along the sidewalls of the trench. A gate conductive material (poly) is then deposited to fill the remaining portion of trench 3802 and then planarized as shown in FIG. 38D. The process continues as in the process flow shown in FIGS. 31J to 31M, for example. The transistor structure is completed.

  As shown in FIG. 38D, this process results in a gate poly 3810 that is self-aligned with the well epi 3804. To lower the bottom of the gate poly 3810 below the epi well 3804, the top surface of the intermediate poly dielectric layer 3809S as shown in FIG. 38C can be slightly etched to the desired location inside the trench 3802. This process thus gives precise control of the distance between the bottom of the gate electrode and the corner of the well. The SEG well formation process is not limited to shielded gate trench transistors, but can be used for many other trench gate transistor structures, some of which are described herein. Will be recognized by those skilled in the art. Other methods of forming SEG mesa structures are described in commonly assigned US Pat. No. 6,391,699 by Madson et al. And US Pat. No. 6,373,098 by Brush et al. The entire contents of the patent are incorporated herein by reference.

  For the purpose of self-alignment, another method of controlling the well corners does not rely on SEG well formation, but instead uses a process that includes corner well filling. 39A and 39B illustrate exemplary steps for this example. For example, as shown in FIGS. 31H and 31I, instead of forming a well after the trench is filled with gate poly, in this embodiment, a shield poly is embedded in a dielectric layer 3908 inside the trench 3902. A first well fill is performed with an arbitrary partial capacitance later and before the remainder of the trench is filled. Thereafter, a second but horned well fill is performed through the sidewalls of the trench 3902, as shown in FIG. 39B. The drive cycle is then completed and the desired profile for the well is obtained at the drift-epi interface at the corner of the trench. Embedded capacity, drive cycle details and energy will vary depending on device structural requirements. This technique can be used in many different device types. In another embodiment, the pitch and angle burying of the trench is assimilated with the region to form a continuous well from neighboring cells when the angle burying is diffused, Eliminate the need for well filling.

Another embodiment for a self-aligned epiwell process for forming a trench device is described in connection with FIGS. 40A-40E. As noted above, in order to reduce the capacitance between the gate and drain, some trench gate transistors are more at the bottom of the trench below the gate poly than the dielectric layer along the internal vertical sidewalls. thick. According to the exemplary process embodiment shown in FIGS. 40A-40E, dielectric layer 4008B is first formed on top of epi drift layer 4006, as shown in FIG. 40A. Dielectric layer 4208B is formed to the desired thickness relative to the bottom of the trench and is then etched leaving the dielectric pillars as shown in FIG. 40B. The dielectric pillar has the same width as the trench to be formed next. Next, in FIG. 40C, a selective epi growth step is performed to form a second epi drift region around the dielectric post 4008B. The second drift epi layer 4006-1 may be the same conductivity type and the same material as the first epi drift layer. Alternatively, other types of materials can be used for the second epi drift layer 4006-1. In one exemplary embodiment, the second drift epi layer 4006-1 is formed by SEG step is silicon germanium (Si _x Ge _1-x) alloy is performed. SiGe alloys improve carrier mobility in the accumulation region near the bottom of the trench. This improves the transistor switching speed and reduces R _DSon . Other compounds such as GaAs or GaN can also be used.

  Thereafter, as shown in FIGS. 40D and 40E, respectively, a blanket epi well layer is formed on the top surface and then etched to form trench 4002. Next, gate oxide formation and gate poly deposition (not shown) are continued. The resulting structure is a trench gate with a self-aligned epiwell. Conventional processing techniques can be used to complete the remaining process steps. Those skilled in the art will recognize that variations are possible. For example, instead of etching the trench 4002 after forming the blanket epiwell layer 4004, the epiwell 4002 is selectively grown only on the top surface of the second drift epilayer 4006-1 and the trench 4002 is formed as it grows. Can be done.

The various processing techniques described above will increase device performance by reducing the well region formation and reduce channel length and R _DSon . By improving other aspects of the process flow, device performance can be enhanced as well. For example, device resistance can be further reduced by reducing the substrate thickness. Therefore, the wafer thinning process is generally performed to reduce the thickness of the substrate. The wafer thinning is usually performed by mechanical polishing and a tape process. The polishing and tape process imparts mechanical force on the wafer, which can cause damage to the wafer surface and cause manufacturing problems.

  In the embodiments described below, the improved wafer thinning process significantly reduces substrate resistance. 40R, 40S, 40T, and 40U illustrate one way to reduce the thickness of the substrate. After the desired circuit is manufactured on the wafer, the wafer surface on which the circuit is manufactured is temporarily bonded to a carrier. FIG. 40R shows the completed substrate 4001 bonded to the carrier 4005 with a binder 4003. Thereafter, the back side of the finished substrate is polished to a desired thickness using processes such as polishing and chemical etching. FIG. 40S shows the same sandwich structure as FIG. 40R with the finished substrate 4001 being thinned. After polishing the back side of the wafer 4001, the back side of the wafer is bonded to a low resistance (eg, metal) wafer 4009, as shown in FIG. 40T. This can be done using conventional methods using, for example, solder 4007 plating under temperature and pressure to adhere the metal wafer 4009 to the thinned finished wafer 4001. Thereafter, the carrier 4005 is removed, and the upper surface of the thinned finished wafer 4001 is cleaned before further processing. A highly conductive metal substrate 4009 facilitates heat dissipation and resistance reduction and provides mechanical strength to the thinned wafer.

Another embodiment achieves a thin wafer without the disadvantages of conventional mechanical processes by performing a final thinning step using a chemical process. According to this embodiment, the active device is formed in the silicon layer of a silicon on thick glass (SOTG) substrate. At the polishing stage, the wafer is thinned by chemically etching the glass on the back side of the SOTG substrate. FIG. 41 shows an exemplary process flow according to this embodiment. Starting with a silicon substrate, first in step 4110 a dopant such as He or H ₂ is implanted into the silicon substrate. Next, in step 4112, the silicon substrate is bonded to the glass substrate. Different bonding processes can be used. In one example, a silicon wafer and a glass wafer are sandwiched and heated, eg, around 400 ° C., to bond the two substrates. The glass can be, for example, silicon oxide and can have a thickness of about 600 μm, for example. Next, in step 4114, optional cutting of the silicon substrate and formation of the SOTG substrate are continued. In order to protect the substrate from stresses during and after processing, the bonding process may be repeated to form a SOTG layer on the opposite side of the substrate (step 4116). Next, an epi layer is deposited on the silicon surface of the substrate (step 4118). This can be done on the back side in addition to the front side. The doping level of the backside epi is preferably similar to the backside silicon, but the frontside epi is doped as required by the device. The substrate is then subjected to various steps in the manufacturing process that form active devices in the front side silicon layer.

  In one embodiment, the back side of the substrate can be patterned to approximate the opposite structure of the front side chip frame to further enhance the substrate strength in resistance to stress introduced by the front side processing steps. . In this method, the glass substrate is etched in a grid, and the thin substrate helps to withstand the stress on the wafer. During polishing, the backside silicon layer is removed by a conventional polishing process (step 4120). Next, another polishing step 4122 is followed to remove a portion (eg, half) of the glass. Thereafter, the remaining part of the glass is removed, for example, by a chemical etching process using hydrofluoric acid. Etching the backside glass can be performed without the risk of attacking the active silicon layer or causing physical damage to the active silicon layer. This eliminates the need to tape the wafer and, as a result, eliminates the need for tape and re-tape equipment and the process risks associated with each of those steps. Thus, this process allows the substrate thickness to be further minimized and enhances device performance. It should be understood that many variations of the improved wafer thinning process are possible. For example, depending on the desired thickness for the final substrate, the thinning step may or may not include polishing, and chemical etching may be sufficient. Also, the improved wafer thinning process is not limited to processing individual devices, but can be used to process other types of devices. Another wafer thinning process is described in commonly assigned US Pat. No. 6,500,764 by Pritchett, the entire contents of which are incorporated herein by reference.

There are many other structural and processing aspects for power transistors and other power devices that can significantly affect their performance. The shape of the trench is one example. In order to reduce damaging electric fields that tend to concentrate around the corners of the trench, it is desirable to avoid pointed corners and instead form trenches with rounded corners. It is also desirable that the trench sidewalls have a smooth surface to improve reliability. Different chemical etches have several reactions such as silicon etch rate, selectivity to mask layer, etch profile (sidewall angle), top corner roundness, sidewall roughness and trench bottom roundness, etc. Give a trade-off between. SF ₆ fluorinated chemistry, for example, gives a high silicon etch rate (1.5 μm / min), a rounded trench bottom and a straight profile. The disadvantage of fluorination chemistry is the difficulty of controlling the surface of the rough sidewalls and trenches (which can be depressions). For example chlorinated a Cl ₂ gives a better control of the smoother side wall and etch profile and the trench surface. The trade-off with chlorides is low silicon etch rate (1.0 μm / min) and low roundness at the bottom of the trench.

Additional gas can be added to each chemical to help surface stabilize the sidewalls during etching. Sidewall surface stabilization is used to minimize lateral etching and etch to the desired trench depth. Further processing steps are used to smooth the trench sidewalls to achieve rounding of the top corner and the bottom of the trench. The surface quality of the trench sidewalls is important. The reason affects the quality of the oxide layer that can be grown on the sidewalls of the trench. Regardless of the chemical used, a breakthrough step is usually used before the main etch step. The purpose of this breakthrough step is to remove the native oxide on the surface of the silicon that can mask the silicon etch during the main etch step. Typical chemicals for breakthrough etching include CF ₄ or Cl ₂ .

One embodiment for the improved etching process shown in FIG. 42A uses a main silicon trench etch based on chlorine, followed by a fluorine based etching process. One example of this process uses a Cl ₂ / HBr main etch step followed by an SF ₆ etch step. A chlorination step is used to etch the main trench to the desired depth. This defines a trench profile with some taper and smooth sidewalls. The next chlorination step is used to etch the rest of the trench, rounding the bottom of the trench and further smoothing the silicon dangling bonds on the sidewalls of the trench. The fluorinated etching process is preferably performed at a relatively low fluorine flow rate, low pressure and low power to control smoothing and rounding. The difference in etch rate between the two chemical etches can balance the time of the two steps to achieve a more reliable and manufacturable process at an acceptable total etch time, The desired trench profile, sidewall roughness and trench bottom roundness are maintained.

In another embodiment shown in FIG. 42B, an improved method for silicon etching includes a main etching step based on fluorine and a second etching step based on chlorine followed by a second. One example of this process includes a main etch of SF ₆ / O ₂ followed by a Cl ₂ step. The fluorine step is used to etch the main trench occupying most of the depth. This step creates a trench with straight sidewalls and a rounded trench bottom. Depending on the situation, oxygen may be added to this step to provide sidewall stabilization and help maintain straight sidewalls by reducing side etching. Subsequent chlorine steps round the corners of the trench tips and reduce sidewall roughness. The fluorine step fast silicon etch rate increases process productivity by increasing the throughput of the etching system.

In yet another embodiment shown in FIG. 42C, an improved silicon etch process is obtained by adding argon to a fluorine-based chemical reaction. An example of chemistry used for the main etching step according to this example is SF ₆ / O ₂ / Ar. By adding argon to the etching step, ion bombardment is increased, resulting in a more physical etching. This is useful for controlling the tip of the trench and prevents the trench tip from becoming a concave angle. The addition of argon can increase the roundness of the trench bottom. An additional etching step may be required for sidewall smoothing.

Another example for an improved silicon etch process is as shown in FIG.
Fluorine-based chemistry is used with oxygen, but oxygen is removed from the starting point of the main etching step. One example of this process, using the SF _6, then step SF ₆ / O ₂ is continued. In the first stage of etching, there is a lack of sidewall stabilization due to lack of O ₂ . This results in an increased amount of lateral etching at the trench tip. Thereafter, a second etching step SF ₆ / O ₂ continues to etch the remainder of the trench depth, resulting in a straight profile and a rounded trench bottom. This results in a wider trench structure at the tip, sometimes referred to as a T-trench. An example of a device using a T-trench structure is the same applicant's US patent application Ser. No. 10/442, entitled “Structure and Method of Forming Trench MOSFET with Self-Alignment” by Robert Herrick. No. 670 (Agent reference number: 18865-131 / 17732-66850). The entire contents of the patent application are incorporated herein by reference. The time for the two main etch steps can be adjusted to achieve the desired etch for each portion of the T-trench (T portion tip, bottom, straight sidewalls). Additional processing can be used to round the tip corners of the T-trench and smooth the sidewalls of the trench. These additional processing methods include, for example, (1) a fluorine-based step at the end of the trench etch recipe or (2) a separate fluorine-based etch in a separate etch system or (3) a sacrificial oxidation Sacrificial oxide or other combinations. A chemical mechanical planarization (CMP) step can be used to remove the tip re-entrant portion of the trench profile. An H ₂ anneal can also be used to assist in rounding or creating a preferred slope trench profile.

  There are additional considerations for high voltage applications where trenches tend to be deeper. For example, due to the deep trench, the silicon etch rate is important to achieve a manufacturable process. The chemical etch for this application is usually fluorination chemistry. This is because hydrochloric acid chemical etching is too slow. A trench profile tapered from a straight line with smooth sidewalls is also desirable. Depending on the depth of the trench, the etching process is also required to have excellent selectivity for the mask layer. If the selectivity is poor, a thick mask layer is required. The thick mask layer increases the overall aspect ratio of the function. Side wall stabilization is also extremely important and requires that a delicate balance be achieved. Excessive sidewall stabilization causes the bottom of the trench to narrow to the point of closure, and excessive sidewall stabilization results in increased lateral etching.

In one embodiment, a deep trench etch process is provided to optimally balance all these requirements. According to this embodiment shown in FIG. 42E, the etching process is based on fluorine with graded O 2 (ramped 2), ramped power and / or ramped pressure. Chemical etching. One exemplary embodiment is to use the SF ₆ / O ₂ etch step in a manner that maintains the etch profile and silicon etch rate during etching. By tilting O ₂ , the sidewall surface stabilization throughput is controlled throughout the etch to prevent side etching from increasing (if there is too little surface stabilization) or the bottom of the trench is constricted. Prevent cutting (when there is too much surface stabilization treatment). An example of using a fluorine-based etch with a graded oxygen gas flow is self-assigned US Pat. No. 6, entitled “Integrated Circuit Trench Etch with Increasing Oxygen Flow” by Grebs et al. , 680,232. The entire contents of the patent are incorporated herein by reference. Increasing the power and pressure assists in controlling the ion flux density and maintaining the silicon etch rate. As the trench is etched deeper, the total etch time increases if the silicon etch rate becomes significantly slower during the etch. This results in low wafer throughput for the etching process. Also, inclining O ₂ results in helping to control the selectivity to the masking material. An exemplary process according to this embodiment, for example for trenches deeper than 10 μm, may have an O ₂ flow rate of 3-5 sccm / min at a power level of 10-20 watts / min and a pressure level of 2-3 mT / min. .

Another example of a deep trench etch process uses a more aggressive chemistry based on fluorine, such as NF ₃ . Since NF ₃ is more reactive than NF ₆ to silicon etching, a faster silicon etch rate is achieved by using NF ₃ . Additional gas may need to be added for sidewall surface stabilization and profile control.

In another embodiment, the SF ₆ / O ₂ process is followed by the NF ₃ etch step. According to this embodiment, the NF ₃ step is used to etch most of the trench depth at high silicon etch rates. An SF ₆ / O ₂ etch step is then used to surface treat the existing trench sidewalls and etch the remainder of the trench depth. In a variation of this embodiment shown in FIG. 42F, the NF ₃ and SF ₆ / O ₂ etch steps are performed in an alternating fashion. This provides a process with a higher silicon etch rate than the standing SF ₆ / O ₂ process. This keeps a balance between the fast etch rate step (NF ₃ ) and the step providing the sidewall surface stabilization process for profile control (SF ₆ / O ₂ ). This balance between steps controls the sidewall roughness. It is also necessary to ramp the O ₂ , power and pressure for the SF ₆ / O ₂ portion of the etch in order to provide sufficient sidewall surface stabilization to help maintain the silicon etch rate and control the etch profile. obtain. It will be appreciated by those skilled in the art that the various process steps described in connection with the above embodiments can be combined in different ways to achieve an optimal trench etch process. It should be understood that these etching steps can be used for any trench in any power device described herein, as well as other types of trenches used in other types of integrated circuits. .

  Prior to the trench etching process, a trench etch mask is formed on the surface of the silicon and patterned to expose the region to be trenched. As shown in FIG. 43A, in a typical device, the trench etch first etches the nitride layer 4305 and another thin layer of pad oxide 4303 prior to etching the silicon substrate. After the trench is formed during the formation of the oxide layer in the trench, the pad oxide 4303 can also grow on the edge of the trench while lifting the underlying nitride layer. This results in what is commonly referred to as a “bird's-eye” structure 4307 as the pad oxide grows locally near the trench edge below the nitride layer 4305. The next source region formed next to the trench edge under the pad oxide with a birdcage structure becomes shallower near the trench. This is highly undesirable. To remove the bird's beak effect, in one embodiment shown in FIG. 43B, a layer of non-oxidized material, such as polysilicon 4309, is sandwiched between the nitride layer 4305 and the pad oxide 4303. . Poly layer 4309 prevents pad oxide 4303 from being further oxidized during subsequent trench oxide formation. In another embodiment shown in FIG. 44A, after etching through nitride layer 4405 and pad oxide 4403, which defines the opening of the trench, a non-oxidized material 4405-1 such as nitride is formed on the surface structure. Is done. Thereafter, the protective layer 4405-1 is removed from the horizontal surface leaving a spacer along the vertical end face of the nitride-pad oxide structure as shown in FIG. 44B. The nitride spacer protects the pad oxide 4403 from further oxidation during the next step of reducing the birdcage effect. In another embodiment, both embodiments shown in FIGS. 43B and 44B can be combined to reduce the degree of birdcage formation. That is, the polysilicon layer can be sandwiched between the pad oxide and the underlying nitride in addition to the spacer resulting from the process described in connection with FIGS. 44A and 44B. Other variations are possible including, for example, adding other layers (eg, oxides) on the nitride surface to help nitride selectivity while etching the silicon trench.

  As described above in connection with various transistors having a shielded gate structure, the dielectric layer insulates the shield electrode from the gate electrode. Interelectrode dielectric layers, sometimes referred to as inter-poly dielectrics or IPDs, are robust and reliable so that they can withstand potential differences that may exist between the shield electrode and the gate electrode. It must be formed in some way. Referring to FIGS. 31E, 31F and 31G, a simplified flow for related process steps is shown. After the etch back of the shield poly 3111 inside the trench, the shield dielectric layer 3108 is etched back to the same level as the shield poly 3111 (FIG. 31F). Thereafter, a gate dielectric layer 3108a is formed on the top surface of the silicon, as shown in FIG. 31G. It is this step that forms the IPD layer. The artifact of recess etching of the shield dielectric is the formation of a shallow trench on the top surface of the shield dielectric and is left on either side of the shield electrode. This is shown in FIG. 45A. The resulting structure with non-planar topography can cause conformality problems, especially in the next filling step. In order to eliminate such problems, various improved methods for forming an IPD have been shown.

  According to one embodiment, after recess etching of the shield dielectric, a polysilicon (poly) liner 4508P is used, as shown in FIG. 45B, using, for example, a low pressure chemical vapor deposition (LPCVD) process. Is deposited. Alternatively, the polyliner 4508P is formed only over the shield poly and shield dielectric, leaving the trench sidewalls substantially poly free by using selective growth over poly or balanced sputtering of poly. Polyliner 4508P is then oxidized to silicon dioxide. This is done by a conventional thermal oxidation process. In embodiments where no poly is formed on the trench sidewalls, this oxidation step also forms a gate dielectric layer 4508G. After etching the oxidized poly layer from the trench sidewalls, a thin layer of gate dielectric 4508G is formed and the remaining trench cavities are filled with gate electrode 4510, as shown in FIG. 45C. The advantage of this process is that the poly is deposited conformally. This minimizes voids and other defects, and a flatter surface is formed once the poly is deposited over the shield dielectric and shield electrode. The result is an improved IPD layer that is more robust and reliable. By lining the trench sidewalls and adjacent silicon surface area with polysilicon prior to oxidation, the next oxidation step is minimized by reducing mesa consumption and unnecessarily widening the trench width. The

  In another embodiment, in the simplified cross-sectional views shown in FIGS. 46A, 46B, and 46C, the cavities inside the trench resulting from the recess etch of the shield poly are filled with dielectric fill material 4608F. The dielectric fill material 4608F has an etch rate similar to the etch rate of the shield dielectric 4608S, which may include high density plasma (HDP) oxide deposition, vapor deposition (CVD) or spin-on glass (SOG). It can be performed using any of the steps. The planarization step is then continued and a plane is obtained at the top of the trench. Thereafter, dielectric fill material 4608F and shield dielectric material 4608S are uniformly etched back so that a layer of insulating material having the required thickness remains on one side of shield electrode 4611 as shown in FIG. 46B. Thereafter, the trench sidewalls are lined with a gate dielectric, after which the remaining trench cavities are filled with a gate electrode, as shown in FIG. 46C. The result is a highly conformal IPD layer with no local non-uniformity.

  An exemplary embodiment for another method of forming a high quality IPD is shown in the simplified cross-sectional views of FIGS. 47A and 47B. After the shield dielectric layer 4708S is formed inside the trench and the cavity is filled with the shield poly 4711, a shield poly etch back step is performed, and the shield poly is buried inside the trench. In this embodiment, the recess etching of the shield poly leaves more poly in the trench, so that the upper surface of the buried shield poly becomes higher than the final target depth. The extra poly thickness on the top surface of the shield poly is designed to be approximately the same as the IPD target thickness. Thereafter, this upper part of the shield electrode is physically modified or chemically transformed to further increase its oxidation rate. A method for chemically converting or physically modifying the electrode is performed by ion-implanting impurities such as fluorine or argon ions into the polysilicon to increase the oxidation rate of the shield electrode, respectively. The implantation is preferably performed at 0 degrees. That is, it is preferably performed at right angles to the shield electrode as shown in FIG. 47A so that the trench sidewall is not physically altered or chemically transformed. Next, the shield dielectric 4708S is etched to remove the dielectric from the trench sidewalls. This shield dielectric recess etch results in a slight recess in the remaining shield dielectric adjacent to shield electrode 4711 (similar to that shown in FIG. 45A). The conventional oxidation step is then continued so that the altered top of shield poly 4711 oxidizes at a faster rate than the trench sidewalls. This results in the formation of a substantially thicker insulator 4708T in the portion across the shield electrode than in the portion along the sidewall of the trench silicon surface. A thick insulator 4708T across the shield electrode forms the OPD. The altered poly oxidizes laterally while simultaneously compensating for some recesses formed in the top surface of the shield dielectric as a result of the shield dielectric recess etch. Thereafter, conventional steps are performed to form a gate electrode in the trench, and the structure shown in FIG. 47B is obtained. In one embodiment, the shield electrode is varied such that the IPD to gate oxide thickness ratio ranges from 2: 1 to 5: 1. As an example, if a 4 to 1 ratio is selected, about 500 A of gate oxide is formed along the trench sidewall for about 2000 A of IPD formed over the shield electrode.

  In another embodiment, the physical modification or chemical conversion step is performed after the shield dielectric recess etch. That is, the shield oxide 4708S is etched to remove the oxide from the trench sidewalls. This exposes the top of the silicon and shield electrode to the physical modification or chemical transformation methods described above. With exposed trench sidewalls, the modification step is limited to the horizontal plane, i.e., the silicon mesa and shield electrode. For example, changing methods such as dopant ion implantation are performed at 0 degrees (perpendicular to the shield electrode) so as not to physically modify or chemically transform the trench sidewalls. Thereafter, conventional steps are performed to form a gate electrode in the trench resulting in a thick dielectric over the shield electrode.

  Yet another example of forming an improved IPD layer is shown in FIG. According to this embodiment, a thick insulating layer 4808T made of, for example, oxide is formed over the buried shield oxide 4808S and shield electrode 4811. Thick insulating film 4808T is selectively formed using a directional deposition method such as high density plasma (HDP) or plasma enhanced chemical vapor deposition (PECVD) (ie, filling from bottom to top). The directional deposition method provides substantially thicker insulation along the horizontal plane (ie, over the shield electrode and shield oxide) than the portion along the vertical plane (ie, across the trench sidewalls), as shown in FIG. Causes body formation. An etching step is then performed to remove the oxide from the sidewalls, leaving enough oxide over the shield polysilicon. Thereafter, conventional steps are performed to form a gate electrode in the trench. The advantage of this embodiment, other than obtaining a conformal IPD, is that the IPD is formed through a deposition process rather than an oxidation process, thus preventing mesa breakdown and trench spreading. Another advantage of this method is the roundness obtained at the top corner of the trench.

  In another embodiment, after the shield dielectric and shield poly are placed, a thin layer of screen oxide 4908P is grown inside the trench. A layer of silicon nitride 4903 is then deposited over the screen oxide 4908P as shown in FIG. 49A. Thereafter, the silicon nitride layer 4903 is isotropically etched so that it is removed from the bottom surface of the trench (ie, on the shield poly) but not from the trench sidewalls. The resulting structure is shown in FIG. 49B. The wafer is then exposed to an oxidizing environment and a thick oxide 4908T will form a shielded polysilicon surface, as shown in FIG. 49C. Since the nitride layer 4903 is resistant to oxidation, no significant oxidation occurs along the trench sidewalls. Thereafter, the nitride layer 4903 is removed by wet etching using, for example, hot phosphoric acid. As shown in FIG. 49D, conventional processes are continued to form the gate oxide and gate electrode.

  In some embodiments, the formation of the IPD layer includes an etching step. For example, for embodiments where the IPD film is deposited over the topography, a film layer that is significantly thicker than the desired final IPD thickness may be deposited first. This is done to obtain a planar film layer, minimizing the indentation of the starting layer in the trench. The thick film trench (which completely fills the trench and extends across the silicon surface) is then etched to reduce its thickness to the target thickness of the IPD layer. According to one embodiment, the IPD etching process is performed in at least two etching steps. The first step is: The purpose is to flatten the film to the silicon surface. The second step is to try to place the IPD layer at the desired depth in the trench. In this second step, the etch selectivity of the IPD film to silicon is important. During the recess etch step, a silicon mesa is exposed and buried in the trench, as well as a silicon trench sidewall such as an IPD layer. The silicon loss in the mesa affects the actual trench depth, and if a T-trench is required, the T depth is also affected.

  In one exemplary embodiment shown in FIG. 50A, an anisotropic plasma etch step 5002 is used to planarize the IPD film down to the silicon surface. An exemplary etch rate for plasma etching may be 5000 A / min. Then isotropic wet etching 5004 is continued to provide an IPD in the trench. Wet etching uses a controlled solution that is selective to silicon so as not to attack the silicon sidewalls when exposed and to provide a reproducible etch to obtain a specific recess depth. Preferably, it is done. An exemplary chemistry for a wet etch may be a 6: 1 buffered oxide etch (BOE) that achieves an etch rate of about 1100 A / min at 25 ° C. Commonly assigned US Pat. No. 6,465,325 by Rodney Ridley provides details on exemplary plasma and wet etch recipes suitable for this process, the entire contents of which are incorporated herein by reference. The first plasma etch step results in less dip of the IPD layer across the trench than the wet etch. The second wet etching process for the recess etching results in better selectivity to silicon and less damage to silicon than that provided by plasma etching. In another example shown in FIG. 50B, a chemical mechanical planarization (CMP) process is used to planarize the IPD film to the silicon surface. Next, wet etching is continued to provide the IPD in the trench. The CMP process results in less dent of the IPD layer across the trench. The wet etch step relative to the recess etch results in good selectivity to silicon and less damage to silicon (caused by CMP). Other combinations of these steps are possible.

  Formation of a high quality insulating layer is desirable in structures other than IPD including trenches and planar gate dielectrics, interlayer dielectrics, and the like. The most commonly used dielectric is silicon dioxide. There are several parameters that define a high quality oxide film. The main properties are in particular uniform thickness, good consistency (low interface trap density), high electric field breakdown strength and low leakage level. One factor that affects many of these properties is the rate at which the oxide grows. It is desirable to be able to accurately control the oxide growth rate. During thermal oxidation, there is a gas phase reaction with charged particles at the wafer surface. In one embodiment, the method of controlling oxidation is performed by influencing charged particles, usually silicon and oxygen, by application of an external potential to the wafer to increase or decrease the rate of oxidation. This differs from plasma oxidation in that plasma (along with reactive species) is not formed on the wafer. Also, according to this embodiment, the gas is not accelerated towards the surface, it simply does not react with the surface. In an exemplary embodiment, a reactive ion etch (RIE) chamber with high temperature performance can be used to adjust the required energy level. The RIE chamber is not used for etching but is used to apply a DC bias to control the energy required to slow down the oxidation or stop the oxidation. FIG. 51 is a flowchart for an exemplary method according to this embodiment. Initially, the RIE chamber is used (5100) to apply a DC bias to the wafer in a test environment. After defining the potential energy required to suppress the surface reaction (5200), a sufficiently large external bias is applied (5200) to prevent oxidation from occurring. Thereafter, even the oxidation rate at ultra high temperatures can be controlled (5130) by manipulating an external bias, such as pulsing or other methods. This method allows the advantages of high temperature oxidation (good oxide flow, low stress, differentiated growth in various crystal orientations, etc.) without the disadvantages of rapid and non-uniform growth.

  Although the method as described above in connection with FIG. 51 can improve the quality of the resulting oxide layer, oxide reliability remains a concern, particularly in trench-gate devices. One of the main degradation mechanisms is due to the high electric field at the corner of the trench, which results from the local thinning of the gate oxide at the corner of the trench. This causes high gate leakage current and low gate oxide breakdown voltage. This effect is expected to become more severe when the trench device is further tuned to reduce on-resistance and when the reduced gate voltage requirement results in a thin gate oxide.

In one embodiment, gate oxide reliability concerns are mitigated by using a dielectric having a higher dielectric constant (high-K dielectric) than silicon dioxide. This allows similar threshold voltages and transconductances with fairly thick dielectrics. According to this embodiment, a high-K dielectric reduces gate leakage and increases gate dielectric breakdown voltage without degradation of device on-resistance or drain breakdown voltage. High-K materials exhibiting the required thermal stability, suitable interface state density to be integrated into trench-gate devices and other power devices are Al ₂ O ₃ , HfO ₂ , Al _x Hf _y O. _z , TiO ₂ and ZrO ₂ .

  As described above, in order to improve the switching speed of the trench gate power MOSFET, it is desirable to minimize the gate-drain capacitance Cgd of the transistor. Using a thicker dielectric layer at the bottom of the trench compared to the trench sidewall is one of the above-described methods for reducing Cgd. One method of forming a thick bottom oxide layer includes forming a thin layer of screen oxide along the sidewalls and bottom of the trench. The thin oxide layer is then covered with a layer of an oxidation inhibiting material such as nitride. Thereafter, all nitride is removed from the horizontal bottom surface of the trench, but the nitride layer is isotropically etched so that the sidewalls of the trench remain covered with the nitride layer. After removing the nitride from the bottom of the trench, an oxide layer having a desired thickness is formed at the bottom of the trench. A thin channel oxide layer is then formed after removing nitride and screen oxide from the trench sidewalls. The method of forming a thick bottom oxide and variations thereof are described in considerable detail in commonly assigned US Pat. No. 6,437,386 by Hurst et al. The content arithmetic of the patent is incorporated herein by reference. Other methods of forming thick oxide at the bottom of the trench, including selective oxide deposition, are described in Murphy, US Pat. No. 6,444,528, the entire contents of which are incorporated herein by reference. Incorporated.

In one embodiment, an improved method of forming a thick oxide at the bottom of the trench is a subatmospheric pressure CVD (SACVD) process. According to this method (exemplary flowchart shown in FIG. 52), after etching the trench (5210), SACVD is used to deposit an oxide film that is very conformal (5220), which Is performed using, for example, hot tetraethyl silicate (TEOS) that fills the trench without voids in the oxide. The SACVD step may be performed at an exemplary temperature in the range of about 450 ° C. to 600 ° C. with a sub-atmospheric pressure in the range of 100 to 700 torr. The ratio of TEOS (mg / min) to ozone (cm ³ / min) can be set, for example, in the range of 2 to 3, but is preferably about 2.4. By using this process, an oxide film having a thickness in the range of about 2000A to 10,000A or more can be formed. These numbers are for illustrative purposes only and may vary depending on other process requirements such as specific process requirements and the atmospheric pressure at the location of the production facility. The optimum temperature can be obtained by balancing the deposition rate with the quality of the resulting oxide layer. At high temperatures, the deposition rate is slowed, which can reduce film shrinkage. Such film shrinkage results in gap formation in the oxide film in the middle of the trench along the thin layer.

  After the oxide film is formed, the oxide film is etched back from the silicon surface and from the interior of the trench, leaving a relatively flat layer of oxide having the desired thickness at the bottom of the trench (5240). . This etching can be performed by using, for example, dilute hydrofluoric acid or a wet etching process or a combination of a wet etching process and a dry etching process. Since oxides formed by SACVD tend to be porous, they absorb environmental humidity after deposition. In a preferred embodiment, a densification step 5250 is performed following the etch back process to improve this effect. Densification can be performed, for example, by heat treatment at 1000 ° C. for about 20 minutes.

  Another advantage to this method is the ability to mask off the trench edges during the SACVD oxide etchback step, leaving an oxide filled termination trench. That is, for the various embodiments of the termination structure described above, including dielectric filled trenches, the same SACVD step can be used to fill the termination trench with oxide. Also, by masking the field termination region during etch back, the same SACVD process step results in the formation of field oxide in the termination region and eliminates the required process of forming thermal field oxide. In addition, this process allows both the terminating dielectric layer and the thick bottom oxide to be completely reworked if significantly etched. The reason is that silicon is not consumed in the thermal oxidation process, but instead is applied to both locations during SACVD deposition.

  In another embodiment, another method of forming a thick oxide at the bottom of the trench uses a directional TEOS process. According to this example (exemplary flowchart shown in FIG. 53), the conformal properties of TEOS are combined with the directional nature of plasma enhanced chemical vapor deposition (PECVD) to selectively deposit oxide. (5310). This combination allows a greater deposition rate in the horizontal plane than in the vertical plane. For example, an oxide film deposited using this process may have a thickness of about 2500 A at the bottom of the trench and an average thickness of about 800 A at the trench sidewalls. The oxide is then isotropically etched until all the oxide is removed from the sidewalls, leaving an oxide layer at the bottom of the trench. The etching process includes an oxide surface dry etch step 5320 followed by a wet buffered oxide etch (BOE) step 5340. For the exemplary embodiment described herein, after etching, an oxide layer having a thickness of, for example, 1250 A remains at the bottom of the trench, and all sidewall oxide has been removed.

In certain embodiments, the dry etching of the oxide surface concentrates on the top surface of the structure and accelerates to etch the oxide from the top region, but etches the oxide at the bottom of the trench at a much slower rate. This type of etching, referred to herein as a fog etch, requires careful adjustment of the etch state and chemical etching to provide the desired selectivity. In one example, this etch is performed at a relatively low power and low pressure using a plasma etcher with a top power source, such as LAM4400. Exemplary values for power and pressure can be anywhere in the range of 200 watts to 500 watts and 250 to 500 millitorr, respectively. Different chemical etches can be used. In one embodiment, a combination of a fluorine compound and chlorine, for example C2F6, mixed at an optimal ratio of, for example, about 5: 1 (eg, C ₂ F ₆ at 190 sccm and Cl at 40 sccm) is a desired choice. Give sex. It is unusual to use chlorine as part of oxide chemical etching. The reason is that chlorine is commonly used for metal or polysilicon etching and usually prevents oxide etching. However, this combination works well for the purpose of this type of selective etching. The reason is, C2 F6 is to etch the oxide near the top surface aggressive (in the upper surface, high energy allows the C ₂ F ₆ overcomes the effects of chlorine), the closer to the bottom of the trench, Chlorine slows down the etching rate. This initial dry etch step 5320 is followed by possibly a clean etch 530 prior to the BOE dipping 5340. It should be understood that according to this embodiment, optimal selectivity is achieved by fine tuning pressure, energy and chemical etching that can vary depending on the plasma etching machine.

  The PECVD / etching process according to this embodiment can be repeated one or more times as necessary so that the bottom oxide has the target thickness. This process results in the formation of thick oxide at the horizontal mesa surface between the trenches. This oxide can be etched after polysilicon is deposited in the trench and etched back at the surface, so that the oxide at the bottom of the trench is protected from the next etching step.

  Other methods of selectively forming a thick oxide at the bottom of the trench are possible. FIG. 54 shows a flow chart for one exemplary method that uses high density plasma (HDP) to prevent oxide from forming on the trench sidewalls (5410). The characteristic of the HDP method is that etching is performed while vapor deposition, and as a result, compared with the directional TEOS method, less oxide is formed on the trench side wall than the oxide at the bottom of the trench. A wet etch (step 5420) is then used to remove or clean the oxide from the sidewalls, leaving a thick oxide at the bottom of the trench. The advantage of this process is that the profile at the top of the trench is inclined (5510) from the trench (5500) as shown in FIG. 55, realizing void-free polyfilling. The fog etching described above (step 5430) can be used to etch some oxide from the top before filling the poly (step 5440) and needs to be etched from the top after the poly etch. There will be less oxide. The HDP process can also be used to deposit oxide between two poly layers in a trench with a buried electrode (eg, a trench MOSFET with a shield gate structure).

  According to yet another method shown in FIG. 56, a selective SACVD process is used to form a thick oxide at the bottom of the trench. This method takes advantage of SACVD's ability to be selective when the TEOS to ozone ratio is lower. The oxide has a very slow deposition rate on silicon nitride, but easily deposits on silicon. As the ratio of TEOS to ozone decreases, deposition becomes more selective. According to this method, after etching the trench (5610), a pad oxide is grown on the silicon surface of the trench array (5620). A thin layer of nitride is then deposited on the pad oxide (5630). Anisotropic etching is then continued to remove nitride from the horizontal surface and leave nitride on the trench sidewalls (5640). Thereafter, selective SACVD oxide is deposited (5650) on the horizontal plane including the trench bottom at a temperature of about 405 ° C., for example at a ratio of TEOS to ozone of about 0.6. Thereafter, if necessary, the SACVD oxide is densified by heat treatment (5660). An oxide-nitride-oxide (ONO) etch is then performed (5670) to remove nitride and oxide on the trench sidewalls.

  As already explained, one reason to use a thick oxide layer at the bottom of the gate trench compared to its sidewalls is to reduce the Qgd or gate-drain charge (improved switching speed). ). The same reason provides that the trench depth is approximately the same as the well junction depth in order to minimize the overlap of the trench into the drift region. In one embodiment, a method for forming a thick dielectric layer at the bottom of a trench extends the thick dielectric layer on the sides of the trench. This allows the bottom oxide thickness to be independent of the trench depth and well junction depth, and allows the poly in the trench and trench to be deeper than the well junction without significantly increasing Qgd. To.

  A method for forming a thick bottom dielectric layer according to this method is illustrated in FIGS. FIG. 57A shows a simplified and partial cross-sectional view of a trench covered with a thin layer of pad oxide 5710 and a nitride layer 5720 after etching to cover only the sidewalls of the trench. This allows the pad oxide 5710 etch to expose the silicon at the bottom of the trench and the top surface of the chip, as shown in FIG. 57B. The exposed silicon is then anisotropically etched, resulting in the structure shown in FIG. 58A (both top silicon and silicon at the bottom of the trench are both removed to the desired depth). In another embodiment, the top silicon can be masked so that only the bottom of the trench is etched during the silicon etch. Next, an oxidation step is performed to grow a thick oxide 5730 in a location not covered by the nitride layer 5720, resulting in the structure shown in FIG. 58B. The oxide thickness can be, for example, about 1200A to 2000A. Thereafter, the nitride layer is removed and the pad oxide 5710 is etched. By etching the pad oxide, the thick oxide 5730 becomes somewhat thinner. The remaining steps can use standard flow to form the gate poly and well and source junctions, resulting in the exemplary structure shown in FIG.

  As shown in FIG. 59, the resulting gate oxide includes a bottom thick layer 5730 that extends above the well junction in region 5740 along the sidewalls of the trench. In some embodiments, channel doping in the well region along the trench is stepped with low doping near the drain side 5740, which is typically a low threshold compared to the region near the source. Has voltage. Thus, by extending the thick oxide along the side of the trench that overlaps the channel in region 5740, the threshold voltage of the device does not increase. That is, this embodiment allows optimization of the well junction depth and sidewall oxide to minimize Qgd without adversely affecting the on-resistance of the device. This method of forming a thick oxide at the bottom of the trench, like any other trench gate device, can be applied to the various devices described above, including shielded gates, dual gates combined with charge control structures. Recognized by those skilled in the art.

Those skilled in the art will also recognize that the above-described steps of forming a thick oxide at the bottom of the trench and the steps described above for IPD can be used in the formation of any trench gate transistor described herein. Other variations on these processes are possible. For example, as in the process described in connection with FIGS. 47A and 47B, chemical conversion or physical modification of silicon can increase its oxidation rate. According to one such exemplary embodiment, halogen ion species such as fluorine and bromine are implanted at 0 degrees into the silicon at the bottom of the trench. The implantation may occur at an exemplary energy of about 15 KeV or less, an exemplary amount greater than 1E ¹⁴ (eg, 1E ^{15 to} 5E ¹⁷ ), and an exemplary temperature in the range of 900 ° C. to 1150 ° C. In the halogen implanted region at the bottom of the trench, the oxide grows at an accelerated rate compared to the trench sidewall.

  Many of the trench devices described above have trench sidewalls that are doped for charge conditioning purposes. For example, all of the embodiments shown in FIGS. 5B, 5C and FIGS. 6-9A have several types of trench sidewall doping structures. Sidewall doping is somewhat limited by the physical constraints of narrow and deep trenches and / or vertical sidewalls of the trenches. A gaseous source or angular implantation may be used to form the doped regions of the trench sidewalls. In one embodiment, the improved trench sidewall doping method utilizes a plasma doping method or a pulsed plasma doping method. This method utilizes a pulsed voltage applied to a wafer surrounded by a plasma of dopant ions. The applied voltage accelerates ions from the cathode sheath toward the wafer and into the wafer. The applied voltage is pulsed and continues for the duration until the desired amount is achieved. This method allows many of these trench devices to be performed with a conformal doping technique. Furthermore, the high throughput of this process reduces the overall cost of the manufacturing process.

  The use of plasma doping or pulsed plasma doping is not limited to trench charge conditioning structures, but can also be applied to other structures including trench termination structures and drain, source or body bonds in which the trenches are formed. . For example, this methodology is used to dope trench sidewalls of shielded trench structures as described in connection with FIGS. 4D, 4E, 5B, 5C, 6, 7, 8, and 9A. Can be done. Furthermore, this method can be used to create a uniformly doped channel region. When the power device is reverse biased, the penetration of the depletion region into the channel region (p-well junction) is controlled by the charge concentration on both sides of the junction. When the doping concentration in the epilayer is high, depletion in the junction requires a longer channel length than is required to allow the punch-through phenomenon to limit the breakdown voltage or to maintain a low on-resistance. To do. A higher channel doping concentration may be required (threshold may be increased) to minimize depletion into the channel. Since the threshold is defined by the peak concentration under the source in the trench MOSFET, a uniform doping concentration in the channel can give a good tradeoff between channel length and breakdown.

  Other methods that can be used to obtain a more uniform channel concentration include forming channel junctions using epitaxial processes, multiple energy injections, and other methods of creating step junctions. Another method uses a starting wafer with a lightly doped cap layer. In this method, the correction is minimized and used to create a channel doping profile with a more uniform up diffusion.

  Trench devices can take advantage of the fact that the threshold is defined by the channel doping concentration along the trench sidewalls. A process that allows a high doping concentration to be removed from the trench while maintaining a low threshold helps to suppress the punch-through mechanism. Providing p-well doping prior to the gate oxidation step allows segregation of p-type impurities (eg, boron) in the well into the trench oxide, reducing the concentration in the channel. As a result, the threshold value is lowered. By combining this with the method described above, a shorter channel length can be provided without the punch-through phenomenon.

  Some power applications require measuring the amount of current flowing through the power transistor. This is done by separately measuring a portion of the total device current that is used to estimate the total current flowing through the device. The total device current separator flows through a current detector or current detector that generates a signal indicative of the amount of the separated current, and is then used to determine the total device current. This process is commonly known as a current mirror. The current detection transistor is usually assembled integrally with a power device, and both share a common substrate (drain) and gate. FIG. 60 is a schematic diagram of a MOSFET 6000 having a current detection device 6002. The current flowing through the main MOSFET 6000 is divided in proportion to each active region between the main transistor and the current detector. Thus, the current flowing through the main MOSFET is calculated by measuring the current through the detector and multiplying that measurement by the active area ratio.

  Various methods of separating the current sensing device from the main device are self-patented by Yedinak et al. Entitled "Method of separating current sensing in power devices while maintaining a continuous strip electrolyser". Application 10 / 315,719. The entire contents of the patent application are incorporated herein by reference. Examples of integrating the sensing device with various power devices, including those having charge control structures, are described below. According to one embodiment, in a power transistor having a charge adjustment structure and a monolithically integrated current detection device, the current detection region is preferably formed with the same continuous MOSFET structure as the charge adjustment structure. Without maintaining conduction in the charge regulation structure, the breakdown voltage of the device will be reduced by a charge mismatch that completely depletes the voltage support region. FIG. 61A shows one exemplary embodiment for a charge adjustment MOSFET 6100 having a planar gate structure and an isolation current detection structure 6115. In this embodiment, the charge control structure has a pillar 6126 with opposite conductivity (p-type in this embodiment) formed inside the drift region 6104 (n-type). The p-type pillar 6126 can be formed, for example, as a trench filled with doped polysilicon or epi. As shown in FIG. 61A, the current regulation structure remains conductive under the current detection structure 6115. The detection pad metal 6113 covering the surface area of the current detection device 6115 is electrically separated from the source metal 6116 by the dielectric region 6117. It should be understood that a current sensing device having a similar structure can be integrated with any other power device described herein. For example, FIG. 61B shows how the current sensing device is integrated with a trench MOSFET with a shield gate (charge adjustment can be obtained by adjusting the depth of the trench and biasing the shield poly inside the trench). Indicates what will be done.

  There are many power applications where it is desirable to integrate the diode on the same chip of the power transistor. Such applications include temperature sensing, electrostatic discharge (ESD) protection, active clamping and partial pressure, among others. With respect to temperature detection, for example, one or more series connected diodes are integrated with the power device so that the anode and cathode terminals of the diodes are either drawn to separate bond pads or are conductively interconnected. Connected to a monolithic control circuit component that uses the connection. The temperature is detected by a change in the quasi-voltage (Vf) of the diode. For example, with appropriate wiring to the gate terminal of the power transistor, the gate voltage is pulled low, reducing the current flowing through the device until the desired temperature is obtained.

  FIG. 62A shows an exemplary embodiment for a MOSFET 6200A having a series temperature sensing diode. MOSFET 6200A has a diode structure 6215 in which doped polysilicon with alternating conductivity forms three series temperature sensing diodes. In this illustrative example, the MOSFET portion of device 6200A uses a charge adjustment trench filled with p-type epi to form a region of opposite conductivity within n-type epi drift region 6204. As shown, the charge conditioning structure preferably remains conductive under the temperature sensing diode structure 6215. The diode structure is formed on a field dielectric (oxide) layer 6219 on the surface of silicon. The p-type junction isolation region 6221 can extend under the dielectric layer 6219 as needed. A device 6200B without this p-type junction is shown in FIG. 62B. To confirm that a forward biased device in series is obtained, the shorting metal 6223 is used to short the P / N + junction that is reverse biased. In one embodiment, p + is implanted and diffused across the junction to form an N + / P / P + / N + structure. In this structure, p + appears under the shorting metal 6223 to obtain an improved ohmic contact. N + with the opposite conductivity is also diffused across the N / P + junction, forming a P + / N / N + / P + structure. This type of temperature sensing diode structure can be used in any of a variety of power devices in combination with many other characteristics described herein. FIG. 62C shows, for example, a MOSFET 6200C having a shield trench gate structure, and shield poly can be used for charge adjustment.

  In other embodiments, asymmetric ESD protection is provided by using a similar isolation method, such as that shown in device 6200 for the temperature sensing diode. For the purpose of ESD protection, one end of the diode structure is connected to the source terminal and the other end is connected to the gate terminal of the device. Alternatively, contrasting ESD protection is obtained by not shorting any of the consecutive N + / P / N + junctions, as shown in FIGS. 63A and 63B. The exemplary MOSFET 6300A shown in FIG. 63A utilizes a planar gate structure and uses pillars with opposite conductivity for charge adjustment, whereas the exemplary MOSFET 6300B shown in FIG. 63B has a shielded gate structure. A trench gate device having: In order to prevent non-uniformities in charge adjustment, the charge adjustment structure is continued under the bond pad metal of the gate and the bond pads of other control elements.

An exemplary ESD protection circuit is shown in FIGS. 64A-64D, where the primary device (the gate is protected by the diode structure described above) uses either charge regulation or other methods. It can be any of the power devices described in this application. FIG. 64A shows a simplified diagram for asymmetrically isolated polydiode ESD protection, while FIG. 64B shows a standard continuous isolated polydiode ESD protection circuit. The ESD protection circuit shown in FIG. 64C uses NPN transistors for BV _cer snap-back. The subscript _cer in BV _cer refers to a reverse-biased collector-emitter bipolar transistor junction, and the connection to the base uses a resistor to control the base current. The low resistance causes most of the emitter current to be removed through the base and prevents the emitter-base junction from being turned on, i.e., injecting minority carriers back into the collector. The on state can be set by a register value. When carriers are injected back into the collector, the sustain voltage between the emitter and collector decreases (a phenomenon called snapback). The current at which BV _cer snapback is triggered can be set by adjusting the value of the base-emitter resistance R _BE . FIG. 64D shows an ESD protection circuit using a silicon controlled rectifier or SCR and a diode as shown. By using the cathode short-circuit structure of the gate, the trigger current can be controlled. The diode breakdown voltage can be used to offset the voltage that the SCR latches. The monolithic diode structure described above can be used for any of these and other ESD protection circuits.

  In some power applications, an important operating characteristic of a power switching device is its equivalent series resistance or ESR, which is a measure of the impedance of the switching terminal or gate. For example, in a synchronous buck converter using a power MOSFET, a lower ESR helps reduce switching losses. In the case of trench gate MOSFETs, their gate ESR is mainly defined by the dimensions of the trench filled with polysilicon. For example, the length of the gate trench can be constrained by package limitations such as minimum wire bond pad size. By applying a silicide film to polysilicon, the gate resistance is reduced. However, the use of poly applied silicide in trench MOSFETs poses many challenges. In a standard planar distributed MOS structure, the gate poly can be treated with silicide after the junction is buried and driven to the respective depth. It is more difficult to apply silicide to trench gate devices where the gate poly is recessed. The use of conventional silicide limits the maximum temperature and the wafer is subjected to post silicide processing to less than about 900 ° C. When diffusion regions such as sources, drains and wells are formed, this creates considerable constraints at the manufacturing process stage. The most typical metal used for silicides is titanium. Other metals such as tungsten, tantalum, cobalt and platinum can also be used, allowing higher thermal budget post silicide processing that provides more processing latitude. Gate ESR can also be reduced by various layout methods.

  Various embodiments for forming charge-regulated power switching devices with low ESR are described below. In one embodiment shown in FIG. 65, step 6500 includes forming a trench with a lower electrode formed at the lower portion of the trench for shielding and / or charge adjustment purposes (see FIG. Step 6502). Next, the process of depositing and etching the IPD layer is continued (step 6504). The IPD layer can be formed by well-known processes. Alternatively, any of the processes described above in connection with FIGS. 45-50 can be used to form the IPD layer. The top electrode or gate poly is then deposited and etched at step 6506 using well known processes. Next, the well and source regions are continued to be buried and driven (step 6508). It is after step 6508 that the silicide is applied to the gate poly at step 6510. Thereafter, dielectric deposition and planarization continues at step 6512. In a variation of this process, step 6512, where the dielectric regions are deposited and planarized, is performed first, after which contact holes are opened to reach the source / body and gate. Thereafter, silicide contacts are formed. These two embodiments rely on high concentration body buried regions that are activated by low temperature annealing below the transition point of the silicide film.

  In other embodiments, the poly gate is replaced by a metal gate. According to this embodiment, the metal gate is formed using a parallel source, for example by depositing titanium, improving the filling performance of the trench structure. After applying the metal gate, once the junction is buried and driven, the dielectric options include HDP and TEOS to insulate the gate from the source / body contacts. In another embodiment, a damascene or dual damask pattern approach with various metal options from aluminum to copper top metal is used to form the gate terminals.

The layout of the gate conductor can also affect the gate ESR and the overall switching speed of the device. In another embodiment shown in FIGS. 66A and 66B, the layout method combines a vertical poly stripe with silicide applied with a recessed trench poly to reduce gate ESR. Referring to FIG. 66A, a highly simplified device structure 6600 is shown with a silicide-covered polyline 6604 extending along the surface of the silicon perpendicular to the trench stripe 6602. FIG. 66B shows a simplified cross-sectional view of device 6600 along the AA ′ axis. Polyline 6604 coated with silicide is in contact with the gate poly at the intersection with the trench. The plurality of polylines 6604 coated with silicide extend on the silicon surface and reduce the resistivity of the gate electrode. This and other layout methods made possible by, for example, a process having two or more layers of interconnect can be used to improve gate ESR in any of the trench gate devices described herein. Can be done.
Due to the dramatic reduction in device on-resistance, as provided by circuit applications such as the various devices and process methods described herein, the chip area occupied by the power device can be reduced. As a result, monolithic integration of these high voltage devices with low voltage logic and control circuitry becomes more feasible. In normal circuit applications, the types of functions that can be integrated on the same chip as the power transistor include power control, detection, protection and interface circuits. An important consideration in monolithic integration of power devices with other circuits is the method used to electrically isolate the high voltage power device from the low voltage logic or control circuitry. There are many well-known methods for accomplishing this, including junction isolation, dielectric isolation, silicon on insulator, and the like.

In the following, many circuit applications for power switching are described, where various circuit components can be integrated on the same chip to varying degrees. FIG. 67 shows a synchronous step-down converter (DC-DC converter) that requires a low-voltage device. In this circuit, the n-channel MOSFET Q1, commonly referred to as a high-side switch, is designed to have a moderately low on-resistance, but to have a fast switching speed to minimize power loss. Designed to. MOSFET Q2, commonly referred to as a low-side switch, is designed to have very low on-resistance and moderately high switching speed. FIG. 68 shows another DC-DC converter that is more suitable for medium to high voltage devices. In this circuit, the main switching device Qa exhibits a fast switching speed and a high blocking voltage. This circuit uses a low current flow through the transistor Qa and a transformer that allows it to have a moderately low on-resistance. Low to very low on-resistance, fast switching speed, very low reverse recovery charge and low inter-electrode capacitance for synchronous rectifier Qs
MOSFETs with can be used. Other embodiments and improvements to such DC-DC converters are described in the same applicant's vendor patent application 10 / 222,481, entitled “Method and Circuit for Reducing Loss in DC-DC Converters” by Elbanhawv. No. (Attorney Docket No. 18865-91-1 / 17732-51430). The entire contents of the patent application are incorporated herein by reference.

  Any of the various power device structures described above can be used to implement the MOSFETs in the converter circuits of FIGS. A dual-gate MOSFET of the type shown in FIG. 4A is a type of device that provides certain advantages when used, for example, in implementing a synchronous buck converter. In one embodiment, a special drive scheme utilizes all the functions provided by the dual gate MOSFET. An example of this embodiment is shown in FIG. 69, where the first gate terminal G2 of the high side MOSFET Q1 is defined by a circuit comprising a diode D1, resistors R1 and R2, and a capacitor C1. Has a potential. The fixed potential at the gate electrode G2 of Q1 can be adjusted for the best Qgd to optimize the transistor switching time. The second gate terminal G1 of the high side switch transistor Q1 receives a normal gate drive signal from a pulse width modulated (PWM) controller / driver (not shown). The two gate electrodes of the low side switch transistor Q2 are similarly driven as shown.

In another embodiment, both gate electrodes of the high side switch are driven separately to further optimize circuit performance. According to this embodiment, the different waveforms drive the gate terminals G1 and G2 of the high-side switch Q1, achieving the highest switching speed during the transition and the best on-resistance R _DSon during the rest of the cycle. In the embodiment shown, the voltage Va of about 5V during switching carries a very low Qgd to the gate of the high-side switch Q1, a high result in switching speeds, but the transition td1, td2 before and after the R _DSon, the minimum value is not. However, this does not adversely affect the operation of the circuit, since R _DSon does not contribute significantly to losses during switching. To ensure the lowest R _DSon during the remainder of the pulse width, the potential Vg2 at the gate terminal G2 is a second higher than Va during time t _p as shown in the timing diagram of FIG. 70B. Driven to voltage Vb. This drive scheme provides optimal efficiency. Variations on these drive schemes are more detailed in commonly assigned US patent application Ser. No. 10 / 686,859 (Attorney Docket No. 17732-66930) entitled “Driver to Dual-Gate MOSFET” by Elbanhawv. The entire contents of which are incorporated herein by reference.
Package Technology An important consideration for all power semiconductor devices is the housing or package used to connect the device to the circuit. The semiconductor chip is typically attached to a metal pad using a metal bonding layer, such as an epoxy adhesive into which solder or metal is injected. The wire is typically bonded to the top surface of the chip and then bonded to a lead protruding through the molded body. Thereafter, the assembly is mounted on a circuit board. The housing provides both electrical and thermal connections between the semiconductor chip, the electronic device and its environment. Low parasitic resistance, capacitance and inductance are desirable electrical features for the housing that allow a better interface to the chip.

  Improvements to packaging technology have been proposed with a focus on reducing resistance and inductance in the package. In some packaging technologies, solder scrap or copper studs are placed on the relatively thin metal surface of the chip (eg, 2-5 μm). By placing the metal connection over a large area of the metal surface, the current path in the metal is shortened and the metal resistance is reduced. If the bump side of the chip is connected to a copper lead frame or a copper trace on a printed circuit board, the resistance of the power device is reduced compared to a wire bonded solution.

  71 and 72 are simplified cross-sectional views of molded and unmolded packages, respectively, using solder scraps or copper studs connecting the lead frame to the metal surface of the chip. A molded package 7100 as shown in FIG. 71 includes a lead frame 7106 that connects to the first surface of the chip 7102 via solder scrap or copper studs 7104. The second surface of the chip 7102 facing away from the lead frame 7106 is exposed through the molding material 7108. In a standard vertical power transistor, the second surface of the chip forms a drain terminal. The second side of the chip can form a direct electrical connection to pads on the circuit board, thus providing a low resistance path and an electrical path to the chip. This type of package and variations thereof are described in commonly assigned US patent application Ser. No. 10 / 607,633, entitled “Flip Chips in Leaded Molded Packages and Methods of Manufacture”. Agent reference number 18865-42-1 / 17732-1342). The entire contents of the patent application are incorporated herein by reference.

  FIG. 72 illustrates an unmolded embodiment of the package 7200. FIG. In the exemplary embodiment shown in FIG. 72, package 7200 has a multilayer substrate 7212 that includes a reference layer 7220 that includes a metal layer 7221 separated by, for example, a metal, insulating layer 7222. A solder structure 7213 (eg, solder scrap) is attached to the substrate 7212. The chip 7211 is attached to the substrate 7212 together with the solder structure 7213 exposed around the chip. The chip 7211 can be coupled to the substrate 7212 with a chip attachment material such as solder 7230. After the illustrated package is formed, the package is turned over and mounted on a circuit board (not shown) or other circuit board. In the embodiment where the vertical power transistor is assembled on chip 7211, the solder scrap 7230 forms the drain terminal connection and the chip surface forms the source terminal. By reversing the connection of the chip 7211 to the substrate 7212, the reverse connection is also possible. As shown, the package 7220 is thin and unmolded when mold material is not required. Various embodiments of this type of unmolded package are described in commonly assigned US patent application Ser. No. 10 / 235,249, entitled “Unmolded Package for Semiconductor Devices,” by Joshi. No. 18865-007110 / 17732.263900.003). The entire contents of the patent application are incorporated herein by reference.

  Other methods have been proposed in which the top surface of the chip is directly connected to copper by solder or conductive epoxy. The stress generated between the copper and the silicon chip increases with the area of the chip. Since the solder or epoxy interface is only significantly stressed before braking, the direct connection method can be limited. On the other hand, bumps can be replaced before braking and have been shown to work with fairly large chips.

  Another important consideration in the package is heat dissipation. Improvements in power semiconductor performance often result in small chip areas. If the power dissipation at the chip is not reduced, the thermal energy is concentrated in a small area, which can lead to high temperatures and poor reliability. Means for increasing the heat transfer rate from the package use materials with high thermal conductivity to reduce the number of thermal interfaces and layers such as silicon, solder, chip attachment and chip attachment pads. Including reducing the thickness. US Pat. No. 6,566,749 by Rajeev Joshi entitled “Semiconductor Chip Package with Improved Thermal and Electrical Performance”, the entire contents of which are incorporated herein by reference. Discusses a solution to the problem of heat dissipation for chips containing vertical power MOSFETs, particularly for RF applications. Another way to improve overall package performance is by US patent application Ser. No. 10 / 271,654 entitled “Thin and thermally improved flip chip in leaded molded packages” by Joshi et al. US Pat. No. 6,133,634 and US Pat. No. 6,469,384 by Rajeev Joshi as well as US Pat. No. 6,865,384, as well as US Pat. Explained. It should be understood that any of the various power devices described herein can be housed in a package described herein or other suitable package.

  Using a larger surface of the housing for heat removal also increases the housing's ability to maintain a low temperature, such as the thermal interface at the top and bottom of the housing. By combining the increased surface area and the airflow around those surfaces, the heat removal rate is increased. The housing design also allows easy interface with the external heat sink. Thermal conduction and infrared methods are common methods, but alternative cooling method applications are possible. For example, US Patent Application No. 10 / 408,471 (Attorney Docket No. 17732-66720) by the same applicant entitled “Power Circuit with Thermoelectric Cooling System” by Reno Rossetti. Thermionic emission as described in the entirety of which is incorporated herein by reference is one method of heat removal that can be used to cool a power device.

  The integration of other logic circuits, including power transfer and control functions in a single package, poses additional challenges. For one, the housing requires more pins to interact with other electrical functions. The package should allow for high current power interconnections and low current signal interconnections in the package. Various packaging technologies that can address these challenges include chip-on-chip and chip-to-chip to leave space in the housing, as well as chip-to-chip wire bonding to remove special interface pads Multi-chip modules that allow multiple silicon technologies to be integrated into a single electrical function. Various embodiments for multi-chip packaging methods are described in US patent application Ser. No. 09/730, filed by Rajeev Jeshi, entitled “Laminated Package Using Flip Chips in Leaded Molded Packaging Technology” No. 932 (Attorney Docket No. 18865-50 / 17732-19450) and US patent application Ser. No. 10 / 330,741 entitled “Multichip Modules Containing Substrate with Interconnected Array” by Rajeev Joshi. No. (Attorney Docket No. 18865-121 / 17732-66650.08). Both of these patent applications are incorporated herein by reference.

  While the above provides a complete description of the preferred embodiment of the present invention, many alternatives, modifications and equivalents are possible. For example, many charge adjustment methods are described herein in the context of MOSFETs, particularly trench gate MOSFETs. It will be appreciated by those skilled in the art that the same method can be applied to other types of devices including IGBTs, thyristors, diodes and planar MOSFETs as well as lateral devices. Thus, for this and other reasons, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

2 is a cross-sectional view of a portion of an exemplary n-type trench power MOSFET. FIG. FIG. 6 illustrates an exemplary embodiment of a dual trench power MOSFET. FIG. 6 illustrates an exemplary embodiment for a planar gate MOSFET having a source shield trench structure. FIG. 6 shows a portion of an exemplary embodiment of a shielded gate trench power MOSFET. FIG. 3B illustrates an alternative embodiment for a shielded gate trench power MOSFET combining the dual trench structure of FIG. 2A with the shielded gate structure of FIG. 3A. FIG. 6 is a simplified partial view of an exemplary embodiment of a dual gate trench power MOSFET. FIG. 5 shows an exemplary power MOSFET combining a planar dual gate structure with a trench electrode for vertical charge control. FIG. 6 illustrates an exemplary implementation of a power MOSFET that combines dual gate and shield gate technology within the same trench. FIG. 6 is a cross-sectional view of another embodiment for a power MOSFET having a deep body structure. FIG. 6 is a cross-sectional view of another embodiment for a power MOSFET having a deep body structure. It is a figure which shows the effect of the deep main body structure in which the trench was formed regarding distribution of a potential line inside the power MOSFET near a gate electrode. It is a figure which shows the effect of the deep main body structure in which the trench was formed regarding distribution of a potential line inside the power MOSFET near a gate electrode. 2 is a cross-sectional view illustrating portions of exemplary power MOSFETs having various vertical charge adjustment structures. FIG. 2 is a cross-sectional view illustrating portions of exemplary power MOSFETs having various vertical charge adjustment structures. FIG. 2 is a cross-sectional view illustrating portions of exemplary power MOSFETs having various vertical charge adjustment structures. FIG. 2 is a simplified cross-sectional view of a power MOSFET combining an exemplary vertical charge control structure with a shield gate structure. FIG. FIG. 6 is a simplified cross-sectional view of another power MOSFET combining an exemplary vertical charge control structure with a dual gate structure. It is a figure which shows an example of the shield gate power MOSFET which has a vertical charge control structure and the integrated Schottky diode. FIG. 3 shows various exemplary embodiments for a power MOSFET with an integrated Schottky diode. FIG. 3 shows various exemplary embodiments for a power MOSFET with an integrated Schottky diode. FIG. 3 shows various exemplary embodiments for a power MOSFET with an integrated Schottky diode. FIG. 6 illustrates an exemplary layout variation for interposing Schottky diode cells in an active cell array of a power MOSFET. FIG. 6 illustrates an exemplary layout variation for interposing Schottky diode cells in an active cell array of a power MOSFET. FIG. 6 illustrates an exemplary layout variation for interposing Schottky diode cells in an active cell array of a power MOSFET. FIG. 3 is a simplified cross-sectional view of an exemplary trench power MOSFET having a buried diode charge adjustment structure. FIG. 5 is a diagram illustrating an embodiment for a power MOSFET that combines shield gate technology with embedded diode charge adjustment. FIG. 6 illustrates an embodiment for a power MOSFET that combines dual gate technology with embedded diode charge adjustment. 2 is a simplified cross-sectional view of an exemplary planar power MOSFET in combination with a Schottky diode integrated with embedded diode charge regulation technology. FIG. FIG. 5 shows a simplified example of an exemplary accumulation mode power transistor having staggered conduction regions arranged parallel to the current flow. FIG. 6 is a simplified diagram of another accumulation mode device having a trench electrode for charge diffusion. 1 is a simplified diagram of an exemplary dual trench accumulation mode device. FIG. FIG. 5 illustrates another simplified embodiment for an exemplary cumulative mode device having a heteropolar exterior liner and having a dielectric filled trench. FIG. 5 illustrates another simplified embodiment for an exemplary cumulative mode device having a heteropolar exterior liner and having a dielectric filled trench. FIG. 6 shows another simplified embodiment for a cumulative mode device that uses one or more buried diodes. 1 is a simplified isometric view of an exemplary cumulative mode transistor including a heavily doped heteropolar region along a surface of silicon. FIG. It is a figure which shows the simplification example of the super junction power MOSFET which has an alternating different polarity area | region in a voltage maintenance layer. FIG. 6 illustrates an exemplary embodiment for a superjunction power MOSFET having heterogeneous islands that are non-uniformly spaced in the vertical direction in the voltage sustaining layer. FIG. 5 illustrates an exemplary embodiment for a super junction power MOSFET having a dual gate structure. FIG. 6 illustrates an exemplary embodiment for a super junction power MOSFET having a shield gate structure. It is a figure which shows the upper side figure of the layout of the active trench with respect to a trench transistor, and a termination | terminus trench. FIG. 6 is a simplified layout diagram of another embodiment for a trench termination structure. FIG. 6 is a simplified layout diagram of another embodiment for a trench termination structure. FIG. 6 is a simplified layout diagram of another embodiment for a trench termination structure. FIG. 6 is a simplified layout diagram of another embodiment for a trench termination structure. FIG. 6 is a simplified layout diagram of another embodiment for a trench termination structure. 2 is a cross-sectional view of an exemplary trench termination structure. FIG. 2 is a cross-sectional view of an exemplary trench termination structure. FIG. 2 is a cross-sectional view of an exemplary trench termination structure. FIG. FIG. 5 illustrates an exemplary device having a termination trench with a large radius curvature. It is sectional drawing of the termination | terminus area | region which has a silicon pillar electric charge adjustment structure. It is sectional drawing of the termination | terminus area | region which has a silicon pillar electric charge adjustment structure. It is sectional drawing of the termination | terminus area | region which has a silicon pillar electric charge adjustment structure. It is sectional drawing of the termination | terminus area | region which has a silicon pillar electric charge adjustment structure. FIG. 2 is a cross-sectional view of an exemplary embodiment of an ultra high voltage device using a super junction method. FIG. 2 is a cross-sectional view of an exemplary embodiment of an ultra high voltage device using a super junction method. FIG. 2 is a cross-sectional view of an exemplary embodiment of an ultra high voltage device using a super junction method. It is a figure which shows the example of the edge part which contacts with respect to a trench device. FIG. 6 illustrates an exemplary process for forming an end contact structure for a trench device. FIG. 6 illustrates an exemplary process for forming an end contact structure for a trench device. FIG. 6 illustrates an exemplary process for forming an end contact structure for a trench device. FIG. 6 illustrates an exemplary process for forming an end contact structure for a trench device. FIG. 6 illustrates an exemplary process for forming an end contact structure for a trench device. FIG. 6 is an example of an active area contact structure for a plurality of buried poly layers. FIG. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. It is a figure which shows the process of forming the active region shield contact structure with respect to a trench. FIG. 6 is a cross-sectional view of another embodiment for an active area shield contact structure. 1 is a layout diagram of an exemplary trench device having an active area shield contact structure. FIG. 1 is a layout diagram of an exemplary trench device having an active area shield contact structure. FIG. FIG. 3 is a simplified layout diagram of two embodiments for making contact with a peripheral trench in a trench device having an interrupted trench structure. FIG. 3 is a simplified layout diagram of two embodiments for making contact with a peripheral trench in a trench device having an interrupted trench structure. FIG. 5 is another example of contacting the trench shield poly layer in the active region. FIG. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 33B is a diagram showing an example of a step of contacting an active area shield structure of the type shown in FIG. 33A. FIG. 6 shows an epi layer with a spacer or buffer (barrier) layer to reduce the thickness of the epi drift region. FIG. 6 illustrates another example for a device having a barrier layer. FIG. 5 shows a barrier layer used for deep body-epi junctions to minimize the thickness of the epi layer. FIG. 6 is a simplified example of a well-drift region junction of a transistor using a diffusion barrier layer. FIG. FIG. 6 illustrates a simplified process for an example of a self-aligned epi-well trench device having a buried electrode. FIG. 6 illustrates a simplified process for an example of a self-aligned epi-well trench device having a buried electrode. FIG. 6 illustrates a simplified process for an example of a self-aligned epi-well trench device having a buried electrode. FIG. 6 illustrates a simplified process for an example of a self-aligned epi-well trench device having a buried electrode. FIG. 6 illustrates an exemplary process for a cornered well trench. FIG. 6 illustrates an exemplary process for a cornered well trench. It is a figure which shows the example of the process of a self alignment epitaxial well. It is a figure which shows the example of the process of a self alignment epitaxial well. It is a figure which shows the example of the process of a self alignment epitaxial well. It is a figure which shows the example of the process of a self alignment epitaxial well. It is a figure which shows the example of the process of a self alignment epitaxial well. It is a figure which shows the method to reduce board | substrate thickness. It is a figure which shows the method to reduce board | substrate thickness. It is a figure which shows the method to reduce board | substrate thickness. It is a figure which shows the method to reduce board | substrate thickness. It is a figure which shows the example of the process which uses a chemical process as the last thinning step. It is a figure which shows the example of the improved etching process. It is a figure which shows the example of the improved etching process. It is a figure which shows the example of the improved etching process. It is a figure which shows the example of the improved etching process. It is a figure which shows the example of the improved etching process. It is a figure which shows the example of the improved etching process. It is a figure which shows the Example of the trench etching process which eliminates the problem of a bird's beak. It is a figure which shows the Example of the trench etching process which eliminates the problem of a bird's beak. It is a figure which shows another etching process. It is a figure which shows another etching process. It is a figure which shows the process of forming the dielectric material layer between improved poly. It is a figure which shows the process of forming the dielectric material layer between improved poly. It is a figure which shows the process of forming the dielectric material layer between improved poly. It is a figure which shows another method of forming an IPD layer. It is a figure which shows another method of forming an IPD layer. It is a figure which shows another method of forming an IPD layer. FIG. 6 is a cross-sectional view of yet another method of forming a high quality interpoly dielectric layer. FIG. 6 is a cross-sectional view of yet another method of forming a high quality interpoly dielectric layer. FIG. 5 shows another embodiment for the formation of an improved IPD layer. FIG. 5 shows another embodiment for the formation of an improved IPD layer. FIG. 5 shows another embodiment for the formation of an improved IPD layer. FIG. 5 shows another embodiment for the formation of an improved IPD layer. FIG. 5 shows another embodiment for the formation of an improved IPD layer. It is a figure which shows the anisotropic plasma etching process with respect to IPD planarization. FIG. 6 shows an alternative IPD planarization method using a chemical mechanical process. 5 is a flowchart for an exemplary method of controlling the oxidation rate. FIG. 6 illustrates an improved method of forming a thick oxide at the bottom of a trench using quasi-atmospheric CVD. 2 is an exemplary flowchart of a method of forming a thick oxide at the bottom of a trench using a directional tetraethoxyorthsilicate process. FIG. 6 illustrates another example of forming a thick bottom oxide. FIG. 6 illustrates another example of forming a thick bottom oxide. It is a figure which shows another process of forming a thick dielectric layer in the bottom part of a trench. It is a figure which shows another process of forming a thick dielectric layer in the bottom part of a trench. It is a figure which shows another process of forming a thick dielectric layer in the bottom part of a trench. It is a figure which shows another process of forming a thick dielectric layer in the bottom part of a trench. It is a simplified diagram of a MOSFET having a current detection device. 2 is an example of a charge adjustment MOSFET having a planar gate structure and a separate current detection structure. It is a figure which shows the example which integrates the current detection apparatus which has trench MOSFET. FIG. 6 shows another embodiment for a MOSFET having a series temperature sensing diode. FIG. 6 shows another embodiment for a MOSFET having a series temperature sensing diode. FIG. 6 shows another embodiment for a MOSFET having a series temperature sensing diode. FIG. 5 shows another embodiment for a MOSFET with ESD protection. FIG. 5 shows another embodiment for a MOSFET with ESD protection. It is a figure which shows the example of an ESD protection circuit. It is a figure which shows the example of an ESD protection circuit. It is a figure which shows the example of an ESD protection circuit. It is a figure which shows the example of an ESD protection circuit. FIG. 6 illustrates an exemplary process for forming a charge tuning power device having a low ESR. It is a figure which shows the layout method for reducing ESR. It is a figure which shows the layout method for reducing ESR. It is a figure which shows the DC-DC circuit which uses power switching. FIG. 3 is a diagram showing another DC-DC converter using power switching. FIG. 6 illustrates an exemplary drive circuit for a dual gate MOSFET. FIG. 5 is a diagram showing another embodiment having gate electrodes that are driven separately. FIG. 70B is a timing chart showing the circuit operation of FIG. 70A. It is a simplified sectional view of a mold package. FIG. 5 is a simplified cross-sectional view of an unmolded package.

Claims (203)

A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A charge control trench extending deeper into the drift region than the active trench and filled with a material that provides vertical charge control in the drift region;
And the active trench has a sidewall surrounded by a dielectric and a bottom, and is filled with a first shield conductive layer and a gate conductive layer, and the first shield conductive layer includes the gate conductive layer. A semiconductor device, wherein the semiconductor device is disposed below the layer and separated from the gate electrode by an interelectrode dielectric.   The semiconductor device of claim 1, wherein the charge control trench is surrounded by a dielectric layer and filled with a conductor.   The semiconductor device according to claim 2, wherein the source electrode connects the conductor inside the charge control trench to the source region.   2. The plurality of conductive layers stacked vertically, separated from each other and separated from a side wall of the charge control trench by a dielectric, are disposed in the charge control trench. Semiconductor devices.   5. The semiconductor device of claim 4, wherein the plurality of conductive layers within the charge control trench are electrically biased to provide vertical charge adjustment in the drift region.   The semiconductor device according to claim 5, wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.   The semiconductor device according to claim 4, wherein the thickness of the plurality of conductive layers inside the charge control trench varies.   The thickness of the first conductive layer at a deeper position inside the charge control trench is smaller than the thickness of the second conductive layer disposed on the first conductive layer. Item 14. A semiconductor device according to Item 1.   2. The semiconductor device according to claim 1, wherein the first shield conductive layer inside the active trench is configured to be electrically biased to a desired potential.   The semiconductor device according to claim 1, wherein the first shield conductive layer and the source region are electrically connected to the same potential.   The semiconductor device according to claim 1, wherein the active trench further includes a second shield conductive layer disposed under the first shield conductive layer.   12. The semiconductor device according to claim 11, wherein the thickness of the first and second shield conductive layers varies.   12. The semiconductor device according to claim 11, wherein the first and second shield conductive layers are configured to be independently biased.   The semiconductor device of claim 1, wherein the charge control trench is filled with a dielectric.   The semiconductor device of claim 14, further comprising a lining of a second conductive material extending along an outer wall of the charge control trench.   The semiconductor device of claim 1, further comprising a Schottky structure formed between the charge control trench and a second adjacent charge control trench. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
In the active trench, a first gate made of a conductive material and a second gate made of a conductive material are separated from each other and separated from the side wall of the active trench by a dielectric layer. A conductive material formed, wherein the first gate is over the second gate, and the active trench is disposed under the second gate and separated from the second gate by a dielectric. And a first shield electrode made of the semiconductor device.   The semiconductor device of claim 17, wherein the first and second gates are configured to be electrically biased independently.   The semiconductor device of claim 18, wherein the second gate is biased at a constant potential with a substantially threshold voltage of the semiconductor device.   The semiconductor device of claim 18, wherein the second gate is biased at a potential greater than the potential applied to the source region.   19. The semiconductor device of claim 18, wherein the second gate is connected to a potential at a substantially threshold voltage of the semiconductor device before a switching phenomenon.   18. The semiconductor device according to claim 17, wherein the first shield electrode is configured to be biased to a desired potential independently.   The semiconductor device according to claim 17, wherein the active trench further includes one or more shield electrodes stacked under the first shield electrode in addition to the first shield electrode.   24. The semiconductor device of claim 23, wherein the first shield electrode and the one or more additional shield electrodes vary in size.   The semiconductor device of claim 17, further comprising a charge control trench extending into the drift region and filled with a material that provides vertical charge control in the drift region.   26. The semiconductor device of claim 25, wherein the source electrode electrically couples the conductive material inside the charge control trench to the source region.   26. The semiconductor according to claim 25, wherein a plurality of conductive layers stacked vertically are arranged in the charge control trench and separated from each other and separated from the charge control trench by a dielectric. device.   28. The semiconductor device of claim 27, wherein the plurality of conductive layers within the charge control trench are electrically biased to provide vertical charge adjustment in the substrate.   29. The semiconductor device of claim 28, wherein the plurality of conductive layers within the charge control trench are configured to be independently biased.   28. The semiconductor device according to claim 27, wherein the size of the plurality of conductive layers inside the charge control trench varies.   The size of the first conductive layer at a deeper position inside the charge control trench is smaller than the size of the second conductive layer disposed on the first conductive layer. 30. The semiconductor device according to 30.   The semiconductor device of claim 17, further comprising a Schottky structure formed between two adjacent trenches. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A charge control trench extending deeper into the drift region than the active trench and filled with a material that provides vertical charge control in the drift region;
In the active trench, a first gate made of a conductive material and a second gate made of a conductive material are separated from each other and separated from the sidewalls and bottom of the active trench by a dielectric layer A semiconductor device, wherein the first gate is overlying the second gate.   34. The semiconductor device of claim 33, wherein the first gate and the second gate are configured to be independently electrically biased.   35. The semiconductor device of claim 34, wherein the second gate is biased at a constant potential with a substantially threshold voltage of the semiconductor device.   35. The semiconductor device of claim 34, wherein the second gate is biased at a potential greater than the potential applied to the source region.   35. The semiconductor device of claim 34, wherein the second gate is coupled to a potential at a substantially threshold voltage of the semiconductor device prior to a switching phenomenon.   34. The semiconductor device of claim 33, wherein the charge control trench is surrounded by a dielectric layer and filled with a conductive material.   39. The semiconductor device of claim 38, wherein the source electrode couples the conductive material within the charge control trench to the source region.   34. The semiconductor device according to claim 33, wherein a plurality of conductive layers that are separated from each other and separated from the trench by a dielectric material and stacked vertically are disposed inside the charge control trench.   41. The semiconductor device of claim 40, wherein the plurality of conductive layers within the charge control trench are electrically biased to provide vertical charge adjustment in the substrate.   42. The semiconductor device according to claim 41, wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.   41. The semiconductor device of claim 40, wherein the size of the plurality of conductive layers within the charge control trench varies.   The size of the first conductive layer at a deeper position inside the charge control trench is smaller than the size of the second conductive layer disposed on the first conductive layer. 46. The semiconductor device according to 46.   34. The semiconductor device of claim 33, wherein the charge control trench is filled with a dielectric.   46. The semiconductor device of claim 45, further comprising a lining of a second conductive material extending along an outer wall of the charge control trench.   34. The semiconductor device of claim 33, further comprising a Schottky structure formed between the charge control trench and a second adjacent charge control trench. A semiconductor device,
A substrate of a first conductivity type;
Spaced apart first and second well regions of a second conductivity type opposite to the first conductivity type and extending into the substrate to a first depth;
An outer edge of each source region and an outer edge of each of the well regions forming the respective first and second channel regions within the first and second well regions having the first conductivity type; A first source region and a second source region respectively formed with a space between
A first gate formed on a substrate that horizontally overlaps the first source region and the first channel region and separated therefrom by a thin dielectric layer;
First and second charge control trenches that extend into the substrate through each of the first and second well regions and are filled with a material that provides vertical charge control in the substrate;
A semiconductor device comprising:   49. The semiconductor device of claim 48, wherein each of the charge control trenches is surrounded by a dielectric layer and filled with a conductive material.   50. The semiconductor device of claim 49, wherein a source electrode formed on the surface of the substrate electrically couples a conductive material inside the charge control trench to the source region.   26. The semiconductor according to claim 25, wherein a plurality of conductive layers stacked vertically are disposed in each of the charge control trenches and separated from each other by a dielectric material. device.   52. The semiconductor device of claim 51, wherein the plurality of conductive layers within each charge control trench are electrically biased to provide vertical charge adjustment in the substrate.   53. The semiconductor device of claim 52, wherein the plurality of conductive layers within each charge control trench are configured to be independently biased.   52. The semiconductor device of claim 51, wherein the size of the plurality of conductive layers within each charge control trench varies.   55. The semiconductor of claim 54, wherein the size of the plurality of conductive layers within each charge control trench is smaller than a size of a second conductive layer disposed on the first conductive layer. device.   49. The semiconductor device of claim 48, wherein the first gate and the second gate are independently electrically biased.   57. The semiconductor device of claim 56, wherein the second gate is biased at a constant potential at a substantially threshold voltage of the semiconductor device.   57. The semiconductor device of claim 56, wherein the second gate is biased at a potential greater than the potential applied to the source region.   57. The semiconductor device of claim 56, wherein the second gate is coupled to a potential at a substantially threshold voltage of the semiconductor device prior to a switching phenomenon. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending deeper into the drift region than the well region, having sidewalls and bottom surrounded by a dielectric, and filled with a gate conductive layer;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A body trench extending deeper than the well region and formed adjacent to the well and its source region;
A layer surrounding the body trench and having an increased concentration of the second conductivity type;
And the body trench is filled with a conductive material.   61. The semiconductor device of claim 60, wherein the body trench is filled with an epitaxial material electrically connected to the source region.   61. The semiconductor device of claim 60, wherein the body trench is filled with doped polysilicon electrically connected to the source region.   61. The semiconductor device of claim 60, wherein the increased concentration layer is formed by a burying process.   61. The semiconductor device of claim 60, wherein the increased concentration layer is formed by a dopant diffusing from the conductive material within the body trench.   61. The semiconductor device of claim 60, wherein a distance L between the active trench wall and the adjacent body trench wall is adjusted to minimize gate-drain capacitance.   66. The semiconductor device according to claim 65, wherein L is 0.3 or less.   61. The semiconductor device of claim 60, wherein a distance between an outer edge of the layer having increased concentration and a wall of an adjacent active trench is adjusted to minimize gate-drain capacitance. .   61. The semiconductor device of claim 60, wherein the body trench is deeper than the active trench.   69. The semiconductor device according to claim 68, wherein the interval L is approximately 0.5 or less.   The active trench includes a first shield electrode made of a conductive material formed under the gate conductive layer, and the shield electrode is insulated from the gate conductive layer and the trench sidewall and bottom by a dielectric. 61. A semiconductor device according to claim 60.   71. The semiconductor device of claim 70, wherein the first shield electrode inside the active trench is electrically biased to a desired potential.   The semiconductor device according to claim 70, wherein the first shield electrode and the source region are electrically connected to the same potential.   71. The semiconductor device of claim 70, wherein the active trench further includes a second shield electrode disposed under the first shield electrode and made of a conductive material.   74. The semiconductor device of claim 73, wherein the first and second shield electrodes vary in size.   74. The semiconductor device of claim 73, wherein the first and second shield conductive layers are independently biased.   61. The semiconductor device of claim 60, further comprising a charge control trench extending into the substrate and filled with a material for vertical charge control in the substrate.   77. The semiconductor device of claim 76, wherein the charge control trench is surrounded by a dielectric layer and filled with a conductive material.   78. The semiconductor device of claim 77, wherein a source electrode electrically couples the conductive material inside the charge control trench to the source region.   77. The semiconductor device according to claim 76, wherein a plurality of conductive layers that are separated from each other and separated from the trench by a dielectric material and stacked vertically are disposed inside the charge control trench.   80. The semiconductor device of claim 79, wherein the plurality of conductive layers within the charge control trench are electrically biased to provide vertical charge control in the substrate.   81. The semiconductor device of claim 80, wherein the plurality of conductive layers within the charge control trench are configured to be independently biased.   80. The semiconductor device of claim 79, wherein the size of the plurality of conductive layers within the charge control trench varies.   The size of the first conductive layer at a deeper position inside the charge control trench is smaller than the size of the second conductive layer disposed on the first conductive layer. 82. A semiconductor device according to 82.   61. The semiconductor device of claim 60, further comprising a Schottky structure formed between two adjacent trenches. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending into the drift region deeper than the well region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A first gate made of a conductive material is formed inside the active trench, separated from the trench wall and bottom by a dielectric, and filled with a dielectric at a lower position of the active trench. 61. The semiconductor device of claim 60, wherein the portion that is extended extends deep into the drift region and is surrounded by a liner of a second conductive material to provide vertical charge control.   86. The semiconductor device of claim 85, further comprising a plurality of discontinuous regions having a second conductivity type formed in the drift region adjacent to an outer wall of the active trench.   86. The active trench further comprises a second gate made of a conductive material formed below the first gate and insulated from the first gate by a dielectric. Semiconductor devices.   90. The semiconductor device of claim 87, wherein the second gate is independently electrically biased.   90. The semiconductor device of claim 88, wherein the second gate is biased at a constant potential at a substantially threshold voltage of the semiconductor device.   90. The semiconductor device of claim 88, wherein the second gate is biased at a potential greater than the potential applied to the source region.   90. The semiconductor device of claim 88, wherein the second gate is coupled to a potential at a substantially threshold voltage of the semiconductor device before a switching phenomenon.   86. The active trench further includes a first shield electrode formed under the first gate and insulated from the first gate by a dielectric and made of a conductive material. Semiconductor devices.   94. The semiconductor device of claim 92, wherein the first shield electrode is independently biased at a desired potential.   95. The semiconductor device of claim 92, wherein the active trench further includes one or more shield electrodes stacked under the first shield electrode in addition to the first shield electrode.   95. The semiconductor device of claim 94, wherein the first shield electrode and the one or more additional shield electrodes vary in size. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A first Schottky structure formed on a first mesa between two adjacent trenches;
The active trench has a sidewall surrounded by a dielectric and a bottom, and is filled with a first conductive layer and a first gate conductive layer, and the first shield conductive layer comprises: A semiconductor device disposed under the first gate conductive layer and separated from the first gate conductive layer by an interelectrode dielectric.   99. The semiconductor device of claim 96, wherein the first conductive layer is configured to be a shield electrode.   99. The semiconductor device of claim 96, wherein the first conductive layer is configured to be a second gate electrode.   97. The semiconductor device of claim 96, wherein the active trench further includes a second conductive layer disposed below the first conductive layer configured to be a shield electrode.   100. The semiconductor device of claim 99, wherein the first and second conductive layers are configured to be electrically biased with a potential.   97. The semiconductor device of claim 96, further comprising a second Schottky structure formed on a second mesa adjacent to the first mesa.   99. The semiconductor device of claim 96, wherein the Schottky structure is formed to be perpendicular to a longitudinal axis of the two adjacent trenches. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A charge control trench having sidewalls surrounded by a dielectric;
The active trench has a sidewall surrounded by a dielectric and a bottom and is filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode; The electrode is disposed on the lower electrode and separated from the lower electrode by an interelectrode dielectric, and one or more diode structures are formed in the charge control trench. Semiconductor device.   The one or more diode structures include a plurality of layers of opposite conductivity stacked alternately within the charge control trench, with a bottom in electrical contact with the drift region. 104. A semiconductor device according to claim 103.   105. The semiconductor device of claim 104, wherein the upper electrode is configured to be a first gate electrode.   106. The semiconductor device of claim 105, wherein the lower electrode is configured to be a second gate electrode.   107. The active trench further includes a third conductive layer disposed under the second conductive layer, and the third conductive layer is configured as a shield electrode. Semiconductor devices.   106. The semiconductor device of claim 105, wherein the lower electrode is configured to be a first shield electrode.   The active trench further includes a third conductive layer disposed under the second conductive layer, and the third conductive layer is configured as a second shield electrode. Item 108. The semiconductor device according to Item 108.   104. The semiconductor device of claim 103, wherein the first and second electrodes are electrically biased.   104. The semiconductor device of claim 103, further comprising a Schottky structure formed on a mesa between two adjacent charge control trenches. A semiconductor device,
A substrate of a first conductivity type;
Spaced apart first and second well regions of a second conductivity type opposite to the first conductivity type and extending into the substrate to a first depth;
An outer edge of each source region and an outer edge of each of the well regions forming the respective first and second channel regions within the first and second well regions having the first conductivity type; A first source region and a second source region respectively formed with a space between
A first gate formed on a substrate overlying the first and second channel regions and separated therefrom by a thin dielectric layer;
First and second charge control trenches extending into the substrate through each of the first and second well regions;
Each of the charge control trenches has a sidewall surrounded by a dielectric, and one or more diode structures are formed in the charge control trench.   The one or more diode structures include a plurality of layers of opposite conductivity stacked alternately within the charge control trench, with a bottom in electrical contact with the drift region. 113. The semiconductor device of claim 112. 113. The semiconductor device of claim 112, further comprising a Schottky structure formed on the mesa between two adjacent charge control trenches. A semiconductor device,
A drift region of a first conductivity type;
A plurality of well regions of a second conductivity type opposite to the first conductivity type;
A source region of the first conductivity type formed within each of the plurality of well regions to define a channel region;
A gate structure formed adjacent to the channel region;
A plurality of floating regions of a second conductivity type disposed in a drift region below each of the plurality of well regions;
The well region extends above the drift region and has a plurality of peak concentrations, the spacing between the floating regions under each well region is between the floating region and the corresponding well region. A semiconductor device characterized by increasing as the distance between them increases.   116. The semiconductor device of claim 115, wherein the gate structure is a planar conductive layer formed over the channel region.   The gate structure is formed over the channel region and partially formed over the first gate overlapping the first portion of the channel region and the second portion of the channel region; 116. The semiconductor device of claim 115, comprising a second overlapping gate.   The gate structure includes a trench extending through a well region into the drift region, the trench having a sidewall and a bottom surrounded by a dielectric and filled with a conductive material. 116. The semiconductor device according to claim 115.   120. The semiconductor of claim 119, wherein the conductive material filling the trench includes an upper portion forming a first gate electrode and a lower portion forming an independent electrode by dielectric separation from the upper portion. device.   120. The semiconductor device of claim 119, wherein the independent electrode is configured as a second gate electrode.   120. The semiconductor device of claim 119, wherein the independent electrode is configured as a shield electrode.   116. The semiconductor device of claim 115, wherein the size of the plurality of floating regions under each well region decreases as the distance between the floating region and its corresponding well region increases.   116. The semiconductor of claim 115, wherein the peak concentration for each of the plurality of floating regions under each well region decreases as the distance between the floating region and its corresponding well region increases. device.   The floating regions under the well region that are closest to the well region are in contact with each other, but the floating regions that are farthest from the well region and under the well region are true floating regions. 116. The semiconductor device according to claim 115. A semiconductor device,
A drift region of a first conductivity type;
A well region extending over the drift region and having a second conductivity type opposite to the first conductivity type;
An active trench extending through the well region and into the drift region;
A source region having the first conductivity type formed in the well region adjacent to the active trench;
A first termination trench extending below the well region and disposed at an outer edge of the active region of the device;
The active trench has a sidewall surrounded by a dielectric and a bottom and is filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode; A semiconductor device, wherein the electrode is disposed on the lower electrode and separated from the lower electrode by an interelectrode dielectric.   126. The semiconductor device of claim 125, wherein the first termination trench is surrounded by a layer of dielectric that is thicker than the dielectric surrounding the sidewalls of the previous active trench and is filled with a conductive material.   126. The semiconductor device of claim 125, wherein the conductive material inside the first termination trench is electrically coupled to a source metal.   127. The semiconductor device of claim 126, wherein the conductive material inside the first termination trench is buried below the dielectric in the lower portion of the termination trench.   126. The semiconductor device of claim 125, wherein the first termination trench is filled with a dielectric.   126. The semiconductor device of claim 125, wherein a width of a mesa formed between the first termination trench and an adjacent active trench is different from a width of a mesa formed between two active trenches. .   126. The semiconductor device of claim 125, wherein the first termination trench surrounds an active area of the device in a ring shape.   132. The semiconductor device of claim 131, further comprising a second termination trench surrounding the active region of the device outside the first termination trench.   135. The distance S1 between the first and second termination trenches is approximately twice the distance S2 between the first termination trench and the end of the active trench. Semiconductor devices.   A termination structure at an outer edge of a semiconductor device, wherein the termination structure includes a plurality of concentric rings of pillars of a first conductivity type, the pillars being opposite to the first conductivity type A termination structure formed within a termination region of a second conductivity type and surrounding the active region of the device, wherein each pillar is separately connected to a conductive field plate.   A large field plate made of a conductive material covers and is dielectrically separated from the plurality of pillar subsets, the separated conductive field plate being a remaining one of the plurality of pillars. 135. The semiconductor device according to claim 134, wherein the semiconductor device is connected to the semiconductor device.   136. The semiconductor device of claim 135, wherein the large field plate is grounded.   135. The semiconductor device of claim 134, wherein the subset of pillars is not covered by a conductive field plate.   135. The semiconductor device according to claim 134, wherein a center-to-center distance between the plurality of pillars varies depending on a distance from an end of the active region.   138. The semiconductor device of claim 138, wherein a center-to-center distance between the plurality of pillars increases with a distance from an end of the active region.   135. The semiconductor device of claim 134, wherein the width of each pillar varies with the distance from the end of the active region.   141. The semiconductor device of claim 140, wherein the width of each pillar decreases with distance from an edge of the active region.   The width of the plurality of pillars in the termination structure is the same, but the width of the heteropolar pillar under the well region inside the active region decreases with the distance from the well region. Item 134. The semiconductor device according to Item 134. A method of forming a buried conductive layer inside a trench formed in a semiconductor substrate,
Forming a first dielectric layer on top of the semiconductor substrate and the trench;
Forming a first conductive material layer over the first dielectric layer;
Patterning the first dielectric layer and the first conductive material layer to extend a first portion extending into the trench along a longitudinal axis of the trench; and a first end of the trench Forming a first conductive electrode having a second portion extending across the surface of the substrate;
Forming a second dielectric layer over the first conductive material layer;
Forming a second dielectric layer over the second conductor material layer;
Patterning the second dielectric layer and the second conductive material layer and extending a first portion extending into the trench along a longitudinal axis of the trench; and the first portion of the first conductive electrode. Forming a second conductive electrode having a second portion extending across the surface of the two portions;
A method for forming a buried conductive layer, comprising: Contacting the first conductor layer through an opening in the first dielectric layer of the second portion of the first conductive electrode;
Contacting the second conductor layer through an opening in the second dielectric layer of the second portion of the second conductive electrode;
144. The method of claim 143, further comprising: A method of forming a buried conductive layer inside a trench formed in a semiconductor substrate,
Forming a first dielectric layer on top of the semiconductor substrate and the trench;
Forming a first conductive material layer over the first dielectric layer;
Patterning the first dielectric layer and the first conductive material layer, a first horizontal portion extending into the trench along the longitudinal axis of the trench, and a first horizontal portion extending to the top surface of the substrate Forming a first conductive electrode having two vertical portions;
Forming a second dielectric layer over the first conductive material layer;
Forming a second dielectric layer over the second conductor material layer;
Patterning the second dielectric layer and the second conductive material layer, a first portion extending into the trench along the longitudinal axis of the trench, and a vertical portion extending to the top surface of the substrate Forming a second conductive electrode having a second portion;
A method for forming a buried conductive layer, comprising:   146. The semiconductor device of claim 145, further comprising contacting the second portion of the first and second conductive electrodes with the surface of the substrate. A method of forming each of a plurality of trenches having a first dielectric layer,
Filling the plurality of trenches with a first conductive material;
Applying a mask layer over one selected from the plurality of trenches;
Forming indentations in the first conductive material layer and the first dielectric layer in the remainder of the plurality of trenches;
Removing the mask layer;
Forming a second dielectric layer on the top surface of the substrate, including top surfaces and sidewalls of the remaining plurality of trenches;
Filling the top of the remaining plurality of trenches with a second conductive material layer;
Covering the second conductive material layer with a third dielectric layer;
A method comprising the steps of: A method of forming a buried conductive layer inside a plurality of trenches in a semiconductor substrate,
Surrounding each sidewall and bottom of the plurality of trenches with a first dielectric layer;
Filling the plurality of trenches with a first conductive material layer;
Removing the first dielectric layer from the top surface of the substrate and the sidewalls of the plurality of trenches to a first depth inside each trench, exposing a portion of the first conductive material layer; The exposed portion of the conductive material layer forming two recesses within each trench;
Applying a second dielectric layer covering the top surface of the substrate, the sidewalls of each trench and the surface of the first conductive material layer;
Filling the two recesses inside each trench with a second conductive material layer;
Covering the second conductive material layer with a third dielectric layer;
A method for forming a buried conductive layer, comprising: A method for controlling the thickness of an epitaxially grown semiconductor material comprising:
Providing a semiconductor substrate doped with a first type of dopant;
Forming a buffer layer on the substrate;
Forming the epitaxially grown layer on the buffer layer;
And the buffer layer is doped with a second type of dopant having a significantly lower diffusivity compared to the first type of dopant.   150. The method of claim 149, wherein the buffer layer is doped with arsenic. A method for controlling the thickness of a semiconductor material to be epitaxially grown, comprising:
Providing a semiconductor substrate doped with a first type of dopant;
Forming a buffer layer on the semiconductor substrate;
Forming the epitaxial growth layer on the buffer layer to a desired thickness;
Wherein the buffer layer has a composition comprising carbon and functions to counter updiffusion of the first type dopant from the substrate into the epitaxial growth layer.   The method of claim 151, wherein forming the buffer layer comprises growing a layer of silicon carbide.   152. The method of claim 151, wherein forming the buffer layer comprises implanting a carbon dopant into a surface of the semiconductor substrate. A method for controlling the thickness of a semiconductor material to be epitaxially grown, comprising:
Providing a semiconductor substrate doped with a first type of dopant;
Forming the epitaxial growth layer on the semiconductor substrate to a desired thickness;
Forming a well region within the epitaxial growth layer;
Forming a diffusion buffer layer at the junction between the epitaxial growth layer and the well region;
The well region has a second type dopant having a conductivity opposite to the first type dopant, and the buffer layer resists dopant diffusion between the well region and the epitaxial growth layer. A method characterized by functioning.   156. The method of claim 154, wherein forming the buffer layer comprises implanting carbon atoms through a window defining the well region. A method of forming a trench gate transistor comprising:
Providing a substrate of a first conductivity type;
Forming a drift region of the first conductivity type on the substrate;
Forming a trench in the drift region;
Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the bottom of the trench with a first conductive material layer;
Covering the first conductive material layer with an interlayer dielectric;
Selectively growing an epitaxial layer of a second conductivity type opposite to the first conductivity type, and forming a well region on the upper surface of the drift region and the upper trench portion of the interlayer dielectric;
A method comprising the steps of: A method for forming a well region in a semiconductor device, comprising:
Providing a substrate of a first conductivity type;
Forming a drift region of the first conductivity type on the substrate;
Forming a trench in the drift region;
Forming a buried electrode encapsulated with a dielectric at the lower portion of the trench, leaving the upper sidewalls of the trench exposed; and
Filling a first well in the upper surface of the drift region with a dopant of a second conductivity type opposite to the first conductivity type;
Performing a second well-filled well with a second conductivity type dopant through the exposed sidewall at the top of the trench;
A method comprising the steps of: A method for forming a well region in a semiconductor device, comprising:
Providing a substrate of a first conductivity type;
Forming a drift layer of the first conductivity type on the substrate;
Forming a dielectric pillar over the drift region;
Forming a second drift layer of the first conductivity type on the first drift layer and around the dielectric pillar;
An epitaxial layer of a second conductivity type opposite to the first conductivity type is selectively grown, and a well region is formed on a top surface of the second drift region and a trench formed on each of the dielectric pillars. Forming a step;
Wherein each of the pillars has a width equal to the width of the trench formed in the next step. A method of thinning a wafer of semiconductor material,
Completing the fabrication of devices on the surface of the wafer;
Temporarily bonding the surface of the wafer to a carrier by a first bonding step;
Thinning the backside of the wafer to a desired thickness;
Bonding the backside of the thinned wafer to a low resistance substrate by a second bonding process;
Removing the carrier and cleaning the surface of the wafer;
A method comprising the steps of:   The method of claim 159, wherein the thinning step comprises a polishing step.   160. The method of claim 159, wherein the thinning step comprises a chemical process. A method of thinning a silicon substrate,
Bonding the back surface of the silicon substrate to a glass substrate;
Forming a silicon-on-thick glass (SOTG) substrate by optically cutting the silicon substrate;
Forming an epitaxial layer on the silicon surface of the SOTG substrate;
Fabricating an active device on a silicon surface of the SOTG substrate;
Removing a part of the glass substrate from the back surface of the silicon substrate by a polishing process;
Removing the remaining portion of the glass substrate from the back surface of the silicon substrate by a chemical etching step;
A method comprising the steps of: A method of etching a trench in a semiconductor substrate comprising:
Performing a first etch to a first depth;
Performing a second etch to a final depth;
Wherein the first etch uses a chlorine-based chemistry, resulting in an intermediate trench having tapered smooth sidewalls, and the second etch uses a fluorine-based chemistry And the second etch based on the fluorine provides rounding of the bottom of the trench and further smoothes the sidewalls of the trench. The first chemical etch includes Cl ₂ / HBr, the second etch chemistry The method of claim 163, wherein the containing SF _6. A method of etching a trench in a semiconductor substrate comprising:
Performing a first etch to a first depth;
Performing a second etch to a final depth;
Wherein the first etch uses a fluorine-based chemistry, resulting in an intermediate trench having straight sidewalls and a rounded bottom, and the second etch is a chlorine-based chemistry Wherein the second fluorine-based etch provides rounding at the top corner of the trench and further smoothes the trench sidewalls. The first chemical etch contains CF ₆ / O2, the second etch chemistry The method of claim 165, wherein the containing Cl _2. A method of etching a trench in a semiconductor substrate comprising:
Performing a first etch using fluorine-based chemistry with argon added to increase ion bombardment and counteract the refraction angle tendency of the surface of the trench;
Performing a second etch to smooth the trench sidewalls;
A method comprising the steps of: Said first etch chemistry The method of claim 167, wherein the containing SF ₆ / O ₂ / Ar. A method of etching a trench in a semiconductor substrate comprising:
Performing a first etch using oxygen-free fluorine-based chemistry;
Performing a second etch using oxygen based fluorine based chemistry; and
And the first etch increases the side etch at the top of the trench, and the second etch provides straight sidewalls and a rounded bottom for the remainder of the trench. A method characterized by that. It said first etch chemistry comprises SF _6, the second etch chemistry The method of claim 167, wherein the containing SF ₆ / O _2. A method of etching a deep trench in a semiconductor substrate,
Using oxygenated fluorine-based chemistry;
Ramping power and pressure to control ion flux density and maintain a constant etch rate;
And oxygen is introduced in a tilted manner to control the surface stabilization treatment of the sidewalls. A method of etching a deep trench in a semiconductor substrate,
A first etch is performed using a more reactive fluorine-based chemistry containing nitrogen, followed by a less reactive fluorine-based chemistry containing SF _6. Method. It said first etch chemistry comprises NF _3, wherein the second etch chemistry The method of claim 172, wherein the containing SF ₆ / O _2.   178. The method of claim 173, further comprising the step of alternately repeating the first and second etching steps. Etching a trench in a semiconductor substrate,
Forming a thin layer of pad oxide on the top surface of the substrate;
Forming a layer of non-oxidized material on the pad oxide;
Forming a layer of silicon nitride over the layer of conductive material;
Patterning the layer of pad oxide, non-oxidized material and silicon nitride to define an opening for forming a pre-trench;
Etching the trench through the opening;
And the insertion of the layer of non-oxidized material between the pad oxide layer and the silicon nitride layer causes the pad oxide to grow at the end of the trench during the next processing step. A process characterized by countering. Etching a trench in a semiconductor substrate,
Forming a thin layer of pad oxide on the top surface of the substrate;
Forming a layer of silicon nitride over the pad oxide;
Patterning the pad oxide and silicon nitride layer to define an opening for forming the trench;
Forming a thin layer of non-oxidized material on the surface structure of the substrate;
Removing a thin layer of oxygen free material from the horizontal surface of the surface structure, leaving a spacer of oxygen free material along the vertical edges of the nitride pad oxide;
Etching the trench through the opening;
Wherein the non-oxidized material spacer counteracts the growth of pad oxide at the end of the trench during the next processing step. Forming a dielectric layer between the electrodes inside the trench,
Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the trench with a first conductive material layer to form a first electrode;
Creating a recess in the first dielectric layer and the first conductive material layer to a first depth inside the trench;
Forming a layer of polysilicon material on top of the conductive material and dielectric inside the trench;
Converting the layer of polysilicon material into a layer of silicon dioxide by oxidizing;
Forming on the silicon dioxide a second electrode made of a conductive material inside the trench and separated from the trench sidewall by a second dielectric layer;
The process characterized by including. Forming a dielectric layer between the electrodes inside the trench,
Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the trench with a first conductive material layer to form a first electrode;
Creating a recess in the first dielectric layer to a first depth inside the trench;
Filling the remainder of the trench with a dielectric fill material;
Recessing the first dielectric layer and the dielectric filling material to a second depth to form an interelectrode dielectric layer;
Forming a second electrode made of a conductive material inside the trench and separated from the trench sidewall by a second dielectric layer on the interelectrode dielectric layer;
The process characterized by including. Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the trench with a first conductive material layer to form a first electrode;
Forming a recess in the first conductive material layer to a first depth inside the trench, and making an upper portion of the concave conductive material higher than a final target depth by a desired depth;
Increasing the oxidation rate of the top of the first conductive material layer by changing its properties;
Removing the first dielectric layer from the remainder of the trench sidewalls;
Performing an oxidation step;
Forming, on the interelectrode dielectric layer, a second electrode made of a conductive material and separated from the trench sidewall by a sidewall dielectric lining inside the trench;
And forming the inter-electrode dielectric thicker than the sidewall dielectric lining by oxidizing the altered top portion of the first conductive material layer at a faster rate than the sidewalls of the trench. Characteristic process.   180. The method of claim 179, wherein increasing the oxidation rate of the upper portion of the first conductive material layer includes changing the upper portion by one of chemical or physical methods.   179. The method of claim 179, wherein increasing the oxidation rate on top of the first conductive material layer comprises implanting impurities perpendicular to the top surface of the first conductive material layer.   181. The method of claim 181, wherein the impurity is one of argon or fluorine. A method of forming an interelectrode dielectric layer in a trench,
Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the trench with a first conductive material layer to form a first electrode;
Creating a recess in the first dielectric layer and the first conductive material layer to a first depth inside the trench;
By selectively forming a second dielectric layer, a relatively thick inter-electrode dielectric layer is formed on the horizontal structure inside the trench and a relatively thin dielectric layer is formed on the sidewall of the trench. Steps formed along;
Removing the relatively thick dielectric layer along the sidewalls of the trench;
Forming, on the interelectrode dielectric layer, a second electrode made of a conductive material and separated from the trench sidewall by a sidewall dielectric lining inside the trench;
The process characterized by including.   184. The method of claim 183, wherein selectively forming the second dielectric layer comprises a directional deposition process.   185. The method of claim 184, wherein the directional deposition step comprises plasma enhanced chemical vapor deposition. A method of forming an interelectrode dielectric layer in a trench,
Surrounding the trench sidewalls and bottom with a first dielectric layer;
Filling the trench with a first conductive material layer to form a first electrode;
Creating a recess in the first dielectric layer and the first conductive material layer to a first depth inside the trench;
Forming a thin layer of screen oxide along vertical and horizontal planes inside the trench;
Forming a layer of silicon nitride overlying the thin layer of screen oxide;
Removing the silicon nitride from the bottom of the trench to expose a horizontal layer of screen oxide but leave the vertical screen oxide covered by silicon nitride;
Exposing the trench to an oxidizing environment and forming a thick interelectrode dielectric layer on a horizontal bottom of the trench;
Removing silicon nitride from the trench sidewalls;
Forming, on the interelectrode dielectric layer, a second electrode made of a conductive material and separated from the trench sidewall by a sidewall dielectric lining inside the trench;
A method comprising the steps of: A method of forming an interelectrode dielectric layer inside a trench formed in a semiconductor substrate,
Forming a first electrode made of a conductive material and separated from the sidewalls and bottom of the trench by a first dielectric lining at the bottom of the trench;
Forming a thick layer of dielectric filling the trench and extending over the semiconductor substrate;
Planarizing the thick layer of dielectric to the top surface of the semiconductor substrate;
Performing an isotropic wet etching process to form a depression in the remaining portion of the thick dielectric layer inside the trench;
A method comprising the steps of:   187. The method of claim 187, wherein the planarizing step includes performing an anisotropic plasma etch process.   188. The method of claim 187, wherein the planarizing step comprises performing a chemical mechanical planarization process. A method for forming an oxide layer on a semiconductor wafer, comprising:
Applying a DC bias to the semiconductor wafer in a test environment;
Defining a DC bias condition that suppresses surface reaction with oxygen;
Applying an external bias to the semiconductor wafer during oxidation;
Manipulating the external bias to optimize the oxidation rate;
A method comprising the steps of: A method of forming a thick oxide at the bottom of a trench formed in a semiconductor substrate,
Forming a conformal oxide film by quasi-atmospheric chemical vapor deposition filling the trench and covering the top surface of the substrate;
Etching the oxide film from the top surface of the substrate and the interior of the trench, leaving a flat layer of oxide having a target thickness at the bottom of the trench;
A method comprising the steps of:   191. The method of claim 191, further comprising performing a heat treatment to make the oxide film dense. A method of forming a thick oxide at the bottom of a trench formed in a semiconductor substrate,
Depositing an oxide film by a directional tetraethyl silicate (TEOS) process that forms a thick oxide film on a horizontal plane including the bottom of the trench from a vertical plane including a trench sidewall;
Etching the oxide film isotropically until all oxide in the trench has been removed leaving a layer of oxide at the bottom of the trench having a target thickness;
A method comprising the steps of:   196. The method of claim 193, wherein the etching step comprises a dry top oxide etch followed by a wet buffered oxide etch.   194. The top oxide etch includes a fog etching step that etches the oxide near the top end of the trench at an accelerated rate compared to the oxide near the bottom of the trench. The method described. A method of forming a thick oxide at the bottom of a trench formed in a semiconductor substrate,
Depositing an oxide film by a high density plasma deposition process that forms a thicker oxide at the bottom of the trench than the trench sidewall;
Removing the oxide from the trench sidewalls by a wet etch process, and tilting the trench profile from the top of the trench;
A method comprising the steps of: A method of forming a thick oxide at the bottom of a trench formed in a semiconductor substrate,
Forming a layer of pad oxide on the substrate;
Depositing a thin layer of silicon nitride on the pad oxide;
Performing anisotropic etching to remove silicon nitride from the horizontal plane leaving silicon nitride on the trench sidewalls;
Depositing oxide on a gastric plane including the bottom of the trench using quasi-atmospheric chemical vapor deposition;
Removing the oxide-nitride-oxide sandwich layer from the trench sidewalls by an etching process;
A method comprising the steps of: A method of forming a thick oxide at the bottom of a trench formed in a semiconductor substrate,
Forming a thin layer of pad oxide on the substrate including sidewalls and bottom of the trench;
Forming a nitride layer on the surface of the pad oxide and etching the nitride on a horizontal plane leaving an adjacent nitride pad oxide layer on the trench sidewall;
Removing the pad oxide from a horizontal plane to expose the top surface of the substrate and the bottom surface of the trench;
Performing anisotropic etching of the exposed horizontal surface to remove semiconductor material from the bottom of the trench to a desired depth to form a lower trench;
Growing an oxide layer in locations not covered by nitride, including the lower trench;
Removing the nitride and pad oxide and extending a thick lower oxide along the sidewalls of the trench;
A method comprising the steps of: A power device formed on a single semiconductor substrate,
A power transistor having a charge adjustment structure formed inside the trench;
A current sensing device formed adjacent to the power transistor and separated from the power device by a dielectric region;
One or more charge conditioning trenches formed under the current sensing device;
A continuity in charge adjustment is maintained across the semiconductor substrate. A power device formed on a single semiconductor substrate,
A power transistor having a charge adjustment structure formed inside the trench;
One or more diode structures formed adjacent to the power transistor and separated from the power device by a dielectric region;
One or more charge control trenches formed under the one or more diode structures;
A continuity in charge adjustment is maintained across the semiconductor substrate. A method of forming an improved power device, comprising:
Providing a semiconductor substrate having a first conductivity type;
Forming an elongated trench in the substrate having a lower electrode formed in a lower portion of the trench, separated from a sidewall and a lower portion of the trench by a first dielectric lining;
Forming an interelectrode dielectric layer on the lower electrode;
Forming an upper electrode separated from the trench sidewall by a second dielectric lining on the interelectrode dielectric layer at the top of the trench;
Forming a well region having a second conductivity type opposite to the first conductivity type adjacent to the trench;
Forming a source region having the first conductivity type within the well region;
Applying silicide to the upper surface of the upper electrode after forming the well region and the source region;
Wherein the upper electrode includes a gate terminal of the power device, and the silicide reduces an equivalent series resistance of the device. A method of forming a power device having a low equivalent series resistance comprising:
Forming a gate structure in a plurality of parallel trenches;
Forming a surface layer of silicide conductive material extending perpendicularly to the plurality of trenches and contacting the trenches at intersections with the plurality of parallel trenches;
A method comprising the steps of: A DC-DC converter,
A high side switch made from a dual gate power transistor having a first gate electrode and a second gate electrode, a source electrode and a drain electrode;
A low side switch made from a dual gate power transistor having a first gate electrode and a second gate electrode, a source electrode and a drain electrode connected to the source electrode of the high side switch;
A first drive circuit coupled to the first gate electrode of the high side switch;
A second drive circuit coupled to the first gate electrode of the low-side switch;
And the second gate electrodes of the high-side switch and the low-side switch are connected to receive the first drive signal and the second drive signal, respectively, and optimize the switching speed of each transistor, DC-DC converter.

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