JP5135663B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor device such as a diode, MOSFET (MOS field effect transistor), IGBT (insulated gate bipolar transistor), and bipolar transistor, and more particularly to its breakdown voltage structure.

In vertical semiconductor devices that require high breakdown voltage, a breakdown voltage structure using field plate electrodes, guard rings, etc. is used to ensure stable breakdown voltage while suppressing leakage current at the outer periphery of the semiconductor chip. Formed in the part. However, since the region where the withstand voltage structure is formed is an ineffective region in which almost no current flows even when conducting, it is desirable that the area occupied by the semiconductor chip (occupied area of the withstand voltage structure) is small. The content disclosed about this pressure | voltage resistant structure is demonstrated below.
For example, in Non-Patent Document 1 and Non-Patent Document 2, a trench is formed in the outer peripheral portion of a semiconductor chip, the trench side wall and a pn junction surface having a withstand voltage are orthogonal to each other, and an insulating film is coated on the side wall and bottom surface of the trench. Thus, the area occupied by the pressure-resistant structure is reduced.
Further, in Patent Document 1, a trench is formed in the outer peripheral portion of a semiconductor chip, the trench side wall and a pn junction surface having a withstand voltage are orthogonal to each other, the trench is filled with an insulating film, and an insulating film is formed on the insulating film. A field plate electrode is formed so as to cover the portion, and the occupied area (width) of the pressure-resistant structure is reduced.
Japanese Patent No. 3031282 Proceedings of ISPSD'02, pp257-260 Proceedings of ISPSD '03, pp 199-202

However, the breakdown voltage structure using the trench is effective in reducing the occupied area of the breakdown voltage structure, but since the insulating film filled in the trench is exposed on the surface, external charges are exposed on the surface of the exposed insulating film. If this occurs, the potential distribution is distorted by this external charge, causing electric field concentration and lowering the breakdown voltage.
FIG. 10 is a diagram showing the relationship between the amount of external charge deposited on the oxide film and the breakdown voltage. FIG. 6 is a simulation diagram when the length L of the field plate electrode on the oxide film is 20 μm and the width W of the trench is 60 μm.
Assuming that the withstand voltage when no external charge is attached is 100%, and the external charge amount attached to the oxide film surface is + 0.5 × 10 ¹² × 1.6 × 10 ⁻¹⁹ C / cm ² , the withstand voltage ratio is In the case of + 1 × 10 ¹² × 1.6 × 10 ⁻¹⁹ C / cm ² , the breakdown voltage ratio decreases to 80%. This charge amount of + 1 × 10 ¹² × 1.6 × 10 ⁻¹⁹ C / cm ² is assumed to be the largest in the actual use environment.

In addition, the trench formed in the outer peripheral portion of the semiconductor chip is easily damaged by mechanical damage. When the mechanical damage causes a crack or the like in the oxide film in the trench or the semiconductor substrate around the trench, the breakdown voltage is lowered.
An object of the present invention is to solve the above-described problems, and to provide a semiconductor device having a high withstand voltage structure that eliminates the influence of external charges, has a small occupied area, has a stable high withstand voltage, and is highly reliable. .

To achieve the above objective,
(1) a second semiconductor layer of a second conductivity type selectively formed on the surface layer of the first main surface of the first semiconductor layer of the first conductivity type;
A third semiconductor layer of a first conductivity type in contact with the first semiconductor layer on the second main surface side of the first semiconductor layer and having a higher concentration than the first semiconductor layer;
A pressure-resistant structure portion formed on an outer peripheral portion of the second semiconductor layer in a surface layer of the first main surface of the first semiconductor layer;
The pressure-resistant structure portion is spaced from the outer peripheral side end of the first semiconductor layer to the inner peripheral side, and penetrates the first semiconductor layer from the first main surface of the first semiconductor layer. A trench that reaches the inside and is formed on the outer peripheral side of the second semiconductor layer;
An insulating film formed in the trench;
A recess formed in the insulating film;
Covers the upper surface on the inner peripheral side of the insulating film in the trench, reaches the upper surface opening of the recess, bends from the upper surface opening into the recess, extends in the depth direction of the recess, and terminates at the bottom A conductive film formed to fill the recess by
A first main electrode formed on the second semiconductor layer and in contact with the conductive film so as to have the same potential as the conductive film;
A second main electrode formed on a main surface opposite to a side in contact with the first semiconductor layer of the main surface of the third semiconductor layer;
An outer peripheral edge of the second semiconductor layer is in contact with the trench;
The thickness of the first semiconductor layer is greater than 10 times the diffusion depth of the second semiconductor layer,
The depth of the conductive film reaching the bottom of the recess is deeper than the diffusion depth of the second semiconductor layer and shallower than the third semiconductor layer, and twice the diffusion depth of the second semiconductor layer. The configuration is 10 times.
(2) a second conductivity type second semiconductor layer selectively formed on a surface layer of the first main surface of the first conductivity type first semiconductor layer;
A third semiconductor layer of a first conductivity type in contact with the first semiconductor layer on the second main surface side of the first semiconductor layer and having a higher concentration than the first semiconductor layer;
A pressure-resistant structure portion formed on an outer peripheral portion of the second semiconductor layer in a surface layer of the first main surface of the first semiconductor layer;
The pressure-resistant structure portion is spaced from the outer peripheral side end of the first semiconductor layer to the inner peripheral side, and penetrates the first semiconductor layer from the first main surface of the first semiconductor layer. A trench that reaches the inside and is formed on the outer peripheral side of the second semiconductor layer;
A first insulating film formed in the trench;
A recess formed in the first insulating film;
A second insulating film formed on the first semiconductor layer between the second semiconductor layer and the first insulating film;
Covers the inner peripheral upper surface of the first insulating film in the trench, reaches the upper surface opening of the recess, bends from the upper surface opening into the recess, and extends in the depth direction of the recess. A conductive film formed to fill the recess by terminating at the bottom;
A first main electrode formed on the second semiconductor layer and the second insulating film and in contact with the conductive film so as to have the same potential as the conductive film;
A second main electrode formed on a main surface opposite to a side in contact with the first semiconductor layer of the main surface of the third semiconductor layer;
The outer peripheral edge of the second semiconductor layer is separated from the trench,
The thickness of the first semiconductor layer is greater than 10 times the diffusion depth of the second semiconductor layer,
The depth of the conductive film reaching the bottom of the recess is deeper than the diffusion depth of the second semiconductor layer and shallower than the third semiconductor layer, and twice the diffusion depth of the second semiconductor layer. The configuration is 10 times.
(3) The third semiconductor layer may be a semiconductor substrate, and the first semiconductor layer may be an epitaxial growth layer formed on the semiconductor substrate.
(4) The conductive film may be metal or polysilicon.
(5) In the method of manufacturing a semiconductor device according to (1) to (3), the insulating film or the first insulating film is an oxide film, and the first semiconductor is formed from the first main surface of the first semiconductor layer. Forming a plurality of grooves toward the inside of the layer; forming a surface of the first semiconductor layer in contact with the grooves; and forming an oxide film on the entire area of the first semiconductor layer sandwiched between the grooves; and The manufacturing method includes a step of forming a recess and forming a conductive film in the recess or forming a conductive film on the entire surface of the oxide film.
(6) before Kimizo lattice shape may be any of the island-like and stripe.
(7) The oxide film may be formed by thermally oxidizing the first semiconductor layer.
(8) The conductive film may be metal or polysilicon.

In the present invention, a trench is formed in the outer peripheral portion of the semiconductor chip, an insulating film is filled in the trench, a recess is dug in the insulating film, and a field plate electrode is formed in the recess, thereby generating a potential distribution. A semiconductor device having a withstand voltage structure that can suppress distortion, eliminate the influence of external charges, prevent electric field concentration, have a small occupation area, and can secure high reliability with a high and stable withstand voltage.
In addition, by covering the entire surface of the insulating film filled in the trench with a field plate electrode, the distortion of the potential distribution is suppressed, the influence of external charges is eliminated, the electric field concentration is prevented, and the occupied area is reduced. Thus, a semiconductor device having a breakdown voltage structure capable of ensuring high reliability with a high and stable breakdown voltage can be obtained. In particular, by covering the trench with the field plate electrode, the mechanical strength in the vicinity of the trench is increased, and mechanical damage in the trench can be prevented.

  Embodiments of the present invention will be described below. In the region where n or p is mentioned below, it means that electrons and holes are majority carriers, respectively. The superscript + indicates a relatively high impurity concentration and-indicates a low impurity concentration. In all the examples, the first conductivity type is defined as n-type and the second conductivity type is defined as p-type, but the embodiment is the same even if this is the opposite. The field plate electrode can be made of metal or polysilicon.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. A trench 3 reaching the n ⁺ semiconductor substrate 1 from the surface of the first main surface of the n semiconductor substrate 100 in which the n epitaxial layer 2 serving as the n drift layer is formed on the n ⁺ semiconductor substrate 1 serving as the n ⁺ drain layer is formed. Then, the trench 3 is filled with the insulating film 4, and the recess 5 is formed in the insulating film 4. A p well region 6 is formed in the surface layer of n semiconductor substrate 100 (surface layer of n epitaxial layer 1) so as to be in contact with trench 3, and n ⁺ source region 7 and p ⁺ are formed in the surface layer of p well region 6. Contact region 8 is formed. A gate electrode 10 is formed on the p well region 6 sandwiched between the n ⁺ source region 7 and the n semiconductor substrate 100 via a gate insulating film 9. A source electrode 12 is formed on the n ⁺ source region 7 and the p ⁺ contact region 8, and the field plate electrode 13 connected to the source electrode 12 is insulated from the insulating film 3 in order to fix the source electrode 12 at a potential. formed in the recess 5 of the film 3 to form the drain electrode 14 on the second main surface of the n semiconductor substrate 100 (n ⁺ drain region to become n ⁺ back surface of the semiconductor substrate 1).

Here, the n semiconductor substrate 100 is an epitaxial substrate in which the n epitaxial layer 2 is formed on the n ⁺ semiconductor substrate 1 (which becomes the n ⁺ drain region), but a single crystal n semiconductor substrate is used. The p well region 6 may be formed on the surface layer of the first main surface, and the n ⁺ drain region may be formed on the surface layer of the second main surface.
Here, the amount of external charge adhering to the surface of the insulating film 4 is −1 × 10 ¹² × 1.60 × 10 ⁻¹⁹ C / cm ² to + 1 × 10 ¹² × 1.60 × 10 ⁻¹⁹ C / cm. ^When the pn junction between the p-well region 6 and the n epitaxial layer 2 is infinitely flat and the avalanche voltage when there is no external charge 15 is an ideal withstand voltage, the ratio to the ideal withstand voltage (ideal withstand voltage) Ratio).
Assuming that the length of the field plate electrode in the insulating film 4 is X and the diffusion depth of the p-well region 6 is e, the ideal withstand voltage ratio is 80% or more when X / e is in the range of 2 to 10 times. . In an ordinary voltage design, if the ideal withstand voltage ratio is 80% or more, a sufficient withstand voltage can be secured in an actual device. The range of the external charge amount is a range that can be considered in an actual use environment.

When X is too small, the withstand voltage is greatly affected by the external charge, and the breakdown voltage is greatly reduced. When X is too large, the influence of the external charge is reduced, but rather the n ⁺ drain region (n ⁺ semiconductor The tip 13a of the field plate electrode gets too close to the substrate 1), and the potential distribution is distorted and the breakdown voltage is lowered.
FIG. 2 is a simulation diagram showing the relationship between the length of the field plate electrode in the insulating film of the semiconductor device of FIG. 1 and the breakdown voltage. The horizontal axis represents the ratio X / e of the length X of the field plate electrode in the recess 5 to the diffusion depth e of the p-well region 6, and the vertical axis represents the ideal withstand voltage ratio. Further, the width of the trench is indicated by f, the width of the surface of the insulating film 4 is indicated by h and g, h is the width of the surface of the insulating film 4 covered with the field plate electrode 13, and g is the exposure of the insulating film 4. The width of the surface. Specific specifications are f = 10 μm, g = h = 2.5 μm, e = 3.5 μm, and the thickness of the n epitaxial layer 2 is 50 μm. X was changed in the range of 0 μm to 38.5 μm.

Normally, the element withstand voltage is set to 80% or more of the ideal withstand voltage, and in order to set the ideal withstand voltage ratio to 80% or more, X / e is preferably set to 2 to 10 times from FIG.
Thus, by setting X / e to 2 to 10 times, the p well region 6 or n when the reverse voltage is applied to the pn junction between the p well region 6 and the n epitaxial layer 2 (n semiconductor substrate 100). The irregular bending of equipotential lines in the epitaxial layer 2 is reduced, electric field concentration generated at the contact point between the pn junction and the trench is less likely to occur, and a stable high breakdown voltage is ensured with a breakdown voltage structure with a small occupied area. it can.
In FIG. 2, the amount of external charge adhering to the surface of the insulating film 4 is −1 × 10 ¹² × 1.60 × 10 ⁻¹⁹ C / cm ² to + 1 × 10 ¹² × 1.60 × 10 ⁻¹⁹ C / It was found that there was no change even in the cm ² range. This is because the field plate electrode 13 covers the insulating film 4 on the side where electric field concentration is likely to occur, and the field plate electrode 13 functions to block the external charges 15.

  The field plate electrode 13 is connected to the source electrode 12. However, if the distance between the field plate electrode 13 and the source electrode 12 is sufficiently short, the field plate electrode 13 is not necessarily connected because it is equivalently fixed to the source potential. It doesn't matter.

FIG. 3 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from FIG. 1 is that the p-well region 6 is formed away from the trench 3. The field plate electrode 13 is formed via an interlayer insulating film 17 which is a field insulating film. This interlayer insulating film 17 may be formed simultaneously with the insulating film 4.
Also in this case, similarly to FIG. 1, by forming the field plate electrode 13 in the recess 5 of the insulating film 4, the distortion of the potential distribution is corrected, the electric field concentration is prevented, and the breakdown voltage structure with a small occupied area is obtained. A stable high breakdown voltage can be secured.

FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The difference from FIG. 1 is that the field plate electrode 13 is covered on the entire surface of the insulating film 4 filling the trench 3. An interlayer insulating film 16 is formed on the n epitaxial layer 2 outside the trench 3 so that the tip 13a of the field plate electrode 13 is in contact with the n epitaxial layer 2 (n semiconductor substrate 100) outside the trench 3 and the breakdown voltage is not lowered. Then, the end 13a of the field plate electrode is positioned on the interlayer insulating film 16.
Since the field plate electrode 13 covers the entire upper surface of the insulating film 4 filled with the trench 3 (the upper entire surface is a projection region on the upper surface because there is a portion covered with the interlayer insulating film 16), the external charge 15, the occupation area is small, a stable high breakdown voltage and high reliability can be secured.

  Furthermore, since the field plate electrode 13 functions to reinforce the trench 3 portion having a low mechanical strength, a pressure-resistant structure that is strong against mechanical damage in the trench 3 portion can be obtained.

FIG. 5 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. The difference from FIG. 4 is that the p-well region 6 is formed away from the trench 3 as in FIG. Also in this case, since the entire surface of the insulating film 4 filled with the trench 3 is covered with the field plate electrode 13, it is not affected by the external charge 15, has a small occupation area, and can secure a stable high breakdown voltage and high reliability. It can be.
Furthermore, since the field plate electrode 13 functions to reinforce the trench 3 portion having a low mechanical strength, a pressure-resistant structure that is strong against mechanical damage in the trench 3 portion can be obtained.

FIG. 6 is a cross-sectional view of the principal part of the semiconductor device according to the fifth embodiment of the present invention. In FIG. 4, even when the external charge 15a enters the insulating film 4 in the trench 3, a p-type impurity, for example, boron is ion-implanted into the sidewall of the trench 3 to form the ion-implanted layer 18, thereby forming the trench 3 By reducing the effective impurity concentration of the n-type epitaxial layer 2 on the side wall or forming an inversion layer, the distortion of the potential distribution can be corrected to prevent the breakdown voltage from decreasing.
When the impurity concentration of the n epitaxial layer 2 is 2.5 × 10 ¹⁴ cm ⁻³ and the external charge amount is + 1 × 10 ¹² × 1.60 × 10 ⁻¹ C / cm ² , for example, the impurity concentration of boron By reducing the peak value of 5 × 10 ¹⁴ cm ⁻³ or more, a decrease in breakdown voltage is prevented. Further, if the boron impurity concentration is too high, the potential distribution is disturbed, so the peak value of the boron impurity concentration is preferably 1 × 10 ¹⁶ cm ⁻³ or less.

FIG. 7 is a graph showing the relationship between the peak value of the impurity concentration of boron and the breakdown voltage. The vertical axis represents the ideal withstand voltage ratio (%). This is a case where the external charge amount is + 1 × 10 ¹² × 1.60 × 10 ⁻¹ C / cm ² .
An ideal breakdown voltage ratio of 80% or more can be ensured when the peak value of the impurity concentration of boron is in the range of 5 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . In FIGS. 1 and 3, this boron implantation method is also effective.

FIGS. 8A to 8D are views showing a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIGS. 8A to 8D are cross-sectional views showing the main part manufacturing steps shown in the order of steps. This manufacturing method is an example of a method for filling an oxide film that is an insulating film in a trench, and is a manufacturing method applicable to FIGS. 1 and 3 to 5.
First, an n semiconductor substrate 100 in which an n epitaxial layer 2 is formed on an n ⁺ semiconductor substrate 1 is prepared. ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching) leaves the silicon as the n semiconductor substrate 100 in a lattice shape (including a strip shape) or a column shape, and etches to reach the n ⁺ semiconductor substrate 1 to form the minute groove 21. Form. However, at this time, (6 × a) /b=1/2.2 to 1 / 2.3 between the width 6 × a of silicon oxidized in the next step and the oxide film region width b after oxidation. It is made to hold (the figure (a)).

Next, the silicon pillar 22 left in the etching process is completely oxidized by heat treatment (for example, pyrooxidation is performed at 1000 ° C. for 10 hours with a width of 1.5 μm of the inferior groove 21 and a width of 1.2 μm of the silicon pillar 22). Then, an oxide film 23 filling the equivalent trench 24 (corresponding to the trench 3 described above) is formed (FIG. 5B).
Next, by depositing the oxide film 25 by a CVD (Chemical Vapor Deposition) method, the concave portion on the surface of the oxide film 23 is completely filled (FIG. 3C).
Next, the entire surface 26 of the oxide film 25 is planarized ((d) in the figure).
As a result, a wide oxide film 27 is formed which is integrated without any cavities or irregularities. In this manner, the n semiconductor substrate 100 having the planarized oxide film 27 that is equivalently filled in the trench 24 is completed. When the semiconductor device of the first to fifth embodiments is manufactured using the n semiconductor substrate 100 (wafer), a semiconductor device having a withstand voltage structure that has a small occupation area and ensures a stable high withstand voltage and high reliability. Can be obtained.

In the case of the semiconductor device of FIG. 6, since boron is ion-implanted into the trench sidewall before filling the insulating film, the width of the minute groove is narrow, so that the ion implantation into the sidewall becomes difficult. A method of forming an insulating film in the trench cannot be adopted. For this reason, in the semiconductor device of FIG. 6, after forming a wide trench, a method of depositing an insulating film in the trench by a CVD method or the like is employed. Of course, this manufacturing method can be adopted in the case of the semiconductor device of FIGS. 1 and 3 to 5 as well as the case of the semiconductor device of FIG.
FIG. 9 is a plan view of the microgroove of FIG. 8. FIG. 9A shows a plurality of microgrooves, and when the microgroove is surrounded by silicon pillars, FIG. This is a case where it is formed in a lattice shape (including a strip-like lattice) and the silicon pillar is surrounded by minute grooves to form an island shape. The micro grooves 21 in FIG. 6A and the silicon pillars 22 in FIG. These silicon pillars 22 can be thermally oxidized to form a wide oxide film such as an oxide film filled in a wide trench (equivalent trench).

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. 1 is a simulation diagram showing the relationship between the length of the field plate electrode in the insulating film of the semiconductor device of FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention Figure showing the relationship between the peak value of impurity concentration of boron and the withstand voltage It is a figure which shows the manufacturing method of the semiconductor device of 6th Example of this invention, (a)-(d) is principal part manufacturing process sectional drawing shown to process order The figure which shows the planar shape of the micro groove of FIG. Diagram showing the relationship between the amount of external charge deposited on the oxide film and the breakdown voltage

Explanation of symbols

1 n ⁺ semiconductor substrate (n ⁺ drain layer)
2 n epitaxial layer (n drift layer)
3 trench 4 insulating film 5 recess 6 p well region 7 n ⁺ source region 8 p ⁺ contact region 9 gate insulating film 10 gate electrode 11 interlayer insulating film 12 source electrode 13 field plate electrode 13a tip of field plate electrode 14 drain electrode 15, 15a External charge 16 Interlayer insulation film 17 Interlayer insulation film (field insulation film)
18 Ion implantation layer 21 Micro groove 22 Silicon pillar 23, 25, 27 Oxide film 24 Equivalent trench 26 Whole surface 100 n Semiconductor substrate

Claims (8)

A second conductivity type second semiconductor layer selectively formed on the surface layer of the first main surface of the first conductivity type first semiconductor layer;
A third semiconductor layer of a first conductivity type in contact with the first semiconductor layer on the second main surface side of the first semiconductor layer and having a higher concentration than the first semiconductor layer;
A pressure-resistant structure portion formed on an outer peripheral portion of the second semiconductor layer in a surface layer of the first main surface of the first semiconductor layer;
The pressure-resistant structure portion is spaced from the outer peripheral side end of the first semiconductor layer to the inner peripheral side, and penetrates the first semiconductor layer from the first main surface of the first semiconductor layer. A trench that reaches the inside and is formed on the outer peripheral side of the second semiconductor layer;
An insulating film formed in the trench;
A recess formed in the insulating film;
Covers the upper surface on the inner peripheral side of the insulating film in the trench, reaches the upper surface opening of the recess, bends from the upper surface opening to the inside of the recess, and extends in the depth direction inside the recess to form the recess A conductive film formed to fill the recess by terminating at the bottom of
A first main electrode formed on the second semiconductor layer and in contact with the conductive film so as to have the same potential as the conductive film;
A second main electrode formed on a main surface opposite to a side in contact with the first semiconductor layer of the main surface of the third semiconductor layer;
An outer peripheral edge of the second semiconductor layer is in contact with the trench;
The thickness of the first semiconductor layer is greater than 10 times the diffusion depth of the second semiconductor layer,
The depth of the conductive film reaching the bottom of the recess is deeper than the diffusion depth of the second semiconductor layer and shallower than the third semiconductor layer, and twice the diffusion depth of the second semiconductor layer. A semiconductor device characterized by being 10 times. A second conductivity type second semiconductor layer selectively formed on the surface layer of the first main surface of the first conductivity type first semiconductor layer;
A third semiconductor layer of a first conductivity type in contact with the first semiconductor layer on the second main surface side of the first semiconductor layer and having a higher concentration than the first semiconductor layer;
A pressure-resistant structure portion formed on an outer peripheral portion of the second semiconductor layer in a surface layer of the first main surface of the first semiconductor layer;
The pressure-resistant structure portion is spaced from the outer peripheral side end of the first semiconductor layer to the inner peripheral side, and penetrates the first semiconductor layer from the first main surface of the first semiconductor layer. A trench that reaches the inside and is formed on the outer peripheral side of the second semiconductor layer;
A first insulating film formed in the trench;
A recess formed in the first insulating film;
A second insulating film formed on the first semiconductor layer between the second semiconductor layer and the first insulating film;
Covers the inner peripheral upper surface of the first insulating film in the trench, reaches the upper surface opening of the recess, bends from the upper surface opening into the recess, and extends in the depth direction inside the recess. A conductive film formed to fill the recess by terminating at the bottom;
A first main electrode formed on the second semiconductor layer and the second insulating film and in contact with the conductive film so as to have the same potential as the conductive film;
A second main electrode formed on a main surface opposite to a side in contact with the first semiconductor layer of the main surface of the third semiconductor layer;
The outer peripheral edge of the second semiconductor layer is separated from the trench,
The thickness of the first semiconductor layer is greater than 10 times the diffusion depth of the second semiconductor layer,
The depth of the conductive film reaching the bottom of the recess is deeper than the diffusion depth of the second semiconductor layer and shallower than the third semiconductor layer, and twice the diffusion depth of the second semiconductor layer. A semiconductor device characterized by being 10 times. 3. The semiconductor device according to claim 1, wherein the third semiconductor layer is a semiconductor substrate, and the first semiconductor layer is an epitaxially grown layer formed on the semiconductor substrate.   The semiconductor device according to claim 1, wherein the conductive film is metal or polysilicon. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film or the first insulating film is an oxide film, and the inside of the first semiconductor layer from the first main surface of the first semiconductor layer. A step of forming a plurality of grooves toward the surface, a step of forming an oxide film on the surface of the first semiconductor layer in contact with the groove and the entire area of the first semiconductor layer sandwiched between the grooves, and forming a recess in the oxide film And a method of manufacturing a semiconductor device, comprising forming a conductive film in the recess.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the groove is in a lattice shape, an island shape, or a stripe shape.   7. The method of manufacturing a semiconductor device according to claim 5, wherein the oxide film is formed by thermally oxidizing the first semiconductor layer.   The method for manufacturing a semiconductor device according to claim 5, wherein the conductive film is a metal or polysilicon.

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