JP2007515140A - Noise-tolerant signaling to help simplify timing recovery and data recovery - Google Patents

Abstract

Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily refected by differential receivers thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit bacchanal signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

Description

BACKGROUND Consumer demand for digital video, high-speed communications, and ever-increasing processing speeds has forced manufacturers to adopt faster data transmission schemes. Typically, the data transmitted is digital, but designers prefer analog communication schemes that employ small amplitude differential signals, especially for moving images within the system. The transmission medium, or “channel”, may be a copper wire pair, but more typically a circuit board trace pair extending between integrated circuits. The use of differential signals enables common-mode noise removal, thereby enabling data transmission with extremely good speed and common-mode noise immunity.

  The Telecommunications Industry Association (TIA) has issued a standard that defines the electrical characteristics of small amplitude differential signal (LVDS) interface circuits that can be used to exchange binary signals. LVDS employs small amplitude differential signals to provide high speed, low power data communications. For a detailed description of this LVDS standard, see “Low-Amplitude Differential Signaling (LVDS) Interface Circuits / Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits /,” incorporated herein by reference. See EIA-644 (March 1996).

  Code distortion limits the sensitivity and bandwidth of any communication system. A form of distortion, commonly referred to as “intersymbol interference” (ISI), is a problem in unbalanced termination and differential communication systems, and is evident in the temporal spread and resulting overlap in individual pulses or “codes” . Severe ISI prevents the receiver from identifying the code and ultimately destroys the integrity of the received signal. To further complicate matters, the characteristics of the high-speed signal depend largely on the destination. That is, the received signal appears to change depending on the characteristics of the communication channel and the receiver. In extreme cases, the transmitter may be far beyond the adjustment range for a particular communication channel and receiver, and the received data may not be understood at all. Therefore, the data transmitter must be tuned to achieve and maintain optimal performance.

  A receiver of a high speed communication system may include a control circuit that monitors various characteristics of the input signal and adjusts the associated transmitter accordingly. Such adjustments to the transmitter may be made once to resolve channel characteristics and process variations, or even continuously or periodically to resolve time-varying parameters such as supply voltage and temperature. Sometimes it is executed. In order to perform such adjustment, the receiver needs to return to the transmitter for communication. This process is sometimes referred to as “reverse channel” communication.

  Providing reverse channel communication can be expensive, especially in systems where the high speed communication channel being monitored and tuned is unidirectional. Since reverse channel communication occurs in the opposite direction to the data flow, it may require one or more additional signal paths and associated pins between the communication circuits. Adding pins and signal paths is expensive and undesirable. In the alternative, reverse channel signals can be supported by two-way communication, but this option may reduce the forward communication bandwidth.

  In “Phantom Mode Signaling in VLSI Systems: VLSI Systems”, Thaddeus Gabara is on the same channel as the high-speed differential signal but reverses the high-speed differential channel by injecting the same-phase signal in the reverse direction. A circuit that facilitates channel communication is described. These circuits take advantage of the capabilities of modern differential receivers to remove common-mode signals, but in practice, injecting common-mode signals into high-speed differential communication channels is a differential receiver perspective. Is the same as injecting common-mode noise. Thus, reverse channel communication schemes that rely on common-mode signaling techniques will unfortunately limit the forward channel communication rate. Accordingly, there is a need for protocols and circuits that facilitate reverse channel communication over high speed differential channels without excessively limiting the bandwidth of the differential signal.

Overview The present invention addresses the need for protocols and circuits that facilitate reverse channel communication over high speed differential channels without unduly limiting the bandwidth of the differential signal. A system according to various embodiments described herein conveys a forward high speed differential signal on a differential communication channel and a reverse relatively slow reverse channel control signal on the same channel. Issue.

  From the perspective of the forward channel differential receiver, the common-mode reverse channel signal is just noise, which typically limits speed performance. Thus, the common mode reverse channel signal is formatted according to some implementations to minimize the impact of the common mode reverse channel signal on the forward communication rate. This common mode signal formatting employs significantly lower signal amplitude, frequency and slew rate compared to the forward channel.

  A common mode signal that minimally affects the forward channel sacrifices the integrity of the common mode signal to maximize forward channel rate performance. Accordingly, common mode receivers according to various embodiments employ a noise resilient data recovery scheme to compensate for signal quality degradation in the reverse channel signal. To take advantage of these embodiments for recovering relatively weak common mode signals, various common mode communication protocols and corresponding common mode receivers are employed.

  In some embodiments, in-phase signals are transmitted without corresponding timing and reference signals. Accordingly, the receivers of those embodiments include circuitry for extracting timing and reference information from the received in-phase signal. Many of the conventional clock and data recovery (CDR) circuits are available for this purpose, but are relatively complex. Thus, a receiver according to some embodiments utilizes a data coding scheme and corresponding data recovery circuit that eliminates the need for complex high speed CDR circuits, ultimately saving area and power.

  The above summary is not intended to limit the invention, but rather the invention is defined by the appended claims.

DETAILED DESCRIPTION FIG. 1 shows a communication system 100 according to one embodiment. As in conventional systems, the system 100 includes a differential transmitter 105 that is connected to a corresponding differential receiver 107 via a differential communication channel 109. The system 100 further includes a reverse channel communication circuit and a common mode transmitter 127 that transmits the reverse channel signal to the common mode receiver 129 via the channel 109 at the timing of the clock signal TCK. The high speed differential link between transmitter 105 and receiver 107 is referred to as the “forward channel”, while the relatively slow common mode link between transmitter 127 and receiver 129 is referred to as the “reverse channel”. be called.

  Various parameters of the differential transmitter 105 must be adjusted to achieve and maintain optimum performance. Such adjustments can affect, for example, termination resistance on the chip, drive current, signal amplitude, equalization (at the transmitter), and phase offset. Furthermore, for systems that support multiple communication modes, the receiver can instruct the transmitter to transmit in a mode supported by the receiver. In order to achieve this object, the differential receiver 107 monitors various attributes of the received differential signal, and generates a transmitter control signal TXC for adjusting the transmitter 105 based on the monitoring result. The common mode transmitter 127 transmits the transmitter control signal TXC to the common mode receiver 129 as a pair of common mode signal components injected into the channel 109. (In other representations herein, TXC refers to both the signal and its corresponding node. It will be clear from the context whether a given alphanumeric representation refers to the signal or node.) The received common mode signal is converted to the original transmitter control signal TXC from the receiver 107 and the differential transmitter 105 is adjusted accordingly. Thus, the system 100 can implement and maintain transmitter setting conditions that optimize forward communication speed.

  2A and 2B show waveforms corresponding to the similarly labeled nodes of FIG. 1 and are used in conjunction with FIG. 1 to describe the operation of the communication system 100. Each vertical axis represents a voltage range for each signal shown, and each horizontal axis represents time. These waveforms are not actual scale ratios, and a differential forward channel signal is typically a signal having a higher frequency and a higher amplitude than a common mode reverse channel signal.

  The top signal pair in FIG. 2A represents the first and second differential signal components DP and DM and is transmitted from the transmitter 105 to the receiver 107 via the respective signal lines TXP and TXM of the channel 109. . The second signal pair in FIG. 2A shows the first and second common mode signal components CP and CM, which are passed from the common mode transmitter 127 to the common mode receiver 129 via the corresponding signal lines of the channel 109. Communicated. Both pairs of signal components can be transmitted simultaneously on the communication channel 109 (first and second composite signal components TXP representing the combination of differential and common mode signal components transmitted over the communication channel 109). And TXM as shown in FIG. 2A). The common mode signal components CP and CM are balanced in the illustrated AC coupling embodiment, and the characters transmitted by using the signal components CP and CM are high enough to pass through the coupling capacitor 111. It is represented by

  From the perspective of the differential receiver 107, the common-mode reverse channel signal is noise, and noise typically limits speed performance. Accordingly, the illustrated common mode transmitter 127 and receiver 129 are designed to minimize the impact of the common mode reverse channel signal on the forward communication rate based on the implementation. For exemplary purposes, it is assumed that the receiver 107 completely removes the common mode of the composite signals TXP, TXM and extracts the transmission data TXD illustrated in FIG. 2B. The means employed by the various embodiments to limit the impact of the reverse channel signal on the forward channel performance is detailed below.

  The transmitter and receiver in the illustrated embodiment are AC coupled by using a set of capacitors. That is, the channel 109 includes first and second signal lines TXP and TXM, each of which is connected to each differential output terminal of the transmitter 105 and each of the receiver 107 via one of the two capacitors 111. Coupled to the differential input circuit terminal. A coupling capacitor may be included on the transmit side of the forward channel instead of or in addition to capacitor 111. The transmitter and receiver are DC coupled in other embodiments, in which case the capacitor 111 is omitted.

  The differential transmitter 105 conventionally includes a forward channel transmitter circuit 119 that is differentially coupled to the input terminal of the output amplifier 121. Receiver 107 conventionally includes a differential receive amplifier 123 that converts the differential signal on channel 109 into a digital data signal TXD that is transmitted to forward channel receiver 125. The receiver 125 transmits received data to a predetermined destination (not shown), and further transmits a transmission control signal TXC for controlling the transmitter 105 according to the necessity of optimizing the received forward channel signal. Create

  The common mode transmitter 127 encodes the transmission control signal TXC into an appropriate code format and transmits a reverse control channel transmission circuit 131 that transmits the formatted control signal as the same common mode signal component pair CM and CP. Including. Since a circuit that only reproduces the input signal will be apparent to those skilled in the art, a detailed description of the transmitter 131 is omitted for the sake of brevity. The matched buffer 133 transmits the signal components CM and CP to the first and second signal lines TXM and TXP of the communication channel 109, respectively. The receiver 129 coupled to the conductors TXM and TXP via the first and second common mode input terminals extracts the signal components CM and CP to recover the transmission control signal TXC.

  The differential amplifier, including the receiving amplifier 123, is characterized in part by its ability to remove common mode signals. This measure of capability is commonly referred to as “common mode rejection ratio” or CMRR. More specifically, the CMRR for a given amplifier is the ratio of the common-mode interference voltage at the amplifier input to the corresponding interference voltage at the output. A typical high speed differential amplifier of the type described herein boasts a CMRR in the range of, for example, 100: 1 to 100: 5. Although these ratios are impressive, any ratio less than complete common-mode rejection allows common-mode noise to interfere with the received differential signal, ultimately limiting speed performance.

  The buffer 133 has a general buffer configuration, but the size adjustment is performed so that the signal components CM and CP are easily removed by the differential receiving amplifier 123. First, the buffer 133 is closely matched to produce practically identical signal components for a given manufacturing process. Since the receiving amplifier 123 amplifies any difference between the two signal components, this matching is important in preventing undesired common-mode to differential signal conversion. Second, the amplitude of the signal component injected into channel 109 is limited to minimize the absolute value of all differences between the two signal components. In embodiments where the transmitter 105 transmits a differential signal having a magnitude of about 1V (eg, two complementary 0.5V signals), each common mode signal component has an amplitude of about 50 millivolts, ie a differential signal. Having a size of about 10%. Third, amplifier 133 provides a very low slew rate compared to amplifier 121, and common mode signal components CM and CP are transmitted at a much lower frequency than forward channel data, both of which are common mode signals. Facilitate removal. For example, in one embodiment, the slew rate of the common mode signal component is sufficiently slow so that its rise or fall time extends across multiple symbols in the fast forward channel. Making the buffer 133 smaller and slower minimizes the capacitive load provided by the buffer 133 and ultimately affects the signal integrity of the buffer 133 and thus the data rate of the forward differential signal. There is an additional advantage with minimizing.

  Fortunately, reverse channel communication typically requires much lower bandwidth than forward channel communication and can thus be realized at relatively low frequencies, slew rates, and voltages. Some implementations sacrifice the common mode signal integrity to maximize forward channel rate performance. To take advantage of these embodiments for recovering relatively weak common mode signals, various common mode communication protocols and corresponding common mode receivers are employed.

  The common mode receiver 129 includes a common mode extraction circuit 135, i.e., a simple averaging circuit that averages the composite signal components TXP and TXM from the channel 109 to generate a common mode signal CMS in this embodiment. The common-mode signal components CP and CM are transmitted without corresponding reference signals, so the receiver 129 of this embodiment includes a reference circuit 140 that extracts the appropriate reference signal from the signal CMS. In this embodiment, the reference circuit 140 is a low pass filter and the reference signal CR is the average level of the signal CMS. The comparator 142 compares the common mode sum signal CMS with the derived reference signal CR to generate a recovered common mode signal RCMS. This embodiment is illustrated in FIG. 2B. The recovered common mode signal RCMS is then passed to the reverse channel receiver 144, which recovers timing and data from the recovered common mode signal RCMS and sends the corresponding recovered transmission control signal TXC to the transmitter 105. To supply.

  The differential transmitter 105 is AC coupled to the receiver 107 and thus sets a low frequency limit for the reverse channel communication frequency. Since we want to minimize noise in the forward channel, we set an upper limit on the amplitude and frequency used to represent the code transmitted through the signal components CP and CM. Some embodiments provide a reverse channel that provides a noise immunity means that allows the use of a very small amplitude reverse channel signal in addition to passing a common mode signal of sufficient frequency to pass through the capacitor 111. Adopt signal protocol.

  FIG. 3 is a waveform schematic 300 illustrating three DC balance signals used to convey common mode data, according to one embodiment. The scheme of FIG. 3 uses a logic “0” character (0) as a signal having a 50% duty cycle and a first frequency, and a “null” character (no data, ie “null”) as a 50% duty cycle and a first frequency. Let the signal have a second frequency that is half the frequency of and the logic “1” character (1) is represented as a signal having a 50% duty cycle and half the frequency of the second frequency. The waveforms representing the three character types (0, null, 1) are orthogonal, thereby minimizing the possibility of misinterpretation. The illustrated coding scheme is in the form of frequency displacement modulation (FSK) (a scheme commonly employed for transmitting digital signals over analog channels). For a simple FSK tutorial, see "Digital Transmitter: Introduction to Frequency Shift Keying, 2002" (Version 2.2) by Matthew Berry. I want to be. Other embodiments may use other coding schemes such as phase shift keying and may use more or fewer characters.

  FIG. 4 is a waveform diagram 400 illustrating an exemplary common mode signal CMS and the recovered common mode signal RCMS representing the “0-null-1” data pattern by using the character of FIG. Used in conjunction with FIGS. 5A and 5B below, illustrate the operation of a reverse channel receiver based on an embodiment that relies on FSK to convey reverse channel signals.

  FIG. 5A is a block diagram of a receiver 500 that is used in one embodiment as reverse channel receiver 144 of FIG. Receiver 500 includes a slicer 510 that oversamples the recovered common mode signal RCMS at a sample frequency Fs that is greater than the maximum frequency used to represent the characters transmitted as signal components CP and CM. Since the data transfer rate of the recovered common mode signal is typically much lower than other data transfer rates supported by the integrated circuit in which the receiver 129 is implemented, oversampling does not require complex high speed circuits. This embodiment eliminates the need for complex clock and data recovery circuits, thus saving area and power. Various versions of slicer 510 are well known to those skilled in the art. Some forms are described, for example, in US Pat. No. 5,412,692.

  A first-in first-out (FIFO) window circuit 515 captures the oversampling signal OSS from the slicer 510 and periodically compares the signal OSS portion with each of the three data correlators 520, 525, 530. The data correlator 520 generates an output signal indicating reception of the “0” character when the correlation between the contents of the window circuit 515 and the “0” pattern has a predetermined degree of accuracy (eg,> 70%). Correlators 525 and 530 similarly output signals indicating “null” and logic “1” characters based on the contents of window circuit 515, respectively.

  Returning to FIG. 4, the operation of the window circuit 515 and the three correlators 520, 525, 530 is simulated by four curly brace sequences below which indicate the relative probabilities of the corresponding pulse sequences. In the leftmost example, the pulse sequence reflects 100 percent of the “0” character, presenting a zero percent chance of “null” or logic “1”. In this case, the zero correlator 520 generates an output indicating logic “0” to the character accumulator 535. The second example from the left of FIG. 4 shows a time window where none of the probabilities exceed the required 70%, so neither correlator represents a letter. The last two emphasized pulse sequences indicate that the reception probability of “null” characters and logic “1” characters is 100%, respectively.

  Character accumulator 535 is optional but can be included to filter out some errors. The accumulator 535 can be configured to remove character strings that do not match a certain predetermined communication protocol. For example, accumulator 535 may discard character sets that contain too many or too few characters, or otherwise contain unacceptable data patterns. The character set 540 that passes the requirements of the accumulator 535 is passed as the transmitter control signal TXC.

  FIG. 5B shows a receiver 550 used as the reverse channel receiver 144 of FIG. 1 in another embodiment. N-bit window circuit 552 (in this embodiment, a FIFO buffer) receives each input bit OSS of the input signal (ie, oversampling signal OSS from slicer 510 of FIG. 5A). According to the clock signal Fs, the window circuit 552 periodically supplies N consecutive data samples to the corresponding input terminals of the data correlation circuit 553, and the data correlation circuit 553 decodes the windowed data into the character string CHAR. . The correlation circuit 553 includes a “1” correlator 555, a “null” correlator 557, and a “0” correlator 559. The “1” correlator 555 will be described and illustrated in some detail, but the remaining correlators are similar and will not be described in detail for simplicity.

  The “1” correlator 555 includes a pattern matching register 560, a mask register 562, and an adding circuit 564. The data loaded into the pattern matching register 560 is adjusted to detect a pattern associated with a logical “1” character (eg, waveform “1” in FIG. 3). Input data in the window circuit 552 is compared bit by bit with the corresponding bit in the pattern matching register 560. Register 560 includes a logic circuit (not shown) that generates a digital signal “1” for mask register 562 for each bit in register 560 that matches a corresponding data bit in register 552. The mask register 562 communicates these bits to the adder circuit 564, but the selected bits in the mask register 562 can be set to prevent them from entering the adder circuit 564. Next, the addition circuit 564 adds “1” from the mask register 562 and provides the resulting correlation result CR_1 to the character interpreter 565. The pattern stored in the pattern matching register 560 is adjusted to detect a logical “1” data character, so the magnitude of the correlation result CR — 1 indicates that the data pattern in the window circuit 552 represents a logical “1”. Represents the probability. The greater the number represented by correlation result CR_1, the greater the probability that the contents of register 552 represent logic “1”. By including registers 560 and 562, the collation pattern and mask can be changed. In other embodiments, the matching pattern or mask, or both, are incorporated into hardware.

  “Null” correlator 557 is similar to “1” correlator 555, but the matching pattern is modified to detect “null” characters (eg, the “null” waveform of FIG. 3). Therefore, the magnitude of the correlation result CR_N represents the likelihood that the data pattern in the window circuit 552 represents a “null” character. Similarly, the zero correlator 559 is similar to the “1” correlator 555, but the matching pattern is modified to detect “0” characters (eg, the “0” waveform of FIG. 3). Therefore, the magnitude of the correlation result CR_0 represents the probability that the data pattern in the window circuit 552 represents the “0” character.

  The character interpreter 565 considers the values of the respective correlation results CR_1, CR_N, CR_0 that identify the receipt of data characters of the type discussed above in connection with FIG. Interpreter 565 detects a character when the corresponding correlation result exceeds a threshold. Interpreter 565 stops for N clock cycles of clock Fs each time a character is detected and the previously considered data sample window circuit 552 is flushed. In one embodiment, as soon as a “null” character is detected following the “1” character, interpreter 565 issues a voltage representing a logical “1” and a “null” character is detected following the “0” character. As soon as this occurs, a voltage representing a logic “0” is issued. Therefore, the character signal CHAR is a digital signal that goes back and forth between “1” and “0”. In other embodiments, interpreter 565 represents an additional group of characters (eg, “null”) and uses various character representations, or both. The data captured in window circuit 552 is typically equal to or greater than the character length.

  The accuracy with which the interpreter 565 identifies characters can be improved by extending the number N of bits captured by the window circuit 552 and considered by the correlators 555, 557, 559. The improvement in character recognition does not increase linearly with the number of bits, so incremental improvement in noise margin requires the receiver 550 to be unbalanced in size. The receiver 550 addresses this problem with a second stage correlation circuit 566. The correlation circuit 566 filters the output CHAR of the character interpreter 565 to further improve the probability of accurate signal interpretation without adding significant circuit complexity.

  In order to utilize the second stage correlation circuit of receiver 550, the transmitter formats the transmitted data using a specific character pattern representing the data code. In a simple example, the transmitter may have a logic “0” as 10 “0” strings, “null” as alternating “1” and “0” characters, and a logic “1” as 10 It may be conveyed as a “1” character string (in this example, each transmitted “1” or “0” character is surrounded by a “null” character). Next, the character pattern CHAR is subjected to the second level correlation in order to further improve the accuracy of the interpretation given by the correlation circuit 553.

  Correlation circuit 566 includes a window circuit 575, a correlator 580, and a second interpreter 582. Window circuit 575 (in this embodiment, a 10-bit FIFO register clocked at character rate Fs2) provides correlator 580 with 10 consecutive character values. In this embodiment, correlator 580 is a simple adder circuit that counts the number sampled as logic “1” and supplies the sum to interpreter 582. Next, if the sum from the correlator 580 is 8 or more, the probability generator 585 in the interpreter 582 issues a signal PRX1 indicating receipt of a logic “1”, and the sum is 3 or less. If there is, a signal PRX0 indicating the estimated reception of logic “0” is issued. Similarly, state machine 590 in interpreter 582 issues a logic “1” and logic “0” data code on line TXC in response to signals PRX0 and PRX1. (An embodiment of state machine 590 is described in detail below as a combination of state machine 635 and counter 636 of FIG. 6, the function of which is described in connection with FIG. 10).

  Receiver 550 can be adjusted to achieve a desired balance between noise margin, code rate, and circuit complexity. For improved noise immunity, for example, the sampling frequency can be increased, either or both of the window circuits 552 and 575 can be expanded to store more data samples or characters, and the correlator can vary in various patterns. And the character interpreters 565 and 582 can be adjusted to require an increase in probability before indicating receipt of a character or code. Receiver 550 can also be extended to recognize additional received characters to include one or more additional correlation levels. Such improvements may be performed in hardware, or configurable resources such as registers may be provided to facilitate system adjustment.

  FIG. 6 illustrates a portion of a communication system 600 according to another implementation. System 600 is similar in many respects to system 100 of FIG. 1, with elements identified by the same reference numbers being the same or similar. System 600 includes a differential receiver circuit and a common mode transmitter circuit similar to those described in connection with FIG. 1, but are omitted here for simplicity.

  System 600 includes a multi-channel transmitter 605 that incorporates multiple differential transmitters 105, each having a corresponding common-mode reverse channel receiver 615. In one embodiment, the common mode receiver 615 controls all the differential transmitters 105 simultaneously, but the following example assumes that the receiver 615 controls each transmitter 105 in turn. In some implementations, the receiver 615 has an input that receives the common mode signal component from each channel 109, but the following description is limited to the control of the bottom channel.

  Receiver 615 includes decoder 620 and reverse channel receiver 625. Decoder 620 extracts the common-mode reverse channel signal from composite signal components TXP and TXM, and then decodes the extracted common-mode signal to generate common-mode data CMD. The reverse channel receiver 625 translates the received common mode data into transmitter control signals TXC for controlling the various transmitters 105. In some implementations, receiver 615 communicates the same control signal to all transmitters 105, and in other implementations, the reverse channel control signal independently controls each forward channel.

  In the illustrated implementation, decoder 620 includes a data interpreter 630, a state machine 635, and a counter 636. The data interpreter 630 interprets the received common-mode signal and upon receipt of a signal pattern possibly representing a logic “1”, issues an “estimated 1” signal PRX1, or upon receipt of a signal pattern possibly representing a logic “0”, Issue an "estimated 0" signal PRX0. The state machine 635 interprets these signals in light of the timing information provided by the counter 636 and generates common mode data CMD. The reverse channel receiver 625 interprets the data CMD and issues an appropriate transmitter control signal TXC.

  FIG. 7 illustrates “1-null-” expressed in the ternary code scheme employed by the embodiment of the system 600 of FIG. 6 that communicates common mode data to the receiver 615 via one or more channels 109. It is a waveform diagram 700 showing a “0” data pattern. The logic “1” and logic “0” characters are represented as a combination of signal edges according to this embodiment (a protocol that allows the receiver 615 to extract both timing and data from the recovered common mode signal).

  FIG. 8 shows details of an implementation of the data interpreter 630 of FIG. 6, which includes a common mode recovery circuit 800, a window circuit 805, a correlator 810, and a data probability generator 815. The recovery circuit 800 extracts common-mode data and timing information from the pair of composite signal components TXP and TXM, and generates a digital recovery common-mode signal RCMS. Window circuit 805 (in this embodiment, a 10-bit FIFO register) supplies the values of 10 consecutive RCMS data samples to correlator 810. In this embodiment, correlator 810 is a simple summing circuit that counts the number sampled as logic “1” and supplies the sum result to probability generator 815. Next, the probability generator 815 issues a signal PRX1 when the estimated reception of logic “1” is received, and issues the signal PRX0 when the estimated reception of logic “0” is received. In one implementation, for example, probability generator 815 issues signal PRX1 when window circuit 805 samples more than eight logic “1” s, and window circuit 805 has two in a given 10-sample window. When the following logic “1” is sampled, a signal PRX0 is issued.

  The data interpreter 630 can be modified to achieve a desired balance between character recognition capability and circuit complexity. For improved character recognition capability, for example, the sampling frequency can be increased, the window circuit 805 can be expanded to store more sampled RCMS bits, and the correlator 810 can be The pattern and mask can be adapted to apply to the sample values, and the probability generator 815 can be adjusted to require an increase in probability before indicating receipt of a character. Correlator 810 can also be extended to include one or more additional correlation levels as described above in connection with FIG. 5B. These modifications can be built into the hardware, or configurable resources such as registers can be provided to facilitate system tuning. The rate at which the transmitter transmits data can be reduced to further improve character recognition capabilities.

  The recovery circuit 800 is connected between the output of the slicer 825 and the input of the comparator 820, the common mode extraction circuit 819, the comparator 820, the oversampling circuit (slicer) 825 that operates in the sampling period Ts of the reception clock RCK. Integrator 830. FIG. 9 is a waveform diagram 900 illustrating the function of the recovery circuit 800.

  A common-mode extraction circuit 819 (in this embodiment, an averaging circuit) averages the signal components TXP and TXM to generate a non-reference common-mode signal CMS. In the embodiment of FIG. 9, the exemplary common mode signal CMS represents a “0-0-0-1” character sequence, leading from a “null” signal, from left to right. Comparator 820 compares signal CMS with reference signal IR derived from the output of slicer 825 integrated by integrator 830. Slicer 825 oversamples the signal from comparator 820 to generate a recovered common mode signal RCMS that is synchronized with the receiver.

  The recovery signal RCMS represents logic “1” and “0” samples as relatively high and low voltage levels, respectively. The recovery signal RCMS is expected to go back and forth between “1” and “0” in response to a “null” signal. Accordingly, the window circuit 805 will store approximately the same number of “1” s as “0”. However, upon receipt of the “0” character, slicer 825 retains a value representing a logical “0” over a series of clock cycles, thereby causing window circuit 805 to communicate a “0”, typically to correlator 810. . This condition is illustrated in FIG. 9 as reception of the leftmost “0” character. If the window circuit contains no more than two logic “1” s and the correlator 810 communicates this small number of “1” s to the probability generator 815, the probability generator 815 will detect the shortage of “1” as a logic “0”. "Is interpreted as an estimated receipt of the character, and as a result, the" estimated 0 "signal PRX0 is asserted. A logical “1” character is interpreted in a similar manner, except that slicer 825 holds a value representing logical “1” over a series of clock cycles, which causes correlator 810 to generate a relatively high number. To the device 815. The probability generator 815 interprets this relatively abundant “1” (eg, 8 or more) as an estimated receipt of a logical “1” character, and eventually asserts an “estimated 1” signal PRX1.

  FIG. 10 includes two state diagrams: a state diagram 1000 illustrating the operation of state machine 635 of FIG. 6 and a state diagram 1010 illustrating the operation of counter 636 of FIG. This example assumes a communication protocol in which data is given within a 4-bit window, and data with more or less than 4 bits is considered erroneous and is consequently ignored. For simplicity, a 4-bit embodiment was chosen, but actual systems can support windows with more or fewer bits. Both state diagrams 1000 and 1010 are timed in one embodiment by using the receive clock RCK.

  As shown in state diagram 1010, counter 636 starts at state 000 and counts the period of the received clock. When the count value reaches the maximum number Max, the counter 636 transitions to state 001 and asserts a saturation signal (Sat = 1). The communication protocol defines a number Max as the number of receiver clock cycles in which subsequent data characters must be received. The state machine uses the output Sat from counter 636 to reject received characters that are more widely spaced than the protocol allows.

  Referring now to the state diagram 1000 and the behavior of the state machine 635, the state machine 635 transitions to the starting state 000 upon receipt of a system reset or as soon as the saturation signal Sat from the counter 636 is asserted. Next, the state machine 635 asserts the counter reset signal Rst to the “0” counter 636. The reset signal Rst may also be used to preset the window circuit 805 to store data indicative of a “null” signal (eg, alternately “1” and “0”). The state machine 635 then moves to the idle state 001, asserts the reset signal Rst so that the counter 636 can increment, and monitors the "estimated 1" and "estimated 0" outputs from the data interpreter 630, PRX and PRO. To do. In the absence of received data characters or noise interpreted as data characters, the state machine 635 goes back and forth between states 000 and 001 each time the counter 636 asserts the saturation signal Sat, as represented by the state machine 1010. Or move.

  Referring to the embodiment of FIG. 9 where the first received data character represents logic “0” when read from left to right, interpreter 630 asserts signal PRX0 and causes state machine 635 to transition from state 001 to state 010. . Next, state machine 635 queues logic “0”, resets counter 636, and transitions to state 011. This example assumes a 4 bit window and only one data sample was received at this point. This window is not full, so state machine 635 transitions to state 100 for an R clock period before returning to idle state 001. The number R of skipped clock periods is selected so that state machine 635 ignores subsequent assertions of signal PRX1 due to the received signal returning to the “null” state. Referring to FIG. 9, for example, the leftmost pulse of signal PRX1 is not due to receipt of a logic “1” data character, but rather is an artifact of signal CMS returning from a logic “0” state to a “null” state. After detecting the assertion of logic “0”, the state machine 635 remains in the state 100 until a subsequent artifact passes. The number R is known in advance for a given system and the state machine 635 is set accordingly.

  In idle state 001, state machine 635 again waits for the assertion of either signal PRX1 or PRO indicating receipt of the second character. If no signal is asserted before the counter 636 asserts the saturation signal Sat (Sat = 1), the state machine 635 returns to state 000 and begins anew. As soon as signal PRO is asserted, state machine 635 repeats the process described above. When signal PRX1 is asserted in response to a recognized logic “1” character, state machine 635 behaves the same, but transitions to state 011 through state 111 instead of through state 010.

  Once state machine 635 receives four consecutive data characters that are close enough to avoid a reset from counter 636, state 011 transitions to state 101 and is queued as common mode data CMD. The number of bits is issued to the reverse channel receiver, and again returns to state 001 via state 000 and waits for the next character. As discussed above in connection with FIG. 6, reverse channel receiver 625 interprets common mode data CMD and issues an appropriate transmission control signal TXC.

  Similar to the system 100 of FIG. 1, the communication system 600 of FIG. 6 employs a very noise-resistant reverse channel communication scheme to support small amplitude common mode signals that are easily distinguished from high-speed differential signals. Thus, these communication schemes enable very high forward channel data transfer rates. It is also important to note that the reverse channel signal used to optimize the transmitter characteristics is very poorly adjusted for the forward channel transmitter and the received forward channel data is not recognizable. Even if you communicate effectively. This insensitivity to differential channel signal quality is a significant improvement over reverse channel communication systems employing high speed differential signals. A system based on the above-described embodiments provides these advantages without adding pins or communication channels and is compatible with AC and DC coupled communication channels. Importantly, the decoder 620 issues the instruction CMD at the same average rate that the instruction CMD is generated by the transmitter, but the timing of the instruction CMD is defined by the reception clock RCK and this reception The clock RCK is not synchronized with the transmission clock TCK (FIG. 1) used for timing the reverse channel data. As a result, the system 600 need not recover the transmit clock TCK from the arriving reverse channel data (characterized by eliminating the need for a complex and area intensive clock recovery circuit). The receive and transmit clocks RCK, TCK are mesochronous in some embodiments.

  FIG. 11 illustrates a simple common mode extraction circuit 1100 according to one embodiment. Extraction circuit 1100 (two series connected resistor sets) is the averaging circuit of FIG. 1 in one embodiment.

  FIG. 12 shows a signal transmission system 1200 that includes a differential transmitter 105, a communication channel 109, and a common mode receiver 1205. System 1200 is similar in many respects to system 100 of FIG. 1, with elements identified by the same reference numbers being the same or similar. In contrast to the common-mode receiver 129 of FIG. 1, the receiver 1205 extracts the common-mode signal from only the signal component TXP, TXM, in the example shown, from the component TXM.

  The embodiment of FIG. 12 assumes that the reverse channel communication frequency is lower than the forward channel frequency. The common-mode extraction circuit 1210 (in this case, a low-pass filter) removes the high-frequency forward channel component of the signal TXM in order to recover the common-mode signal component CM. A second low-pass filter 1215 having a cutoff frequency lower than that of the extraction circuit 1210 derives a reference signal CR. The remaining part of the receiver 1205 functions similarly to the receiver 129 of FIG.

  Unless otherwise stated, terminals, lines, conductors, and traces that carry a given signal fall within the generic term “node”. In general, the choice of a given description “circuit node” is a matter of style and is not limiting. Similarly, the term “connected” is not limiting unless otherwise specified. Further, some parts are shown connected directly to each other, while others are shown connected via intermediate parts. In each embodiment, some desired telecommunications is established between two or more nodes by way of interconnection, or “coupling”. Such coupling can often be achieved by using multiple circuit configurations as will be appreciated by those skilled in the art.

  Although the invention has been described with reference to particular embodiments, variations of those embodiments will be apparent to those skilled in the art. For example, the usefulness of the communication scheme described above is not limited to reverse channel communication, and data can be transmitted in either or both directions along a differential channel. Accordingly, the spirit and scope of the appended claims should not be limited to the above description. In particular, only the claims reciting “means” or “process” should be construed as required in 35 USC 112, sixth paragraph.

Brief Description of Drawings
1 illustrates a communication system 100 according to one embodiment. 2A and 2B show waveforms corresponding to the similarly labeled nodes of FIG. FIG. 3B is a waveform schematic 300 illustrating three DC balance signals used to convey common mode data, according to one implementation. FIG. 4B is a waveform diagram 400 illustrating an exemplary common mode signal CMS and a corresponding recovered common mode signal RCMS. FIG. 5A is a block diagram of a receiver 500 used in one embodiment of the reverse channel receiver 144 of FIG. 1, and FIG. 5B is a reverse channel receiver 144 of FIG. 1 according to another embodiment. A receiver 550 is shown as used. 2 illustrates a portion of a communication system 600 according to another implementation. 7 is a waveform diagram 700 illustrating a “1-null-0” data pattern represented in a ternary code scheme employed by the system 600 of FIG. An embodiment of the data interpreter 630 of FIG. 6 will be described in detail. 6 is a waveform diagram 900 illustrating the function of the recovery circuit 800. FIG. A pair of state diagrams 1000, 1010 illustrating the operation of the state machine 635 and counter 636 of FIG. 1 illustrates a simple common mode extraction circuit 1100 according to one embodiment. A signal transmission system 1200 is shown that includes a differential transmitter 105, a communication channel 109, and a common mode receiver 1205.

Claims (62)

a) a differential transmitter having first and second differential output terminals for transmitting differential signals;
b) i. A common-mode extraction circuit having an extraction circuit input terminal and an extraction circuit output terminal, wherein the extraction circuit input terminal is coupled to the first differential output terminal, and the extraction circuit is connected to the first and second differences. A common mode extraction circuit for extracting a common mode signal from at least one of the dynamic output terminals;
ii. A reference circuit having a reference circuit input terminal coupled to the extraction circuit output terminal and a reference circuit output terminal, wherein a common mode reference signal is derived from the common mode signal, and the common mode reference signal is derived from the reference circuit. A common mode receiver having a reference circuit provided to the output terminal;
Integrated circuit including.   The integrated circuit of claim 1, wherein the extraction circuit includes a second extraction circuit input terminal coupled to a second signal line.   The integrated circuit of claim 2, wherein the extraction circuit includes a voltage divider across the first and second signal lines.   The integrated circuit of claim 1, wherein the extraction circuit includes a filter having a corner frequency.   The integrated circuit of claim 4, wherein the filter is a low pass filter.   5. The integrated circuit of claim 4, wherein the reference circuit includes a second filter having a second corner frequency that is lower than the first mentioned corner frequency.   The integrated circuit of claim 4, wherein the second filter is a low-pass filter.   The common mode receiver further includes a comparator having a first comparator input terminal coupled to the output terminal of the extraction circuit and a second comparator input terminal coupled to the reference circuit output terminal. The integrated circuit according to claim 1.   The common mode signal represents a first logical character by using a first data pattern having a first period, and a second logical character by using a second data pattern having a second period. The integrated circuit of claim 1 that represents   The integrated circuit of claim 1, wherein the common-mode receiver issues a transmitter control signal to the differential transmitter.   11. The integrated circuit of claim 10, wherein the common-mode receiver includes a slicer that receives the common-mode signal and a reception clock and samples the common-mode signal by the reception clock to generate sampled common-mode data. circuit.   The integrated circuit of claim 1, wherein the differential transmitter is one of a plurality of transmitters, each transmitter having first and second differential output terminals.   The integrated circuit of claim 12, wherein the common-mode receiver is coupled to the differential output terminal of each of the plurality of transmitters. a) a differential transmitter having first and second differential output terminals for transmitting differential signals;
b) i. A first common mode input terminal coupled to the first differential output terminal and receiving a first common mode signal component;
ii. A second common mode input terminal coupled to the second differential output terminal and receiving a second common mode signal component;
iii. A data interpreter having a first interpreter input terminal coupled to the first common-mode input terminal, a second interpreter input terminal coupled to the second common-mode input terminal, and an interpreter output port; A common mode signal decoder comprising:
iv. When the first and second common-mode signal components together represent a data character that represents a probability of 50% to 100% representing a logic “1”, the data interpreter outputs “estimated logic” to the interpreter output port. -1 "data interpretation, and a common-mode signal decoder;
Integrated circuit including.   The integrated circuit of claim 14, wherein the data interpreter generates probability data representing the probability.   The integrated circuit of claim 14, wherein the data interpreter includes an oversampling circuit that receives the common mode signal component and a sample clock signal.   And a state machine having a state machine input port coupled to the interpreter output port, the state machine including at least one of the "estimation-logic-1" data interpretation and the "estimation-logic-0" data interpretation. 15. The integrated circuit of claim 14, wherein the integrated circuit issues common mode data in response to a series of data interpretations including one.   The first and second common mode signal components represent a first logical character by using a first data pattern having a first period, and use a second data pattern having a second period. The integrated circuit of claim 14, thereby representing a second logical character.   The integrated circuit of claim 18, wherein the first and second data patterns have a duty cycle of about 50%.   15. The reverse channel receiver of claim 14, wherein the common mode receiver includes a reverse channel receiver coupled to the common mode decoder and receiving a common mode signal derived from the first and second common mode signal components. Integrated circuit.   The integrated circuit of claim 14, wherein the differential transmitter is one of a plurality of transmitters, each transmitter having first and second differential output terminals.   The integrated circuit of claim 21, wherein the common-mode receiver is coupled to the differential output terminal of each of the plurality of transmitters. A method for controlling a differential signal transmitted from a differential transmitter to a differential receiver via first and second differential conductors,
a) generating a transmitter control signal in the differential receiver;
b) converting the transmitter control signal into first and second common mode signal components, each signal component representing the transmitter control signal as a character sequence, each character representing a logical value and approximately A process having a 50% duty cycle;
c) inserting the first common mode signal component into the first conductor and the second common mode signal component into the second conductor, whereby the first and second common mode signal components; Transmitting to the differential transmitter;
d) combining the first and second common mode signal components at the transmitter to generate a common mode signal representative of the transmitter control signal;
e) filtering the common mode signal to obtain a reference signal;
f) comparing the reference signal with the common mode signal to obtain a recovered common mode signal;
g) changing the characteristics of the differential signal in response to the recovered common mode signal;
Including methods.   24. The method of claim 23, wherein filtering the common mode signal comprises passing the common mode signal through a low pass filter.   24. The method of claim 23, wherein filtering the common mode signal comprises oversampling the common mode signal.   26. The method of claim 25, wherein filtering the common mode signal further comprises integrating the oversampled common mode signal.   The step of filtering the common-mode signal includes recovering a second character sequence from the common-mode signal, and for one of the second character sequences, the one of the second character sequences is logical. 24. The method of claim 23, further comprising calculating a probability representing "1" or logic "0". a) a common mode signal encoder having first and second encoder output nodes for transmitting first and second common mode signal components, respectively;
b) a first signal line coupled to the first encoder output node and conducting the first common-mode signal component;
c) a second signal line coupled to the second encoder output node and conducting the second common-mode signal component;
d) i. An extraction circuit input node coupled to the first signal line for receiving the first common-mode signal component; and a common-mode signal extracted from at least one of the first and second common-mode signal components. An extraction circuit having an extraction circuit output node to provide;
ii. A filter having a filter input node and a filter output node coupled to the extraction circuit output node;
iii. A common mode signal decoder having a data sampling circuit having a first sampling circuit input terminal coupled to the extraction circuit node and a second sampling circuit input terminal coupled to the filter output node;
Including system.   30. The system of claim 28, wherein the extraction circuit further comprises a second extraction circuit input node connected to the second signal line and receiving half of the second common mode signal.   30. The system of claim 28, wherein the first and second common mode signal components are DC balanced signals.   30. The system of claim 28, wherein the first and second signal lines are capacitively coupled to the first and second input nodes.   30. The system of claim 28, further comprising a differential transmitter having first and second differential output nodes connected to the first and second input nodes, respectively. a) a differential transmitter having first and second differential output terminals for transmitting differential signals;
b) i. A first signal line coupled to the first differential output terminal;
ii. A differential communication channel having a second signal line coupled to the second differential output terminal;
c) a differential receiver having a first differential input terminal coupled to the first signal line and a second differential input terminal coupled to the second signal line, wherein the difference A differential receiver for receiving the differential signal from the differential transmitter via a dynamic communication channel;
d) a common mode transmitter having a first common mode output terminal coupled to the first signal line and a second common mode output terminal coupled to the second signal line, wherein A transmitter for transmitting a first common-mode signal component to one signal line and a second common-mode signal component to the second signal line;
e) i. A first common-mode input terminal coupled to the first signal line and receiving the first common-mode signal component;
ii. A second common-mode input terminal coupled to the second signal line and receiving the second common-mode signal component;
iii. Means for removing the differential signal to generate a common mode signal;
iv. Means for deriving a common mode reference from the common mode signal, and a common mode receiver comprising:
A communication system including:   34. The communication system of claim 33, wherein the means for deriving a common mode reference includes a low pass filter.   34. A communication system according to claim 33, wherein the means for deriving a common mode reference comprises an integrator. a) a first window circuit adapted to periodically output a window of N data samples;
b) Compare each of the N windows of the data samples with a first pattern and output a data character for each of the windows of the N data samples that matches the first pattern. A first correlation circuit adapted to
c) a second window circuit adapted to receive the data character from the first correlation circuit and to periodically output M windows of the data character;
d) comparing each of the M windows of the data characters with the second pattern and outputting a data code for each of the M windows of the data characters matching the second pattern. A second correlation circuit adapted to
Including receiver.   40. The receiver of claim 36, further comprising a slicer adapted to oversample an input data stream to generate the data samples.   The first correlation circuit includes a data correlator, and the data correlator periodically compares a set of N data samples with a first pattern to generate a first correlation result series. The receiver according to claim 36.   The first correlation circuit includes a second data correlator, and the second data correlator periodically compares a set of data samples with a second pattern to generate a second correlation result series. 40. The receiver of claim 38.   The first correlation circuit includes a third data correlator, and the third data correlator periodically generates a third correlation result series by comparing a set of data samples with a third pattern. 40. The receiver of claim 39.   41. The receiver of claim 40, wherein the first pattern is a logic “1” data pattern and the second pattern is a logic “0” data pattern.   37. The receiver of claim 36, wherein the first correlation circuit includes a character interpreter that receives the first correlation result sequence, the character interpreter generating the data character.   37. The receiver of claim 36, wherein at least one of the first and second window circuits is a FIFO buffer.   37. The first window circuit receives a first clock having a first frequency, and the second window circuit receives a second clock having a second frequency lower than the first clock frequency. As described in the receiver. A method for recovering data encoded as a data stream, comprising:
a) oversampling the data stream to generate a data sample sequence;
b) periodically correlating a subset of the data sample series with a character pattern indicating a character value;
c) generating a character for each subset of the data sample sequence correlated with the character pattern to generate a data character sequence;
d) periodically correlating a subset of the data character sequence with a code pattern indicating a code value;
e) generating a code for each subset of the data character sequence correlated with the code pattern to generate a data code sequence;
Including methods.   46. The method of claim 45, wherein the subsets of the data sample series overlap.   Each subset of the data sample series includes N data samples, a first series of the data sample series includes 0 to N−1 data samples, and a second series of the data sample series includes 1 to N 48. The method of claim 46, comprising a data sample.   46. The method of claim 45, further comprising correlating the subset of the data sample series with a second character pattern indicative of a second character value.   49. The method of claim 48, wherein either the first character value or the second character value represents a logical "1".   46. The method of claim 45, further comprising correlating the subset of the data sample series with a third character pattern indicative of a third character value.   51. The method of claim 50, wherein the third character value represents a “null” value.   46. The method of claim 45, further comprising correlating the subset of data character sequences with a second code pattern indicative of a second code value.   53. The method of claim 52, wherein either the first code value or the second code value represents a logical "1".   46. The method of claim 45, wherein the subset of the data sample sequence includes N data samples, and the subset of the data character sequence includes M data characters, where M is less than N. A receiver for recovering data encoded as a data stream,
a) oversampling means for sampling the data stream to generate a data sample sequence;
b) means for periodically correlating a subset of the data sample series with a character pattern indicating a character value;
c) means for generating a character for each subset of the data sample sequence correlated with the character pattern to generate a data character sequence;
d) means for periodically correlating a subset of the data character sequence with a code pattern indicating a code value;
e) means for generating a code for each subset of the data character sequence correlated with the code pattern to generate a data code sequence;
Including receiver. a) a transmitter having a transmitter clock terminal for receiving a transmission clock signal at a transmission clock frequency and a transmitter output terminal for transmitting the signal, wherein the signal includes a plurality of transmission data bits for each of a plurality of transmission data bits; A transmitter including a rising signal transition and a plurality of falling signal transitions;
b) i. A receiver clock terminal for receiving a reception clock signal asynchronous to the transmission clock signal and having a reception clock frequency greater than the transmission clock frequency;
ii. A data recovery circuit connected to the transmitter output terminal, wherein the data recovery circuit oversamples the signal by using the received clock signal to provide an oversampled data signal;
iii. A data correlator that correlates the oversampled data signal with at least one data pattern, the data correlator issuing a probability signal in response to at least one possible reception of the data bits. Machine,
A communication system including:   57. The communication system according to claim 56, wherein the transmitter transmits a signal as a common mode signal.   57. The communication system according to claim 56, wherein the oversampled data signal is a version from which the common mode signal is received.   57. The communication system according to claim 56, wherein the data correlator issues a second probability signal in response to a possible second reception of a second data bit of the data bits.   57. The communication system according to claim 56, wherein the reception clock signal is mesochronous with respect to the transmission clock signal.   57. The communication system according to claim 56, wherein the signal is DC balanced.   57. The communication system of claim 56, wherein the signal represents the data bits by using at least three signal levels.

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