JP2007208076A - Method of dry etching silicon carbide semiconductor substrate - Google Patents

Method of dry etching silicon carbide semiconductor substrate Download PDF

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JP2007208076A
JP2007208076A JP2006026191A JP2006026191A JP2007208076A JP 2007208076 A JP2007208076 A JP 2007208076A JP 2006026191 A JP2006026191 A JP 2006026191A JP 2006026191 A JP2006026191 A JP 2006026191A JP 2007208076 A JP2007208076 A JP 2007208076A
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etching
semiconductor substrate
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silicon carbide
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JP4609335B2 (en
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Yasuyuki Kawada
泰之 河田
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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<P>PROBLEM TO BE SOLVED: To provide a method of dry etching a silicon carbide semiconductor substrate which can easily form an etching mask having an etching resistance high to dry etching using a plasma generated by ionizing a gas containing fluoride, and can easily release the etching mask after the dry etching. <P>SOLUTION: In the method of dry etching a silicon carbide semiconductor substrate, an etching mask is selectively formed on the silicon carbide semiconductor substrate, a trench is formed in an exposed part of the semiconductor substrate using a plasma, and the etching mask is made of laminated layer films of silicon oxide and tin oxide. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、高耐圧、大電流用炭化珪素（以下、ＳｉＣ）半導体装置を製造する際の半導体基板へのトレンチ形成のためのドライエッチング方法に係る。   The present invention relates to a dry etching method for forming a trench in a semiconductor substrate when manufacturing a high breakdown voltage, high current silicon carbide (hereinafter, SiC) semiconductor device.

インバータや電力制御などに用いられるシリコン（以下Ｓｉ）半導体パワーデバイスとしてはパワーＭＯＳＦＥＴやＩＧＢＴなどが周知であり、広く用いられている。しかしながら、半導体材料としてのＳｉはパワーデバイスではその半導体特性の面からは、もはやその物性値的な限界に近いと思われる使われ方がされるようになってきた。そこで、半導体Ｓｉよりはその物性的限界の高い材料である半導体ＳｉＣが着目されるようになってきた。この半導体ＳｉＣ（４Ｈ−ＳｉＣの結晶形態）材料はその絶縁破壊電界が半導体Ｓｉに比べ一桁高く、さらにバンドギャップは２．９倍、熱伝導率は３．２倍、真性半導体となる温度が３〜４倍とそれぞれＳｉより高く、特にパワーデバイス材料として用いる場合に、その物性的限界に優れた半導体特性の特長が大いに発揮される。従って、この半導体ＳｉＣ材料を用いたパワーデバイスは高耐圧と低オン抵抗を併有するデバイスとして期待され、近年製品化へのアプローチが多く試みられるようになった。しかし、パワーデバイスとして製品化するための製造プロセスには、まだまだ解決すべき課題も多い。   As a silicon (hereinafter referred to as Si) semiconductor power device used for an inverter, power control, and the like, a power MOSFET, an IGBT, and the like are well known and widely used. However, Si as a semiconductor material has been used in power devices that are considered to be close to the limits of physical properties in terms of semiconductor characteristics. Thus, attention has been focused on semiconductor SiC, which is a material having a higher physical limit than semiconductor Si. This semiconductor SiC (4H-SiC crystal form) material has an electrical breakdown field that is an order of magnitude higher than that of semiconductor Si, and further has a band gap of 2.9 times, a thermal conductivity of 3.2 times, and an intrinsic semiconductor temperature. When used as a power device material, which is 3 to 4 times higher than Si, the characteristics of semiconductor characteristics excellent in physical properties are greatly exhibited. Accordingly, a power device using this semiconductor SiC material is expected as a device having both a high breakdown voltage and a low on-resistance, and in recent years, many approaches to commercialization have been attempted. However, there are still many problems to be solved in the manufacturing process for commercialization as a power device.

一方、近年、半導体Ｓｉを用いたパワーＭＯＳＦＥＴやＩＧＢＴのオン抵抗を低減するためにトレンチゲートが採用されている。トレンチ型ＭＯＳＦＥＴの製造方法においては、このトレンチ形状を精密に形成することが欠かせないので、そのエッチング工程は非常に重要である。トレンチゲート構造を形成する際には、トレンチの深さは耐圧等によって異なるが数百Ｖの耐圧で数μｍ必要である。このような所望の深さの制御と精密な形状のトレンチを得るためのエッチングプロセス技術は半導体Ｓｉ基板では可能になっている。   On the other hand, in recent years, trench gates have been adopted to reduce the on-resistance of power MOSFETs and IGBTs using semiconductor Si. In the trench MOSFET manufacturing method, it is indispensable to precisely form the trench shape, and the etching process is very important. When the trench gate structure is formed, the depth of the trench varies depending on the withstand voltage or the like, but requires several μm with a withstand voltage of several hundred volts. Such a desired depth control and an etching process technique for obtaining a precise-shaped trench are possible in a semiconductor Si substrate.

しかしながら、半導体ＳｉＣを用いたＭＯＳＦＥＴやＩＧＢＴの場合は、ウエットエッチングを可能とする実用的なエッチング溶液すら未だ発見されず、通常は精密な形状のトレンチの形成プロセスとしてはドライエッチングが用いられる。しかし、現状の公知のドライエッチング技術では半導体ＳｉＣのエッチングレートが低い上にマスクとなる材料とのエッチング選択性も小さいため、特に深さの点が問題であり、深いトレンチを形成することが容易ではない。たとえば、数μｍ程度の深さのトレンチでさえ形成するのは容易とはいえないレベルである。通常、エッチングレートを稼ぐためには公知のＩＣＰ（誘導結合プラズマ）方式などによる高密度プラズマを用いてドライエッチングが行なわれるが、それでも前述の深い（数μｍ）トレンチを形成するには長時間を要する。このため、エッチングマスクに用いられる材料が化学的および物理的にも、半導体ＳｉＣとのエッチング選択比が十分高くないと、半導体ＳｉＣ基板に形成されるトレンチが目標とするエッチング深さに到達する前にマスクがエッチングされて無くなるという問題が起きる。たとえば、厚さが２μｍのＳｉＯ２膜をマスクとしてＳｉＣ基板をエッチングすると選択比は３程度であるので、ＳｉＣが６μｍ程度エッチングされたところでマスクのＳｉＯ２膜が消失し、それ以上のトレンチ形成ができなくなる。マスクの膜厚を厚くすると、成膜に時間がかかる上に、厚くなったマスク材に対する良好な精度のパターニングが難しくなるという問題が新たに生じ、前記問題の解消とはとても言い難い。 However, in the case of MOSFETs and IGBTs using semiconductor SiC, even a practical etching solution that enables wet etching has not yet been found, and usually dry etching is used as a precise trench forming process. However, the current known dry etching technique has a low etching rate of semiconductor SiC and a low etching selectivity with a material serving as a mask. Therefore, the depth is a problem, and it is easy to form a deep trench. is not. For example, it is not easy to form even a trench having a depth of about several μm. Usually, in order to increase the etching rate, dry etching is performed using high-density plasma by a known ICP (inductively coupled plasma) method or the like, but it still takes a long time to form the above-mentioned deep (several μm) trench. Cost. For this reason, if the material used for the etching mask is chemically and physically low in etching selectivity with the semiconductor SiC, the trench formed in the semiconductor SiC substrate will reach the target etching depth. In other words, the mask is etched away. For example, when a SiC substrate is etched using a 2 μm thick SiO 2 film as a mask, the selectivity is about 3. Therefore, when the SiC is etched by about 6 μm, the SiO 2 film of the mask disappears and a trench is formed beyond that. become unable. When the thickness of the mask is increased, it takes a long time to form the film, and a new problem arises that it becomes difficult to perform patterning with good accuracy on the thickened mask material, and it is very difficult to say that the problem is solved.

また、ＧａＮ系半導体基板やＳｉＣ基板のドライエッチングにおけるエッチング選択比の高いマスク材料としてはＴｉ膜とＮｉとＡｇ、Ｓｎ、Ｐ、Ｂなどとの合金膜との積層膜が知られており、そのエッチング選択比は３０以上であるという記述もある（特許文献１−実施例１）。
特開２００５−３２２８１１号公報 As a mask material having a high etching selectivity in dry etching of a GaN-based semiconductor substrate or SiC substrate, a laminated film of a Ti film and an alloy film of Ni and Ag, Sn, P, B, etc. is known. There is also a description that the etching selectivity is 30 or more (Patent Document 1-Example 1).
JP 2005-322811 A

しかしながら、前述の特許文献１に記載のＴｉ膜およびＮｉ合金膜を用いたエッチングマスクは、真空蒸着やスパッタリング法により形成される金属膜であるため、トレンチエッチング中に前記金属マスク表面から金属粒子がエッチング面に飛散して、または溶解した金属のエッチング面への再付着によりマイクロマスクを形成し易く、エッチング面の全面を平滑面とし難いという問題がある。   However, since the etching mask using the Ti film and the Ni alloy film described in Patent Document 1 described above is a metal film formed by vacuum deposition or sputtering, metal particles are removed from the surface of the metal mask during trench etching. There is a problem that it is easy to form a micromask by scattering on the etched surface or reattaching the dissolved metal to the etched surface, and it is difficult to make the entire etched surface smooth.

本発明はそのような問題点に鑑みてなされたものであり、ＳｉＣ半導体基板への、フッ化物を含むガスを電離させて生成したプラズマを用いるドライエッチングに対するエッチング耐性が高いエッチングマスクを容易に作成でき、ドライエッチング後に容易に前記エッチングマスクを剥離することができるＳｉＣ半導体基板のドライエッチング方法を提供することである。   The present invention has been made in view of such problems, and easily creates an etching mask having high etching resistance to dry etching using plasma generated by ionizing a gas containing fluoride to a SiC semiconductor substrate. Another object of the present invention is to provide a dry etching method for a SiC semiconductor substrate, which can easily peel off the etching mask after dry etching.

特許請求の範囲の請求項１記載の本発明によれば、炭化珪素半導体基板上に選択的なエッチングマスクを形成後、露出する前記半導体基板部分にプラズマを用いてトレンチを形成するドライエッチング方法において、前記エッチングマスクが酸化シリコンと酸化スズとの積層膜からなる炭化珪素半導体基板のドライエッチング方法とすることにより、前記本発明の目的は達成される。   According to the first aspect of the present invention, in the dry etching method, after forming a selective etching mask on a silicon carbide semiconductor substrate, a trench is formed using plasma in the exposed semiconductor substrate portion. The object of the present invention is achieved by employing a dry etching method for a silicon carbide semiconductor substrate in which the etching mask is a laminated film of silicon oxide and tin oxide.

特許請求の範囲の請求項２記載の本発明によれば、前記エッチングマスクは前記炭化珪素半導体基板上に０．１μｍ乃至０．５μｍの厚さの酸化シリコンと０．５μｍ乃至１μｍの厚さの酸化スズとがこの順に成膜された積層膜である請求項１記載の炭化珪素半導体基板のドライエッチング方法とすることが好ましい。   According to the second aspect of the present invention, the etching mask is formed on the silicon carbide semiconductor substrate with a silicon oxide thickness of 0.1 μm to 0.5 μm and a thickness of 0.5 μm to 1 μm. 2. The silicon carbide semiconductor substrate dry etching method according to claim 1, wherein the tin oxide is a laminated film formed in this order.

特許請求の範囲の請求項３記載の本発明によれば、前記ドライエッチングに用いられるプラズマはフッ化物を含むガスを電離して得られる誘導結合プラズマである請求項１または２記載の炭化珪素半導体基板のドライエッチング方法とすることがより好ましい。   3. The silicon carbide semiconductor according to claim 1, wherein the plasma used for the dry etching is inductively coupled plasma obtained by ionizing a gas containing fluoride. It is more preferable to use a dry etching method for the substrate.

本発明によれば、ＳｉＣ半導体基板への、フッ化物を含むガスを電離させて生成したプラズマを用いるドライエッチングに対するエッチング耐性が高いエッチングマスクを容易に作成でき、ドライエッチング後に容易に前記エッチングマスクを剥離するＳｉＣ半導体基板のドライエッチング方法を提供することができる。 According to the present invention, it is possible to easily create an etching mask having high etching resistance against dry etching using plasma generated by ionizing a gas containing fluoride to a SiC semiconductor substrate, and the etching mask can be easily formed after dry etching. A dry etching method for a SiC semiconductor substrate to be peeled can be provided.

（実施の形態）
以下、本発明にかかる炭化珪素半導体基板のドライエッチング方法について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。 (Embodiment)
Hereinafter, a dry etching method for a silicon carbide semiconductor substrate according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

図１は本発明の炭化珪素半導体基板のドライエッチング方法にかかる炭化珪素半導体基板上にエッチングマスクを形成した段階の半導体基板の要部断面図である。図２は本発明にかかるエッチングマスクを形成する前にフォトレジストパターンを形成した段階の半導体基板の要部断面図である。図３は本発明の炭化珪素半導体基板のドライエッチング方法にかかる炭化珪素半導体基板上にエッチングマスクを形成した段階の半導体基板の要部断面図である。図４は本発明にかかるドライエッチングのエッチング時間とエッチング量との関係図である。   FIG. 1 is a cross-sectional view of a principal part of a semiconductor substrate at a stage where an etching mask is formed on the silicon carbide semiconductor substrate according to the dry etching method for a silicon carbide semiconductor substrate of the present invention. FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate at a stage where a photoresist pattern is formed before forming an etching mask according to the present invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate at a stage where an etching mask is formed on the silicon carbide semiconductor substrate according to the silicon carbide semiconductor substrate dry etching method of the present invention. FIG. 4 is a relationship diagram between the etching time and the etching amount of dry etching according to the present invention.

図１に本発明にかかるＳｉＣ基板１をドライエッチングする際に用いるエッチングマスクの積層構造２、３を示す。ＳｉＣ基板１上にＳｉＯ２膜２を形成し、さらにその上にＳｎＯ２膜３を形成する。ＳｉＯ２膜２およびＳｎＯ２膜３はフォトリソグラフィにより所望のパターンを形成する。以下、そのプロセスについて図２、図３を参照して詳細に説明する。ＳｉＣ基板１をよく洗浄した後にフォトレジストをスピンコート法により全面塗布する。その後、クリーンオーブンに８５℃で３０分投入し、フォトレジストをベークした。ベーク後、紫外線を用いた露光装置で所望のパターンを有するフォトマスクを用いて初期露光を行なった。初期露光後、１１５℃で１５分のベークを行ない、その後、マスクを用いないで基板全体を全面露光した。全面露光後、現像を行ない、所望のパターン以外の不要なフォトレジストを除去し、図２のようなフォトレジストパターン４を形成した。このときのフォトレジスト４の膜厚は約２μｍである。 FIG. 1 shows stacked structures 2 and 3 of etching masks used when dry etching the SiC substrate 1 according to the present invention. An SiO 2 film 2 is formed on the SiC substrate 1, and an SnO 2 film 3 is further formed thereon. The SiO 2 film 2 and the SnO 2 film 3 form a desired pattern by photolithography. Hereinafter, the process will be described in detail with reference to FIGS. After thoroughly cleaning SiC substrate 1, a photoresist is applied over the entire surface by spin coating. Thereafter, the photoresist was baked by putting it in a clean oven at 85 ° C. for 30 minutes. After baking, initial exposure was performed using a photomask having a desired pattern with an exposure apparatus using ultraviolet rays. After the initial exposure, baking was performed at 115 ° C. for 15 minutes, and then the entire substrate was exposed without using a mask. After the entire surface exposure, development was performed to remove unnecessary photoresist other than the desired pattern, and a photoresist pattern 4 as shown in FIG. 2 was formed. At this time, the film thickness of the photoresist 4 is about 2 μm.

フォトレジストパターン４を形成後、スパッタ法によりＳｉＯ２膜２を室温で形成する。成膜圧力を１ＰａとしてＡｒ＋１０％Ｏ２ガス中でＲＦにてＳｉＯ２ターゲットをスパッタする成膜条件により、ＳｉＯ２膜２を０．５μｍの厚さに形成した。続いて真空を切らずに、スパッタ法によりＳｎＯ２膜３を室温で形成した。成膜圧力を１ＰａとしてＡｒ＋１０％Ｏ２ガス中でＲＦにてＳｎＯ２ターゲットをスパッタする成膜条件によりＳｎＯ２膜３を０．５μｍの厚さに形成した。このように形成されたＳｉＯ２膜２とＳｎＯ２膜３のうち、特には表面側のＳｎＯ２膜３はトレンチエッチングの際にも、ほとんどエッチングされないので、溶解してトレンチエッチング予定面に再付着し平滑なトレンチエッチングを妨げる現象はほとんど起きない。トータル膜厚１μｍのＳｉＯ２およびＳｎＯ２の積層膜（以下ＳｉＯ２／ＳｎＯ２と記述）が載置されたＳｉＣ基板をフォトレジスト剥離液につけてフォトレジストを除去するいわゆるリフトオフ法でＳｉＯ２／ＳｎＯ２積層膜のパターニングを行なった。パターニングされた線幅は本実施例では２μｍ幅である。図３はこのリフトオフ法によりパターニングされたＳｉＣ基板１上の積層マスク構造２、３の断面を示す。ＳｉＯ２膜は、ＳｎＯ２膜のエッチングが困難なため、ＳｎＯ２膜単独膜とするとパターニングができないことから設けられる膜である。ＳｎＯ２膜の下側にＳｉＯ２膜を形成することにより、リフトオフ法によるＳｎＯ２膜のパターニングを可能にするのである。従って、ＳｉＯ２膜の厚さは厚くする必要はなく、０．１μｍ以上あればよく、上限は積層膜の熱膨張係数の関係から０．５μｍ以下が好ましい。ＳｎＯ２膜は厚い方が深いトレンチエッチングを可能にするので、０．５μｍ以上が好ましい。また、積層膜の熱膨張係数の関係から厚すぎると、ウエハのそりの発生によるプロセス上に問題が生じるので、１μｍ以下の厚さが好ましい。 After forming the photoresist pattern 4, the SiO 2 film 2 is formed at room temperature by sputtering. The SiO 2 film 2 was formed to a thickness of 0.5 μm under the film forming conditions where the film forming pressure was 1 Pa and the SiO 2 target was sputtered by RF in Ar + 10% O 2 gas. Subsequently, the SnO 2 film 3 was formed at room temperature by sputtering without breaking the vacuum. The SnO 2 film 3 was formed to a thickness of 0.5 μm under the film forming conditions where the film forming pressure was 1 Pa and the SnO 2 target was sputtered by RF in Ar + 10% O 2 gas. Of the SiO 2 film 2 and SnO 2 film 3 formed in this way, the SnO 2 film 3 on the surface side, in particular, is hardly etched even during trench etching, so it melts and reattaches to the trench etching planned surface. However, a phenomenon that prevents smooth trench etching hardly occurs. SiO 2 / SnO so-called lift-off method for removing the photoresist with a SiC substrate SiO 2 and SnO 2 of the laminated film (hereinafter SiO 2 / SnO 2 and described) is placed in the total thickness 1μm on photoresist stripping solution Two laminated films were patterned. The patterned line width is 2 μm in this embodiment. FIG. 3 shows a cross section of the laminated mask structures 2 and 3 on the SiC substrate 1 patterned by the lift-off method. Since the SiO 2 film is difficult to etch the SnO 2 film, it is a film provided because patterning cannot be performed if the SnO 2 film is a single film. By forming the SiO 2 film on the lower side of the SnO 2 film is to allow patterning of the SnO 2 film by a lift-off method. Therefore, the thickness of the SiO 2 film does not need to be increased, and may be 0.1 μm or more, and the upper limit is preferably 0.5 μm or less in view of the thermal expansion coefficient of the laminated film. Since a thicker SnO 2 film enables deep trench etching, 0.5 μm or more is preferable. Further, if the thickness is too large due to the thermal expansion coefficient of the laminated film, a problem arises in the process due to the warpage of the wafer.

リフトオフ法を用いるのはＳｎＯ２膜３についても、ドライエッチングでもウエットエッチングでも極めてエッチングが難しいため、リフトオフ法でのパターニングが適しているからである。次に、得られたＳｉＯ２／ＳｎＯ２積層膜２、３をＳｉＣ基板１のドライエッチングのマスクとして用い、ＩＣＰ−ＲＩＥ装置（図示せず）でドライエッチングを行なった。このときの条件はＩＣＰ電力２００Ｗ、バイアス電力２５ＷでＳＦ６＋５０％Ｏ２ガスを用い１Ｐａの圧力でトレンチエッチングを行なった。このＩＣＰ−ＲＩＥ装置によれば、誘導結合コイルによる大電力のプラズマ励起により形成される高密度プラズマをＳｉＣ基板のエッチングに利用できる。所定時間エッチングを行ない、所望の深さのトレンチを形成した後、前記ＩＣＰ−ＲＩＥ装置から取り出し、バッファードフッ酸にＳｉＣ基板をつけてマスク材のＳｉＯ２膜部分を溶解させ、ＳｉＯ２／ＳｎＯ２マスクを除去した。ＳｎＯ２膜は溶解されないが、ＳｉＯ２膜の剥離と共に除去される。
図４に、ＩＣＰ−ＲＩＥ装置を用いて形成される高密度プラズマを用いてＳｉＣ基板をエッチングした場合のエッチング時間に対するＳｉＯ２／ＳｎＯ２積層膜マスクのエッチング量とＳｉＣ基板のエッチング量とを示す。ＳｉＯ２／ＳｎＯ２積層膜のマスクに対するエッチングは、１ｎｍ／分程度のエッチング量のため、１時間エッチングしても０．０６μｍ以下のエッチング量であり、実質的にマスクはほとんどエッチングされないことが分かる。若干エッチングされているのは物理的（スパッタ）要因によるものであり、化学的には極めてエッチング耐性が高いのがわかる。このときのＳｉＣ基板のエッチング量は５０ｎｍ／分程度あり、マスクのエッチング量／ＳｉＣのエッチング量＝１／５０程度有り、極めて選択性が高いことが分かる。エッチングマスク材にＮｉやＡｌなどの金属または合金膜を使った場合、エッチング条件によっては金属粒子が飛散しマイクロマスクの発生原因になりエッチングに支障をきたす場合があるが、酸化物であるＳｎＯ２はフッ素系ガスによるドライエッチングでも酸・アルカリによるウエットエッチングでもほとんどエッチングできない。このためマイクロマスクの発生がなく、ドライエッチングやウエットエッチングのマスクとして用いることに優れている。このようにマスクの最表面がＳｎＯ２になっていることで、マスクがほとんどエッチングされずＳｉＣを深くドライエッチングすることができる。 The lift-off method is used because the SnO 2 film 3 is also very difficult to be etched by either dry etching or wet etching, so that patterning by the lift-off method is suitable. Next, dry etching was performed with an ICP-RIE apparatus (not shown) using the obtained SiO 2 / SnO 2 laminated films 2 and 3 as a mask for dry etching of the SiC substrate 1. At this time, trench etching was performed at a pressure of 1 Pa using SF 6 + 50% O 2 gas with an ICP power of 200 W and a bias power of 25 W. According to this ICP-RIE apparatus, high-density plasma formed by high-power plasma excitation by an inductively coupled coil can be used for etching a SiC substrate. Etching is carried out for a predetermined time to form a trench having a desired depth, and then taken out from the ICP-RIE apparatus. An SiC substrate is attached to buffered hydrofluoric acid to dissolve the SiO 2 film portion of the mask material, and SiO 2 / SnO Two masks were removed. The SnO 2 film is not dissolved, but is removed together with the removal of the SiO 2 film.
FIG. 4 shows the etching amount of the SiO 2 / SnO 2 laminated film mask and the etching amount of the SiC substrate with respect to the etching time when the SiC substrate is etched using the high-density plasma formed using the ICP-RIE apparatus. . Since the etching of the SiO 2 / SnO 2 laminated film mask is about 1 nm / min, the etching amount is 0.06 μm or less even if it is etched for 1 hour, and the mask is hardly etched. . The slight etching is due to physical (sputtering) factors, and it can be seen that the etching resistance is extremely high chemically. At this time, the etching amount of the SiC substrate is about 50 nm / min, the etching amount of the mask / the etching amount of SiC = 1/50, and it can be seen that the selectivity is extremely high. When a metal or alloy film such as Ni or Al is used for the etching mask material, metal particles may be scattered depending on the etching conditions, which may cause micromasks and hinder etching, but SnO 2 is an oxide. Can hardly be etched by either dry etching with fluorine-based gas or wet etching with acid / alkali. For this reason, there is no generation of a micromask and it is excellent for use as a mask for dry etching or wet etching. Thus, since the outermost surface of the mask is SnO 2 , the mask is hardly etched and SiC can be deeply dry etched.

この条件で４時間のエッチングを行なったが、マスクは表面のＳｎＯ２が０．２５μｍ程度エッチングされたがＳｉＣは約１２μｍエッチングでき、深いトレンチが形成できることが確認できた。確認はしていないがマスクはこのエッチング時間ではまだ半分残っているので２０μｍ以上のエッチングが可能と考えられる。このトレンチ形成技術を用いることにより、ＳｉＣ基板を用いたＭＯＳＦＥＴやＩＧＢＴなどのパワーデバイスの耐圧を飛躍的に向上できる。 Although etching was performed for 4 hours under these conditions, it was confirmed that SnO 2 on the surface of the mask was etched by about 0.25 μm, but SiC could be etched by about 12 μm and a deep trench could be formed. Although it has not been confirmed, half of the mask still remains in this etching time, so it is considered that etching of 20 μm or more is possible. By using this trench formation technique, the breakdown voltage of power devices such as MOSFETs and IGBTs using a SiC substrate can be dramatically improved.

本発明の炭化珪素半導体基板のドライエッチング方法にかかる炭化珪素半導体基板上にエッチングマスクを形成した段階の半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate of the stage which formed the etching mask on the silicon carbide semiconductor substrate concerning the dry etching method of the silicon carbide semiconductor substrate of this invention. 本発明にかかるエッチングマスクを形成する前にフォトレジストパターンを形成した段階の半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate of the stage in which the photoresist pattern was formed before forming the etching mask concerning this invention. 本発明の炭化珪素半導体基板のドライエッチング方法にかかる炭化珪素半導体基板上にエッチングマスクを形成した段階の半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate of the stage which formed the etching mask on the silicon carbide semiconductor substrate concerning the dry etching method of the silicon carbide semiconductor substrate of this invention. 本発明にかかるドライエッチングのエッチング時間とエッチング量との関係図である。It is a relationship diagram of the etching time and etching amount of dry etching concerning the present invention.

符号の説明Explanation of symbols

１ 炭化珪素（ＳｉＣ）基板
２ ＳｉＯ２膜（マスク）
３ ＳｎＯ２膜（マスク）
４ フォトレジスト膜。 1 Silicon carbide (SiC) substrate 2 SiO 2 film (mask)
3 SnO 2 film (mask)
4 Photoresist film.

Claims (3)

炭化珪素半導体基板上に選択的なエッチングマスクを形成後、露出する前記半導体基板部分にプラズマを用いてトレンチを形成するドライエッチング方法において、前記エッチングマスクが酸化スズと酸化シリコンの積層膜からなることを特徴とする炭化珪素半導体基板のドライエッチング方法。 In a dry etching method in which a trench is formed using plasma in the exposed semiconductor substrate portion after a selective etching mask is formed on the silicon carbide semiconductor substrate, the etching mask is made of a laminated film of tin oxide and silicon oxide. A method for dry etching a silicon carbide semiconductor substrate. 前記エッチングマスクは前記炭化珪素半導体基板上に０．１μｍ乃至０．５μｍの厚さの酸化シリコンと０．５μｍ乃至１μｍの厚さの酸化スズとがこの順に成膜された積層膜であることを特徴とする請求項１記載の炭化珪素半導体基板のドライエッチング方法。 The etching mask is a laminated film in which silicon oxide having a thickness of 0.1 μm to 0.5 μm and tin oxide having a thickness of 0.5 μm to 1 μm are formed in this order on the silicon carbide semiconductor substrate. The method for dry etching a silicon carbide semiconductor substrate according to claim 1, wherein the silicon carbide semiconductor substrate is dry-etched. 前記ドライエッチングに用いられるプラズマはフッ化物を含むガスを電離して得られる誘導結合プラズマであることを特徴とする請求項１または２記載の炭化珪素半導体基板のドライエッチング方法。 3. The method for dry etching a silicon carbide semiconductor substrate according to claim 1, wherein the plasma used for the dry etching is inductively coupled plasma obtained by ionizing a gas containing fluoride.
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