JP2007199256A - Device and method for designing integrated circuit, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly design an integrated circuit by more accurately recognizing a correction error of OPC processing. <P>SOLUTION: A method for designing the integrated circuit is provided in which the integrated circuit is manufactured by using a mask and a reticle manufactured by applying the OPC processing to a pattern regulated by layout pattern data 51. The method includes a step 53 of calculating a pattern after OPC processing obtained by using the mask and reticle manufactured by performing the OPC processing and a step 54 of calculating the OPC correction error by comparing the pattern regulated by the layout pattern data with the pattern subjected to OPC processing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a design method, a design apparatus, and a program for an integrated circuit manufactured using a mask / reticle manufactured by performing OPC (Optical Proximity effect Correction) processing on a pattern defined by layout pattern data.

  In designing and manufacturing an integrated circuit, a functional design that designs a circuit diagram that realizes a desired operation is performed, a layout design that designs the arrangement and wiring of circuit elements in the circuit diagram is performed, and a layout pattern is created based on the layout design. To design. Then, an exposure pattern is created based on the layout pattern, and a manufacturing process is performed. The design procedure from the layout design to the generation of the exposure pattern will be described.

  First, layout pattern data is generated based on the layout design. Next, an operation simulation is performed to verify whether the desired operation is performed with the generated layout pattern data, and the result of the operation simulation is determined, and when the result that the desired operation is not performed is obtained, Return to the original, perform a process such as correcting a part of the layout pattern data for the problem part, and perform an operation simulation. If there is a problem, the above operation is repeated to perform a desired operation to design layout pattern data. When a desired operation is performed, an OPC (Optical Proximity effect Correction) process is performed to generate an exposure pattern. In addition to the operation simulation, various other processes may be performed. Here, the operation simulation will be described as an example.

  The OPC process is described in, for example, Patent Documents 1 and 2, and is widely known. FIG. 1 is a diagram illustrating the OPC process. For example, as shown in FIG. 1A, when a process is performed by exposing a single line pattern having a width as shown in the layout pattern data indicated by the broken line 11, the actually obtained pattern is indicated by the solid line 12. It becomes very thin and the length is also shortened. Further, when a pattern in which a plurality of lines arranged adjacent to the layout pattern data indicated by the broken line 11 in FIG. 1B and another line exists opposite to one end is exposed, it is actually obtained. In the pattern, as indicated by a solid line 12, the center line has a wider line width and the interval between adjacent lines is shorter. Further, the line becomes longer on the side where another line exists, but the line becomes shorter on the side where no other line exists. Also, the corner of the line is dull.

  Therefore, as shown in FIGS. 1C and 1D, an exposure pattern as shown by the solid line 13 is created for the pattern shown by the broken line 11, and the actually obtained pattern defines the layout pattern data. I try to get as close to the pattern as possible. Such a pattern correction needs to be performed for the line width, the distance between lines, the line length, the rounded corners, the distance from the end points, the density, and the like.

  As the OPC processing, model-based OPC processing and rule-based OPC processing are widely used, and hybrid OPC processing combining them is also used. In general, the model-based OPC process has the best correction accuracy, and the correction accuracy decreases in the order of the hybrid OPC process and the rule-based OPC process, but the time required for the OPC process is the shortest in the rule-based OPC process. Processing time increases in the order of hybrid OPC processing and model-based OPC processing.

  The pattern edge position change in the OPC process is performed in stages. This is because the pattern edge creation position in the mask / reticle can be changed in stages, and when the number of stages is increased, the time required for OPC processing increases. In any case, the OPC process requires correction for all parts of the pattern, and is a process with a very long processing time. Since the OPC processing is described in Patent Documents 1 and 2 and is well known, further explanation is omitted here.

  As described above, the position change of the pattern edge in the OPC process is performed in stages. FIG. 2 shows the generation of an error in the line width of a single line due to the stepwise change of the position of the pattern edge in the OPC process, in other words, the layout pattern data of the actually obtained single line pattern. FIG. 6 is a diagram for explaining the generation of a line width error from a pattern defined by.

  In FIG. 2, the line width of a single line pattern is corrected according to the line width “before OPC processing”, and the actually obtained pattern has a line width as indicated by “after OPC processing”. Actually, there are errors at the time of exposure, process errors, and the like, and the line width of the obtained line varies from the line width indicated by “after OPC processing”, which is not directly related to the present invention, and is omitted.

  Since the OPC process is performed in stages, the line width after “OPC process” is within the width of one stage (10 nm in this case) of the OPC process as shown in the figure. In other words, the line width after the OPC process has a correction error that is one half of the maximum OPC process (± 5 nm in this case) with respect to the line width of the pattern defined by the layout pattern data.

  The previous operation simulation was performed on the pattern specified by the layout pattern data. However, a correction error is inevitably generated in the OPC process, and the correction error is not taken into account, so that the accuracy of the operation simulation is insufficient. There was a problem. Therefore, an operation simulation is performed when the width of the upper limit (+3 nm in FIG. 2) and the width of the lower limit (−3 nm in FIG. 2) of the correction error generated in the OPC processing are performed. Generated layout pattern data. Although only the line width has been described here, the same applies to other line intervals, line lengths, and the like. As described above, conventionally, the operation simulation is performed by uniformly applying the limit value of the correction error due to OPC. Even when processing other than the operation simulation is performed at this stage, similarly, the limit value of the correction error by OPC is applied uniformly.

JP 2003-322945 A JP 2003-344985 A

  As described above, conventionally, processing such as operation simulation has been performed by uniformly applying the limit value of the correction error due to OPC. When the design rule, i.e., the line width is large and the correction error due to the OPC process is relatively small with respect to the line width as in the conventional case, no significant problem has occurred. However, as the miniaturization progresses and the line width becomes very narrow as in recent years, the influence of the correction error due to OPC in processing such as operation simulation cannot be ignored. For example, if the line width is 60 nm and the correction error due to OPC is 10 nm (± 5 nm), the correction error alone is just over ± 8%, and the variation problem has become apparent, and this is a large error that cannot be ignored. It has become.

  In the conventional example, layout pattern data is corrected or redesigned when a desired operation is not realized in the operation simulation. However, this operation simulation is a uniform application of the limit value of the correction error due to OPC, and in fact, a desired operation may be realized with a small correction error in the OPC process. For example, in FIG. 2, the line width after OPC processing indicated by P is an error of −4% with respect to the line width defined by the layout pattern data, and an operation simulation was performed with a limit value of + 8% or −8%. In some cases, even if the desired operation is not realized, when an operation simulation is performed with an actual correction error of −4%, this error is uniformly applied as a variation at the time of simulation. It becomes a cause.

  An object of the present invention is to solve the above-described problems, and it is an object of the present invention to make it possible to recognize a correction error due to an OPC process more accurately and perform an appropriate design in designing an integrated circuit.

  In order to achieve the above object, according to the present invention, in designing an integrated circuit, a correction error due to the OPC process can be calculated and used before the OPC process is actually performed.

  That is, the integrated circuit design method of the present invention is a method of designing an integrated circuit manufactured using a mask / reticle manufactured by performing OPC processing on a pattern defined by layout pattern data, The step of calculating a post-OPC pattern obtained by using a mask / reticle manufactured by processing is compared with the post-OPC pattern and the pattern defined by the layout pattern data to reduce the OPC correction error. And a step of calculating.

  According to the present invention, since the correction error due to the OPC process is calculated before the actual OPC process, the design can be performed by appropriately determining the influence of the correction error due to the OPC process.

  For example, when performing an operation simulation, calculation of circuit element correction errors and extraction of element parameters are performed in consideration of OPC correction errors, and operation simulation can be performed based on the calculation, so that simulation can be performed under conditions closer to actual conditions. And accuracy is improved. In addition, a situation in which the result of the operation simulation is unnecessarily deteriorated is thereby prevented, so that unnecessary layout pattern data can be prevented from being corrected, and the design throughput can be improved.

  Further, the allowable range of the correction error due to the calculated OPC process is set to be smaller than the error range of the OPC process actually performed in the next step so that the calculated correction error due to the OPC process falls within this allowable range. In addition, by correcting the layout pattern data, it is possible to avoid a situation in which correction cannot be performed by actual OPC processing.

  In addition, after calculating the correction error by the OPC processing, the operation simulation is performed by uniformly applying the limit value of the correction error by the OPC similarly to the conventional case, and the calculated OPC is performed only for a portion where the desired operation cannot be realized. An operation simulation may be performed by applying a correction error due to the processing, and it may be confirmed whether a desired operation can be realized. In this case, if the calculated correction error due to the OPC process is close to the limit value of the correction error due to the OPC, there is a possibility that the desired operation can be realized even if the operation simulation is performed again by applying the calculated correction error due to the OPC process. Therefore, the correction may be performed only when the difference between the calculated correction error due to the OPC process and the limit value of the correction error due to the OPC is large.

  Further, similarly to the conventional method, the limit value of the correction error by OPC is uniformly applied to perform an operation simulation, and only for a portion where a desired operation cannot be realized, the correction error is calculated by the OPC process, and the correction by the calculated OPC process is performed. An error may be applied to perform an operation simulation to confirm whether a desired operation can be realized. Also in this case, only when the calculated correction error due to the OPC process has a large difference from the limit value of the correction error due to the OPC, the operation simulation using the calculated correction error due to the OPC process may be performed.

  According to the present invention, in designing an integrated circuit, the correction error due to the OPC process can be recognized more accurately and the design can be performed, and not only the design accuracy is improved but also the redesign and operation of a useless layout pattern. Since the simulation is reduced, the throughput of the design is improved.

  FIG. 3A is a diagram showing the configuration of the design apparatus (tool) of the first embodiment of the present invention. The design tool is realized by a computer system and a program installed therein. The integrated circuit to be designed according to the present invention is an integrated circuit manufactured using a mask / reticle manufactured by performing OPC processing on a pattern defined by the layout pattern data, and almost all current integrated circuits are targets. It becomes.

  As shown in the figure, the design tool of the first embodiment performs the OPC processing on the layout pattern data 51 stored in the storage device and the OPC processing table 52 storing information for performing the OPC processing, and the layout pattern data 51. A pattern calculation means 53 after OPC processing for calculating a pattern after performing OPC processing based on information in the table 52, and each pattern after OPC processing is compared with the layout pattern data 51 to calculate a correction error due to OPC processing. A comparison means 54 for each pattern; an element correction error calculation means 55 for calculating a circuit element correction error in consideration of the OPC correction error; an element parameter extraction means 56 for extracting an element parameter based on the circuit element correction error; Netlist output to output element parameter netlist including circuit element correction error And means 57, it has.

  FIG. 3B shows an example of a netlist, in which a correction error is described in addition to the channel length and channel width of the N-channel transistor.

  The design tool of the first embodiment is provided with means for simulating the operation of the integrated circuit, which is the same as the conventional one, and performs the operation simulation based on the element parameters included in the netlist. However, the operation simulation is performed based on element parameters including a circuit element correction error.

  The OPC processing table desirably stores information that can obtain the same result as the OPC processing performed later, and the same table as that used in the OPC processing can be used. However, a portion that does not greatly affect the operation simulation or the like may be simple. FIG. 4 is a diagram showing an example of a simple OPC processing table, and shows the amount of OPC processing performed according to the line width and the distance between adjacent lines. In any case, the correction amount is calculated for all patterns defined by the layout pattern data in the OPC processing, whereas the post-OPC processing pattern calculation means 53 only needs to perform the OPC processing for the patterns necessary for the operation simulation. Therefore, the processing amount may be small and the processing can be performed in a short time.

  FIG. 5 is a flowchart showing a design procedure in the first embodiment. In step 201, an OPC process is performed on the pattern defined by the layout pattern data 51 in accordance with the OPC correction information described in the OPC process table 52, and a post-OPC pattern is calculated.

  In step 202, an OPC correction error is calculated by comparing the pattern after OPC processing with the pattern defined by the layout pattern data. In step 203, the comparison result, that is, the calculated OPC correction error is notified. Various processes can be performed using the notified OPC correction error. In the first embodiment, the OPC correction error is used for an operation simulation.

  In step 204, the circuit element correction error is calculated in consideration of the OPC correction error. In step 205, element parameters are extracted based on the calculated circuit element correction error. In step 206, an element parameter netlist including a circuit element correction error is output.

  Thereafter, an operation simulation of the integrated circuit is performed based on the element parameter. Here, the element parameter includes a circuit element correction error, and the operation simulation of the integrated circuit is performed in consideration of the OPC correction error. .

  In the first embodiment, the OPC correction error is used for the operation simulation. However, other OPC correction errors can be used. In the second embodiment, the calculated OPC correction error is fed back to the layout pattern data and the OPC correction error is generated. It is made smaller than a predetermined target value. As a result, an OPC correction error that actually occurs when the OPC process is performed later is reduced, and an operation simulation or the like may be performed with the OPC correction error, thereby ensuring appropriate variation.

  FIG. 6 is a flowchart showing the design procedure of the second embodiment of the present invention. The configuration of the design apparatus of the second embodiment is the same as that of the first embodiment.

  In step 301, layout pattern data is created and is usually called physical design. In step 302, whether the created layout pattern data conforms to the design rule is checked, and this is called physical verification. Although not shown, if the design rule is not met, the layout pattern data is of course corrected.

  In step 303, the processing of steps 201 and 202 in FIG. 5 is performed to calculate the OPC correction error. In step 304, it is determined whether the OPC correction error is smaller than a target value, for example, a value that is half of the correction error in the OPC process. If larger, the process proceeds to step 305, where an error part where the OPC correction error is larger than the target value is notified, and the process returns to step 301 to correct the layout pattern data for the error part. This process is repeated until the OPC correction error becomes smaller than the target value.

  When the OPC correction error is smaller than the target value, the process proceeds to step 306 and an operation simulation is performed. In step 307, the result of the operation simulation is determined. If there is a problem, the process returns to step 301 to correct the layout pattern data, and if there is no problem, the process proceeds to the next OPC processing step.

  As described above, conventionally, the operation simulation is performed by uniformly applying the limit value of the correction error by OPC. The layout pattern data is corrected or redesigned when the desired operation is not realized in the operation simulation. However, when the limit value of the correction error by OPC is uniformly applied, the layout pattern data that does not need to be changed is corrected. In some cases, extra design time was required. In the third embodiment, such waste is eliminated by using the calculated OPC correction error.

  FIG. 7 is a flowchart showing the design procedure of the third embodiment of the present invention. The configuration of the design apparatus of the third embodiment is the same as that of the first embodiment.

  As described in the second embodiment, layout pattern data is generated in step 401, and an OPC correction error is calculated in step 402. In step 403, the OPC correction error is stored.

  In step 404, the limit circuit element correction error is calculated in consideration of the limit value of the correction error due to OPC, as in the conventional case, the element parameter is extracted in step 405, the operation simulation of the integrated circuit is performed in step 406, In 406, the result of the operation simulation is determined, and if there is no problem, the process proceeds to the OPC process in the next step. The above steps 404 to 407 are the same as in the conventional example.

  If a desired operation simulation result is not obtained in step 407, the process proceeds to step 408, and element parameters are extracted for the problematic (NG) part in consideration of the OPC correction error calculated in step 402. Then, the operation simulation is performed for that part. In step 410, the result of the operation simulation in step 409 is determined. If there is no problem, the process proceeds to the OPC process of the next process. If there is still a problem, the process returns to step 401 to correct the problem part of the layout pattern data and find Repeat the process until it runs out.

  Note that in the case of extracting element parameters in consideration of the OPC correction error in step 408, if the calculated OPC processing correction error is close to the limit value of the correction error due to OPC, the same result as the operation simulation in step 406 is obtained. Since it is predicted that it will be obtained, it is useless even if the operation simulation is performed again. Therefore, if the difference between the calculated OPC correction error and the limit value of the correction error due to OPC is small, the process returns to step 401 without performing steps 408 to 410, and the difference between the OPC correction error and the limit value of the correction error due to OPC is calculated. Only when the difference is large, steps 408 to 410 may be performed.

  FIG. 8 is a flowchart showing the design procedure of the fourth embodiment of the present invention. In the third embodiment, the OPC correction error is calculated before performing the operation simulation considering the limit value of the correction error due to the conventional OPC, but in the fourth embodiment, the operation simulation considering the limit value of the correction error due to the OPC. The OPC correction error is calculated only for the portion where the desired operation cannot be obtained, and the operation simulation is performed again only for that portion. The other parts are the same as those of the third embodiment, and the description is omitted.

(Appendix 1)
A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating an OPC-processed pattern obtained by using a mask / reticle manufactured by performing the OPC process;
And a step of calculating an OPC correction error by comparing the post-OPC pattern with a pattern defined by the layout pattern data.
(Appendix 2)
Calculating a circuit element correction error in consideration of the OPC correction error;
Extracting element parameters based on the circuit element correction error;
The integrated circuit design method according to claim 1, further comprising: outputting a netlist of the element parameters including the circuit element correction error.
(Appendix 3)
The integrated circuit design method according to claim 2, further comprising a step of performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error included in the netlist.
(Appendix 4)
After calculating the OPC correction error, further comprising determining whether the OPC correction error is a predetermined value or less;
Note that when the OPC correction error is equal to or greater than the predetermined value, the layout pattern data is redesigned for a portion where the OPC correction error is equal to or greater than the predetermined value so that the OPC correction error is equal to or smaller than the predetermined value. 2. A method for designing an integrated circuit according to 1.
(Appendix 5)
A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating an OPC-processed pattern obtained by using a mask / reticle manufactured by performing the OPC process;
Comparing the post-OPC pattern and the pattern defined by the layout pattern data to calculate an OPC correction error;
Calculating a limit circuit element correction error in consideration of a limit value of an allowable range of the OPC correction error determined in the OPC process;
Extracting element parameters based on the limit circuit element correction error;
Performing an operation simulation of the integrated circuit based on the element parameters including the limit circuit element correction error;
Calculating the circuit element correction error in consideration of the OPC correction error for an unfavorable portion when the operation simulation is not good;
Extracting element parameters based on the circuit element correction error;
And a step of performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error.
(Appendix 6)
A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating a limit circuit element correction error in consideration of a limit value of an allowable range of the OPC correction error determined in the OPC process;
Extracting element parameters based on the limit circuit element correction error;
Performing an operation simulation of the integrated circuit based on the element parameters including the limit circuit element correction error;
Calculating a post-OPC process pattern obtained by using a mask / reticle manufactured by performing the OPC process on an unsatisfactory part when the operation simulation is not good;
Comparing the post-OPC pattern and the pattern defined by the layout pattern data to calculate an OPC correction error;
Calculating a circuit element correction error in consideration of the OPC correction error;
Extracting element parameters based on the circuit element correction error;
And a step of performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error.
(Appendix 7)
An integrated circuit design apparatus manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Means for calculating a post-OPC pattern obtained by using a mask / reticle manufactured by performing the OPC process;
An integrated circuit design apparatus comprising: means for calculating an OPC correction error by comparing the post-OPC pattern and a pattern defined by the layout pattern data.
(Appendix 8)
Means for calculating a circuit element correction error in consideration of the OPC correction error;
Means for extracting element parameters based on the circuit element correction error;
The integrated circuit design apparatus according to claim 7, further comprising means for outputting a netlist of the element parameters including the circuit element correction error.
(Appendix 9)
9. The integrated circuit design apparatus according to appendix 8, further comprising means for performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error included in the netlist.
(Appendix 10)
A program for causing a computer to design an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculate a pattern after OPC processing obtained by using a mask / reticle manufactured by performing the OPC processing,
A program characterized in that an OPC correction error is calculated by comparing the post-OPC pattern with a pattern defined by the layout pattern data.

  The present invention can be applied to any case when designing an integrated circuit manufactured by performing OPC processing at the time of manufacturing an exposure pattern, and is designed by a method, a design apparatus, and a computer for designing such an integrated circuit. The present invention is applied to a program for realizing an apparatus, and an integrated circuit designed using such a method, apparatus, and program.

FIG. 1 is a diagram illustrating an example of the OPC process. FIG. 2 is a diagram for explaining the generation of a correction error due to the OPC process. FIG. 3 is a diagram showing a configuration of an integrated circuit design apparatus (tool) according to the first embodiment of the present invention and an example of an output netlist. FIG. 4 is a diagram showing an example of a simple OPC processing table used in the first embodiment. FIG. 5 is a flowchart showing the design procedure of the first embodiment. FIG. 6 is a flowchart showing the design procedure of the second embodiment. FIG. 7 is a flowchart showing the design procedure of the third embodiment. FIG. 8 is a flowchart showing the design procedure of the fourth embodiment.

Explanation of symbols

51 layout pattern data 52 OPC processing table 53 post-OPC pattern calculation means 54 comparison means for each pattern 55 element correction error calculation means 56 element parameter extraction means 57 netlist generation means

Claims (5)

A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating an OPC-processed pattern obtained by using a mask / reticle manufactured by performing the OPC process;
And a step of calculating an OPC correction error by comparing the post-OPC pattern with a pattern defined by the layout pattern data. A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating an OPC-processed pattern obtained by using a mask / reticle manufactured by performing the OPC process;
Comparing the post-OPC pattern and the pattern defined by the layout pattern data to calculate an OPC correction error;
Calculating a limit circuit element correction error in consideration of a limit value of an allowable range of the OPC correction error determined in the OPC process;
Extracting element parameters based on the limit circuit element correction error;
Performing an operation simulation of the integrated circuit based on the element parameters including the limit circuit element correction error;
Calculating the circuit element correction error in consideration of the OPC correction error for an unfavorable portion when the operation simulation is not good;
Extracting element parameters based on the circuit element correction error;
And a step of performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error. A method for designing an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculating a limit circuit element correction error in consideration of a limit value of an allowable range of the OPC correction error determined in the OPC process;
Extracting element parameters based on the limit circuit element correction error;
Performing an operation simulation of the integrated circuit based on the element parameters including the limit circuit element correction error;
Calculating a post-OPC process pattern obtained by using a mask / reticle manufactured by performing the OPC process on an unsatisfactory part when the operation simulation is not good;
Comparing the post-OPC pattern and the pattern defined by the layout pattern data to calculate an OPC correction error;
Calculating a circuit element correction error in consideration of the OPC correction error;
Extracting element parameters based on the circuit element correction error;
And a step of performing an operation simulation of the integrated circuit based on the element parameter including the circuit element correction error. An integrated circuit design apparatus manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Means for calculating a post-OPC pattern obtained by using a mask / reticle manufactured by performing the OPC process;
An integrated circuit design apparatus comprising: means for calculating an OPC correction error by comparing the post-OPC pattern and a pattern defined by the layout pattern data. A program for causing a computer to design an integrated circuit manufactured using a mask / reticle manufactured by performing an OPC process on a pattern defined by layout pattern data,
Calculate a pattern after OPC processing obtained by using a mask / reticle manufactured by performing the OPC processing,
A program characterized in that an OPC correction error is calculated by comparing the post-OPC pattern with a pattern defined by the layout pattern data.

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