JP2009026045A - Layout creating device and manufacturing method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout creation device and a manufacturing method for a semiconductor circuit for preventing occurrence of a pseudo error in checking a design rule due to coexistence of an actual circuit pattern and a dummy pattern in a layout pattern for performing an accurate and reliable design rule check on the actual circuit pattern. <P>SOLUTION: The layout creation device is provided with an actual circuit pattern recognition part 41 for recognizing an actual circuit pattern from finished layout patterns; a layer change part 42, which distributes data of the actual circuit pattern to a layer dedicated to actual circuit pattern data and distributes data of other patterns to another layer, a DRC execution part 70 for performing DRC to collate and confirm whether a predetermined design rule is satisfied or not on the data distributed to the layer dedicated to the actual circuit pattern data and generating the result, and a data output part 200 outputting a check result by the DRC execution part 70. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit layout creation apparatus and a semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit based on data of a finish layout pattern including a dummy pattern.

  Patent Document 1, Patent Document 2, and Patent Document 3 propose a method for manufacturing a semiconductor device including a sidewall processing process. The sidewall processing process makes it possible to form a fine pattern that has been practically extremely difficult or impossible to achieve with a pattern forming technique based on photolithography. In general, the side wall processing process is that the side wall portion is made of a conductive material such as a metal conductor, and is used as at least a part of an actual circuit, or made of an insulating material or a high resistance material. In some cases, it is used as a spacer for ensuring insulation between adjacent wirings or between elements. In either case, a pattern used as an actual circuit (hereinafter referred to as an actual circuit pattern) is formed in the sidewall processing process, but the pattern does not directly affect the operation of the semiconductor integrated circuit during the sidewall processing process. (Hereinafter referred to as a dummy pattern) is also inevitably formed. The dummy pattern may be removed in the middle of the sidewall processing process, but may be left as it is because it is technically difficult to remove the portion where the distance between the actual circuit patterns is narrow.

  By the way, conventionally, in the design work of a large-scale semiconductor integrated circuit supported by a computer, the arrangement of elements on an integrated circuit is determined according to a logic circuit diagram or an electronic circuit diagram, which is called layout wiring design or layout design, and a wiring path between these elements Then, there is a drawing process for making a mask based on these. As is well known, layout verification is performed in layout design. This layout verification is to confirm the correctness of the design with respect to the drawing data (artwork data) for mask production at the final design stage.

  In this layout verification, verification called design rule check (hereinafter referred to as DRC) is performed. This is a step of verifying whether or not the drawing data violates a geometric design rule designed in consideration of various constraints obtained after considering the manufacturing process, that is, the design rule.

  More specifically, a DRC tool that is currently used generally uses a layout editor for layout data recorded in a data format called GDS (or GDS2) drawn on a CAD tool called a layout editor. In many cases, the DRC is set to be executed. Typical examples include Cracence DRC (product name) of Cadence (company name), Caliber DRC (product name) of Mentor Graphics (company name), and Hercules DRC (product name) of Synopsys (company name). These DRC tools are sold in the state of so-called semi-finished products so as to be compatible with the technology of each company and each generation, and the GDS number and layer name according to the company's technology in the CAD support department of each company. Generally, after the layer color and pattern are set, it is provided to the designer.

US Patent 6,063,688 US Patent 6,140,217 US Patent 6,475,891 JP 2000-124320 A JP 2006-286792 A

  However, in the typical DRC tool currently used generally as exemplified above, the existence of a dummy pattern that is inevitably formed during the side wall processing process, which is a new process, is not considered at all. For this reason, for example, the GDS data of the finished pattern obtained by simulating the sidewall processing process has no distinction whether it is a real circuit pattern or a dummy pattern if they are the same layer. Considering it as an actual circuit pattern, DRC will be executed for all of these patterns. This causes many pseudo errors. In general, since DRC tools generally perform graphic calculation processing on a large number of figures, calculation including unnecessary graphic data becomes a factor that requires an enormous amount of time for the original DRC. In addition, the output of a large number of pseudo errors occupies a large amount of memory and HDD capacity in the DRC tool, which may cause trouble in the layout verification work, and the true error becomes a pseudo error. It may be buried, making its detection difficult, and the reliability of the DRC itself may be impaired.

  The present invention eliminates the problem of occurrence of a pseudo error due to such a mixture of dummy patterns, and can perform accurate and reliable DRC on an actual circuit pattern without delay. And a method of manufacturing a semiconductor integrated circuit.

  A layout creation apparatus for a semiconductor integrated circuit according to an embodiment of the present invention includes a logic circuit diagram design unit that designs a logic circuit diagram of a semiconductor integrated circuit based on specification information, the logic circuit diagram, and the specification information. A layout design unit that creates data of a finished layout pattern formed by mixing a dummy pattern and an actual circuit pattern; an actual circuit pattern identifying unit that identifies the actual circuit pattern from the finished layout pattern; and the actual circuit pattern Are allocated to the layer dedicated to the actual circuit pattern data, and the pattern data other than the actual circuit pattern data is allocated to a layer different from the layer dedicated to the actual circuit pattern data, and the layer dedicated to the actual circuit pattern data. Based on the distributed data, A DRC execution unit that performs verification to confirm whether or not the actual circuit pattern that is generated satisfies a predetermined design rule, and generates a result thereof; and a data output unit that outputs a check result by the DRC execution unit; It is provided with.

  In addition, a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention designs a logic circuit diagram of a semiconductor integrated circuit based on specification information, and implements a dummy pattern and an actual pattern based on the specification information and the logic circuit diagram. Creating a finish layout pattern data mixed with the circuit pattern, identifying the actual circuit pattern from the finish layout pattern, distributing the actual circuit pattern data to the actual circuit pattern data dedicated layer, and the actual circuit The pattern data other than the pattern data is allocated to a layer different from the actual circuit pattern data dedicated layer, and the actual circuit pattern generated based on the data allocated to the actual circuit pattern data dedicated layer DR that checks whether or not the design rule satisfies the specified design rule The go to produce a result, and outputs the check result by the DRC process, characterized in that for producing a semiconductor integrated circuit based on the data of the finishing layout pattern.

  According to an embodiment of the present invention, a semiconductor integrated circuit capable of performing accurate DRC on an actual circuit pattern by solving the problem of generation of a pseudo error due to the mixture of dummy patterns in the DRC of the actual circuit pattern The layout creating apparatus and the semiconductor integrated circuit manufacturing method can be provided.

  Hereinafter, a semiconductor integrated circuit layout creating apparatus and a semiconductor integrated circuit manufacturing method according to an embodiment of the present invention will be described. However, the present invention is not limited to the following embodiment. Moreover, in one embodiment, the same code | symbol is attached | subjected about the same structure and it may not explain anew.

  FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit layout creating apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram partially showing an actual circuit pattern identifying unit, a layer changing unit, and a DRC executing unit in the semiconductor integrated circuit layout creating apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, the layout creation apparatus 20 according to the present embodiment includes a logic circuit diagram design unit 30, a layout design unit 40, a layout verification unit 50, and a data output unit 200 as main parts thereof. Yes.

  The logic circuit diagram design unit 30 first describes hardware with an abstraction level called RTL (Register Transfer Level) using a hardware description language based on the semiconductor integrated circuit specification information 10. Next, the logic circuit diagram design unit 30 synthesizes this description using a logic synthesis tool, and expands it to an abstraction level called a gate level (level described by the logic circuit). That is, logic circuit diagram data can be obtained as a result of logic synthesis. A net list can be generated from the data of this logic circuit diagram, and is generally output as a SPICE net list.

  The layout design unit 40 arranges elements on the integrated circuit based on the information of the logic circuit diagram designed by the logic circuit diagram design unit 30, and determines the wiring path between these elements, thereby creating a mask. Create layout data. This is called layout design. The created layout data is sent to the layout verification unit 50 to perform verification work, and when correction is required, the layout data is corrected again. This verification / correction operation is repeated until a predetermined design condition is satisfied. In order to create the above layout data, the layout design unit 40 has a layout data generation function.

  Further, as described above, since the layout data designed by the layout design unit 40 is verified by the layout verification unit 50, processing such as graphic logic operation is performed in the layout design unit 40 as pre-processing for the verification. Is applied to the layout verification unit 50. Further, as one of the characteristic functions in the preprocessing, an actual circuit pattern identification function and a layer change function are provided. These functions are executed by the actual circuit pattern identifying unit 41 and the layer changing unit 42 as shown in FIG. The actual circuit pattern identification unit 41 and the layer change unit 42 are both provided in the layout design unit 40.

  The layout verification unit 50 includes an LVS execution unit 60 and a DRC execution unit 70. The layout verification unit 50 receives the layout data created by the layout design unit 40, identifies the actual circuit pattern data identified as the actual circuit pattern from the layout data and distributed to the real circuit pattern data dedicated layer. Whether or not the actual circuit pattern generated based on the data satisfies the geometric design rules determined based on the constraints of the manufacturing equipment, etc. It is verified whether or not the connection is correctly realized by the layout design.

  Specifically, verification is performed mainly on LVS and DRC. That is, the layout verification unit 50 has a function of performing LVS and a function of performing DRC. The sharing of these functions is set so that the LVS execution unit 60 performs LVS and the DRC execution unit 70 performs DRC. Note that LVS (Layout Versus Schematic) is a process of verifying whether or not information on elements and connections between elements created in the logic circuit diagram design stage is correctly realized in the layout data.

  The LVS execution unit 60 performs LVS. Specifically, pre-processing such as graphic logic operation is performed in the layout design unit 40, and the gate-level connection information is restored from the layout data identified as the actual circuit pattern and distributed to the layer dedicated to the actual circuit pattern data. Furthermore, after the gate level connection information is converted into the transistor level connection information, whether or not the transistor level connection information matches the logic circuit diagram information, and further, between the element node and the element It is verified whether or not the potential information input to the node of the connection matches the information in the logic circuit diagram.

  The DRC execution unit 70 performs DRC as described above. Specifically, the layout design unit 40 performs real circuit pattern identification and layer change pre-processing, and the figure to be verified from the layout data identified as the real circuit pattern and distributed to the real circuit pattern data dedicated layer. Recognizing design rules (DRC rule 701) such as the width, the distance between two figures, and the standard value (allowable minimum / maximum interval value) of a margin when a certain figure is included in another figure, It is determined whether or not the figure width and space of the layout data satisfy the design rule. Then, the data of the error part that does not match is transmitted to the layout design unit 40. The layout design unit 40 corrects the layout of the error part and repeats the layout correction until there are no errors. In addition, the layout design unit 40 sends data holding the result of determining whether or not the graphic width and space of the layout data satisfy the design rule as described above to the data output unit 200. When the data is received, the data output unit 200 displays and outputs information such as the execution result report 201 and the error GDS output 202 (see FIG. 2) on the screen of the display device or the print device. The above is the DRC flow in the DRC execution unit 70. In order to perform such verification, the DRC execution unit 70 has a layout data recognition function and a DRC function.

  The data output unit 200 is created by the layout design unit 40, passes various LVS and DRC verifications by the layout verification unit 50, receives the completed layout data from the layout design unit 40, and outputs it as data outside the layout creation device 20. Output. In addition, information output such as the execution result report 201 and the error GDS output 202 (see FIG. 2) is displayed and / or printed. The error GDS output 202 is output by the error GDS output unit 203 shown in FIG.

  In addition, the data output unit 200 is identified by the actual circuit pattern identifying unit 41, and based on the actual circuit pattern data distributed to different layers by the layer changing unit 42 and other data, A finishing layout pattern display function for displaying patterns other than those in figures of different colors or patterns as illustrated in FIGS. 21, 22, and 23 is provided. 21 shows only the actual circuit pattern 801 extracted and displayed, FIG. 22 shows the finished layout pattern 901, and FIG. 23 shows the actual circuit pattern 801 and the dummy pattern 802 in different colors and patterns. Is displayed.

  The above is the schematic configuration of the semiconductor integrated circuit layout creating apparatus 20 according to an embodiment of the present invention. The most characteristic part of the layout creating apparatus 20 is particularly shown in FIG. It ’s like that. That is, the characteristic parts are the actual circuit pattern identification unit 41, the layer change unit 42, the DRC execution unit 70, and the error GDS output unit 203.

  The actual circuit pattern identification unit 41 uses the logic circuit diagram 301 sent from the logic circuit diagram design unit 30 to finish the dummy layout sent from the layout design unit 40 and the actual circuit pattern. A function of identifying an actual circuit pattern from the patterns is provided. The actual circuit pattern is identified by a method of tracing a pattern from one side terminals a and b as shown in FIG. 6A, or a pattern from both side terminals a and b as shown in FIG. This is performed by identifying, as an actual circuit pattern, a pattern that connects two or more input / output terminals in the finished layout pattern, such as a tracing method. In addition, each arrow line shown in FIGS. 6A and 6B indicates a direction in which the pattern is traced.

  The layer changing unit 42 distributes the data of the actual circuit pattern identified by the actual circuit pattern identifying unit 41 to the actual circuit pattern data dedicated layer, and the pattern data other than the actual circuit pattern data is the actual circuit pattern data dedicated layer. It has a function to distribute to different layers.

  The DRC execution unit 70 verifies whether or not the actual circuit pattern generated based on the data allocated to the actual circuit pattern data dedicated layer satisfies a predetermined design rule (DRC rule 701). It has a function to execute the DRC and generate the result. In the DRC execution unit 70, the actual circuit pattern is extracted by tracing the pattern as shown in FIG. 6 and the like, and the dummy pattern is obtained by graphic calculation processing using the actual circuit pattern and the finishing layout pattern. Here, an example of the graphic calculation processing is illustrated in FIGS. The DRC execution unit 70 performs DRC on the graphic data of the dummy pattern obtained by performing the graphic operation processing illustrated in FIGS. 7A to 7E. Here, the graphic calculation processing shown in FIG. 7A forms a dummy pattern graphic C from the logical sum of graphic A and graphic B. 7B forms a dummy pattern figure C from the logical product of the figure A and the figure B. FIG. The graphic calculation process of FIG. 7C is to remove the logical product of the graphic A and the graphic B from the graphic A to form a dummy pattern graphic C. In addition, in the figure calculation process of FIG. 7D, a predetermined dimension X is added to each of the vertical and horizontal dimensions so that the figure A is enlarged at a desired enlargement ratio (or the same size as when enlarged at the enlargement ratio). The figure B is formed. Further, in the graphic calculation processing of FIG. 7E, the predetermined dimension y is subtracted from the vertical and horizontal dimensions so that the graphic A is reduced at a desired reduction ratio (or the same size as when the graphic A is reduced at the reduction ratio). A) A figure B is formed.

  If an error is detected as a result of the check by the DRC execution unit 70, the error GDS output unit 203 outputs information on the error GDS by display output, print output, or both.

  FIG. 3 is a flowchart showing an example of a series of processes for creating layout data in the layout data creating method according to the embodiment of the present invention. The layout data verification process performed by the layout creating apparatus 20 for the semiconductor integrated circuit according to the configuration shown in FIGS. 1 and 2 will be mainly described with reference to FIG.

  First, the designer determines the specifications of the semiconductor integrated circuit (semiconductor integrated circuit specification information 10) (step S101).

  Next, the designer designs a logic circuit diagram using the logic circuit diagram design unit 30 based on the semiconductor integrated circuit specification information 10 determined in step S101 (step S102).

  Next, the layout design unit 40 creates layout data based on the logic circuit diagram designed in step S102 (step S103).

  Subsequently, in the layout design unit 40, as preprocessing for executing LVS and DRC, preprocessing such as identification of an actual circuit pattern and layer change is performed based on the layout data created in step S103. That is, the real circuit pattern identification unit 41 identifies the real circuit pattern from the layout pattern, and the layer change unit 42 distributes the data of the real circuit pattern to the layer dedicated to the real circuit pattern data, and other than the real circuit pattern data. The pattern data is assigned to a layer different from the actual circuit pattern data dedicated layer (step S104).

  After the preprocessing in step S104, LVS processing (steps S105 to S106), DRC processing (steps S107 to S108), and subsequent layout correction processing (steps S109 to S110) are performed. After the description, DRC and subsequent layout correction processing will be described.

  The LVS execution unit 60 executes LVS. Specifically, the gate-level connection information is restored from the layout pattern, and the gate-level connection information is converted into transistor-level connection information. It is checked whether or not the information matches, and further whether or not the potential information input to the element node and the connection node between the elements matches the logic circuit diagram information (step S105).

  As a result of the LVS in step S105, if the transistor level connection information and the logic circuit diagram information completely match, the LVS execution unit 60 determines that there is no error in the layout data (step S106: No). ), And reports the determination result (step S111). This report is transmitted to the layout design unit 40. The layout design unit 40 corrects the layout by combining the report of the DRC verification result executed by the DRC execution unit 70 in steps S107 to S108 described later and the report.

  On the other hand, if the result of LVS in step S105 shows that the transistor level connection information and the logic circuit diagram information do not match at all, the LVS execution unit 60 determines that there is an error location in the layout data (step S105). (S106: Yes), the error part is reported to the layout design unit 40 (step S109).

  Next, the layout data is corrected by the layout design unit 40 for the portion reported as an error by the LVS execution unit 60 as a result of the LVS. At this time, the determination result by the DRC performed in steps S107 to S108 described later Together with the report, a necessary correction is made (step S110). For the layout data with this modification, the LVS execution unit 60 executes the LVS in steps S105 to S106 again. Further, the DRC execution unit 70 repeatedly executes DRC in steps S107 to S108 based on the corrected layout data. The LVS in step S105 to step S106, the DRC in step S107 to step S108, and the subsequent layout correction work in step S109 to step S110 are performed until the error location is not detected in step S106 and step S108. The LVS execution unit 60 and the DRC execution unit 70 execute iteratively.

  In parallel or continuously with the above LVS, the DRC execution unit 70 executes DRC.

  First, in step S104, in the layout design unit 40, pre-processing such as identification of actual circuit patterns and layer change is performed, the identification is made as an actual circuit pattern, and is distributed to an actual circuit pattern dedicated layer. The graphic data such as the wiring width and interval (line and space) of the actual circuit pattern extracted as is sent to the DRC execution unit 70. The DRC execution unit 70 performs DRC and verifies whether or not the graphic data satisfies the allowable minimum value and the allowable maximum value determined by the design rule (step S107).

  When the DRC is performed and the values such as the width and interval (line and space) of all the wirings in the graphic information extracted from the layout data satisfy the design rule, the DRC execution unit 70 adds the design rule to the layout data. It is determined that the violated error portion does not exist (step S108: No), and is transmitted to the layout design unit 40 as a report indicating that the layout data satisfies the design rule.

  Upon receiving the report indicating that the layout data satisfies the design rule, the layout design unit 40 comprehensively determines the result and the results of the LVS in steps S105 and 106, and no error is detected in any of them. In this case, it is determined that the layout data has been completed (step S108: No to step S111), and the layout data is transmitted to the data output unit 200. The data output unit 200 outputs the determination result by displaying or printing out the completed layout data on the display device (step S112), and ends the series of DRCs (step S113).

  On the other hand, as a result of DRC, if there is a value that does not satisfy the design rule among values such as the width and interval (line and space) of each wiring in the graphic information extracted from the layout data, the layout design unit 40 Determines that there is an error location that violates the design rule in the layout data (step S108: Yes), and outputs a report indicating the error location to the layout design unit 40 (step S109).

  Next, as a result of the DRC, the layout design unit 40 modifies the layout data for the part that the DRC execution unit 70 reported as an error. At this time, the layout design unit 40 performs the process in steps S105 to S106 described above. The overall determination is made together with the LVS determination result report, and necessary corrections are made (step S110). The DRC execution unit 70 executes the DRC of step S107 and step S108 again for the layout data with this modification. The DRC from step S107 to step S108 and the subsequent layout correction operation from step S109 to step S110 are repeatedly performed by the layout design unit 40 and the DRC execution unit 70 until no error location is detected in step S108.

  The above is a schematic series of the flow of the layout creation method according to the embodiment of the present invention. The most characteristic process in such a layout creation method is particularly after the layout design process shown in FIG. Are included in the pre-processing and DRC as shown in FIG.

  That is, prior to the preprocessing and DRC in FIG. 5, first, as shown in FIG. 4, a logic circuit is designed based on the determined semiconductor integrated circuit specification information 10, and an actual circuit pattern of the finished layout pattern is set. A resist pattern corresponding to the assumption is designed (step S401). This process is performed by the logic circuit diagram design unit 30 and the layout design unit 40.

  Subsequently, the designed resist pattern is subjected to graphic operation processing as schematically shown in FIG. 7 to create a layout pattern including a dummy pattern (step S402). Then, a loop cut is performed to obtain a finished layout pattern (step S403). A pattern such as a terminal and a contact corresponding to the logic circuit diagram 301 is further arranged in the finishing layout pattern, and at the same time, a terminal name corresponding to the logic circuit diagram 301 is given to the pattern (step S404). The process so far is mainly performed by the layout design unit 40. Also included in steps S101 to S103 in the overall flow shown in FIG.

  The created finish layout pattern 901 (see FIG. 2) is input to the actual circuit pattern identification unit 41 in the layout design unit 40. As shown in FIG. 5, the actual circuit pattern identification unit 41 first extracts the terminal name and the connection information between the terminals from the logic circuit diagram 301 (step S501), and based on the obtained connection information, A portion having a corresponding connection relationship on the finishing layout pattern is determined as an actual circuit pattern, and the other pattern is determined as a dummy pattern (a pattern that does not substantially constitute an actual circuit) (step S502). Alternatively, using an LVS tool that basically has a function of verifying whether a layout pattern can be drawn as shown in the circuit diagram 301, a path on the layout pattern traced by the LVS tool is set as an actual circuit. There is also a way to identify. However, since this method cannot be executed unless the output result of the LVS tool holds information on which node on the layout pattern is traced, such node and path information is required. This process is included in step S104 in the overall flow shown in FIG.

  Subsequently, the pattern data determined as the actual circuit pattern is distributed to the actual circuit pattern dedicated layer by the layer changing unit 42. Further, the dummy patterns other than the actual circuit pattern data are allocated to a dummy pattern dedicated layer different from the actual circuit pattern dedicated layer (step S503). In order to make it easy for designers to distinguish between the two layers at the time of work, for example, a layer name such as “metal” or a layer number “10” is given to the real circuit pattern dedicated layer, and “dummy” The layer name or the layer number “20” or the like may be assigned so that the two layers can be clearly distinguished. These pattern data are all in the same format as the data format used in the design / verification system, such as in the GDS2 format when design and DRC are performed in a design system in the GDS2 format, for example. Of course, it is desirable. This process is included in step S104 in the overall flow shown in FIG.

  Then, the DRC execution unit 70 performs DRC on the distributed two layers (real circuit pattern dedicated layer and dummy pattern dedicated layer) based on the DRC rule 701 (step S504). At this time, for the actual circuit pattern and the dummy pattern, based on the DRC rule as illustrated in FIG. 19, the width check, the interval check, the inclusion distance check, etc. as illustrated in FIG. 20, DRC for each item is performed. This process is included in step S107 in the overall flow shown in FIG.

  Here, an example of FIGS. 19 and 20 will be described. In the DRC rule, check contents corresponding to the real circuit pattern dedicated layer and the dummy pattern dedicated layer are described. At the stage of executing the DRC, the already finished layout pattern is distributed to the real circuit pattern dedicated layer and the dummy pattern dedicated layer different from that, so the DRC is executed for each of these layers. Briefly explaining the description example of the DRC rule in FIG. 19, 1-1 defines a minimum wiring width (so-called line width) of an actual wiring pattern, and an actual wiring pattern less than this wiring width causes a DRC error. 2-2 defines the minimum interval (so-called space) between the actual wiring patterns, and a DRC error occurs when the interval between the adjacent wirings is less than b2 in a portion where the width is greater than a1 and less than a2. Become. 3-2 defines the minimum space between the actual wiring pattern and the dummy pattern, and when the corresponding portion of the wiring pattern having a width larger than A1 and smaller than A2 is less than B2, the interval between the adjacent dummy patterns is less than B2. Becomes a DRC error.

  Subsequently, when it is detected that there is a DRC error as a result of performing the DRC as described above, the error GDS output unit 203 in FIG. For example, display output is performed on the display screen, or printing is performed by the printing apparatus (step S505). If no error is detected, the data is output assuming that the layout data is complete. This process is included in Yes to S109 of Step S108 or No to Step S112 of Step S108 in the overall flow shown in FIG.

  According to the semiconductor integrated circuit layout creation apparatus and semiconductor integrated circuit manufacturing method according to an embodiment of the present invention as described above, the actual circuit pattern is identified from the finished layout pattern, and the data of the actual circuit pattern is implemented. In addition to allocating to the circuit pattern data dedicated layer, other pattern data is allocated to a layer different from the actual circuit pattern data dedicated layer, and DRC of the actual circuit pattern is applied to the data allocated to the actual circuit pattern data dedicated layer. Therefore, it is possible to solve the problem of the occurrence of a pseudo error due to the mixture of dummy patterns in the DRC of the actual circuit pattern, and to perform accurate DRC on the actual circuit pattern.

  Here, as a comparative example, a case where a conventional general DRC tool is used for a side wall processing process will be considered. In the conventional general technique, there are several methods for verification using different design rules for each layout pattern. For example, a technique proposed in Japanese Patent Application Laid-Open No. 2006-286792 is a technique for applying design rules in accordance with different operating voltages on the layout. This is to determine whether or not the element is a high voltage element by a layer or a combination of layers, and execute DRC for a high voltage element at the corresponding location. However, since the actual layout pattern and the dummy pattern are mixed in the same layer, the finish layout pattern in the side wall processing process assumed by the present invention cannot be distinguished from each other by this method. It is not possible to perform dedicated DRC for an actual circuit pattern such as the method and apparatus according to the above, or perform dedicated DRC for a dummy pattern.

  In the technique proposed in Japanese Patent Laid-Open No. 2000-124320, a high voltage application portion on a layout pattern is identified using a circuit diagram, and a dummy layer is applied to the corresponding portion. Then, in the side wall process, it is necessary to distinguish the actual circuit pattern in advance, and since an extra dummy layer is automatically stretched, the number of graphic operations in DRC is further increased, and the DRC execution time is further increased. There is a risk of causing. In addition, there are various inconveniences such as a further increase in the data size of the layout pattern due to the automatic extension of the dummy layer, which is not preferable.

  Here, more specifically, a main flow of a manufacturing method of a semiconductor device (semiconductor integrated circuit or the like) as hardware including a sidewall processing process will be briefly described. 9 to 12 are plan views showing an example of a layout pattern (including a resist pattern) used in a series of manufacturing processes when the finishing layout pattern having the sidewall pattern shown in FIG. FIG. 13 is a plan view schematically showing DRC performed for the finishing layout pattern. 14 to 17 show an example of a layout pattern (including a resist pattern) used in a series of manufacturing processes when the finishing layout pattern having the sidewall pattern shown in FIG. 8 is formed with the sidewall portion as an insulator. FIG. 18 is a plan view schematically showing DRC performed for the finishing layout pattern.

  FIG. 24 and FIG. 25 show a series of semiconductor device manufacturing processes in which the side wall portion is left as a wiring by patterning the side wall into a conductive material such as a metal material. Show. FIG. 26 and FIG. 27 show a series of cases in which the sidewall is patterned into an insulating material, and a conductive material such as a metal material is embedded between the insulating materials to form a wiring. 2 shows a manufacturing process of a semiconductor device.

  When the side wall portion is left as a wiring, as shown in FIG. 24, first, a core material 621 is formed on a silicon substrate 600 in which a conductive layer is formed on an insulating layer (FIG. 24A); (B): Plan view). Subsequently, the core material 621 is slimmed to form the core material 601 (FIG. 24 (c); sectional view, (d); plan view). Needless to say, it is not necessary to use a photomask or the like in this slimming process. However, the side wall core material 601 formed by slimming the core material 621 shown in FIG. 9 is, for example, as shown in FIG. Further, the pattern 601 is further thinned. Note that “register2” illustrated in FIG. 10 indicates the pattern 601. Subsequently, a side wall 602 is formed on the side surface of the slimmed core material 601 (FIG. 24E; cross-sectional view, (f); plan view, and FIG. 11). A sidewall material layer is deposited on the sidewall 602 by using, for example, CVD (Chemical Vapor Deposition). Then, the sidewall material layer is formed by anisotropic etching by a dry etching method. Here, in FIG. 11, a portion that is loop-cut in a later process is shown by being surrounded by a dotted line and a reference numeral 622. Note that “sokuheki” shown in FIG.

  Subsequently, as shown in FIG. 25, the core member 601 is removed while leaving the side wall 602 (FIG. 25 (a); sectional view, (b); plan view, and FIG. 12 (a)). Then, by etching the silicon substrate 600 to a predetermined depth (thickness) using the side wall 602 as a mask, a portion of the silicon substrate 600 remaining under the side wall 602 becomes a wiring pattern 603 (FIG. 25 (FIG. 25). c); sectional view, (d); plan view). Thereafter, the side wall 602 on the wiring pattern 603 is removed, and the main part of the wiring of this semiconductor device is formed (FIG. 25 (e); sectional view, (f); plan view). Here, in FIG. 8, FIG. 12, and FIG. 13, the pattern of the signal wiring terminal is indicated by reference numeral 623. The finished layout pattern corresponding to the actual pattern of the wiring and dummy pattern shown in FIG. 12B formed as described above is as shown in FIG. In the finished layout pattern, the actual circuit pattern and the dummy pattern are identified by the actual circuit pattern identifying unit 41 based on the connection relationship between the pattern and the signal wiring terminal 623, thereby FIG. As schematically shown in FIG. 5, the real circuit pattern 603 is assigned to the real circuit pattern dedicated layer (metal layer), and the dummy pattern 632 is assigned to the dummy pattern dedicated layer (dummy layer). As schematically shown in FIG. 13, various spaces such as a space 633 between the actual circuit patterns 603, a space 634 between the actual circuit pattern 603 and the dummy pattern 632, a line width 635 of the actual circuit pattern 603, and the like. The DRC for the check item is accurately performed by the DRC execution unit 70 without causing misrecognition or the like due to the mixture of the actual circuit pattern 603 and the dummy pattern 632.

  Alternatively, when the sidewall portion is patterned into an insulator and wiring is formed between the insulators, as shown in FIG. 26, first, a core material is formed on a silicon substrate 600 having an insulating layer formed on the surface. 621 is formed (FIG. 26 (a); sectional view, (b); plan view). Subsequently, the core material 621 is slimmed to form the core material 601. The relationship between the core material 621 and the core material 601 of the slimmed side wall is, for example, that the pattern 621 shown in FIG. 14A is slimmed to form a thinned pattern 601 shown in FIG. 14B. Subsequently, a side wall 602 is formed on the side surface of the core material 601 (FIG. 26 (c); sectional view, (d); plan view, and FIG. 15 (a)). The formation process of the side wall 602 is the same as that in the case of patterning the side wall portion as a wiring. Subsequently, the core member 601 is removed leaving the side wall 602 (FIG. 26 (e); sectional view, (f); plan view, and FIG. 15 (b)).

  Then, as shown in FIG. 27, the silicon substrate 600 is etched to a predetermined depth (thickness) using the side wall 602 as a mask (FIG. 27 (a); sectional view, (b); plan view). . The portion of the silicon substrate 600 remaining under the side wall 602 becomes the second side wall 605. After that, a conductive material 636 such as Cu (copper) is embedded between the adjacent side walls 602 and 605 (FIG. 27E; sectional view, FIG. 27D; plan view). Then, planarization polishing is performed (FIG. 27E; cross-sectional view, (f) plan view, and FIG. 16A). The wiring 603 is obtained after identifying the actual circuit pattern and the dummy pattern for the figure (FIG. 16B) subjected to the loop cut (FIG. 17). In this way, the main part of the wiring of this semiconductor device is formed. Here, in FIG. 17, the portion remaining as the dummy pattern is shown with the same hatching as that of the conductive material 636 shown in FIG. Further, the signal wiring terminal pattern is indicated by reference numeral 623. In the finished layout pattern having the real circuit pattern 603 and the dummy pattern 636 shown in FIG. 17 formed as described above, the real circuit pattern 603 and the dummy pattern 636 are identified with each of the patterns 603 and 636 and signals. Based on the connection relationship with the wiring terminal 623, the actual circuit pattern identification unit 41 performs the distribution of the actual circuit pattern 603 to the actual circuit pattern dedicated layer (metal layer) as schematically illustrated in FIG. The dummy pattern 636 is distributed to a dummy pattern dedicated layer (dummy layer). As schematically illustrated in FIG. 18, various spaces such as a space 633 between the actual circuit patterns 603, a space 634 between the actual circuit pattern 603 and the dummy pattern 636, a line width 635 of the actual circuit pattern 603, and the like. The DRC for the check item is accurately performed by the DRC execution unit 70 without causing misrecognition or the like due to the mixture of the actual circuit pattern 603 and the dummy pattern 636.

  In the semiconductor device manufacturing method according to the layout creation method according to the embodiment of the present invention, a pattern based on the layout data may be directly drawn on the substrate by a processing apparatus such as an electron beam.

  In addition, according to the method for manufacturing a semiconductor device by the layout creation method according to the embodiment of the present invention, accurate DRC is performed even in the case of a semiconductor device manufactured by a manufacturing method including a sidewall processing process. Since highly reliable layout data can be created, the reliability, yield, and throughput of the semiconductor device can be improved. As a result, the effect of shortening the product development period and reducing the product development cost can be obtained.

  In the above embodiment, the case where the present invention is applied to the layout creating apparatus 20 is illustrated. However, the series of processes shown in the flowcharts of FIGS. 3 to 5 is programmed, and the program is executed in a general-purpose computer system. You may make it perform. That is, in a computer system composed of a CPU (Central Processing Unit), an I / O, a display device, a storage device, and the like, a program including the above-described series of processes is stored in the storage device, and the CPU is stored in the storage device. Accordingly, the present invention may be realized by executing a series of processes shown in the flowcharts of FIGS. The program including the series of processes may be stored in a portable storage medium. That is, in a computer system having a drive device for driving a storage medium, the storage medium is set in the drive device, and the CPU expands the program stored in the storage medium in the internal memory, and the above-described programs shown in FIGS. The present invention may be realized by executing a series of processes shown in the flowchart.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit layout creation device according to an embodiment of the present invention; FIG. 3 is a block diagram partially extracting and showing an actual circuit pattern identification unit, a layer change unit, and a DRC execution unit in the semiconductor integrated circuit layout creation device according to the embodiment of the present invention. It is a flowchart which shows an example of a series of processes which produce the layout data in the layout data creation method concerning one Embodiment of this invention. It is a figure which shows the main flows of the layout design process which concerns on one Embodiment of this invention. It is a figure which extracts and shows the characteristic process in the layout creation method which concerns on one Embodiment of this invention. It is a figure which shows typically an example of the identification method of the real circuit pattern which concerns on one Embodiment of this invention. It is a figure which shows typically an example of the figure calculation process which concerns on one Embodiment of this invention. It is a figure which shows the finishing layout pattern which has a side wall pattern which concerns on one Embodiment of this invention. It is a figure which shows the pattern of the core material of the side wall which concerns on one Embodiment of this invention. It is a figure which shows the pattern after the slimming of the core material of the side wall which concerns on one Embodiment of this invention. It is a figure which shows the pattern of the core of the side wall which concerns on one Embodiment of this invention, a side wall, and a loop cut layer. It is a figure which shows the pattern of the step which removed the core of the side wall concerning one Embodiment of this invention, and identified the pattern of an actual circuit and a dummy. It is a figure which shows typically DRC of the real circuit pattern which concerns on one Embodiment of this invention, and DRC of a dummy pattern. It is a figure which shows the change of the pattern width before and behind slimming which concerns on one Embodiment of this invention. It is a figure which shows the process which removes the core material which concerns on one Embodiment of this invention, and leaves a side wall. It is a figure which shows the process of Cu embedding and side wall removal, and loop cut based on one Embodiment of this invention. It is a figure which shows typically the recognition process of the terminal arrangement | positioning and actual wiring which concern on one Embodiment of this invention. It is a figure which shows typically DRC which concerns on one Embodiment of this invention. It is a figure which shows the example of a description of the DRC rule which concerns on one Embodiment of this invention. It is a figure which shows typically an example of DRC which concerns on one Embodiment of this invention. It is a figure which shows an example of the display output which extracted and displayed only the actual circuit pattern 801 which concerns on one Embodiment of this invention. It is a figure which shows an example of the display output which displayed the finishing layout pattern 901 which concerns on one Embodiment of this invention. It is a figure which shows an example of the display output which displayed the actual circuit pattern and dummy pattern which concern on one Embodiment of this invention with a different color tone and pattern. It is a figure which shows a series of manufacturing processes in the case of patterning the side wall part which concerns on one Embodiment of this invention as wiring. FIG. 25 is a diagram showing a series of manufacturing processes in the case where the side wall portion is patterned as a wiring following FIG. 24. The side wall part which concerns on one Embodiment of this invention is patterned into an insulator, and a series of manufacturing processes in the case of embedding a conductive material such as a metal material between the insulators to form a wiring are shown. FIG. FIG. 27 is a diagram illustrating a series of manufacturing processes in the case where the side wall portion is patterned into an insulator, and a conductive material such as a metal material is embedded between the insulators to form a wiring, following FIG. 26. is there.

Explanation of symbols

20 layout creation device 30 logic circuit diagram design unit 40 layout design unit 41 actual circuit pattern identification unit 42 layer change unit 50 layout verification unit 60 LVS execution unit 70 DRC execution unit 200 data output unit 203 error GDS output unit

Claims (5)

A logic circuit diagram design unit for designing a logic circuit diagram of a semiconductor integrated circuit based on the specification information;
Based on the logic circuit diagram and the specification information, a layout design unit that creates finish layout pattern data in which dummy patterns and actual circuit patterns are mixed,
An actual circuit pattern identifying unit for identifying the actual circuit pattern from the finishing layout pattern;
The real circuit pattern data is distributed to the real circuit pattern data dedicated layer, and the pattern change data other than the real circuit pattern data is assigned to a layer different from the real circuit pattern data dedicated layer,
DRC is performed on the data allocated to the real circuit pattern data dedicated layer to check whether the actual circuit pattern generated based on the data satisfies a predetermined design rule, and the result is generated. A DRC execution unit that
A semiconductor integrated circuit layout creation device, comprising: a data output unit that outputs a check result by the DRC execution unit.   2. The layout creation of a semiconductor integrated circuit according to claim 1, wherein the actual circuit pattern identifying unit identifies a pattern connecting two or more input / output terminals in the finishing layout pattern as the actual circuit pattern. apparatus.   The DRC execution unit performs the design rule check on the graphic data of the dummy pattern obtained by performing graphic calculation processing using the real circuit pattern from the graphic data of the real circuit pattern and the finishing layout pattern. 3. The semiconductor integrated circuit layout creating apparatus according to claim 1, wherein the layout creating apparatus is performed.   Based on the actual circuit pattern data identified by the actual circuit pattern identification unit and distributed to different layers and the other data, the actual circuit pattern and the other pattern are different in tone or pattern from each other. 4. The semiconductor integrated circuit layout creating apparatus according to claim 1, further comprising a finish layout pattern display unit for displaying the figure as a figure. Design the logic circuit diagram of the semiconductor integrated circuit based on the specification information,
Based on the specification information and the logic circuit diagram, create data of a finishing layout pattern in which a dummy pattern and an actual circuit pattern are mixed,
Identifying the actual circuit pattern from the finishing layout pattern;
The real circuit pattern data is distributed to the real circuit pattern data dedicated layer, and the pattern data other than the real circuit pattern data is distributed to a layer different from the real circuit pattern data dedicated layer,
DRC is performed on the data allocated to the real circuit pattern data dedicated layer to check whether the actual circuit pattern generated based on the data satisfies a predetermined design rule, and the result is generated. And
Output the check result by the DRC process,
A method of manufacturing a semiconductor integrated circuit, comprising manufacturing a semiconductor integrated circuit based on the data of the finishing layout pattern.