JP2007199234A - Method and device for designing photomask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and a device for designing photomask that make it possible to manufacture a semiconductor device having more excellent characteristics than before. <P>SOLUTION: A control section 11 designs a layout of unit cells in a unit cell developing stage 16 and makes OPC corrections. In a functional block developing stage 17, a layout of functional blocks is designed by using data of the unit cells developed in the unit cell developing stage and OPC corrections are made. In a chip designing stage, a layout of the whole semiconductor chip is designed by using data of the functional blocks developed in the functional block developing stage and OPC corrections are made. Layout data of the semiconductor chip developed in the chip designing stage are converted into data for photomask manufacture, which are output to a tape through a tape output section 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a photomask design method and design apparatus (CAD: Computer Aided Design) used in the manufacture of semiconductor devices and the like, and in particular, a photomask design method for performing optical proximity effect correction (Optical Proximity effect Correction) and It relates to a design device.

  FIG. 1 is a flowchart showing a device design process (pattern design process) performed at the time of designing a photomask (reticle) used for manufacturing a semiconductor device (LSI) and a subsequent LSI manufacturing process. In the device design process, as shown in FIG. 1, a unit cell development process (step S1) for developing a unit cell used for a desired electronic circuit (pattern design), and a pass / fail judgment (OK or OK) of the developed unit cell. NG) function determination step (step S2), function block development step (step S3) for developing a function block (pattern design) composed of one or a plurality of unit cells using unit cell data, A function determination step (step S4) for determining pass / fail of the developed function block, and a chip design step (step S5) for pattern design of the entire semiconductor chip composed of one or a plurality of function blocks using the data of the function block And the function determination process (step S6) which performs the pass / fail determination of chip design is implemented in order. Next, the process proceeds to a mask manufacturing process, and optical proximity effect correction (hereinafter referred to as OPC correction) is performed on the pattern of the entire semiconductor chip in step S7.

  Thereafter, the process proceeds to step S8 to produce a photomask, and in step S9, the pass / fail of the photomask is determined. If it is determined in step S9 that the state of the manufactured photomask is good (in the case of OK), the process proceeds to step S10, and if it is determined that the state of the manufactured photomask is not good (in the case of NG), step S7 is performed. Or it returns to step S8 and manufactures a photomask again.

  In step S10, a wafer process is performed using the manufactured photomask to manufacture a semiconductor device (LSI). Thereafter, in step S11, whether the manufactured LSI is acceptable or not is determined. If it is determined that the manufactured LSI is not in good condition (NG), the process returns to step S1, step S3, step S4, or step S7.

  As shown in the flowchart of FIG. 1, when it is determined that the desired function cannot be obtained in the function determination process (step S2) for determining whether the unit cell is acceptable or not (in the case of NG), the unit cell development process (step S1). ) And redo the unit cell development. Similarly, if it is determined that the desired function cannot be obtained in the function determination step (step S4) for determining whether or not the function block is acceptable (NG), the function block is returned to the function block development step (step S3). When it is determined that the desired function cannot be obtained (in the case of NG) in the function determination process (step S6) for determining whether the chip design is acceptable or not, the process returns to the chip design process (step S5) and the semiconductor chip Redo design.

  FIG. 2 is a flowchart showing details of the unit cell development process. As shown in FIG. 2, in the unit cell development process, a logic design process (step S21) for performing logic design of the unit cell, a function determination process (step S22) for determining whether or not the logic design is accepted, and the logic of the unit cell. A circuit design process (step S23) for performing circuit design based on the design, a function determining process (step S24) for determining whether the circuit design is acceptable, and a layout design for each element constituting the unit cell based on the circuit design. Layout design process (step S25), physical verification process (step S26) for performing physical verification (DRC (Design Rule Check) and ERC (Electrical Rule Check)) based on layout design, and function determination process after physical verification (step S26) Step S27) is performed in order.

  If it is determined that the desired function cannot be obtained (in the case of NG) in the function determination step (step S22) for determining whether the logic design is acceptable or not, the logic design is performed again by returning to the logic design step (step S21). Similarly, when it is determined that a desired function cannot be obtained (in the case of NG) in the function determination step (step S24) for determining whether the designed circuit is acceptable or not, the process returns to step S23 to perform circuit design again. If it is determined that the desired function cannot be obtained (in the case of NG) in the function determination step (step S27) for determining whether the layout has been accepted or not, the layout design is performed again by returning to step S25.

  In the functional block development process (step S3) and the chip design process (step S5) in FIG. 1, as in the unit cell development process shown in FIG. 2, a logic design process (step S21), a function determination process (step S22), A circuit design process (step S23), a function determination process (step S24), a layout design process (step S25), a physical verification process (step S26), and a function determination process (step S27) are sequentially performed.

Patent Document 1 aims to efficiently extract mask patterns to be subjected to OPC correction, classify mask patterns according to the shape and positional relationship of each mask pattern, and then perform OPC correction on each classified mask pattern. It is described to do. Patent Document 2 discloses a verification method and a verification apparatus for verifying whether or not an OPC corrected pattern is appropriate.
JP 2000-162758 A JP 2005-157043 A

  However, the present inventors consider that the conventional photomask design method described above has the following problems.

  Conventionally, as shown in the flowchart of FIG. 1, the pass / fail determination of the chip design is performed in the function determination process (step S6), and the OPC correction is performed in the mask manufacturing process for the pattern on the entire surface of the semiconductor chip determined to be “OK”. is doing. In this case, the device designer does not image the figure corrected by the OPC correction, and only performs physical verification (DRC and ERC) based on the design rule created by feedback from the process process. Pass / fail judgment is performed.

  In recent years, there has been a demand for higher integration and higher functionality of semiconductor devices, and accordingly, further miniaturization of photomask patterns has been required. However, in the conventional method, since the OPC correction is performed after the device design process is completed, the characteristics of the transistor and the like may change from the characteristics at the time of design.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a photomask design method and design apparatus that can manufacture a semiconductor device having better characteristics than conventional ones.

  According to one aspect of the present invention, a unit cell development process for creating a unit cell layout diagram used in an electronic circuit, and a functional block layout diagram using the unit cell layout diagram created in the unit cell development process. A functional block development process to create, and a chip design process to create a layout diagram of the semiconductor chip using a layout diagram of the functional block created in the functional block development process, and in the chip design process, There is provided a photomask design method for performing optical proximity effect correction on a layout diagram and generating photomask production data based on the corrected layout diagram.

  In the present invention, at least in the chip design process, optical proximity effect correction is performed on the layout diagram of the semiconductor chip. As a result, the device designer can grasp the layout diagram corrected for the optical proximity effect, and the device design can be performed in consideration of changes in the characteristics of elements such as transistors or circuits due to the optical proximity effect correction. As a result, it is possible to manufacture a semiconductor device having even better characteristics than in the past.

  The optical proximity effect correction is preferably performed not only in the chip design process but also in the unit cell development process and the functional block development process. As a result, the design of the photomask with optical proximity effect correction is made efficient. However, since the pattern of the peripheral part of the unit cell is affected by other adjacent unit cells or wiring, the peripheral part of the unit cell is set as a recalculation area in the functional block process, and the optical proximity effect of the functional block is set. When correction is performed, it is preferable to correct the optical proximity effect also in the recalculation area. For the same reason, in the chip design process, when the peripheral portion of the functional block is set as the recalculation area and the optical proximity effect correction of the entire semiconductor chip is performed, the recalculation area portion also has the optical proximity effect. It is preferable to correct.

  When an exposure simulation is performed using a layout diagram corrected for the optical proximity effect, a finished image (wafer view) of the wafer is obtained. Using this wafer finished image, it is possible to design a design in consideration of the wafer finished image.

  According to another aspect of the present invention, in a photomask design apparatus configured with a control unit, an internal database, and a data output unit to design a photomask, the control unit includes one or more functional blocks. Optical proximity effect correction is performed when creating a layout diagram of the semiconductor chip to be configured, and photomask production data is transmitted via the data output unit based on the layout diagram of the semiconductor chip after optical proximity effect correction. An apparatus for designing an output photomask is provided.

  In the present invention, the optical proximity effect correction is performed by the control unit when creating the layout diagram of the semiconductor chip. Then, photomask manufacturing action data is created based on the layout diagram of the semiconductor chip after this optical proximity effect correction. As a result, the device designer can grasp the layout diagram corrected for the optical proximity effect, and the device design can be performed in consideration of changes in the characteristics of elements such as transistors or circuits due to the optical proximity effect correction. As a result, it is possible to manufacture a semiconductor device having even better characteristics than in the past. Further, in the photomask designing apparatus of the present invention, as described in the above photomask designing method, it is possible to perform device design in consideration of the image of the finished wafer.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 3 is a block diagram showing a configuration of a photomask design apparatus (CAD apparatus) according to the embodiment of the present invention. The photomask design apparatus of this embodiment is composed of a computer (hardware) and dedicated software, and includes a control unit 11, an operation unit 12, a display unit 13, an internal database 14, and a tape output unit 15. Have. The control unit 11 sequentially executes the unit cell development process 16, the functional block development process 17 and the chip development process 18 using the data stored in the internal database 14, and determines a photomask pattern. Then, the control unit 11 converts the format of the determined photomask pattern into photomask production data and outputs it to the tape by the tape output unit 15. In the mask manufacturing process, a photomask is manufactured using this tape.

  As will be described later, the control unit 11 performs a function determination process in the middle of each process of the unit cell development process 16, the function block development process 17 and the chip development process 18, and after the process ends.

  FIG. 4 is a flowchart showing a photomask design method (device design process) and a subsequent LSI manufacturing process according to the embodiment of the present invention. With reference to FIG. 4, a photomask design method using the above-described photomask design apparatus will be described.

  As shown in FIG. 4, the photomask design method of this embodiment includes a unit cell development process (step S31) for developing a unit cell (pattern design) to be used in a desired electronic circuit, and the pass / fail of the developed unit cell. A function determining step (step S32) for determining, a function block developing step (step S33) for developing a function block (pattern design) composed of one or a plurality of unit cells using unit cell data, and a development A function determination step (step S34) for determining pass / fail of the function block, a chip design step (step S35) for pattern design of the entire semiconductor chip composed of one or a plurality of function blocks using the data of the function block Then, a function determination step (step S36) for determining whether or not the chip design is acceptable is performed in order. In this embodiment, as will be described later, OPC correction is performed in each of the unit cell development process (step S31), the functional block development process (step S33), and the chip design process (step S35). Create an OPC correction layout diagram.

  Next, the process proceeds to a mask manufacturing process. In step S37, it is confirmed whether or not the OPC correction has been performed on the entire semiconductor chip. If there is a part that has not been subjected to the OPC correction, the OPC correction is performed on that part. Thereafter, the process proceeds to step S38, and a photomask is manufactured using the data of the OPC correction layout diagram of the entire chip.

  Next, the process proceeds to step S39 to determine whether the manufactured photomask is acceptable. If it is determined in step S39 that the manufactured photomask is in good condition (OK), the process proceeds to step S40. If it is determined that the manufactured photomask is not in good condition (in the case of NG), step S37 is performed. Alternatively, the process returns to step S38 and the photomask is manufactured again.

  In step S40, a wafer process is performed using the manufactured photomask to manufacture a semiconductor device (LSI). Thereafter, the process proceeds to step S41, and the pass / fail determination of the LSI is performed. If it is determined in step S41 that the manufactured LSI is not in good condition (NG), the process returns to step S31, step S33, step S35, or step S37.

  As shown in the flowchart of FIG. 4, when it is determined that the desired function cannot be obtained in the function determination step (step S32) for determining whether or not the unit cell is acceptable (in the case of NG), the unit cell development step ( Returning to step S31), the unit cell is developed again. Similarly, when it is determined that a desired function cannot be obtained (in the case of NG) in the function determination step (step S34) for determining whether or not the function block is acceptable, the function block is returned to the function block development step (step S33). When it is determined that the desired function cannot be obtained (in the case of NG) in the function determination step (step S36) for determining whether the chip design is acceptable or not, the process returns to the chip design step (step S35) to return the semiconductor chip. Redo design.

  FIG. 5 is a flowchart showing details of the unit cell development process (step S31). As shown in FIG. 5, in the unit cell development process, a logic design process (step S51) for performing logic design of the unit cell, a function determination process (step S52) for determining whether or not the logic design is accepted, and the logic of the unit cell. A circuit design process (step S53) for performing circuit design based on the design, a function determination process (step S54) for determining whether the circuit design is acceptable, and a layout design for each element constituting the unit cell based on the circuit design. A layout design step (step S55), an OPC correction / simulation step (step S56) for performing OPC correction on the pattern after layout design and performing exposure simulation to calculate a pattern shape on the wafer, and an OPC corrected pattern Physical verification process (step for performing physical verification (DRC and ERC)) And 57), it executes a function determination step after physical verification (step S58) in order.

  If it is determined that the desired function cannot be obtained in the function determination step (step S52) for determining whether the logic design is acceptable or not (NG), the logic design is performed again by returning to the logic design step (step S51). Similarly, when it is determined that a desired function cannot be obtained (in the case of NG) in the function determination step (step S54) for determining whether the designed circuit is acceptable or not, the process returns to step S53 and the circuit design is performed again. The function determination step for determining whether the layout has been accepted (when it is determined in step S58 that the desired function cannot be obtained (in the case of NG), the process returns to step S55 and the layout design is performed again.

  In the functional block development process (step S33) and the chip design process (step S35) of FIG. 4, as in the unit cell development process shown in FIG. 5, a logic design process (step S51), a function determination process (step S52), A circuit design process (step S53), a function determination process (step S54), a layout design process (step S55), an OPC correction / simulation process (step S56), a physical verification process (step S57), and a function determination process (step S58). It is carried out in order.

  FIG. 6 is a schematic diagram specifically showing the operation in the unit cell development process. First, unit cell data used for a desired electronic circuit is read from an internal database (internal DB) 14, and a circuit diagram is created based on the data. Here, the case where the unit cell is an inverter is shown. After the unit cell function determination (step S52), the circuit design (step S53), and the designed circuit function determination (step S54), the unit cell layout design is performed (step S55). Is created. The circuit diagram and layout diagram of the unit cell are stored in the internal database 14.

  In the OPC correction / simulation step (step S56), OPC correction conditions and correction parameters are read from recipes (OPC correction conditions, photomask creation process conditions and various parameters, etc.) stored in the internal database 14, and an OPC correction table is stored. Created. The control unit 11 performs an OPC correction process on the layout diagram using the OPC correction table to generate an OPC correction layout diagram. The OPC correction includes rule-based OPC correction and model-based (simulation-based) OPC correction, as described in Patent Document 1 described above. In the present embodiment, rule-based OPC correction may be performed, or model-based OPC correction may be performed. The data of the OPC correction layout diagram created by the OPC correction process is stored in the internal database 14.

  In the OPC correction / simulation process, the process conditions and simulation parameters at the time of photomask creation are read from the recipe stored in the internal database 14, and a simulation table is created. Using this simulation table, the exposure when the pattern of the OPC layout diagram is used is simulated, and a pattern (wafer diagram) formed on the wafer is obtained. The wafer diagram data obtained by this simulation is also stored in the internal database 14.

  7 and 8 are schematic diagrams specifically showing the operation in the functional block development process. In the functional block development process, as shown in FIG. 7, by utilizing the circuit diagram, layout diagram, OPC correction layout diagram and wafer diagram of the unit cell stored in the internal database 14, the logical design of the functional block and the circuit Design and layout design. In the functional block layout design, the peripheral portion (hatched portion in FIG. 7) of the OPC correction layout diagram generated in the unit cell development process is set as the recalculation area. This is because the functional block is usually composed of a plurality of unit cells, and the optical proximity effect in the peripheral portion of the unit cell is affected by the adjacent unit cell and wiring.

  FIG. 8 is a schematic diagram showing a functional block 22 composed of a plurality of unit cells 21. In FIG. 8, the whitened portion is a portion that uses the result of the OPC correction performed in the unit cell development process (step S31 in FIG. 4) as it is, and the hatched portion is the OPC in the function block development step (step S33). The part which correct | amends is shown.

  After creating the OPC correction layout diagram of the functional block in this way, the control unit 11 reads out process conditions and simulation parameters from the internal database 14 to create a simulation table, and exposure when using the pattern of the OPC correction layout diagram. To create a functional block wafer diagram. The circuit diagram, layout diagram, OPC correction layout diagram, and wafer diagram created in the functional block development process are stored in the internal database 14.

  FIG. 9 is a schematic diagram specifically showing the operation in the chip design process. In the chip design process, the logic diagram, circuit design, and layout design of the semiconductor chip are performed by utilizing the circuit diagram, layout diagram, OPC correction layout diagram, and wafer diagram of the functional block stored in the internal database 14. A circuit diagram and a layout diagram of the entire chip are created. Then, OPC correction conditions and correction parameters are read from the internal database 14 to create an OPC correction table, and OPC correction is performed on the layout diagram to create an OPC correction layout diagram. When creating this OPC correction layout diagram, the OPC correction is performed by setting the peripheral portion of the OPC correction layout diagram of the functional block generated in the functional block development process as a recalculation area.

  FIG. 9 shows a semiconductor chip 23 composed of a plurality of functional blocks 22, and the white portions indicate portions where the results of OPC correction performed in the functional block development process (step S33 in FIG. 4) are used as they are. The hatched portion indicates a portion where OPC correction is performed in the chip design process (step S35).

  After creating the OPC correction layout diagram of the semiconductor chip in this way, the process conditions and simulation parameters are read from the internal database 14 to create a simulation table, and the exposure when using the pattern of the OPC correction layout diagram is simulated. A pattern (wafer drawing) formed on the wafer is obtained. The circuit diagram, layout diagram, OPC correction layout diagram, and wafer diagram data created in the chip design process are also stored in the internal database 14.

  Next, the control unit 11 creates input data for creating a photomask based on the layout diagram and the OPC layout diagram stored in the internal database 14, and outputs the data to the tape via the tape output unit 15.

  In the mask manufacturing process, it is confirmed whether or not the OPC correction is performed on the entire semiconductor chip (step S37). If there is an uncorrected portion, the portion is subjected to the OPC correction and then a photomask is manufactured.

FIG. 10 is a diagram showing a photomask manufacturing process. First, as shown in FIG. 10A, a Cr (chrome) film 32 is formed on the entire upper surface of a transparent substrate 31 made of, for example, SiO ₂ by sputtering or the like, and a photosensitive resist film 33 is formed thereon. . The thickness of the Cr film 32 is set to a thickness that can sufficiently block light used for exposure.

  Next, after exposing the photosensitive resist film 33 using a mask formed from the input data, development processing is performed, and an opening portion having a desired pattern is formed in the resist film 33 as shown in FIG. 33a is formed. Next, as shown in FIG. 10C, the Cr film 32 is etched using the resist film 33 as an etching mask to form a desired pattern.

  Next, as shown in FIG. 10D, the resist film 33 is peeled off. Thereby, a photomask having a predetermined light shielding pattern is completed.

  FIG. 11 is a schematic diagram showing a wafer exposure process. First, a photosensitive resist is applied on the wafer 41 to form a photosensitive resist film (not shown). Thereafter, light is irradiated through the photomask 42 manufactured in the previous process, and the photosensitive resist film on the wafer 41 is exposed. By this exposure, the pattern of the photomask 42 is transferred to the photosensitive resist film on the wafer 41 through the projection lens 43. Thereafter, the photosensitive resist film is developed. Thereby, a resist film having a desired pattern is formed on the wafer.

  In this embodiment, the OPC correction of the unit cell layout pattern, the functional block layout pattern, and the semiconductor chip layout pattern is performed in the device design process, so that the device designer grasps the OPC layout diagram and the wafer diagram, and the OPC. It is possible to design based on the influence of transistor characteristics due to correction. As a result, it is possible to manufacture a semiconductor device having even better characteristics than in the past.

  In the present embodiment, the wafer design (Wefer View) is created by simulating the exposure when the pattern of the OPC correction layout diagram is used in the device design process, so that the device design is performed in consideration of the finished image of the wafer. be able to.

  Furthermore, in the conventional design method, when the design is changed, it is necessary to start the design of the photomask from the beginning. In the present embodiment, the circuit diagram and layout diagram of each unit cell and functional block are stored in the internal database 14. Since the OPC correction layout diagram and the wafer diagram are stored, it is possible to respond quickly by redesigning only the changed unit cell or functional block.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) A unit cell development process for creating a layout diagram of a unit cell used in an electronic circuit,
A functional block development process for creating a functional block layout using the unit cell layout created in the unit cell development process;
A chip design process for creating a layout diagram of a semiconductor chip using a layout diagram of the functional block created in the functional block development process,
In the chip design step, optical proximity effect correction is performed on the layout diagram of the semiconductor chip, and photomask production data is generated based on the corrected layout diagram. .

(Appendix 2) In the unit cell development process, optical proximity effect correction is performed on the layout diagram of the unit cell created,
In the block development process, a layout diagram of the functional block is created using a layout diagram of the unit cell after optical proximity effect correction, optical proximity effect correction is performed on the layout diagram of the functional block,
2. The photomask design method according to appendix 1, wherein in the chip design process, a layout diagram of the semiconductor chip is created using a layout diagram of functional blocks after optical proximity effect correction.

(Supplementary Note 3) In the functional block development process, the result of the optical proximity effect correction performed in the unit cell development process is directly adopted for the region excluding the peripheral portion of the unit cell after the optical proximity effect correction, Create a functional block layout diagram after optical proximity effect correction by performing optical proximity effect correction for areas other than
In the chip design process, the result of the optical proximity effect correction performed in the functional block development process is adopted as it is for the area excluding the peripheral portion of the functional block after the optical proximity effect correction, and the other areas are optically processed. The method of designing a photomask according to appendix 2, wherein a layout diagram of the semiconductor chip is created by performing proximity effect correction.

(Additional remark 4) In the photomask design apparatus which comprises a control part, an internal database, and a data output part and designs a photomask,
The control unit performs optical proximity effect correction when creating a layout diagram of a semiconductor chip composed of one or a plurality of functional blocks, and performs photo processing based on the layout diagram of the semiconductor chip after optical proximity effect correction. An apparatus for designing a photomask, characterized in that mask production data is output via the data output unit.

  (Additional remark 5) The said control part implements an optical proximity effect correction also, when producing the layout figure of the said functional block, and the layout figure of the unit cell which comprises the said functional block. The photomask design apparatus described.

  (Supplementary Note 6) When creating the layout diagram of the functional block, the control unit performs optical proximity effect correction by setting a peripheral portion of the layout diagram of the unit cell as a recalculation region, and the semiconductor The photomask design according to appendix 5, wherein an optical proximity effect correction is performed by setting a peripheral portion of the layout diagram of the functional block as a recalculation area when creating a layout diagram of the chip. apparatus.

  (Supplementary note 7) The internal database stores correction conditions and correction parameters necessary for optical proximity effect correction, process conditions and simulation parameters at the time of photomask fabrication, and the control unit stores the correction conditions and correction parameters. The optical proximity effect correction of the layout diagram is performed using the parameters, and the exposure when the corrected layout diagram pattern is used is simulated using the process conditions and the simulation parameters, and a simulation diagram is created. The apparatus for designing a photomask according to appendix 4, characterized in that:

FIG. 1 is a flowchart showing a conventional photomask design method (device design process) and a subsequent LSI manufacturing process. FIG. 2 is a flowchart showing details of the unit cell development process. FIG. 3 is a block diagram showing a configuration of a photomask design apparatus (CAD apparatus) according to the embodiment of the present invention. FIG. 4 is a flowchart showing a photomask design method (device design process) and a subsequent LSI manufacturing process according to the embodiment of the present invention. FIG. 5 is a flowchart showing details of the unit cell development process. FIG. 6 is a schematic diagram specifically showing the operation in the unit cell development process. FIG. 7 is a schematic diagram (part 1) specifically showing the operation in the functional block development process. FIG. 8 is a schematic diagram (part 2) specifically showing the operation in the functional block development process. FIG. 9 is a schematic diagram specifically showing the operation in the chip design process. FIG. 10 is a diagram showing a photomask manufacturing process. FIG. 11 is a schematic diagram showing a wafer exposure process.

Explanation of symbols

11 ... control unit,
12 ... operation part,
13 ... display part,
14 ... Internal database,
15 ... tape output section,
16 ... Unit cell development process,
17 ... Function block development process,
18 ... chip design,
21 ... Unit cell,
22 ... functional blocks,
23. Semiconductor chip,
31 ... substrate,
32 ... Cr film,
33 ... photosensitive resist film,
41 ... wafer,
42 ... Photomask,
43. Projection lens.

Claims (5)

A unit cell development process for creating a layout diagram of a unit cell used in an electronic circuit;
A functional block development process for creating a functional block layout using the unit cell layout created in the unit cell development process;
A chip design process for creating a layout diagram of a semiconductor chip using a layout diagram of the functional block created in the functional block development process,
In the chip design step, optical proximity effect correction is performed on the layout diagram of the semiconductor chip, and photomask production data is generated based on the corrected layout diagram. . In the unit cell development process, optical proximity effect correction is performed on the layout diagram of the created unit cell,
In the block development process, a layout diagram of the functional block is created using a layout diagram of the unit cell after optical proximity effect correction, optical proximity effect correction is performed on the layout diagram of the functional block,
2. The photomask design method according to claim 1, wherein, in the chip design step, a layout diagram of the semiconductor chip is created using a layout diagram of functional blocks after optical proximity effect correction. In the functional block development step, the result of the optical proximity effect correction performed in the unit cell development step is directly adopted for the region excluding the peripheral portion of the unit cell after the optical proximity effect correction, and the other regions Perform optical proximity effect correction to create a layout diagram of the functional block after the optical proximity effect correction,
In the chip design process, the result of the optical proximity effect correction performed in the functional block development process is adopted as it is for the area excluding the peripheral portion of the functional block after the optical proximity effect correction, and the other areas are optically processed. 3. The photomask design method according to claim 2, wherein a proximity effect correction is performed to create a layout diagram of the semiconductor chip. In a photomask design apparatus configured with a control unit, an internal database, and a data output unit to design a photomask,
The control unit performs optical proximity effect correction when creating a layout diagram of a semiconductor chip composed of one or a plurality of functional blocks, and performs photo processing based on the layout diagram of the semiconductor chip after optical proximity effect correction. An apparatus for designing a photomask, characterized in that mask production data is output via the data output unit.   5. The photo according to claim 4, wherein the control unit also performs optical proximity effect correction when creating a layout diagram of the functional block and a layout diagram of unit cells constituting the functional block. Mask design equipment.

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