JP2007181052A - Image output system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image output system in which problems of an amount of data and a transfer rate required for transferring image data between two integrated circuits are solved. <P>SOLUTION: The image output system transfers the image data from a first integrated circuit 1 to a second integrated circuit 5 via a data bus 6 and outputs an image based on an output of the second integrated circuit 5. The first integrated circuit 1 is provided with an encoder 10 which compresses and encodes the image data, and the second integrated circuit 5 is provided with a decoder 20 which expands and decodes the compressed image data received via the bus 6. It is assured that the encoder 10 encodes one frame or one line image data at an actual compression ratio equal to or more than a prescribed compression ratio. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device such as liquid crystal, plasma, and organic EL display, and an image output system such as a printer.

  For example, taking a liquid crystal display device of a mobile phone as an example, the number of pixels on a display has increased in recent years and the number of gradations per pixel has increased in order to perform high-definition display. The current mainstream QVGA (240 x 320 dots) will be shifted to VGA (480 x 640 dots) or WVGA (480 x 800 dots). In QVGA, the gradation value per pixel is 16 bits or 18 bits. However, with VGA or WVGA, the gradation is increased to 18 bits or 24 bits.

  The increase in the number of pixels and the gradation value seriously affects the increase in the data transfer rate and the increase in the frame memory capacity.

  Increasing the transfer clock frequency and data bus width will increase EMI (Electro Magnetic Interference) and power consumption. The increase in power consumption is fatal for mobile devices such as mobile phones.

  The adoption of a high-speed serial interface as a solution is difficult to implement because it is an analog circuit, and measures against noise are indispensable because of its high frequency.

  The increase in the frame memory cannot be found unless the driver IC with built-in RAM is fundamentally reconsidered. For example, the change of QVGA → VGA increases the memory area by a factor of 4, and the area of the RAM built-in driver IC also increases significantly. In that case, a driver IC with a built-in RAM mounted on a glass substrate by COG (Chip On Grass) increases the glass substrate area of the liquid crystal panel only for mounting the driver IC, and the number of panels to be taken when divided from the manufacturing substrate. Decrease. In addition, the shape of the rectangular conventional driver IC whose long axis is the short side of the glass substrate cannot be maintained. COG mounting is no longer possible, and it must be completely changed to COF (Chip On Film).

The above problem is not limited to liquid crystal display devices, but high-definition image data is transferred between an integrated circuit serving as an image output source that receives or generates an image and an integrated circuit that drives a display unit or a printer. Is common.
Japanese Patent Laid-Open No. 1-112377 JP 2001-257888 A

  An object of the present invention is to provide an image output system capable of solving the problems of data amount and transfer rate when image data is transferred between two integrated circuits.

  Another object of the present invention is to provide an image output system capable of reducing the capacity of a memory for storing an image transferred between two integrated circuits.

One embodiment of the present invention is an image output system for transferring image data from a first integrated circuit to a second integrated circuit via a data bus and outputting an image based on an output of the second integrated circuit. ,
An image encoding device that encodes the image data is provided in the first integrated circuit,
The second integrated circuit is provided with an image decoding device for decoding compressed image data received via the data bus.

  When high-definition image output is required, the amount of image data increases, and the transfer frequency for transferring image data for one frame within a predetermined time is increased. In the present invention, since the first integrated circuit is equipped with an image encoding device and transfers compressed image data, the amount of transferred data is reduced. Therefore, depending on the compression rate, it is possible to use a conventional transfer method (transfer frequency, bit width) as it is while ensuring high-definition image output.

  In one aspect of the present invention, the image encoding device can ensure that the image data of each frame for one frame is encoded at an actual compression rate equal to or higher than a specified compression rate. Here, for example, when the specified compression rate is 50%, the actual compression rate equal to or higher than the specified compression rate means a compression rate such as 50%, 40%, 30%, etc., and the actual high compression does not exceed 50%. (The smaller the numerical value indicating%, the higher the compression rate, and the larger the numerical value, the lower the compression rate). Alternatively, this image encoding device can ensure that the image data of each line for one line is encoded at an actual compression rate equal to or higher than a specified compression rate. Therefore, it becomes easy to change the transfer frequency or bit width described below.

  In one aspect of the present invention, the first integrated circuit includes a transfer clock generation unit that generates a transfer clock for transferring the image data to the data bus, and the transfer clock generation unit receives a reference clock. By dividing the frequency based on the specified compression rate, it is possible to lower the frequency of the transfer clock when transferring the compressed image data than when transferring the uncompressed image data.

  Thus, since the transfer frequency is lowered according to the specified compression rate, it is effective as an EMI countermeasure. Further, since the data amount of the compressed image data is reduced, the power consumption consumed by the load on the transfer line during transfer is also reduced.

  In one aspect of the present invention, the first integrated circuit includes a memory that stores the compressed image data from the image encoding device, and a transfer clock that generates a transfer clock for transferring the code to the data bus. A generation unit, wherein the image encoding device outputs an actual compression rate when an image for one frame is compressed, and the transfer clock generation unit uses a reference clock based on the actual compression rate of one frame. The frequency of the transfer clock for transferring the compressed image data for one frame can be varied for each frame.

  Since the actual compression rate is higher than the specified compression rate, the transfer frequency can be further lowered.

  In one aspect of the present invention, the first integrated circuit includes a memory that stores the compressed image data from the image encoding device, and a transfer clock that generates a transfer clock for transferring the code to the data bus. The image encoding device outputs an actual compression rate for each line, and the transfer clock generator divides the reference clock based on the actual compression rate of one line, The frequency of the transfer clock for transferring the compressed image data for one line can be varied for each line.

  By varying the transfer frequency for each line, optimum transfer according to the data amount of the compressed image data can be performed.

  In one aspect of the present invention, the first integrated circuit may include a bit width variable unit that varies a bit width transferred by one clock of the transfer clock based on the specified compression rate.

  By changing the bit width, the amount of compressed image data transferred by one clock of the transfer clock can be reduced, and the power consumption is reduced.

  In one aspect of the present invention, the first integrated circuit includes a memory that stores the compressed image data from the image encoding device, and a bit width variable unit that varies a bit width transferred by one clock of the transfer clock. The image encoding device outputs an actual compression rate for each frame, and the bit width variable unit varies the bit width for each frame based on the actual compression rate of one frame. be able to.

  By varying the bit width for each frame, it is possible to perform optimum transfer according to the data amount of the compressed image data.

  In one aspect of the present invention, the first integrated circuit includes a memory that stores the compressed image data from the image encoding device, and a bit width variable that varies a bit width transferred by one clock of the transfer clock. The image encoding device outputs the actual compression rate for each line, and the bit width variable unit sets the bit width for each line based on the actual compression rate of one line. Can be variable.

  By varying the bit width for each line, more optimal transfer according to the data amount of the compressed image data can be performed.

  In one aspect of the present invention, the first integrated circuit device includes a transfer clock generation unit that generates a transfer clock for transferring the compressed image data to the data bus, and the transfer clock generation unit includes: Based on the specified compression rate, the transfer clock can be output only during a period in which the compressed image data is transferred in the transfer period in which the uncompressed image data is transferred, and the transfer clock can not be output in the remaining period.

  Since the transfer clock is output only when compressed image data is transferred, power consumption can be reduced.

  In one aspect of the present invention, the first integrated circuit device generates a transfer clock for transferring the code to a data bus and a memory that stores the compressed image data from the image encoding device. A clock generator, wherein the image encoding device outputs the actual compression rate for each frame, and the transfer clock generator is configured to generate a non-frame for one frame based on the actual compression rate of one frame. The transfer clock is output only during a period in which the compressed image data for one frame is transferred in the transfer period for transferring the compressed image data, and the transfer clock is not output in the remaining period.

  Based on the actual compression rate, output of the transfer clock can be stopped, and the certainty of outputting the transfer clock only when compressed image data is transferred is increased.

  In one aspect of the present invention, the first integrated circuit device generates a memory for storing the compressed image data from the image encoding device and a transfer clock for transferring the image data to the data bus. A transfer clock generation unit, wherein the image encoding device outputs an actual compression rate for each line, and the transfer clock generation unit is configured to output a non-line for one line based on the actual compression rate for one line. The transfer clock is output only during a period in which the compressed image data for one line is transferred in the transfer period for transferring the compressed image data, and the transfer clock is not output in the remaining period.

  The output of the transfer clock can be stopped for each line, and the certainty of outputting the transfer clock only when compressed image data is transferred is further increased.

  In one aspect of the present invention, the first integrated circuit supplies the first color signal for one pixel to the front stage of the image encoding device with a bit number smaller than the bit number of the first color signal. A color signal conversion circuit for converting to a second color signal, wherein the compression ratio achieved by the color signal conversion circuit is k (k <1), and the prescribed compression achieved by the image coding apparatus If the rate or the actual compression rate is α, the compression rate used for transfer control of the compressed image data can be set to k × α.

  A high compression rate can be realized by combining compression by an image encoding device and compression by color signal conversion.

  In one aspect of the present invention, the first integrated circuit switches and transfers uncompressed image data and the compressed image data via the data bus, and transmits an uncompressed / compressed switching signal to the uncompressed image data. Data or compressed image data can be transmitted in synchronization with a vertical synchronization signal transmitted at the time of transfer. In this way, uncompressed image data and compressed image data can be switched and displayed, and the degree of freedom of image output in accordance with user needs is increased.

  Since the compressed image data memory stores compressed image data whose data amount has been reduced by compression, an increase in memory capacity can be suppressed even when high-definition image output is required. As a result, the size of the second integrated circuit does not increase.

  In one aspect of the present invention, when a decoding error occurs in the image decoding device of the second integrated circuit, an interrupt signal is supplied from the second integrated circuit to the first integrated circuit, and the interrupt signal The first integrated circuit receives the image encoding device so as to retransmit only the compressed image data of one frame including only the line where the decoding error has occurred or the line where the decoding error has occurred. Can be controlled.

  Unlike uncompressed image data, the decoding error of compressed image data has a great influence because it relates to decoding of subsequent compressed image data. With the above-described control, it is possible to minimize the influence accompanying the decoding error.

  In one aspect of the present invention, when the amount of uncompressed image data is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory is S bits, M > S> M × α is established. Therefore, even if high-definition image output is required by bringing the effective storage capacity of the compressed image data memory close to the lower limit, the memory size, and hence the size of the second integrated circuit, is not increased.

  In one aspect of the present invention, the first integrated circuit supplies the first color signal for one pixel to the front stage of the image encoding device with a bit number smaller than the bit number of the first color signal. A color signal conversion circuit for converting to a second color signal; a compression rate achieved by the color signal conversion circuit is k (k <1); an amount of uncompressed image data is M bits; When the specified compression rate is α (α <1) and the effective storage capacity of the compressed image data memory is S bits, M> S> M × α × k is established.

  In this way, by combining the compression by the image encoding device and the compression by the color signal conversion, the memory size, and thus the size of the second integrated circuit can be kept small.

  In one aspect of the present invention, the second integrated circuit further includes an image data processing unit that synthesizes image data for N frames (N is an integer of 2 or more) and processes the image data for one frame. N × M>, where the data amount of uncompressed image data for one frame is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory is S bits. S> N × M × α is established.

  As an example in which the amount of image data increases, there is a case in which image data for N frames is processed into a single frame image. Also in this case, the memory capacity can be reduced based on the specified compression rate.

  In one aspect of the present invention, the first integrated circuit supplies the first color signal for one pixel to the front stage of the image encoding device with a bit number smaller than the bit number of the first color signal. A color signal conversion circuit for converting the image data into a second color signal; and the second integrated circuit synthesizes image data for N frames (N is an integer equal to or greater than 2) to form image data for one frame. An image data processing unit for processing, the compression rate achieved by the color signal conversion circuit is k (k <1), the amount of uncompressed image data for one frame is M bits, When the compression rate is α (α <1) and the effective storage capacity of the compressed image data memory is S bits, N × M> S> N × M × α × k holds.

  Even when the amount of image data increases due to data processing, the memory size and thus the size of the second integrated circuit can be kept small by combining the compression by the image encoding device and the compression by the color signal conversion.

In one aspect of the present invention, the second integrated circuit further includes a compressed image data memory that stores the compressed image data transferred via the data bus in the preceding stage of the image decoding device,
When the data amount of one line of uncompressed image data is ML bits, the specified compression rate is α (α <1), and the effective storage capacity on one line of the compressed image data memory is SL bits, ML>SL> ML × α is established.

  In this way, downsizing can be performed in one line direction of the compressed image data memory, and the degree of layout freedom is increased.

  In one aspect of the present invention, the first integrated circuit supplies the first color signal for one pixel to the front stage of the image encoding device with a bit number smaller than the bit number of the first color signal. A color signal conversion circuit for converting to a second color signal; and the second integrated circuit is provided in a preceding stage of the image decoding device and stores compressed image data transferred via the data bus. A compression image data memory, wherein the compression rate achieved by the color signal conversion circuit is k (k <1), the data amount of one line of uncompressed image data is ML bits, and the specified compression rate Is α (α <1), and the effective storage capacity on one line of the compressed image data memory is S bits, ML> SL> ML × α × k holds.

  As described above, the downsizing effect is great also in one line direction of the compressed image data memory by combining the compression by the image encoding device and the compression by the color signal conversion.

In one aspect of the present invention, the first integrated circuit supplies the first color signal for one pixel to the front stage of the image encoding device with a bit number smaller than the bit number of the first color signal. A color signal conversion circuit for converting to a second color signal; and the second integrated circuit is provided in a preceding stage of the image decoding device and stores compressed image data transferred via the data bus. A compressed image data memory; and an image data processing unit that is provided at a subsequent stage of the image decoding device and synthesizes image data for N (N is an integer of 2 or more) frames and processes the image data for one frame;
The compression rate achieved by the color signal conversion circuit is k (k <1), the amount of uncompressed image data for one line is ML bits, and the specified compression rate is α (α < 1) and when the effective storage capacity of the compressed image data memory is SL bits, N × ML>SL> N × ML × α × k holds.

  In this way, even when processing an N-frame image into a single-frame image, downsizing can be performed in one line direction of the compressed image data memory.

  In one aspect of the present invention, the compressed image data memory can store the head data of the compressed image data of each line in a storage element at the same address of each line of the image compression memory.

  In data processing, compressed image data for each line is often read and processed, so that if the access to the head address of the line is simple, the processing speed is also improved.

In one aspect of the present invention, the second integrated circuit sends a write start signal synchronized with a vertical synchronization signal to the first integrated circuit, and the first integrated circuit is based on the write start signal. Transferring the compressed image data to the second integrated circuit via the data bus;
The timing at which writing to the compressed image data memory is started based on the write start signal can be preceded by the read start timing with respect to the compressed image data memory.

  In this way, the situation where the write address overtakes the read address can be prevented.

  In one aspect of the present invention, the second integrated circuit includes a first line buffer provided in a preceding stage of the compressed image data memory, and a first line buffer provided between the compressed image data memory and the image decoding device. And two line buffers. In this case, the compressed image data for one line is simultaneously written into the compressed image data memory from the first line buffer, and the compressed image data for one line is simultaneously output from the compressed image data memory, so that the second Stored in the line buffer. Alternatively, the second integrated circuit may further include first and second read line buffers between the compressed image data memory and the image decoding device. In this case, the compressed image data for one line read from the compressed image data memory is alternately stored in the first and second read line buffers and is alternately read.

  In this way, even if the start time of writing to the compressed image data memory is not limited, a situation in which the write address overtakes the read address does not occur.

  Embodiments of an image output system according to the present invention will be specifically described below with reference to the drawings.

1. 1. First embodiment 1.1. Overview of Image Output System FIG. 1 shows an embodiment in which an image output system of the present invention is applied to a mobile phone. In FIG. 1, a baseband engine (BBE: first integrated circuit in a broad sense) 1 is an LSI (Large Scale Integrated Circuit) that controls the basic functions of a mobile phone, and is a video, still image, or camera received via the Internet. It is an output source of various image data such as photographed natural images, menu screens necessary for operation of a mobile phone, and character / graphic information such as icons.

  In FIG. 1, a liquid crystal panel 2 is provided as a display of a mobile phone. The liquid crystal panel 2 has a liquid crystal sealed between two glass substrates 3 and 4. The large glass substrate 3 is an active matrix substrate, for example, and each pixel is provided with a TFT (Thin Film Transistor) which is an active element. A transparent pixel electrode is connected to the drain terminal of the TFT of each pixel, a source line that is a data line is connected to the source terminal, and a gate line that is a scanning line is connected to the gate terminal. A transparent electrode is provided on the glass substrate 4 facing the glass substrate 3. A driver IC (second integrated circuit in a broad sense) 5 for driving the liquid crystal panel 2 is COG mounted on the glass substrate 3 along the short side of the glass substrate 3. The driver IC 5 supplies the scanning signal to the gate line of the liquid crystal panel 2 and the data signal to the source line to drive the liquid crystal panel 2 for display.

  The baseband engine 1 and the driver IC 5 are connected by a plurality of bus lines 6 and transfer image data, horizontal / vertical synchronization signals, clock signals, and various commands.

  In the present embodiment, an image encoding device (also referred to as an encoder) 10 is mounted on the baseband engine 1, and an image decoding device (also referred to as a decoder) 20 is mounted on the driver IC 5.

  The encoder 10 compresses image data of each frame for one frame at a compression ratio (for example, 40%, which means a high compression ratio not exceeding 50%) that is equal to or higher than a specified compression ratio (for example, 50%). Encoding is guaranteed, and details thereof will be described later. The encoder 10 can also ensure that the image data of each line for one line is compressed and encoded at a compression rate equal to or higher than a specified compression rate. The decoder 20 decompresses and decodes the compressed image data transferred via the bus line 6, and details thereof will be described later.

1.2. Transfer Frequency When the liquid crystal panel 2 displays a high definition, the amount of image data increases, and the transfer frequency for transferring image data for one frame within a predetermined time increases. In the present embodiment, the baseband engine 1 is equipped with the encoder 10 and transfers compressed image data, so that the amount of transfer data decreases. Therefore, depending on the compression rate, the conventional transfer method (transfer frequency, bit width) can be used as it is. In the following embodiment, an example in which the transfer frequency can be reduced as compared with the case of transferring uncompressed image data will be described.

1.2.1. Setting of Transfer Frequency Based on Specified Compression Ratio FIG. 2 is a block diagram of a part of the baseband engine 1. In FIG. 2, the baseband engine 1 is connected via a system bus 30 to an uncompressed image data memory 31 that is a working memory of the baseband engine 1. The encoder 10 is connected to the internal bus 32 of the baseband engine 1 connected to the system bus 30. Therefore, the uncompressed image data in the uncompressed image data memory 31 is transferred to the encoder 10 via the system bus 30 and the internal bus 32, where it is compressed and encoded at a compression rate equal to or higher than a specified compression rate. The specified compression ratio (for example, 50%) is stored in the compression ratio setting unit 33 and used for frequency control of the reference clock from the oscillator 34.

  The baseband engine 1 is provided with a panel data generation unit 35. The panel data generation unit 35 is provided with a transfer clock generation unit 36 and a data transfer unit 37. The transfer clock generator 36 divides the reference clock from the oscillator 34 according to the specified compression rate from the compression rate setter 33 to generate a transfer clock. The data transfer unit 37 sends the compressed image data received from the encoder 10 via the internal bus 32 to the data bus according to the transfer clock. The transfer clock is sent to the clock transfer bus separately from the compressed image data.

  3A and 3B are timing charts for explaining the setting of the transfer clock frequency. As shown in FIG. 3A, the reference clock CLK from the oscillator 34 in FIG. 2 is used as a transfer clock PCLK1 of uncompressed image data D0, D1, D2,... As shown in FIG. If the specified compression ratio is, for example, 50%, the transfer clock generation unit 36 divides the reference clock CLK, and as shown in FIG. A clock PCLK2 is generated. This transfer clock PCLK2 is used as a transfer clock for compressed image data D0 ', D1', D2 ',... Having a specified compression rate of 50%. Thus, since the transfer frequency is lowered according to the specified compression rate, it is effective as an EMI countermeasure. Further, since the data amount of the compressed image data is reduced, the power consumption consumed by the load on the transfer line during transfer is also reduced.

1.2.2. Setting of Transfer Frequency Based on Actual Compression Ratio In FIG. 4, in addition to the configuration shown in FIG. In the compression rate setting unit 33 of FIG. 4, an actual compression rate that is equal to or higher than a specified compression rate (for example, 50%) when an uncompressed image is compressed by the encoder 1 is set by the encoder 1. The compressed image data memory 38 is used as a temporary storage buffer because the actual compression rate is not determined until compressed image data for one frame is generated.

  In the embodiment of FIG. 4, for example, when the actual compression rate is 25% or less, the reference clock CLK is divided by the transfer clock generator 36 as shown in FIG. In contrast, a transfer clock PCLK3 having a frequency of 1/4 is generated. This transfer clock PCLK3 is used as a transfer clock for the compressed image data D0 ', D1', D2 '... having an actual compression rate of 25%. As described above, when the actual compression rate is used, the transfer frequency is further lowered, which is effective for EMI noise countermeasures and power consumption reduction.

  The actual compression rate can be set in the compression rate setting unit 33 by the encoder 10 every time one frame of uncompressed image data is compressed. In this case, if the actual compression rate is different for each frame, the frequency divider 34 can vary the transfer frequency for each frame.

  In addition, the encoder 10 can set an actual compression rate that is equal to or higher than a specified compression rate for each line, as will be described later. Therefore, the frequency divider 34 can vary the transfer frequency for each line based on the actual compression rate for each line.

1.2.3. Fixed Image Data Transfer Frequency FIG. 5 shows an example in which fixed image data is stored in the compressed image data memory 38, such as a menu screen. In this case, the specified compression rate or actual compression rate of the compressed image data is stored and set in the compression rate setting unit 33. Therefore, when the fixed image data is transferred to the side by the liquid crystal panel, it can be transferred at a lower transfer frequency as in the example of FIG. 2 or FIG.

1.3. Data bit width per transfer clock Instead of changing the transfer frequency based on the specified compression rate or actual compression rate, the bit width of uncompressed image data per transfer clock is changed to the data transfer unit (bit width variable unit in a broad sense). ) 37 may be changed. As shown in FIG. 6, the interface of the driver IC 5 has 24 data terminals, an input terminal for the vertical synchronization signal Vsync, an input terminal for the horizontal synchronization signal Hsync, an input terminal for the clock CLK, a data enable (DE) terminal, a serial Input / output terminals are provided. A maximum of 24 bits of data can be received using 24 data terminals, but if the bit width is 12 bits, only 12 data terminals need be used. If the bit width is 6 bits, only 6 data terminals need be used. Thus, if the bit width is reduced, the number of data buses used is reduced, so that power consumption can be reduced.

  In any of the configurations of FIGS. 2, 4 and 5, the bit width can be changed as shown in FIGS. 7A to 7D. FIG. 7A shows the reference clock CLK from the oscillator 34. In FIG. 7B, uncompressed image data D0, D1, D2,... Are transferred with a standard bit width per transfer clock (for example, 24 bits per pixel) using the same transfer clock PCLK as the reference clock CLK. ing.

  FIG. 7C shows an example in which the specified compression ratio is 50%, and the compressed image data D0 ′, D1 ′, D2 ′,... Are converted into bits per transfer clock using the same transfer clock PCLK as the reference clock CLK. For example, the width is transferred as 12 bits per pixel.

  FIG. 7D shows an example in which the actual compression rate is 25%, and the compressed image data D0 ′, D1 ′, D2 ′,... Are converted into bits per transfer clock using the same transfer clock PCLK as the reference clock CLK. For example, the width is transferred as 6 bits per pixel.

  The actual compression rate can be set in the compression rate setting unit 33 by the encoder 10 every time one frame of uncompressed image data is compressed. In this case, if the actual compression rate differs for each frame, the data transfer unit 37 can vary the bit width for each frame.

  In addition, since the encoder 10 can set an actual compression rate that is equal to or higher than the specified compression rate for each line, the data transfer unit 33 can change the bit width for each line based on the actual compression rate for each line. You can also

1.4. Intermittent transfer clock The transfer clock generation unit 34 is based on a specified compression rate or actual compression rate, and in a transfer period (one vertical period or one horizontal period) for transferring uncompressed image data for one frame or one line. Control may be performed so that the transfer clock is output only during the period during which the compressed image data is transferred, and the transfer clock is not output during the remaining period.

  In any of the configurations of FIGS. 2, 4 and 5, as shown in FIGS. 8A to 8D, the generation period of the transfer clock PCLK is controlled to be an intermittent clock in which no clock is generated. be able to. FIG. 8A shows a reference clock CLK generated continuously from the oscillator 34. In FIG. 8B, uncompressed image data D0, D1, D2,... D11 in one frame or one line is transferred using the same transfer clock PCLK as the reference clock CLK. In this case, it is not an intermittent clock.

  FIG. 8C shows an example in which the specified compression rate is 50%, and compressed image data D0 ′, D1 ′, D2 ′,. The transfer clock PCLK is generated only during the period, and the transfer clock PCLK is stopped in the remaining period of one vertical period or one horizontal period.

  FIG. 8D is an example in which the actual compression rate is 25%, and is a period during which compressed image data D0 ′, D1 ′, D2 ′ obtained by compressing uncompressed data D0, D1, D2,. Only the transfer clock PCLK is generated, and the transfer clock PCLK is stopped in the remaining period of one vertical period or one horizontal period.

  Thus, the power consumption can be reduced by shortening the substantial data transfer period.

1.5. The high compression encoder 10 using the color signal conversion circuit can compress the color signal as it is, regardless of whether the uncompressed image data is an RGB signal or a YUV signal, as will be described later. Since the liquid crystal display panel 2 has an RGB color filter, even if it is finally converted into an RGB signal, the color signal is not distinguished at the stage of compression / expansion.

  However, in order to further compress the uncompressed image data, the color signal may be converted as shown in FIG. 9 or FIG. However, in the present embodiment, explanation will be made ignoring the compressed image data memory 51 in FIGS. 9 and 10 (for explanation in the second embodiment described later).

  In FIG. 9, an RGB-YUV conversion circuit (color signal conversion circuit in a broad sense) 40 is provided before the encoder 10 of the baseband engine 1. In addition, a YUV-RGB conversion circuit 41 is provided after the decoder 20 of the driver IC 5. Here, the RGB-YUV conversion circuit 40 converts an RGB signal for one pixel into a YUV signal having a bit number smaller than the bit number of the RGB signal.

  As an example, when the RGB-YUV conversion circuit 40 converts RGB888 (24 bits) in which each RGB sub-pixel is 8 bits into YUV422 (16 bits), 67% (100 × 16/24) data is obtained by the conversion. Compression is achieved. Therefore, if the specified compression rate or the actual compression rate in the encoder 10 is α (α <1) and the compression rate by color signal conversion is k (k <1), a total compression rate of α × k can be achieved. In the example of FIG. 9, this total compression rate α × k can be set in the compression rate setting unit 33 of FIG. 2, FIG. 4 or FIG. The transfer clock frequency, bit width, or intermittent clock described above can be set according to the total compression rate α × k. When α = 0.5 and k = 0.67, α × k = 0.335, and a higher compression ratio can be achieved.

  As another example, when the RGB-YUV conversion circuit 40 converts RGB888 (24 bits) to YUV420 (12 bits), k = 50% (100 × 12/24) data compression is achieved by the conversion, The total compression rate α × k = 0.25, which is a high compression rate.

  As another example, when the RGB-YUV conversion circuit 40 converts RGB565 (16 bits) to YUV420 (12 bits), data conversion of k = 75% (100 × 12/16) is achieved by the conversion. The total compression rate α × k = 0.385 and a high compression rate.

  In FIG. 10, a UV sampling conversion circuit (color signal conversion circuit in a broad sense) 42 is provided before the encoder 10 of the baseband engine 1. Further, a UV interpolation circuit 43 is provided after the decoder 20 of the driver IC 5. Also in this case, the UV sampling conversion circuit 42 converts the YUV signal for one pixel into a YUV signal having a bit number smaller than the bit number of the YUV signal.

  As an example, when the UV sampling conversion circuit 42 converts YUV444 (24 bits) to YUV422 (16 bits), 67% (100 × 16/24) data compression is achieved by the conversion, and the total compression ratio α × k = 0.335 and a high compression rate.

  As another example, when the UV sampling conversion circuit 42 converts YUV444 (24 bits) to YUV420 (12 bits), k = 50% (100 × 12/24) data compression is achieved by the conversion, and the total The compression rate α × k = 0.25, which is a high compression rate.

  As yet another example, when the UV sampling conversion circuit 42 converts YUV422 (16 bits) to YUV420 (12 bits), k = 75% (100 × 12/16) data compression is achieved by the conversion, The total compression rate α × k = 0.385 and a high compression rate.

1.6. Non-compression / compression switching The baseband engine 1 can switch and transfer uncompressed image data or compressed image data via a data bus. In this case, it is preferable to send the non-compression / compression switching signal in synchronization with the vertical synchronization signal Vsync transmitted when transferring the non-compressed image data or the compressed image data.

  FIG. 11 shows a situation where non-compressed data → compressed data → compressed data as shown in FIG. 11 (B) for each vertical period Vsync in FIG. 11 (A). In the case of the driver IC having the serial input / output terminal SIO shown in FIG. 6, the non-compression / compression switching command Cmd shown in FIG. 11C is sent from the baseband engine 1 to the vertical scanning period Tn in which the first compressed image data is transferred. Is received in the vertical scanning period Tn−1 before. As a result, the driver IC 5 can decode the received compressed image data by the decoder 20. Not limited to this, as shown in FIG. 11D, a compression enable signal CE that becomes active in synchronization with the vertical scanning period Tn may be transmitted from the baseband engine 1 to the driver IC 5. In this case, the driver IC 5 has a receiving terminal for a compression enable signal.

2. Second Embodiment FIG. 12 shows a second embodiment of the present invention, and is different from FIG. 1 in that a compressed image data memory 51 is provided in the preceding stage of the decoder 20 of the driver IC 50. Therefore, in this embodiment, all the items described in the first embodiment can be satisfied, and the data capacity of the compressed image data memory provided in the driver IC 5 can be reduced.

2.1. Total Storage Capacity of Compressed Image Data Memory As shown in FIG. 13, the data amount of uncompressed image data is M bits, the specified compression rate at the encoder 10 is α (α <1), and the compressed image data memory 51 When the effective storage capacity (not including redundant memory) is S bits, M>S> M × α holds. That is, the encoder 10 is guaranteed to compress uncompressed image data at a compression rate equal to or higher than the specified compression rate α, and does not fall below the specified compression rate α. Therefore, if the storage capacity S of the compressed image data memory 51 is designed as a memory capacity close to the lower limit of the above inequality formula, the size of the compressed image data memory 51 can be reduced, the driver IC 50 can also be maintained at a small size, and COG mounting Is possible.

  When the color signal conversion circuits 40 and 42 are provided as shown in FIG. 9 or FIG. 10, the compression rate achieved by the color signal conversion circuits 40 and 42 is k (k <1) as shown in FIG. When the data amount of uncompressed image data is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory is S bits, M> S> M × α × k is satisfied. To do. Therefore, the capacity of the compressed image data memory 51 can be further reduced.

2.2. Storage capacity on one line of the compressed image data memory The encoder 10 can ensure that the image data of each line for one line is encoded at an actual compression rate equal to or higher than a specified compression rate. In this case, as shown in FIG. 15, the data amount of one line of uncompressed image data is ML bits, the specified compression rate is α (α <1), and the compressed image data memory 51 is on one line. When the effective storage capacity is SL bits, ML>SL> ML × α is established. That is, if the compressed image data memory 51 is, for example, an SRAM, it means that the size in the word line direction is shortened.

  In such a compressed image data memory 51, as shown in FIG. 15, the head data of the compressed image data of each line is stored in the storage element at the same address of each line of the image compression memory. In this way, the head address of each line can be easily detected.

  In the example of FIG. 15, when the color signal conversion circuits 40 and 42 as shown in FIG. 9 or 10 are provided, the compression rate achieved by the color signal conversion circuits 40 and 42 is k (k <1). When the data amount for one line of uncompressed image data is ML bits, the specified compression rate is α (α <1), and the effective storage capacity on one line of the compressed image data memory 51 is S bits, ML> SL> ML × α × k is established. Thereby, for example, the size of the compressed image data memory 51 in the word line direction is further reduced.

2.3. Decoding error countermeasure In the decoder 20 of the driver IC 5, when an error occurs in the middle of a certain line Ln of a certain frame Fn, the data on the same line Ln downstream from the error occurrence position cannot be decoded. If it is non-compressed image data, only one error is required, and the visual problem is not serious. However, in the case of compressed image data, it becomes impossible to decode after the error occurrence position, so a countermeasure is necessary.

  In the present embodiment, when a decoding error occurs in the decoder 20 of the driver IC 5, an interrupt signal from the serial input / output terminal SIO shown in FIG. 6 of the driver IC 5 is supplied to the baseband engine 1. The baseband engine 1 that has received the interrupt signal controls the encoder 10 to retransfer the compressed image data from the line Ln where the decoding error has occurred or from the beginning of the frame Fn where the decoding error has occurred. This minimizes the degradation of image quality due to decoding errors.

  That is, unlike the uncompressed image data, the decoding error of the compressed image data is related to the decoding of the subsequent compressed image data. Therefore, if the compressed image data from the compressed image data memory 51 is continuously sent, the display is adversely affected. large. With the above-described control, it is possible to minimize the influence accompanying the decoding error.

3. Third Embodiment FIG. 16 shows an embodiment in which a display control IC (second integrated circuit in a broad sense) 60 is added between the baseband engine 1 and the liquid crystal panel 2. At this time, the driver IC 52 in FIG. 15 is different from the driver IC 5 in FIG. 1 and the driver IC 50 in FIG. 12, and neither the decoder 20 nor the compressed image data memory 51 is mounted.

  In the present embodiment, the advantages associated with the data transfer described in the first embodiment can also be enjoyed by the data transfer between the baseband engine 1 and the display unit tongue roll IC 60.

  A display control IC 60 shown in FIG. 16 is provided to reduce tasks necessary for the display operation of the baseband engine 1, and includes an image compression data memory 61, a decoder 20, and a data processing unit 62.

  Here, the main role of the display control IC 60 is to process display data in the data processing unit 62. Display data processing includes enlargement, reduction, rotation, and composition of images. For example, taking image synthesis as an example, image data for N frames (N is an integer of 2 or more) transferred from the baseband engine 1 may be synthesized and processed into image data for one frame.

  In this case, as shown in FIG. 17, the amount of uncompressed image data for one frame is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory 61 is S bits. N × M> S> N × M × α is established.

  In this manner, by compressing N images and transferring the data after storing the compressed images, storing them in the compressed image data memory 61 has the advantage of reducing the storage capacity of the compressed image data memory 61 in addition to the merit in data transfer.

  In the example of FIG. 16, when the color signal conversion circuits 40 and 42 as shown in FIG. 9 or FIG. 10 are provided, the compression ratio achieved by the color signal conversion circuits 40 and 42 is k (k <1). When the data amount of uncompressed image data for one frame is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory 61 is S bits, N × M> S> N × M × α × k is established. As a result, the size of the compressed image data memory 61 can be further reduced.

  The encoder 10 can ensure that the image data of each line for one line is encoded at an actual compression rate equal to or higher than a specified compression rate. In this case, as in FIG. 15, the data amount of one line of uncompressed image data is ML bits, the specified compression rate is α (α <1), and the compressed image data memory 51 is effective on one line. When the storage capacity is SL bits, N × ML> SL> N × ML × α is established. That is, if the compressed image data memory 51 is, for example, an SRAM, it means that the size in the word line direction is shortened.

  Also in such a compressed image data memory 61, the head data of the compressed image data of each line is stored in the storage element at the same address of each line of the image compression memory, as in FIG. In this way, the head address of each line can be easily detected.

  This is particularly preferable in that the data processing unit 62 that processes data after decoding the output from the compressed image data memory 61 can easily specify the start address of each line accompanying the data processing.

4). Fourth Embodiment From the compressed image data memories 51 and 61 shown in FIGS. 12 and 16, one line of compressed image data is read out in synchronization with a horizontal synchronizing signal for driving the liquid crystal panel 2. On the other hand, data is written to the compressed image data memories 51 and 61 at high speed according to the control of the baseband engine 1 on the upstream side. Therefore, the reading speed is slower than the writing speed. In this case, as shown in FIG. 18, there may occur a situation in which the write address overtakes the read address on the same line Ln of the compressed image data memories 51 and 61. At this time, new data is written in the addresses after the read address on the line Ln, so that noise display is performed. In order to prevent this, the following measures are implemented.

4.1. Write Timing Setting Taking the embodiment of FIG. 16 as an example, as shown in FIG. 19, the display control IC 60 sends a write start signal RS (see FIG. 20) synchronized with the vertical synchronization signal Vsync to the baseband engine 1. . The timing T1 at which writing is started in the compressed image data memory 51 based on the writing start signal RS is always preceded by the reading start timing T2 with respect to the compressed image data memory 51. In this way, the high-speed writing is performed in advance, so that the adverse effects shown in FIG. 18 can be prevented.

  As shown in FIG. 19, the display control IC 6 has first and second stage line buffers 63 and 64 in the subsequent stage of the decoder 20. The first stage line buffer 63 sequentially stores the image data from the decoder 20. After the image data for one line is prepared in the first stage line buffer 63, the image data for one line is latched in the second stage line buffer 64, and the image data for one line is received from the second stage line buffer 64. Parallel output.

4.2. In FIG. 21, the write start signal RS in FIG. 20 is not used, but instead, the first and second line buffers 65 and 66 are provided before and after the compressed image data memory 61. The compressed image data for one line is simultaneously written in the compressed image data memories 51 and 61 from the first line buffer 65 in one access. On the other hand, compressed image data for one line is simultaneously output from the compressed image data memories 51 and 61 in one access and stored in the second line buffer 66. The compressed image data is sequentially output from the second line buffer 66 to the decoder 20. In this way, even if the write timing is not adjusted, the compressed image data for one line is simultaneously written / read in one access to the compressed image data memory 61, so that the disadvantage shown in FIG. 18 can be prevented.

  In FIG. 22, compressed image data for one line is alternately stored sequentially between the compressed image data memories 51 and 61 and the decoder 20, and first and second read line buffers 67 and 68 that are sequentially read sequentially. Have For example, it is assumed that after one line of compressed image data is stored in the first read line buffer 67, the next one line of compressed image data is sequentially read and stored in the second read line buffer 68. . At this time, it is assumed that writing of new compressed image data is started for the same line. In this case, the reading to the second read line buffer 68 is on standby until the writing to the same line is completed. The storage of the compressed image data in the second read line memory 68 may be performed again from the head address of the line where writing has been completed, or may be restarted from the address at which writing has been stopped. During this time, since the compressed image data is supplied from the first read line buffer 67 to the decoder 20, the display data does not underflow.

5. Image encoder (encoder)
Hereinafter, an embodiment of the image encoding device 20 used in the above-described embodiment will be specifically described. In the following embodiment, the guaranteed specified compression rate is, for example, 50%, and it is guaranteed that the pixel data is always encoded at a high compression rate equal to or higher than the specified compression rate.

5.1. Image Input Unit FIG. 23 is a block diagram of the image encoding device 10. The image input unit 100 inputs pixel data serially, and outputs each pixel data of a plurality of, for example, four pixels P, X, A, and B adjacent on one line in parallel. Here, as shown in FIG. 24, the pixel X is the encoding target pixel, the pixel P is the preceding pixel of the encoding target pixel X, and the pixel A is the first subsequent pixel of the encoding target pixel X. , Pixel B is the second succeeding pixel of the encoding target pixel X. The data of each pixel may be either R, G, B pixel data or YUV (luminance signal + color difference signal) pixel data. In the present embodiment, each pixel data is a total of 24-bit data in which sub-vicels are each composed of 8-bit R, G, and B.

5.2. Predictive coding unit (lossy coding unit)
The predictive encoding unit 110, which is an example of the irreversible encoding unit, sets the pixel data (24-bit data) of the encoding target pixel X to a specified compression rate (for example, 50%) in the irreversible mode (also referred to as Lossy mode). Is encoded into fixed-length data (for example, 12-bit data). This predictive encoding unit 110 performs DPCM (Differential Pulse Code Modulation) encoding that performs PCM encoding on the difference between adjacent pixels, and uses a look-up table in the software as in the predictive encoder of Patent Document 2. However, in this embodiment, it is configured by hardware as shown in FIG. However, although the predictive encoder of Patent Document 2 performs variable length coding such as a Huffman code, in this embodiment, variable length coding is not employed in order to ensure a specified compression rate.

  25 is a block diagram of the predictive coding unit 110 shown in FIG. The sub-pixel R, G, B data constituting the encoding target pixel X is subtracted from the R, G, B data of the preceding pixel P by the subtractor 111. This difference data is quantized and encoded by the nonlinear quantization unit 112 (details will be described later). While the encoded data is output, it is inversely quantized for each of R, G, and B by the nonlinear inverse quantization unit 113 that performs the reverse operation of the nonlinear quantization unit 112. The inversely quantized R, G, B data is added to the R, G, B data of the preceding pixel P by the adder 114 and stored in the one-pixel delay registers 115R, 115G, 114B. The data stored in the one-pixel delay registers 115R, 115G, and 115B is used as the pixel data of the preceding image difference P for the next encoding target pixel X. That is, by switching the switch 116, the R, G, B data of the preceding pixel P is subtracted by the subtractor 111 for each sub-pixel R, G, B of the next encoding target pixel X.

  The nonlinear quantization unit 111 nonlinearly quantizes a 9-bit (-256 to 255) difference value (1 bit is a plus / minus sign) to 4 bits. However, since “1111” is used as an encoding mode transition code (reversible mode → irreversible mode), 15 codes from 0 to 14 are assigned as quantization values. Note that the coding mode transition code from the irreversible mode to the reversible mode is selected based on a signal from the coding control unit 150 shown in FIG. Each 8-bit R, G, B data is quantized into 4 bits, and 24-bit data is encoded into 12-bit data (4 bits × 3) in units of pixels. It is encoded with.

  The nonlinear quantization unit 111 includes a plurality of types of quantization tables, and changes the quantization table to be used according to the value (predicted value) immediately before the encoding target pixel X. Since the range of the prediction error (difference from the input value) is limited to a certain range depending on the predicted value, the quantized representative value is arranged only in the range and the limited encoded code is used effectively. It is a device for. That is, the input R, G, B data is 8 bits (0 to 255), and the predicted value that is the value of the preceding pixel P is known, so that the prediction error that is the difference between the input value and the predicted value is The possible range is limited by the predicted value. As an example, if the predicted value is 0, the prediction error that is the difference between the input value and the predicted value does not become negative, so the range of the positive region (0 to 255) may be used as the quantization table.

  A specific example of the nonlinear quantization table is shown below.

1) When predicted value is 96 or more and less than 160 In this case, the range of possible prediction errors is -159 to 159. Therefore, a quantization code is assigned as shown in FIG.

  Here, linear quantization means that the prediction error (9 bits, 1 bit is a sign) as a result of subtracting the encoding target pixel X and the preceding pixel P is closer to 0 (the encoding target pixel X and the preceding pixel P are preceded). The smaller the difference from the pixel P, the smaller the quantization. This is because a slight difference in color is clearly recognized. On the other hand, the further the prediction error is from 0 (the larger the difference between the encoding target pixel X and the preceding pixel P and the preceding pixel P), the coarser the quantization. This is because it is difficult to detect a subtle difference in color when the difference in luminance components is large. In this way, non-linear quantization that is not linear but non-linear depending on the magnitude of the prediction error is non-linear quantization. Also in FIG. 26, the prediction error is fine near zero, and is quantized coarsely as the absolute value of the prediction error increases. As is apparent from FIG. 26, the data quantized by the nonlinear quantization unit 112 is irreversible data.

2) When the predicted value is 64 or more and less than 96 The range of possible prediction errors is -95 to 191. Therefore, a quantization code is assigned as shown in FIG.

3) When the predicted value is 160 or more and less than 192 The range of possible prediction errors is -191 to 95. Therefore, a quantization code is assigned as shown in FIG.

4) When the predicted value is 32 or more and less than 64 The range of possible prediction errors is -63 to 223. Therefore, a quantization code is assigned as shown in FIG.

5) When the predicted value is 192 or more and less than 224 The range of possible prediction errors is -223 to 63. Therefore, a quantization code is assigned as shown in FIG.

  The linear inverse quantization unit 113 may perform an operation opposite to the operation of the linear quantization unit 112 described above, and in this case, the inverse quantization table may be switched according to the immediately preceding pixel value.

5.3. First moving dictionary encoding unit (lossless encoding unit)
The leading movement dictionary encoding unit 120, which is an example of a lossless encoding unit that encodes in a lossless mode (also referred to as a lossless mode), uses R, G, B format pixel data (24 bits) as it is as one uncompressed data. Handle and encode as fully decodable lossless data. The encoding method itself by the head movement dictionary is basically the same as that of Patent Document 2 (Japanese Patent Laid-Open No. 2001-257888). However, in this embodiment, variable-length coding such as Huffman code is not performed. This is because the specified compression rate cannot be guaranteed.

  In this embodiment, a dictionary of pixel values is shared between encoding and decoding, and the dictionary is updated by moving the head. Accordingly, pixel values that are frequently used are placed at the beginning of the dictionary. The dictionary size consists of 8 indexes from 0 to 7. Encoding can be performed by variable-length encoding this index.

  The left column of FIG. 31 shows, for example, seven colors stored in an initialized dictionary. An example of initialization is an example, and other colors may be used, or the same meal may be used. FIG. 31 shows how the dictionary is rearranged from the left column to the right column when the input color is red. If the color of the input pixel is red, index 2 is moved to the beginning of the dictionary. Then, white and black are shifted backward. On the other hand, if the input pixel color (for example, X) is not in the dictionary, X (24 bits) to be newly registered is output. In this case, the condition including the escape code of index 8 (conditions 1 to 3 in FIG. 33) is encoded, X is registered at the head of the dictionary, and the originally registered color is shifted backward. As a result, the color originally registered in the index 7 is lost from the dictionary.

  The index value indicating the position registered in the dictionary, the conditional code that performs lossless encoding when it does not exist in the dictionary, and the code that indicates the transition from the lossless mode to the lossy mode are all reduced to 1/6 of 24 bits per pixel. It is expressed as a compressed 4-bit fixed length code. The meaning of the 4-bit code is as shown in FIG.

  The left column of FIG. 32 is a code in which the reversible mode is continued, and the right column of FIG. 32 is a code immediately after the transition from the lossy mode to the reversible mode. The left column and the right column in FIG. 32 differ in the encoding operation when the pixel data X of the encoding target pixel does not exist in the dictionary. Note that the coding mode transition code shown in FIG. 32 means a transition from the irreversible mode to the reversible mode, and this code is coded based on the head movement dictionary based on the signal from the coding control unit 150 shown in FIG. Output from the unit 120.

  Here, the encoded content shown in FIG. 32 shows a mode in which 2 pixels (X, A) or 3 pixels (X, A, B) are encoded together. For this purpose, as shown in FIG. 23, a peripheral pixel value evaluation unit 130 is provided.

5.4. Peripheral Pixel Value Evaluating Unit In FIG. 23, a peripheral pixel value evaluating unit 130 evaluates the relationship between pixel data of, for example, four pixels (P, X, A, B: see FIG. 2) input in parallel from the pixel input unit 110. To do. In the present embodiment, the peripheral pixel value evaluation unit 130 evaluates whether three or two of the four pixels have a certain relationship. Specifically, as shown in FIG. 33 or FIG. 34, it is evaluated whether the pixel data of three pixels or two pixels is the same.

  Here, in the present embodiment, the condition is that the 24-bit pixel data is equal to each other. For example, at least one upper bit of at least three subpixels constituting one pixel matches among the plurality of pixels, and the least significant bit or Only the lowest bit group on the least significant side is different, that is, ranges that can be regarded as substantially the same may be defined as the same.

5.5. Surplus Code Counter The surplus code counter 140 shown in FIG. 23 counts up the surplus code bits (surplus code) to achieve a specified compression rate (for example, 50%), and counts down surplus bits that are consumed. If the accumulated count value of the surplus counter 140 does not fall below an initial value (for example, 0 = means a specified compression ratio) (for example, does not become a negative value), the specified compression ratio can be achieved. In this embodiment, the surplus counter 140 is achieved. The cumulative count value is controlled so that it does not fall below the initial value. As a result, the encoding in the lossless mode always ensures a high compression rate that is equal to or higher than the specified compression rate by the control of the surplus counter. Since encoding in the lossy mode is performed with a fixed-length code that provides a specified compression rate, the total compression rate in the lossless / irreversible mode is always higher than the specified compression rate. Can be guaranteed.

  Specifically, in the reversible mode, if X is present in the dictionary, 8 bits for a compression rate of 50% (12-bit target) when 24 bits of one pixel data can be encoded with a fixed length code of 4 bits. (In this case, 8 bits are referred to as a surplus code). The surplus code counter 140 is a counter for counting surplus bits generated when encoding can be performed with less than 12 bits per pixel. The surplus code counter 140 counts down when surplus bits are consumed, such as when the pixel data X (24 bits) of the encoding target pixel is directly output as a code. Note that one count value indicates a 4-bit surplus code. Further, in the present embodiment, the surplus code counter 140 counts up / down only in the reversible mode and does not count in the lossy mode. In the lossy mode, all are encoded with a fixed length code of 12 bits per pixel (4 bits per sub-vixel), the compression rate is always 50%, and no surplus code is generated and the surplus code is not consumed. Because.

  The surplus counter 140 can be reset every time encoding of all pixels in one line is completed. Since the peripheral pixel value evaluation unit 130 evaluates the relationship with respect to pixels on one line, the pixel data can be obtained while looking at the correlation between pixels for each line, although this embodiment compresses each pixel. Is encoded. Therefore, management so that the surplus counter 140 does not fall below the initial value after reset (that is, a value equal to the specified compression rate) may be performed for each line. In this way, the memory that stores the code after encoding the pixel data sets the total number of bits of the pixel data on one line of the screen to NL, and sets them to ML effective memory elements (one In the case of storing 1 bit in a memory element), the maximum number ML of effective memory elements on one line of the memory is NL × α <when the specified compression ratio is α (α <1). Since ML <NL, the size of the memory in one line direction can be reduced.

  However, the surplus counter 140 may be reset every time encoding of all pixels in one line is completed. As a whole screen, the surplus counter 140 may not be less than the initial value after reset (that is, a value equal to the specified compression rate). In this case, the memory for storing the code after the pixel data is encoded is when the total number of bits of all the pixel data constituting one screen is N and stored in M effective memory elements in the memory. In this case, the maximum number M of effective memory elements in the memory is N × α <M <N when the specified compression ratio is α (α <1), and the memory size can be reduced.

  In order to control the transfer frequency, bit width, and intermittent transfer clock, the actual compression rate per line is obtained from the count value when the surplus code counter 140 is reset for each line, and is reset for each frame. The actual compression rate per frame is obtained from the count value at the time of recording.

5.6. Encoding Control Unit The encoding control unit 150 illustrated in FIG. 23 is configured to switch between the reversible mode and the irreversible mode based on outputs from the head movement dictionary encoding unit 120, the surrounding pixel value evaluation unit 130, and the surplus code counter 140. The transition condition and the continuation condition of the lossless mode are determined to determine transition / continuation, and in accordance with the determination, the predictive encoding unit 110, the head movement dictionary encoding unit 120, the surplus code counter 140, and the code It controls the multiplexing / multiplexing unit 160.

  Specifically, the encoding control unit 150 determines whether or not any transition condition from the irreversible mode to the reversible mode illustrated in FIG. 33 is satisfied, whether the head movement dictionary encoding unit 120, the surrounding pixel value evaluation unit, Judgment is made on the basis of outputs from 130 and the surplus code counter 140. Of the conditions shown in FIG. 33, the encoding control unit 150 first preferentially determines whether or not the image data X of the encoding target pixel is registered in the dictionary shown in FIG. When the image data X of the encoding target pixel is not registered in the dictionary, the encoding control unit 150 determines the conditions 1, 2, and 3 shown in FIG. 33 in that order. When the encoding control unit 150 determines that any transition condition from the lossy mode to the lossless mode shown in FIG. 33 is satisfied, the encoding control unit 110 controls the prediction encoding unit 110 as shown in FIG. Then, an encoding mode transition code representing a transition from the irreversible mode to the reversible mode by a fixed length code (4 bits) is output. As shown in FIG. 33, when the image data X of the encoding target pixel is registered in the dictionary shown in FIG. 31, a dictionary index (4 bits) is output from the head movement dictionary encoding unit 120. The As shown in FIG. 33, when the image data X of the encoding target pixel is not registered in the dictionary shown in FIG. 31 and satisfies any of the conditions 1 to 3, the encoding control unit 150 controls the leading moving dictionary encoding unit 140 to output a code representing each condition by a fixed-length code (4 bits). At this time, the head movement dictionary encoding unit 140 registers the image data X of the encoding target pixel at the head of the dictionary as shown in FIG. Furthermore, the encoding control unit 150 causes the surplus code counter 140 to count down necessary points when the conditions 2 and 3 shown in FIG.

  Only when the encoding control unit 150 determines that none of the transition conditions from the irreversible mode to the reversible mode shown in FIG. Nonlinear quantized data represented by (4 bits) is output.

  Further, the encoding control unit 150 determines whether or not the condition for maintaining the lossless mode shown in FIG. 34 is satisfied based on the outputs from the leading movement dictionary encoding unit 120, the surrounding pixel value evaluation unit 130, and the surplus code counter 140. Judgment.

  In order to achieve a high compression rate equal to or higher than the specified compression rate (50%), the encoding control unit 150 moves the head within a range in which the count value of the surplus counter 140 does not become a value indicating a compression rate lower than the specified compression rate. It is important to continue the encoding operation in the dictionary encoding unit 120. This is because the predictive encoding unit 110 can only achieve a compression rate equal to the specified compression rate, and outputs a coding mode transition code represented by a fixed-length code in order to transition between the lossless mode and the lossy mode. This is because the code is consumed. In addition, since the predictive encoding unit 110 compresses in the lossy mode, it cannot be completely decoded into the original pixel data.

  In FIG. 34, when the image data X of the encoding target pixel is registered in the dictionary shown in FIG. 31, the single compression rate of the pixel data X of the encoding target pixel is the specified compression rate (50%, 12 bits). ), And only a fixed-length code (4-bit) dictionary index needs to be output. This is the first priority processing performed by the head movement dictionary encoding unit 120. By performing the processing of the first priority, the surplus code counter 140 can count up 2 points (8 bits).

  34, the image data X of the encoding target pixel is not registered in the dictionary shown in FIG. 31, and the relationship between the pixels from the peripheral pixel value evaluation unit 130 is any one of the conditions 4 to 7. When the relationship is satisfied, the average compression rate of the pixel data of a plurality of pixels encoded together is a compression rate higher than the specified compression rate. This aspect is the process of the second priority processing order by the head movement dictionary encoding unit 120, and the pixel data of a plurality of pixels are encoded in association with each other. Among the items of the second priority processing order shown in FIG. 34, the conditions 4 to 7 are determined in order from the youngest number. By performing the second priority processing, the surplus code counter 140 can count up 2 points (8 bits).

  In FIG. 34, the image data X of the encoding target pixel is not registered in the dictionary shown in FIG. 31 and is counted by the extra code counter 140 and the relationship between the pixels from the peripheral pixel value evaluation unit 130. When the accumulated surplus code satisfies any of the conditions 8 to 10, the single compression rate of the pixel to be encoded (condition 10 in FIG. 34) or a plurality of pixels that are encoded together The apparent average compression ratio of data (conditions 8 and 9 in FIG. 34) becomes equal to the specified compression ratio. Here, the apparent single compression rate or the average compression rate is a compression rate per pixel calculated by subtracting a part or all of the accumulated surplus codes from the code originally required for encoding. In the example of condition 8 in FIG. 34, the average compression rate per pixel calculated by subtracting the surplus code (4 bits) from the code (28 bits) originally required for encoding for 2 pixels is 100 × (28-4). ) / (2 × 24) = 50%, which is equal to the specified compression rate. However, in this case, since the surplus code consumes 4 bits, the surplus code counter 140 counts down by 1 point (4 bits). When the condition 8 is not satisfied, the judgment is made in the order of the conditions 9 and 10, and the consumed surplus code is counted down by the surplus counter 140.

  The encoding control unit 150 determines the conditions illustrated in FIG. 34 in the order of priority processing order, and when any of the conditions illustrated in FIG. 34 is satisfied, the lossless mode is continued and the specified compression rate (50%) is maintained. The control is performed so that the surplus codes are stored by increasing the number of opportunities for high compression. Then, only when none of the conditions shown in FIG. 34 is satisfied, the encoding control unit 150 outputs a signal to the predictive encoding unit 110, and the encoding mode transition code corresponding to the code number 15 (reversible mode → non-reversal mode → non-existing) Reversible mode).

  The encoding control unit 150 controls the code multiplexing unit 160 so that the control result signal described above is output from the code multiplexing unit 160 shown in FIG. That is, the encoding control unit 150 includes the nonlinear quantized data from the predictive encoding unit 110 (including a 4-bit, mode transition code from the lossless mode to the lossy mode) and the encoding target pixel from the image input unit 100. A signal for controlling which code to output, such as pixel data X (24 bits), dictionary index from the head movement dictionary encoding unit 120, a condition code, a mode transition code from the irreversible mode to the reversible mode, is encoded Output to the multiplexing / multiplexing unit 160.

5.7. Code Multiplexing Control Unit FIG. 35 is a diagram for explaining the operation of the code multiplexing control unit 160 that operates according to the control of the coding control unit 150.

  First, when the pixel data X of the first encoding target pixel is input to the image input unit 100, for example, the first pixel data X is encoded by the prediction encoding unit 110. That is, the R, G, B subpixel data constituting the image data X is nonlinearly quantized, and a 12-bit nonlinear quantization code compressed at a specified compression rate (50%) is output from the code multiplexing unit 160. Is done.

  If all the pixel data X does not satisfy the transition condition from the lossy mode to the lossless mode in FIG. 33, all the pixel data X are encoded by the lossy encoding mode loop shown in FIG. 35 and compressed. The rate is 50%, and the specified compression rate (50%) is achieved.

  However, such a case is rare, and any one of the image data X or the image data of the surrounding pixels satisfies the transition condition from the irreversible mode to the reversible mode in FIG. In this case, the code combined according to the conditions shown in FIG. For example, when the image data X of the encoding target pixel is registered in the dictionary shown in FIG. 31, a total of 8 bits of the encoding mode transition code (4 bits) + the dictionary index (4 bits) is the code multiplexing unit. 160 is output. If the image data X of the encoding target pixel is not registered in the dictionary shown in FIG. 31 and if, for example, the condition 1 shown in FIG. 33 is satisfied, the encoding mode transition code (4 bits) + condition The code multiplexing unit 160 outputs a total of 32 bits: a code indicating 1 (4 bits) + pixel data X (24 bits).

  When the pixel data X of the last pixel to be encoded satisfies the condition shown in FIG. 33, all the processing is completed by the encoding in the head movement dictionary encoding unit 120.

  Otherwise, the process proceeds to the lossless encoding mode loop shown in FIG. Here, as long as any of the conditions shown in FIG. 34 is satisfied, the processing in the loop is continued. In this case, the output from the code multiplexing unit 160 is as shown in FIG. For example, when the image data X of the encoding target pixel is registered in the dictionary illustrated in FIG. 31, only the dictionary index (4 bits) is output from the code multiplexing unit 160. If the image data X of the encoding target pixel is not registered in the dictionary shown in FIG. 31 and the condition 4 shown in FIG. 34 is satisfied, for example, the pixel data X, A, and B of three pixels are The code multiplexing unit 160 outputs a total of 28 bits of the code indicating the condition 4 (4 bits) + pixel data X (24 bits) as the associated code.

6). Image decoding device (decoder)
FIG. 36 shows the image decoding device 20 used in the above-described embodiment. Based on the encoding syntax shown in FIG. 35 in the above-described image encoding device, a code is read, decoded (decoded), and a pixel Data is output. As shown in FIG. 36, the image decoding device 20 includes a code separation control unit 200, a prediction decoding unit 210, a head movement dictionary decoding unit 220, and a pixel output control unit 230.

6.1. Code Separation Control Unit The operation of the code separation control unit 200 differs depending on the first pixel data in the above-described image coding apparatus, the irreversible mode, the transition from the irreversible mode to the reversible mode, and the reversible mode. Since the code separation control unit 200 knows in which mode the received code is encoded by the encoding mode transition code, the code separation control unit 200 performs control according to the above four modes.

6.1.1. When Decoding Start As described with reference to FIG. 35, when decoding starts, pixel data is embedded in the compressed stream output from the code multiplexing unit 160. Therefore, the code separation control unit 200 sends the 24-bit pixel data directly to the image output control unit 230.

6.1.2. In the lossy encoding mode In the lossy mode, the code separation control unit 200 reads the quantized values for each component shown in FIGS. 26 to 30 and the like from the compressed stream, and sends them to the prediction decoding unit 210.

6.1.3. At the time of transition from the lossy mode to the lossless mode When the code separation control unit 200 receives the code indicating the coding mode transition shown in FIG. 33, the decoding mode is changed from the lossy mode to the lossless mode. Specifically, the code separation control unit 200 determines whether the code is a dictionary index or a code indicating the conditions 1, 2, and 3 by looking at the 4 bits following the code indicating the coding mode transition. If the received code is a dictionary index, the code separation control unit 200 sends the received code to the first moving dictionary decoding unit 220. If not, the code separation control unit 200 extracts 24-bit pixel data and sends it directly to the pixel output control unit 230. Then, a control signal based on the condition code is sent to the pixel output control unit 230.

6.1.4. In the reversible mode In the reversible mode, the code separation control unit 200 looks at the 4-bit code shown in FIG. 34 and determines whether it is a dictionary index or the condition 4-10. If the received code is a dictionary index, the code separation control unit 200 sends the received code to the first moving dictionary decoding unit 220. If not, the code separation control unit 200 extracts 24-bit pixel data and sends it directly to the pixel output control unit 230. Then, a control signal based on the condition code is sent to the pixel output control unit 230.

6.2. Prediction Decoding Unit and Leading Moving Dictionary Decoding Unit The prediction decoding unit 210 performs irreversible decoding of pixel data by performing the reverse operation of the prediction encoding unit 110 shown in FIG. Similarly to the head movement dictionary encoding unit 120, the head movement dictionary decoding unit 220 has a dictionary equivalent to that shown in FIG. If pixel data not registered in the dictionary is input, the dictionary is registered in the same manner as in FIG. On the other hand, when the dictionary index is received, the pixel data at the registered position in the dictionary is output to the pixel output control unit 230.

6.3. Pixel Output Control Unit The pixel output control unit 230 includes pixel data from the code separation control unit 200, pixel data decoded by the predictive decoding unit 210, pixel data decoded by the top moving dictionary decoding unit 220, and code separation Based on the control signal from the control unit 200, the output of the decoded pixel data is controlled.

  As shown in FIG. 37, the pixel output control unit 230 includes three multiplexers MUX0 to MUX2, three registers R0 to R2, and a control circuit 232. The control circuit 232 controls the multiplexers MUX0 to MUX2 based on the control signal separated by the code separation control unit 200.

  The pixel output control unit 230 also differs depending on the first pixel data in the above-described image encoding device, the irreversible mode, the transition from the irreversible mode to the reversible mode, and the reversible mode.

6.3.1. First Pixel The pixel data of the first pixel is separated by the code separation control unit 200 in FIG. 36, and then directly stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232, and output in the next cycle. The

6.3.2. Non-reversible mode In the non-reversible mode, the pixel data supplied from the predictive decoding unit 210 is stored in the register R0 via the multiplexer MUX0 and output after one cycle.

6.3.3. Lossless mode Output control is performed as follows according to the encoding conditions shown in FIG.

6.3.3.1. When the pixel data X is registered in the dictionary, the top movement dictionary decoding unit 220 reads out the pixel data at the registration position indicated by the dictionary index from the dictionary, stores it in the register R0 via the multiplexer MPU0, and outputs it after one cycle.

6.3.3.2. When the condition 4 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 in FIG. 37, and the same value X is obtained via the multiplexers MUX1 and MUX2. It is also stored in the registers R1 and R2. That is, the pixel data X is stored in all the registers R12 and R2 (condition 4 is X = A = B). Then, the same pixel data X is sequentially output over three cycles. In addition, while the same pixel data X is output, new code acquisition is suppressed.

6.3.3.3. When the condition 5 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232 and is stored in the register R0 until just before. The pixel data P is also stored in the registers R1 and R2 via the multiplexers MUX1 and 2 (condition 5 is P = A = B), and the pixel data X, P, and P are sequentially output over 3 cycles. To do. During this time, new code acquisition is suppressed.

6.3.3.4. When the condition 6 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the MUX0 controlled by the control circuit 232, and is also stored in the register R1 via the multiplexer MUX1. Store (Condition 6 is one of the requirements where X = A). Further, the pixel data P that has been stored in the register R0 until immediately before is stored in the register R2 via the multiplexer MUX2 (condition 6 is another requirement of P = BT). Then, the pixel data X, X, and P are sequentially output over three cycles. During this time, new code acquisition is suppressed.

6.3.3.5. When the condition 7 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232, and is stored in the register R2 via the multiplexer MU2. (Condition 7 is one of the requirements where X = B). Further, the pixel data P that has been stored in the register R0 until immediately before is stored in the register R1 via the multiplexer MUX1 (condition 7 is another requirement of P = A). Then, pixel data X, P, and X are sequentially output over three cycles. During this time, new codes are not taken in).

6.3.3.6. When the condition 8 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232, and is stored in the register R0 until just before. The pixel data P is stored in the register R1 via the multiplexer MUX1 (condition 8 requires P = A). Then, pixel data X and P are sequentially output over two cycles. During this time, new codes are not taken in).

6.3.3.7. When the condition 9 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232, and is stored in the register R2 via the multiplexer MU2. (Condition 9 requires X = A). Then, pixel data X and X are sequentially output over two cycles. During this time, new codes are not taken in).

6.3.3.7. When the condition 10 in FIG. 34 is met, the pixel data X captured by the code separation control unit 200 is stored in the register R0 via the multiplexer MUX0 controlled by the control circuit 232, and is output in the next cycle.

3.4. When the mode transition from the irreversible mode to the reversible mode When the code of the condition 1 is received, the operation is the same as that of the condition 4 described above. When the code of the condition 2 is received, the operation of the condition 9 described above is received. When the code for condition 3 is received, the operation is the same as that for condition 10 described above.

  The image data is encoded by the image encoding device, decoded by the image decoding device, displayed on the liquid crystal display device, and compared with the image directly displayed without image compression. Apparently, it could not be identified with the naked eye.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  In the above-described embodiment, the liquid crystal display of the mobile phone has been described as an example. Needless to say.

It is a schematic explanatory drawing which shows an example of the image output system of this invention. It is a block diagram of the circuit which makes transfer frequency variable based on a compression rate. 3A to 3D are timing charts of the circuit illustrated in FIG. FIG. 3 is a block diagram of a circuit that is a modification of FIG. 2. FIG. 10 is a block diagram of a circuit which is still another modification of FIG. 2. It is a schematic explanatory drawing for demonstrating the terminal of driver IC. 6 is a timing chart of an operation example in which the bit width per transfer clock is variable based on the compression rate. 6 is an operation timing chart in which a transfer clock is intermittently clocked. It is a block diagram showing an example of data compression by a color signal conversion circuit. It is a block diagram which shows another example of data compression in a color signal conversion circuit. Uncompressed. It is a timing chart for demonstrating switching of a compressed image. It is a schematic explanatory drawing for demonstrating the other example of the image output system of this invention. It is a schematic explanatory drawing for demonstrating the capacity | capacitance of compressed image data memory. It is a schematic explanatory drawing for demonstrating the capacity | capacitance of the compression image data memory when it is set as the high compression rate using color signal conversion. It is a schematic explanatory drawing for demonstrating the capacity | capacitance of the compression image data memory when the compression rate of one line is ensured. It is a schematic explanatory drawing of other embodiment of this invention. It is a schematic explanatory drawing for demonstrating the capacity | capacitance of the compression image data memory when processing N frame image and compressing it to the image of 1 frame. It is a schematic explanatory drawing for demonstrating the phenomenon in which a memory write address overtakes a memory read address. It is a block diagram for demonstrating embodiment which sets the timing of a write start signal. FIG. 20 is an operation chart of the configuration shown in FIG. 19. FIG. It is a block diagram for demonstrating the modification of FIG. It is a block diagram for demonstrating the further another modification of FIG. It is a block diagram of the image coding apparatus which concerns on embodiment of this invention. It is a schematic explanatory drawing for demonstrating the image data input into the image input part of FIG. 23 sequentially. It is a block diagram which shows an example of the prediction encoding part shown in FIG. It is a schematic explanatory drawing which shows the example of a nonlinear quantization table in case a predicted value is 96-160. It is a schematic explanatory drawing which shows the example of a nonlinear quantization table in case a predicted value is 64 or more and less than 96. It is a schematic explanatory drawing which shows the example of a nonlinear quantization table in case a predicted value is 160-192. It is a schematic explanatory drawing which shows the example of a nonlinear quantization table in case a predicted value is 32-64. It is a schematic explanatory drawing which shows the example of a nonlinear quantization table in case a predicted value is 192 or more and less than 224. It is a schematic explanatory drawing for demonstrating the dictionary which the head movement dictionary encoding part shown in FIG. 23 or the head movement dictionary decoding part shown in FIG. 37 has. FIG. 24 is a schematic explanatory diagram for explaining the contents of 16 types of codes represented by fixed-length codes (4 bits) in the head movement dictionary encoding unit shown in FIG. 23. It is schematic description for demonstrating the transition conditions from a lossy encoding mode to a lossless encoding mode. It is a schematic explanatory drawing for demonstrating the continuation conditions of a lossless encoding mode. It is a figure which shows the code syntax output from the code multiplexing part shown in FIG. It is a block diagram of the image decoding apparatus which concerns on embodiment of this invention. It is a figure which shows an example of the block diagram of the pixel output control part shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Baseband engine (1st integrated circuit), 2 Liquid crystal panel, 5 Driver IC (2nd integrated circuit), 10 Image coding apparatus, 20 Image decoding apparatus, 33 Compression ratio setting part, 34 Oscillator, 35 Panel data Generation unit, 36 transfer clock generation unit, 37 data transfer unit, 40, 42 color signal conversion circuit, 50 driver IC (second integrated circuit), 51, 61 compressed image data memory, 60 display control IC (second integration) Circuit), 65-68 line buffer, 100 image input unit, 110 prediction encoding unit (irreversible encoding unit), 111 subtractor, 112 nonlinear quantization unit, 113 nonlinear inverse quantization unit, 114 adder, 115R- 115B register, 120 first moving dictionary encoding unit (lossless encoding unit), 130 peripheral pixel value evaluation unit, 140 surplus code count , 150 the encoding control unit, 160 code multiplexing unit, 200 code separation controller, 210 prediction decoding unit, 220 first move dictionary decoding unit, 230 a pixel output control unit, 232 control circuit, R0-R2 register, MUX0-MUX2 multiplexer

Claims (27)

In an image output system for transferring image data from a first integrated circuit to a second integrated circuit via a data bus and outputting an image based on an output of the second integrated circuit,
An image encoding device that encodes the image data is provided in the first integrated circuit,
An image output system comprising an image decoding device for decoding compressed image data received via the data bus in the second integrated circuit. In claim 1,
The image output system is characterized in that the image encoding device is guaranteed to encode the image data of each frame for one frame at an actual compression rate equal to or higher than a specified compression rate. In claim 1,
The image output system is characterized in that the image encoding device is guaranteed to encode the image data of each line for one line at an actual compression rate equal to or higher than a specified compression rate. In claim 2 or 3,
The first integrated circuit includes a transfer clock generation unit that generates a transfer clock for transferring the image data to the data bus,
The transfer clock generation unit divides the reference clock based on the specified compression rate, and lowers the transfer clock when transferring the compressed image data than when transferring the uncompressed image data. A featured image output system. In claim 2,
The first integrated circuit includes:
A memory for storing the compressed image data from the image encoding device;
A transfer clock generator for generating a transfer clock for transferring the code to the data bus;
Have
The image encoding device outputs an actual compression rate when an image for one frame is compressed,
The transfer clock generation unit divides the reference clock based on the actual compression rate of one frame, and varies the frequency of the transfer clock for transferring the compressed image data for one frame for each frame. An image output system characterized by that. In claim 3,
The first integrated circuit includes:
A memory for storing the compressed image data from the image encoding device;
A transfer clock generator for generating a transfer clock for transferring the code to the data bus;
Have
The image encoding device outputs an actual compression rate for each line,
The transfer clock generator divides a reference clock based on the actual compression rate of one line, and varies the frequency of the transfer clock for transferring the compressed image data for one line for each line. An image output system characterized by that. In claim 2 or 3,
The image output system according to claim 1, wherein the first integrated circuit includes a bit width variable unit that varies a bit width transferred by one clock of the transfer clock based on the specified compression rate. In claim 2,
The first integrated circuit includes:
A memory for storing the compressed image data from the image encoding device;
A bit width variable unit that varies a bit width transferred by one clock of the transfer clock;
Have
The image encoding device outputs an actual compression rate for each frame,
The bit width varying unit varies the bit width for each frame based on the actual compression rate of one frame. In claim 3,
The first integrated circuit includes:
A memory for storing the compressed image data from the image encoding device;
A bit width variable unit that varies a bit width transferred by one clock of the transfer clock;
Have
The image encoding device outputs the actual compression rate for each line;
The bit width varying unit varies the bit width for each line based on the actual compression rate of one line. In claim 2 or 3,
The first integrated circuit device includes a transfer clock generation unit that generates a transfer clock for transferring the compressed image data to the data bus,
The transfer clock generation unit outputs the transfer clock only during a period in which the compressed image data is transferred out of a transfer period in which uncompressed image data is transferred based on the specified compression rate, and the transfer clock is transmitted in a remaining period. An image output system characterized by not outputting a clock. In claim 2,
The first integrated circuit device includes:
A memory for storing the compressed image data from the image encoding device;
A transfer clock generator for generating a transfer clock for transferring the code to the data bus,
The image encoding device outputs the actual compression rate for each frame;
The transfer clock generation unit is configured to transfer the compressed image data for one frame only during a period in which the uncompressed image data for one frame is transferred based on the actual compression rate of one frame. An image output system which outputs a transfer clock and does not output the transfer clock in the remaining period. In claim 3,
The first integrated circuit device includes:
A memory for storing the compressed image data from the image encoding device;
A transfer clock generating unit that generates a transfer clock for transferring the image data to the data bus,
The image encoding device outputs an actual compression rate for each line,
The transfer clock generation unit is configured to transfer the compressed image data for one line only during a period during which the uncompressed image data for one line is transferred based on the actual compression rate of one line. An image output system which outputs a transfer clock and does not output the transfer clock in the remaining period. In any one of Claims 1 to 12,
The first integrated circuit converts a first color signal for one pixel into a second color signal having a number of bits smaller than the number of bits of the first color signal before the image encoding device. A color signal conversion circuit for
When the compression rate achieved by the color signal conversion circuit is k (k <1) and the specified compression rate or the actual compression rate achieved by the image encoding device is α, the compression image data An image output system, wherein a compression rate used for transfer control is set to k × α. In any one of Claims 1 thru | or 13.
The first integrated circuit switches and transfers the uncompressed image data and the compressed image data via the data bus, and transfers the uncompressed / compressed switching signal to the uncompressed image data or the compressed image data. An image output system for transmitting in synchronization with a vertical synchronization signal transmitted at times. In any one of Claims 1 thru | or 14.
The second integrated circuit further includes a compressed image data memory for storing the compressed image data transferred via the data bus in a preceding stage of the image decoding device. In claim 15,
When a decoding error occurs in the image decoding device of the second integrated circuit, an interrupt signal is supplied from the second integrated circuit to the first integrated circuit, and the first signal that has received the interrupt signal is received. The integrated circuit controls the image encoding device so as to retransmit only the compressed image data of one frame including only the line in which the decoding error has occurred or the line in which the decoding error has occurred. Image output system. In claim 15,
When the data amount of uncompressed image data is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory is S bits, M>S> M × α An image output system characterized by being established. In claim 15,
The first integrated circuit converts a first color signal for one pixel into a second color signal having a number of bits smaller than the number of bits of the first color signal before the image encoding device. A color signal conversion circuit for
The compression rate achieved by the color signal conversion circuit is k (k <1), the data amount of uncompressed image data is M bits, the specified compression rate is α (α <1), and the compressed image data memory An image output system characterized in that M>S> M × α × k holds when the effective storage capacity of S is S bits. In claim 15,
The second integrated circuit further includes an image data processing unit that synthesizes image data for N (N is an integer of 2 or more) frames and processes the image data for one frame,
When the data amount of uncompressed image data for one frame is M bits, the specified compression rate is α (α <1), and the effective storage capacity of the compressed image data memory is S bits, N × M> S An image output system characterized in that> N × M × α is established. In claim 15,
The first integrated circuit converts a first color signal for one pixel into a second color signal having a number of bits smaller than the number of bits of the first color signal before the image encoding device. A color signal conversion circuit for
The second integrated circuit further includes an image data processing unit that synthesizes image data for N (N is an integer of 2 or more) frames and processes the image data for one frame,
The compression ratio achieved by the color signal conversion circuit is k (k <1), the amount of uncompressed image data for one frame is M bits, and the specified compression ratio is α (α <1). An image output system characterized in that N × M>S> N × M × α × k holds when the effective storage capacity of the compressed image data memory is S bits. In claim 3, 6, 8 or 12,
The second integrated circuit further includes a compressed image data memory for storing the compressed image data transferred via the data bus in a previous stage of the image decoding device,
When the data amount of one line of uncompressed image data is ML bits, the specified compression rate is α (α <1), and the effective storage capacity on one line of the compressed image data memory is SL bits, An image output system in which ML>SL> ML × α is established. In claim 3, 6, 8 or 12,
The first integrated circuit converts a first color signal for one pixel into a second color signal having a number of bits smaller than the number of bits of the first color signal before the image encoding device. A color signal conversion circuit for
The second integrated circuit further includes a compressed image data memory that is provided in a preceding stage of the image decoding device and stores compressed image data transferred via the data bus,
The compression rate achieved by the color signal conversion circuit is k (k <1), the data amount of one line of uncompressed image data is ML bits, and the specified compression rate is α (α <1). An image output system characterized in that ML>SL> ML × α × k holds when the effective storage capacity on one line of the compressed image data memory is S bits. In claim 3, 6, 8 or 12,
The first integrated circuit converts a first color signal for one pixel into a second color signal having a number of bits smaller than the number of bits of the first color signal before the image encoding device. A color signal conversion circuit for
The second integrated circuit includes:
A compressed image data memory that is provided in a preceding stage of the image decoding device and stores compressed image data transferred via the data bus;
An image data processing unit that is provided at a subsequent stage of the image decoding device and synthesizes image data for N (N is an integer of 2 or more) frames to process the image data for one frame;
Further comprising
The compression rate achieved by the color signal conversion circuit is k (k <1), the data amount of uncompressed image data for one line is ML bits, the specified compression rate is α (α <1), and An image output system characterized in that N × ML>SL> N × ML × α × k holds when the effective storage capacity of the compressed image data memory is SL bits. 24.
The compressed image data memory is characterized in that head data of compressed image data of each line is stored in a storage element at the same address of each line of the image compression memory. 25. Any one of claims 15 to 24.
The second integrated circuit sends a write start signal synchronized with a vertical synchronization signal to the first integrated circuit;
The first integrated circuit transfers the compressed image data to the second integrated circuit via the data bus based on the write start signal,
The image output system, wherein a timing at which writing starts to the compressed image data memory based on the writing start signal precedes a read start timing with respect to the compressed image data memory. In claim 25,
The second integrated circuit includes:
A first line buffer provided in a preceding stage of the compressed image data memory;
A second line buffer provided between the compressed image data memory and the image decoding device;
The compressed image data for one line is simultaneously written from the first line buffer to the compressed image data memory, and the compressed image data for one line is simultaneously output from the compressed image data memory to An image output system stored in a second line buffer. In claim 25,
The second integrated circuit further includes first and second read line buffers between the compressed image data memory and the image decoding device,
The compressed image data for one line read from the compressed image data memory is alternately stored in the first and second read line buffers, and alternately read out.

Images