JP2007141132A - Dynamically-reconfigurable processor and processor control program which controls the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamically-reconfigurable processor having a wiring structure capable of flexibly mapping a program to the processor with a small wiring area. <P>SOLUTION: The dynamically-reconfigurable processor comprises: an arithmetic circuit group Ui composed of arithmetic circuits of kinds Ai (i=1, 2, ..., N); an arithmetic circuit group Vi composed of a part of the arithmetic circuit group included in the arithmetic circuit group Ui, and an arithmetic circuit group of a kind B which is connected to the part and which is different from the arithmetic circuits of the kind Ai; an arithmetic circuit wiring Xi for connecting each of the arithmetic circuits of the kind Ai and each of the arithmetic circuits of the kind B; and a switch group Si for changing the order of connection of the arithmetic circuits in the arithmetic circuit group Vi wherein the arithmetic circuit wiring Xi in the arithmetic circuit group Vi is different from the other arithmetic circuit wiring Xi. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a dynamically reconfigurable processor whose configuration can be dynamically changed, and more particularly to a technique effectively applied to a processor having a plurality of arithmetic circuits and a plurality of wirings between arithmetic circuits as components. .

  2. Description of the Related Art Conventionally, there has been a reconfigurable processor device having a connection matrix for providing interconnection between a plurality of processing devices and a plurality of processing devices, as described in, for example, Japanese Patent Application Laid-Open No. 11-251442 (Patent Document 1). there were.

  Also, in a dynamically reconfigurable processor composed of different types of arithmetic circuits, Takayuki Sukegawa, Keisuke Kei and Ando Tomoyoshi Sato, ”IC E Trans Information and System, Volume E 87 D, Number 8, 1997 to 2003, August 2004 (Takayuki SUGAWARA, Keisuke IDE, and Tomoyoshi PTD)“ Dynamically Reconfigurable PD As described in “Hnology”, IEICE TRANS. INF. & SYSTEM, Vol. E87-D, No. 8, pp. 1997-2003, August 2004) (Non-patent Document 1), wiring between arithmetic circuits is uniform. It was something.

  In such a processor, the wiring between the arithmetic circuits is an interconnection bus composed of a uniform two-way bus, an X bus and a Y bus, and the routing between the data transfer source arithmetic circuit and the transfer destination arithmetic circuit is the X bus. Alternatively, control is performed by selecting a wiring included in the Y bus with a switch box. The function of this switch box is set with a pre-programmed configuration.

  The reason why the dynamic reconfigurable processor in which a large number of arithmetic circuits are arranged two-dimensionally includes the different types of arithmetic circuits as described above is to improve the operation rate of the arithmetic circuits.

If all the arithmetic circuits have the same function and support various types of arithmetic operations such as addition, subtraction, multiplication, and logical operation, it is easy to map a program to this arithmetic circuit array. However, for example, when a program that includes a few multiplications and includes many additions, subtractions, and logical operations is mapped to this processor, many of the multiplications that require a large area are not used, and the use efficiency of the circuit area is poor. This is not preferable because an increase in the area of the LSI leads to an increase in the price of the LSI. Therefore, it is important to improve the operation rate of each arithmetic circuit with as small an area as possible. For this purpose, some arithmetic circuits include only arithmetic operations mainly including multiplication, while other arithmetic circuits mainly include addition / subtraction and logical operations, and an arithmetic circuit array including non-uniform arithmetic circuits is provided. One solution. In such a processor, there are cases where many wires are provided in order to improve the ease of programming. This makes it possible to easily use the arithmetic circuit using abundant wiring even if the required arithmetic operation is at a distant position.
Japanese Patent Laid-Open No. 11-251442 From Takayuki Sukegawa, Keisuke Ide, and Satoshi Tomoyoshi, “Dynamically Reconfigurable Processor Implied with IP Flexs DAPDNA Technology”, ICC Trans Information and System, Volume E87 D, Number 8, 1997 2003, August 2004 (Takayuki SUGAWARA, Keisuke IDE, and Tomoyoshi Sato, “Dynamically Reconfigurable Processor ID I. S & D. 1997-2003, August 2004)

  However, in the above-described prior art, for example, a dynamic structure having a non-uniform configuration, which is composed of two types of arithmetic circuits A and B, most of which are arithmetic circuits A and the remaining few arithmetic circuits B are arranged close to each other. In order to flexibly map a program to a reconfigurable processor, it is necessary to add more wiring than a dynamically reconfigurable processor composed of uniform arithmetic circuits. As a whole, there is a problem that a large wiring area is consumed.

  That is, since it is necessary to have a uniform wiring structure, it is necessary to add wiring not only to the periphery of the arithmetic circuit B but also to the entire processor.

  An object of the present invention is to provide a dynamically reconfigurable processor having a wiring structure that can flexibly map a program to the same processor with a small wiring area and a processor control program for controlling the processor.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The dynamically reconfigurable processor according to the present invention includes an arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N) and some arithmetic circuit groups included in the arithmetic circuit group Ui. And an arithmetic circuit group Vi composed of a type B arithmetic circuit group different from the type Ai arithmetic circuit connected thereto, and an inter-arithmetic circuit wiring Xi connecting the type Ai arithmetic circuit and the type B arithmetic circuit, respectively. The inter-operation circuit wiring Xi in the arithmetic circuit group Vi is set to an inter-operation circuit wiring different from the other arithmetic circuit wiring Xi, and the switch group Si for changing the connection order between the arithmetic circuits in the arithmetic circuit group Vi. It is equipped with.

  The dynamically reconfigurable processor according to the present invention includes an arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N) and some arithmetic operations included in the arithmetic circuit group Ui. Arithmetic circuit wiring Vi for connecting the arithmetic circuit group Vi composed of the arithmetic circuit group of type B different from the circuit group and the arithmetic circuit of type Ai connected thereto, and the arithmetic circuit group of type Ai and the arithmetic circuit of type B to each other Xi, a wiring Zi added to the inter-arithmetic circuit wiring Xi that connects the arithmetic circuits in the arithmetic circuit group Vi in a different order from the inter-arithmetic circuit wiring Xi, and either the inter-arithmetic circuit wiring Xi or the wiring Zi And a switch group Si that activates.

  The processor control program according to the present invention includes an arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N), a part of arithmetic circuit groups included in the arithmetic circuit group Ui, An arithmetic circuit group Vi composed of an arithmetic circuit group of type B different from the arithmetic circuit of type Ai connected to them, and an inter-arithmetic circuit wiring Xi connecting the arithmetic circuit of type Ai and the arithmetic circuit of type B; The wiring Zi added to the inter-arithmetic circuit wiring Xi that connects the arithmetic circuits in the arithmetic circuit group Vi in a different order from the inter-arithmetic circuit wiring Xi, and either the inter-arithmetic circuit wiring Xi or the wiring Zi is made effective. A processor control program for controlling a dynamically reconfigurable processor having a switch group Si, and based on information on a logical circuit configuration for operating the dynamically reconfigurable processor Controls switches Si, and changes the connection order of the arithmetic circuit in the arithmetic circuit and the type B type Ai.

  The processor control program according to the present invention includes an arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N), a part of arithmetic circuit groups included in the arithmetic circuit group Ui, An arithmetic circuit group Vi composed of an arithmetic circuit group of type B different from the arithmetic circuit of type Ai connected to them, and an inter-arithmetic circuit wiring Xi connecting the arithmetic circuit of type Ai and the arithmetic circuit of type B; The wiring Zi added to the inter-arithmetic circuit wiring Xi that connects the arithmetic circuits in the arithmetic circuit group Vi in a different order from the inter-arithmetic circuit wiring Xi, and either the inter-arithmetic circuit wiring Xi or the wiring Zi is made effective. A switch group Si, and a switch for changing the inter-arithmetic circuit wiring for connecting a set of the arithmetic circuit of type Ai and the arithmetic circuit of type B connected by the inter-arithmetic circuit wiring Xi in the arithmetic circuit group Vi. A processor control program for controlling a dynamically reconfigurable processor having a group Ti and controlling a switch group Si based on information on a logical circuit configuration for operating the dynamically reconfigurable processor; The connection order of the arithmetic circuit of type Ai and the arithmetic circuit of type B is changed, the switch group Ti is controlled in conjunction with the control signal of the switch group Si, and the arithmetic circuit group Vi is connected by the inter-operation circuit wiring Xi. The inter-arithmetic circuit wiring for connecting the sets of the type Ai arithmetic circuit and the type B arithmetic circuit is changed in conjunction with the state of the switch group Si.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, a program can be flexibly mapped to a dynamically reconfigurable processor composed of non-uniform arithmetic circuit groups with a small increase in wiring area.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<Overview of dynamically reconfigurable processor>
The outline of the dynamically reconfigurable processor according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is an explanatory diagram for explaining an outline of a dynamically reconfigurable processor according to the first embodiment of the present invention.

  In FIG. 1, Ai (i = 1, 2,..., N) is an arithmetic circuit of type Ai, B is an arithmetic circuit of type B different from the arithmetic circuit of type Ai, and Ui is an arithmetic circuit of type Ai. Several arithmetic circuit groups, Vi is a part of arithmetic circuit groups included in the arithmetic circuit group Ui and a type B arithmetic circuit group connected to them, Xi is an inter-arithmetic circuit wiring, Zi is an inter-arithmetic circuit wiring Xi An added wiring, which connects the arithmetic circuits in the arithmetic circuit group Vi in a different order from the inter-arithmetic circuit wiring Xi, Si is a switch group added to the wiring X, and the inter-arithmetic circuit wiring Xi And a switch for enabling either one of the wiring Zi.

  In the dynamically reconfigurable processor according to the present embodiment, as shown in FIG. 1, the type Ai arithmetic circuit includes a type B arithmetic circuit different from the type Ai arithmetic circuit, and the type Ai. The arithmetic circuit of type B and the arithmetic circuit of type B are wired in a matrix by inter-arithmetic circuit wiring Xi.

  A wiring Zi for changing the order of connection between the type Ai arithmetic circuit and the type B arithmetic circuit is provided in the inter-arithmetic circuit wiring Xi for connecting the type Ai arithmetic circuit and the type B arithmetic circuit, and the switch group Si is provided. By controlling, the connection location of the type B arithmetic circuit can be changed in the matrix wiring.

  The switch group Si is controlled by processing such as a processor control program for controlling a dynamically reconfigurable processor, for example.

  As a result, the order of the arithmetic circuit of type Ai and the arithmetic circuit of type B can be changed as necessary, and the program can be flexibly mapped to the dynamically reconfigurable processor with a small increase in wiring area. is there.

<System configuration including dynamically reconfigurable processor>
Next, a system configuration including a dynamically reconfigurable processor according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a configuration diagram showing a configuration of a system including a dynamically reconfigurable processor according to the first embodiment of the present invention, and FIG. 3 is a wiring changeover switch of the dynamically reconfigurable processor according to the first embodiment of the present invention. 4 is a diagram showing effective wiring when the upper input is selected, and FIG. 4 is a diagram showing effective wiring when the dynamically reconfigurable processor wiring changeover switch according to the first embodiment of the present invention selects the lower input. is there.

  In FIG. 2, a system including a dynamically reconfigurable processor includes a CPU 10, a main memory 20, a bus 30, and a dynamically reconfigurable processor 100.

  The dynamically reconfigurable processor 100 includes a configuration management unit 40 that manages a configuration that is information representing the configuration of the dynamically reconfigurable processor, and a total of six types of two arithmetic circuits 501 indicated by A and B. An arithmetic circuit array unit 50 in which two-dimensionally arranged 506, arithmetic circuits 501, 503, 504, and 506 of type A, arithmetic circuits 502 and 505 of type B different from type A, and two arrows in contact with the left side thereof A wiring changeover switch 510 that selects data on any one of the wirings to be represented and flows to the wiring that is in contact with the right side of 510, and a wiring between vertical arithmetic circuits that connects the arithmetic circuits in the vertical direction 520, an additional wiring (dotted line portion) 530, and an arithmetic circuit array unit 50, a wiring additional portion (broken line portion) 60 representing a portion where the wiring is increased Arithmetic circuit position change line 70 to control the switching of the wire changeover switch 503 is configured local memory 80 and 81, from the data line 90.

  Since the wiring of the wiring expansion unit 60 including the added wiring 530 and the other arithmetic circuit array unit (including the arithmetic circuits 503 and 506) are different, the wiring is not uniform as viewed from the entire arithmetic circuit array unit 50. I understand that.

  In FIG. 2, the effective wiring when the wiring changeover switch 510 selects the upper side input is a diagram in which the wiring 530 shown in FIG. 2 is deleted, as shown in FIG. In this case, the six arithmetic circuits are simply connected in the vertical and horizontal directions.

  Further, in FIG. 2, as the effective wiring when the wiring changeover switch 510 selects the lower input, the wiring 530 shown in FIG. 1 is effective as shown in FIG. In this case, the connection of the six arithmetic circuits is as follows.

  First, connection of the upper arithmetic circuits 501, 502, and 503 will be described.

  Data input from the left local memory 80 is input to the arithmetic circuit 502, then input to the arithmetic circuit 501, and finally input to the arithmetic circuit 503.

  Similarly for the lower arithmetic circuit, data input from the left local memory 80 is input to the arithmetic circuit 505, then input to the arithmetic circuit 504, and finally input to the arithmetic circuit 506.

  On the other hand, in the vertical connection, the arithmetic circuits 501 and 504 and 502 and 505 are always connected regardless of the operation of the wiring changeover switch 510.

  From the above, it can be seen that when the wiring changeover switch 510 selects the lower input, the connection is made such that the positions of the first column arithmetic circuit and the second column arithmetic circuit are switched.

  This means to the programmer that the type B arithmetic circuit appears to be in the first column.

  That is, as can be seen from FIGS. 3 and 4, the programmer can control whether the arithmetic circuit of type B is logically in the first column or the second column by switching the wiring changeover switch 510. ,That's what it means.

<Mapping program of dynamically reconfigurable processor>
Next, the program mapping of the dynamically reconfigurable processor according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a diagram showing an example of a logical circuit configuration that can be selected by the programmer in the dynamically reconfigurable processor according to the first embodiment of the present invention, and FIG. 5A shows the wiring switching shown in FIG. FIG. 5B shows a circuit configuration when the switch 510 selects the upper input, and FIG. 5B shows a circuit configuration when the wiring changeover switch 510 shown in FIG. 3 selects the lower input. 6 is a diagram showing a simple display example of the dynamically reconfigurable processor according to the first embodiment of the present invention, and FIG. 7 is a diagram of an arithmetic circuit in the dynamically reconfigurable processor according to the first embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a structure and a wiring structure in an arithmetic circuit, FIG. 8 is a diagram illustrating an example of a program of a dynamically reconfigurable processor according to the first embodiment of the present invention, and FIG. 9 is a first embodiment of the present invention. FIG. 10 is a diagram showing a control data flow graph (CDFG) for the program shown in FIG. 8 in the dynamically reconfigurable processor according to FIG. 10, and FIG. 10 shows two multipliers in the dynamically reconfigurable processor according to the first embodiment of the present invention. FIG. 11 is a diagram showing an example of failure in mapping the CDFG of FIG. 9 to the dynamically reconfigurable processor in the case of the column. FIG. 11 shows one column of multipliers in the dynamically reconfigurable processor according to Embodiment 1 of the present invention. In eye It is a diagram showing a mapping example of CDFG 9 on Dynamically Reconfigurable Processor if.

  In FIG. 5, it is assumed that the type A arithmetic circuit can perform addition / subtraction and logical operation, and the type B arithmetic circuit can perform multiplication.

  At this time, in FIG. 5A, the arithmetic circuit array has a calculation formula for performing addition / subtraction on the input data, performing multiplication, and finally performing a logical operation (representing a right shift “>>” in the figure). This means that it can be easily mapped.

  On the other hand, FIG. 5B shows that a calculation expression that performs multiplication, addition and subtraction on input data, and finally performs a logical operation can be easily mapped to the arithmetic circuit array.

  A simple display example of such a dynamically reconfigurable processor is shown in FIG. For the sake of clarity, the arithmetic circuit B is represented by a hexagon. The wiring between the arithmetic circuits is omitted except for those that are necessary.

  Hereinafter, a specific program mapping is displayed using the arithmetic circuit array unit 50 of FIG. 6 to show the effectiveness of the present embodiment.

  First, the internal structure of the arithmetic circuit is as shown in FIG. 7, and FIG. 7A shows a type A arithmetic circuit represented by 501 in FIG.

  The type A arithmetic circuit 501 has an ALU 5010 capable of executing addition / subtraction and logical operation, and one of these operations can be selected by configuration.

  The memory 5011 stores constants. The constants are set by configuration.

  Further, as the switch, a wiring changeover switch 5012 that selects data on any two wirings from the data on the wirings represented by the five arrows in contact with the left side thereof and flows them to the wiring in contact with the right side of 5102, A wiring changeover switch 5013 that selects one of the data on the wiring from the data on the wiring expressed by two arrows in contact with the lower side thereof and flows the data to the wiring in contact with the upper side of 5103, and 4 in contact with the left side thereof. A wiring changeover switch 5014 that selects any one of the data on the wiring from the data on the wiring represented by the arrows and passes the data to the wiring in contact with the right side of 5104 is provided.

  The wiring connected to the wiring changeover switch 5014 is a through wiring, and is used for transferring data to another arithmetic circuit via the arithmetic circuit 501.

  As a result, calculation is performed by selecting two of the inputs of the upper one, the left two, and the lower one, and the calculation results are obtained by calculating the upper one, the right two (output of the same calculation result), the lower It is possible to output to an arbitrary wiring of one side, and one of the inputs of the upper one, the left two, and the lower one is selected, the upper one, the right two, and the lower one It can be output to any wiring of the book other than the wiring used for outputting the calculation result.

  FIG. 7B shows a type B arithmetic circuit represented by 502 in FIG.

  The type B arithmetic circuit 502 has an ALU 5020 capable of executing multiplication, and the arithmetic is controlled by the configuration. In other respects, the configuration of the arithmetic circuit 501 of type A shown in FIG.

  An example of the program is a program as shown in FIG. 8, the first line is a for loop, and the value of the variable i is incremented by 1 from 0 to N−1 (N is a constant). The process of the 2nd line and the 3rd line is repeated until it becomes.

  The second line calculates the sum of the result of multiplying the values of the i-th element of the arrays a and x and the value of the i-th element of the arrays b and y, and adds 1 to the result to 2 It represents dividing and assigning to the array v.

  The third row takes the difference between the result of multiplying the values of the i-th element of the arrays a and x and the value of the i-th element of the arrays b and y, and adding 1 to the result to 2 It represents dividing and assigning to the array z.

  The control data flow graph (CDFG) for the program shown in FIG. 8 is as shown in FIG.

In FIG. 9, each rectangle represents data or calculation. Multiplication is represented by “*”, addition is “+”, subtraction is “−”, and division by 2 is replaced by 1-bit right shift “>> 1”.
Arrows indicate the flow of data.

  Since the result of multiplying the values of the i-th element of the arrays a, and x is used for addition and subtraction, the multiplication result is used for both “+” and “−”.

  Here, the mapping of the control data flow graph (CDFG) shown in FIG. 9 will be described.

  First, as shown in FIG. 10, in the mapping of the CDFG of FIG. 9 to the dynamically reconfigurable processor when the multiplier is in the second column, two multiplications and addition / subtraction are mapped, but the right shift is The mapping is unsuccessful because it is not mapped.

  Note that the input to the multiplication is represented by two arrows from the left side, but the upper one represents the through wiring, and the lower one represents the constant 0 and the input data stored in the memory. Indicates that the calculation result is output on the right side. The latter represents the same result as when the through wiring is used, that is, the input data is transferred as it is. By these, the same effect as two through wirings can be obtained.

  A broken line arrow in an arithmetic circuit including addition and subtraction represents a through wiring that transfers data input from the left side to the lower side (in the case of addition) or the upper side (in the case of subtraction).

  Further, as shown in FIG. 11, the mapping is successful in the mapping of the CDFG of FIG. 9 to the dynamically reconfigurable processor when the multiplier is in the first column.

  As shown in FIGS. 10 and 11, by changing the logical circuit configuration using the wiring changeover switch 510, the flexibility of the dynamically reconfigurable processor is increased, and the type B arithmetic circuit is logically first. It can be seen that a program that could not be mapped in the case of the line can be mapped by logically placing the type B arithmetic circuit in the second line.

<Comparison with conventional dynamically reconfigurable processors>
Here, with reference to FIGS. 12 to 17, as a comparative example, consider the case where the CDFG of FIG. 12 is a diagram showing an example of a conventional dynamic reconfigurable processor as a comparative example, FIG. 13 is a diagram showing the structure of each wiring switch in FIG. 12, and FIG. 14 is a simple table of conventional dynamic reconfigurable. FIG. 15 is a diagram showing the structure and wiring structure of the arithmetic circuit in FIG. 12, FIG. 16 is a diagram showing an example of mapping failure of the CDFG of FIG. 9 to the conventional dynamic reconfigurable processor, and FIG. It is a figure which shows the example of mapping of CDFG of FIG. 9 to the conventional dynamically reconfigurable processor which increased the number of wiring.

  In FIG. 12, the dynamically reconfigurable processor 100 is connected by a wiring 1102.

  Each of the wirings 1102 is connected via a switch box 1100, and each of the four rhombuses represents a routing switch, and has a function of outputting any one of the upper, lower, left, and right inputs to either the upper, lower, left, or right. Details will be described with reference to FIG.

  In addition, it has a switch-wiring junction 1101 that allows a non-selected state, and this junction 1101 can select a wiring connected to one of the two wirings 1102, but neither is selected. It is a switch that can also be used.

  In the arithmetic circuits 501 to 506, the programmer controls the flow of data on the wiring in the arithmetic circuit array by setting the routing switch in the switch box 1100 by configuration, and sets the switch in the junction 1101 by configuration. By doing so, the exchange of data on the arithmetic circuit and the wiring is controlled.

  In FIG. 13, FIG. 13 (a) is an enlarged view of the switch 1101 and the wiring 1101 that allow a non-selected state. The joint 1101 includes a terminal 1200 that is not connected to any wiring and a switch 1201. The switch 1201 connects the wiring 1202 to one of the wirings 1203 and 1204 or connects the wiring 1202 to the terminal 1200 depending on the configuration. The latter is the same as not connecting the wiring 1202 to any wiring.

  FIG. 13B is an enlarged view of the switch box 1100. The switch box 1100 includes one routing switch 1205 in the switch box.

  FIG. 13C shows a configuration example of the routing switch 1205. The routing switch 1205 is a switch 1206 having the same function as the switch 1201 shown in FIG. However, the switch 1206 selects whether one wiring and one wiring are connected or not. The switch 1207 is a switch having the same function as the switch 1201 shown in FIG. The switch 1208 is a switch that always selects one of the wirings in contact with the lower right.

  The routing switch 1205 can output data input from any direction, up, down, left, and right, in any direction other than that direction. In some cases, the signals can be output in two directions at the same time. For example, data input from the left side can be output in two directions, upper side and right or lower side. In some cases, two data transfers can be performed simultaneously. For example, data input from the left side can be output to the upper side and data input from the right side can be output to the lower side at the same time. However, when data input from the left side is output to other than the upper side (right side or lower side), since the wiring 1209 is used, other data transfer cannot be performed simultaneously.

  Here, FIG. 14 shows a simple display example of the conventional dynamic reconfigurable capability shown in FIG. In FIG. 14, the wiring between the arithmetic circuits is omitted except for necessary ones.

  Hereinafter, the CDFG shown in FIG. 9 is mapped by using the arithmetic circuit array unit 50 of FIG. 14, and it is shown that mapping cannot be performed with two wirings 1102 and mapping can be performed with three wirings 1102.

  FIG. 15 shows the structure and wiring structure of the arithmetic circuit in FIG. The arithmetic circuit is the same as that shown in FIG. 7 except that there is no through wiring.

  An example of the mapping failure of the CDFG of FIG. 9 to the conventional dynamically reconfigurable processor is as shown in FIG. 16, and the bold line represents the flow of data. The four data flows at the left end of FIG. 16 represent data input from the left local memory 80 to the arithmetic circuit array 50. Each of these reaches the multiplication circuit through the upper and lower wirings. The calculation results of the multiplication circuit 502 are output from the upper direction and the right direction, and reach the arithmetic circuits 503 and 506, respectively. Similarly, the calculation result of the multiplication circuit 505 is output from the downward direction and the right direction, and reaches the arithmetic circuits 506 and 503, respectively. The calculation results in the arithmetic circuits 503 and 506 are output upward and downward, respectively, and reach the arithmetic circuits 501 and 504, respectively.

  As described above, all operations are mapped, but mapping is unsuccessful because there is no wiring for outputting the result of the right shift to the right local memory 81.

  Conventionally, in order to successfully map the CDFG of FIG. 9 to the dynamically reconfigurable processor, the number of wirings is increased as shown in FIG.

  As shown in FIG. 17, by using three wirings 1102, the right shift result of FIG. 16 can be output to the right as shown in the figure, and the mapping of CDFG of FIG. 9 can be successful.

  Here, the number of wirings used in the prior art shown in FIG. 12 is compared with the total wiring length in the present embodiment shown in FIG.

  It is assumed that the arithmetic circuit array has m rows and n columns, the arithmetic circuit has a square shape, the length of each side is L, and one wiring is composed of b-bit wiring.

  In the prior art, the number of wirings 1102 is a. In the prior art, it is assumed that the length of the wiring connecting the arithmetic circuit and the wiring 1102 and the wiring in the arithmetic circuit is negligible.

  At this time, the total wiring length according to the prior art is a * b * L * (2 * m * n + m + n).

  On the other hand, in the present invention, a / 2 wirings are used. This wiring represents a through wiring in the arithmetic circuit.

  It is assumed that the wiring length for connecting the input / output of the ALU in the arithmetic circuit and the arithmetic circuit in the arithmetic circuit array can be ignored. At this time, the total wiring length of the through wiring is a * b * m * L * n / 2. The total wiring length of the wiring 530 is a * b * m * L * 4. Therefore, the total wiring length according to the present invention is a * b * m * L * (4 + n / 2).

  Therefore, the total wiring length according to the present embodiment is shortened by a * b * L * (3 * m * (n−2) / 2 + n). This indicates that the wiring area is smaller in the present embodiment when there are two or more arithmetic circuit arrays.

(Embodiment 2)
In Embodiment 2, the arithmetic circuit 501 and the arithmetic circuit 504, and the arithmetic circuit 502 and the arithmetic circuit 505 are connected to each other by the vertical wiring 520, but the arithmetic circuit 501 is connected to the arithmetic circuit 502 or the arithmetic circuit. Similarly, wiring and switches are added so that the arithmetic circuit 503 can be connected to the arithmetic circuit 502 or the arithmetic circuit 505 so that the arithmetic circuit 503 can be connected to the arithmetic circuit 505.

<Configuration of dynamically reconfigurable processor>
Next, the configuration of the dynamically reconfigurable processor according to the second embodiment of the present invention will be described with reference to FIG. FIG. 18 is a configuration diagram showing a configuration of a dynamically reconfigurable processor according to the second embodiment of the present invention.

  First, the difference between FIG. 2 of the first embodiment and FIG. 18 of the present embodiment will be described.

  In FIG. 2 in Embodiment 1, the arithmetic circuit 501 and the arithmetic circuit 504, and the arithmetic circuit 502 and the arithmetic circuit 505 are connected by the vertical wiring 520.

  In FIG. 18 of this embodiment mode, wiring and switches are added in a similar manner so that the arithmetic circuit 501 can be connected to the arithmetic circuit 502 or 505 so that the arithmetic circuit 503 can be connected to the arithmetic circuit 502 or 505. .

  In FIG. 18, the dynamically reconfigurable processor includes an added switch 521 and an added wiring 522. The added switch 521 constitutes a switch group Ti.

  In FIG. 2 of the first embodiment, there is only one arithmetic circuit position change wiring 70, but in FIG. 18 of the present embodiment, there are two arithmetic circuit position change wirings 70 and arithmetic circuit position change wiring 74. , Each can have a different setting.

  The wiring 71 is a wiring separated from the arithmetic circuit position changing wiring 70 and sends the same signal as the arithmetic circuit position changing wiring 70. The wiring 73 is a wiring separated from the arithmetic circuit position change wiring 74 and sends the same signal as the arithmetic circuit position change wiring 74.

  Signals from the wiring 71 and the wiring 73 are input to an arithmetic unit 75 that calculates an exclusive OR, and the calculation result is input to the switch 521 through the wiring 72.

  The symbol “0” entered in the vicinity of the switch 521 indicates the input wiring selected when the result of the exclusive OR operation is “0”, and the symbol “1” indicates that the operation result of the exclusive OR is “ The input wiring selected when “1”.

  That is, when a signal “1” is input from the computing unit 75 to the switch 521, a signal from the wiring 522 added in this embodiment is output from the switch 521.

  Thus, when the same value flows through the arithmetic circuit position change wiring 70 and the arithmetic circuit position change wiring 74, the vertical arithmetic circuits are connected in the same manner as in FIG. That is, the arithmetic circuit 501 is connected to the arithmetic circuit 504, and the arithmetic circuit 502 is connected to the arithmetic circuit 505.

  In this state, since the same value flows through the arithmetic circuit position change wiring 70 and the arithmetic circuit position change wiring 74, the connection order of the arithmetic circuit 501 and the arithmetic circuit 502 and the connection order of the arithmetic circuit 504 and the arithmetic circuit 505 are the same. Therefore, in this state, the connection is always the same as in the first embodiment.

  On the other hand, when different values flow through the arithmetic circuit position changing wiring 70 and the arithmetic circuit position changing wiring 74, the arithmetic circuits in the vertical direction are connected by a method different from that in FIG. That is, the arithmetic circuit 501 is connected to the arithmetic circuit 505, and the arithmetic circuit 502 is connected to the arithmetic circuit 504.

  Thus, for example, even when the arithmetic circuit in the first row is logically arranged in the order of the arithmetic circuit 501 and the arithmetic circuit 502, and the arithmetic circuit in the second row is logically arranged in the order of the arithmetic circuit 505 and the arithmetic circuit 504, for example. As for the relationship between the arithmetic circuits in the vertical direction, the arithmetic circuit 501 and the arithmetic circuit 505 are connected, the arithmetic circuit 502 and the arithmetic circuit 504 are connected, and the arithmetic circuits are set without contradiction.

<Logical circuit configuration that programmers can select>
Next, a logical circuit configuration that can be selected by the programmer in the dynamically reconfigurable processor according to the second embodiment of the present invention will be described with reference to FIG. FIG. 19 is a diagram showing a logical circuit configuration that can be selected by the programmer in the dynamically reconfigurable processor according to the second embodiment of the present invention.

  First, in FIG. 18, it is assumed that the switch 510 that controls the replacement of the arithmetic units in the left and right direction selects the upper wiring when the value flowing through the arithmetic circuit position changing wiring 70 is 0, and selects the lower wiring when the value is 1. .

  When the signals “0” and “0” are given to the wiring 70 and the wiring 74, respectively, their exclusive OR becomes “0”, and the arithmetic circuit 501, the arithmetic circuit 504, and the arithmetic circuit Since the 502 and the arithmetic circuit 505 are connected, a logical circuit configuration as seen from the programmer is given in FIG. Here, it is assumed that addition is selected in the type A arithmetic circuit and multiplication is selected in the type B arithmetic circuit.

  On the other hand, when signals “1” and “1” are applied to the wiring 70 and the wiring 74, respectively, their exclusive OR becomes “0”, and the arithmetic circuit 502, the arithmetic circuit 505, and the arithmetic circuit Since the 501 and the arithmetic circuit 504 are connected, a logical circuit configuration as seen from the programmer is given in FIG.

  Next, when signals “1” and “0” are given to the wiring 70 and the wiring 74, respectively, their exclusive OR becomes “1”, and the arithmetic circuit 502, the arithmetic circuit 504, and Since the arithmetic circuit 501 and the arithmetic circuit 505 are connected, a logical circuit configuration that can be seen by the programmer is given in FIG.

  Finally, when signals “0” and “1” are given to the wiring 70 and the wiring 74, respectively, their exclusive OR becomes “1”, and the arithmetic circuit 501, the arithmetic circuit 505, and Since the arithmetic circuit 502 and the arithmetic circuit 504 are connected, a logical circuit configuration that can be seen by the programmer is given in FIG.

  As described above, in the dynamically reconfigurable processor of this embodiment, the programmer can set various circuit configurations as shown in FIGS. 18A to 18D, so that programming becomes very easy. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a dynamically reconfigurable processor whose configuration can be dynamically changed, and is particularly applicable to a processor having a plurality of arithmetic circuits and a plurality of wirings between arithmetic circuits as components.

It is explanatory drawing for demonstrating the outline | summary of the dynamically reconfigurable processor which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the system containing the dynamically reconfigurable processor which concerns on Embodiment 1 of this invention. It is a figure which shows effective wiring when the wiring changeover switch of the dynamically reconfigurable processor which concerns on Embodiment 1 of this invention selects upper side input. It is a figure which shows the effective wiring when the dynamically reconfigurable processor wiring changeover switch concerning Embodiment 1 of this invention selects lower input. 4 is a diagram illustrating an example of a logical circuit configuration that can be selected by a programmer in the dynamically reconfigurable processor according to the first embodiment of the present invention. FIG. It is a figure which shows the example of a simple display of the dynamic reconfigurable processor which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the structure of the arithmetic circuit in the dynamically reconfigurable processor which concerns on Embodiment 1 of this invention, and the wiring structure in an arithmetic circuit. It is a figure which shows an example of the program of the dynamically reconfigurable processor which concerns on Embodiment 1 of this invention. FIG. 9 is a diagram showing a control data flow graph (CDFG) for the program shown in FIG. 8 in the dynamically reconfigurable processor according to the first embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a failure in mapping the CDFG of FIG. 9 to the dynamically reconfigurable processor when the multipliers are arranged in the second column in the dynamically reconfigurable processor according to the first embodiment of the present invention. FIG. 10 is a diagram illustrating a mapping example of the CDFG of FIG. 9 to the dynamically reconfigurable processor when the multiplier is in the first column in the dynamically reconfigurable processor according to the first embodiment of the present invention. It is a figure which shows an example of the conventional dynamic reconfigurable processor as a comparative example. It is a figure which shows the structure of each wiring switch in FIG. It is a figure which shows the example of a simple display of the conventional dynamic reconfigurable. It is a figure which shows the structure and wiring structure of the arithmetic circuit in FIG. FIG. 10 is a diagram illustrating an example of mapping failure of the CDFG of FIG. 9 to a conventional dynamically reconfigurable processor. It is a figure which shows the example of mapping of CDFG of FIG. 9 to the conventional dynamically reconfigurable processor which increased the number of wiring. It is a block diagram which shows the structure of the dynamically reconfigurable processor which concerns on Embodiment 2 of this invention. It is a figure which shows the logical circuit structure which a programmer can select in the dynamically reconfigurable processor concerning Embodiment 2 of this invention.

Explanation of symbols

  Ai (i = 1, 2,..., N)... Type Ai arithmetic circuit, B... Type B arithmetic circuit different from type Ai arithmetic circuit, Ui. A circuit group, Wi: a certain arithmetic circuit group included in the arithmetic circuit group Ui, Vi: an arithmetic circuit group in Ui not included in any Wi, and a certain arithmetic circuit group of type B connected thereto, X ... Wiring between arithmetic circuits, Zi... Wiring added to wiring X, wiring connecting arithmetic circuits in arithmetic circuit group Vi in an order different from X, Si... Switch added to wiring X, Switch for enabling one of the inter-arithmetic circuit wiring X and the wiring Zi, 10..., CPU, 20... Main memory, 30... Bus, 40 .. configuration management unit, 50 ... arithmetic circuit array unit, 501, 503, 504 5 6: Type A arithmetic circuit, 502, 505 ... Type B arithmetic circuit, 510 ... Wiring changeover switch, 520 ... Vertical inter-arithmetic circuit wiring, 530 ... Additional wiring, 60 ... Wiring expansion section, 70 ... Arithmetic circuit Position change wiring, 80 ... local memory, 81 ... local memory, 90 ... data wiring, 100 ... dynamically reconfigurable processor.

Claims (5)

An arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N);
An arithmetic circuit group Vi composed of a part of arithmetic circuit groups included in the arithmetic circuit group Ui and an arithmetic circuit group of type B different from the arithmetic circuit group of type Ai connected thereto;
An inter-arithmetic circuit wiring Xi connecting the arithmetic circuit of the type Ai and the arithmetic circuit of the type B;
Switch for changing the connection order between the arithmetic circuits in the arithmetic circuit group Vi, with the inter-arithmetic circuit wiring Xi in the arithmetic circuit group Vi being different from the other arithmetic circuit wiring Xi. A dynamically reconfigurable processor comprising a group Si. An arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N);
An arithmetic circuit group Vi composed of a part of arithmetic circuit groups included in the arithmetic circuit group Ui and an arithmetic circuit group of type B different from the arithmetic circuit group of type Ai connected thereto;
An inter-arithmetic circuit wiring Xi connecting the arithmetic circuit of the type Ai and the arithmetic circuit of the type B;
A wiring Zi added to the inter-arithmetic circuit wiring Xi for connecting the arithmetic circuits in the arithmetic circuit group Vi in a different order from the inter-arithmetic circuit wiring Xi;
A dynamically reconfigurable processor comprising a switch group Si that enables one of the inter-operation circuit wiring Xi and the wiring Zi. The dynamically reconfigurable processor of claim 1 or 2,
In the arithmetic circuit group Vi, the inter-arithmetic circuit wiring for connecting the group consisting of the arithmetic circuit of type Ai and the arithmetic circuit of type B connected by the inter-arithmetic wiring Xi is linked to the state of the switch group Si. A dynamically reconfigurable processor characterized by comprising a switch group Ti to be changed. An arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N), a part of arithmetic circuit groups included in the arithmetic circuit group Ui, and the type Ai connected to them. An arithmetic circuit group Vi composed of a type B arithmetic circuit group different from the arithmetic circuit, an arithmetic circuit wiring Xi for connecting the type Ai arithmetic circuit and the type B arithmetic circuit, and the arithmetic circuit group Vi The arithmetic circuit wiring Xi is connected to the arithmetic circuit wiring Xi in a different order from the arithmetic circuit wiring Xi, and either the arithmetic circuit wiring Xi or the wiring Zi is enabled. A processor control program for controlling a dynamically reconfigurable processor comprising a switch group Si,
Controlling the switch group Si based on information on a logical circuit configuration for operating the dynamically reconfigurable processor, and changing a connection order of the type Ai arithmetic circuit and the type B arithmetic circuit. A featured processor control program. An arithmetic circuit group Ui composed of arithmetic circuits of type Ai (i = 1, 2,..., N), a part of arithmetic circuit groups included in the arithmetic circuit group Ui, and the type Ai connected to them. An arithmetic circuit group Vi composed of a type B arithmetic circuit group different from the arithmetic circuit, an arithmetic circuit wiring Xi for connecting the type Ai arithmetic circuit and the type B arithmetic circuit, and the arithmetic circuit group Vi The arithmetic circuit wiring Xi is connected to the arithmetic circuit wiring Xi in a different order from the arithmetic circuit wiring Xi, and either the arithmetic circuit wiring Xi or the wiring Zi is enabled. In the arithmetic circuit group Vi, the inter-arithmetic circuit wiring for connecting the group consisting of the arithmetic circuit of the type Ai and the arithmetic circuit of the type B connected to each other in the arithmetic circuit group Vi is changed. A processor control program for controlling the dynamically reconfigurable processor with a switch group Ti,
Based on information on a logical circuit configuration for operating the dynamically reconfigurable processor, the switch group Si is controlled, the connection order of the type Ai arithmetic circuit and the type B arithmetic circuit is changed, and The switch group Ti is controlled in conjunction with the control signal of the switch group Si, and includes the type Ai arithmetic circuit and the type B arithmetic circuit connected by the inter-arithmetic circuit wiring Xi in the arithmetic circuit group Vi. A processor control program for changing wiring between arithmetic circuits for connecting sets in conjunction with the state of the switch group Si.

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