JP2007122754A - Semiconductor storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage system capable of reducing time required for reading/writing from/to a plurality of semiconductor storage elements and enhancing the efficiency of such reading/writing. <P>SOLUTION: The semiconductor storage system is provided with: a semiconductor storage element which has chip selection signal input, output enable signal input, write enable signal input, address input and data input/output and performs high speed reading/writing of data by an interface via a bus connected to the address input and data input/output; a semiconductor storage element which has the chip selection signal input, output enable signal input, the write enable signal input, the address input and the data input/output and transmits a command from the data input/output to read/write the data and a controller which controls reading/writing operations of each semiconductor storage element. When a predetermined mode is set to the controller, the controller is passed, allowing direct access to each semiconductor storage element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory system including a plurality of semiconductor memory elements and a controller that performs read / write control of each semiconductor memory element.

  An example of a conventional semiconductor storage system will be described with reference to FIG. FIG. 22 is a block diagram schematically showing a conventional semiconductor memory system having a plurality of semiconductor memory elements, and in which a data read / write operation in the semiconductor memory elements is executed by a CPU provided outside. The semiconductor memory system 90 includes first and second semiconductor memory elements 91 and 92 having different control methods at the time of data reading / writing. Data reading / writing operations in these semiconductor memory elements 91 and 92 are externally performed. It is controlled in accordance with a command from the CPU 99 provided in.

The first semiconductor memory element 91 has a chip select signal input “/ S”, an output enable signal input “/ OE”, a write enable signal input “/ W”, and an address input as interface terminals with the CPU 99. The first semiconductor memory element 91 has “A0 to Am” and data inputs / outputs “DQ1 to DQ16”, and uses the memory bus between the semiconductor memory element 91 and the CPU 99 at high speed. Data is read / written.
On the other hand, the second semiconductor memory element 92 has, as interface terminals with the CPU 99, a chip select signal input “CE #”, an output enable signal input “OE #”, a write enable signal input “WE #”, The second semiconductor memory element 92 includes a read protect signal input RP #, a write protect signal input WP #, an address input “A0 to An”, and a data input / output “DQ0 to DQ15”. Data is read / written by sending a command from address input or data input / output.

  Further, the CPU 99 serves as a terminal for interfacing with each of the semiconductor memory elements 91 and 92 as a chip select signal output “/ CSm” connected to “/ S” of the first semiconductor memory element 91 via the control bus 96; A chip select signal output “/ CSn” connected to “CE #” of the second semiconductor memory element 92 via the control bus 93a, and “/ OE” and “OE” of the first and second semiconductor memory elements 91 and 92 The read signal output “/ RD” connected to “#” via the control bus 93 b and the “/ WE” and “WE #” of the first and second semiconductor memory elements 91 and 92 are connected via the control bus 93 c. The input / output port “I / OPort1” connected to the write signal output “/ WD” and the “RP #” of the second semiconductor memory element 92 via the control bus 93d. The input / output port “I / OPort2” connected to “WP #” of the second semiconductor memory element 92 via the control bus 93e, and “A0 to Am” of the first and second semiconductor memory elements 91 and 92. , “A0 to An” are connected to the address outputs “MAX0 to MAX” via the address bus 94, and “DQ1 to DQ16” and “DQ0 to DQ15” of the first and second semiconductor memory elements 91 and 92 are data buses. 95, data input / output “D0 to D15” connected through the terminal 95.

  Data read / write operations in the semiconductor storage system 90 having such a configuration will be described. First, the CPU 99 selects the chip select signal output “/ CSm” or “/ CSn”, and accesses either the first semiconductor memory element 91 or the second semiconductor memory element 92. When the CPU 99 accesses the first semiconductor memory element 91, “/ CSm” is set to “L”, “A0 to Am” is set on the address bus 95, and / RD is set to “L”. If set, data can be read from the first semiconductor memory element 91. On the other hand, if “DQ 1 to DQ 16” is set on the data bus 95 and “/ WR” is set to “L”, data can be written to the first semiconductor memory element 91.

When the CPU 99 accesses the second semiconductor memory element 92, both RP # and WP # are set to “H” and “/ CSn” is set to “L” using “I / OPport1 and 2”. Then, the second semiconductor memory element 92 is selected. Then, while setting a read command (Read Command) on the data bus 95, setting / WR to "L", setting the address bus 94 and setting / RD to "L" in the next cycle. , Data is output from the second semiconductor memory element 92. Similarly, a program command (Program Command) is set to the data bus 95, / WR is set to "L", the address bus 94 and the data bus 95 are set in the next cycle, and / WR is set to "L". If set, data is input to the second semiconductor memory element 92.
JP 2001-510612 A

  In the prior art, when the same data is written to separate semiconductor memory elements having different control methods at the time of data reading / writing, it is necessary to perform the writing operation on each semiconductor memory element at different cycles. For this reason, a write operation is required for each semiconductor memory element, and the processing time is generally long.

  The present invention has been made in view of the above technical problems, and basically provides a semiconductor memory system capable of realizing reduction in time and efficiency of reading / writing with respect to a plurality of semiconductor memory elements. With the goal.

  According to a first aspect of the present invention, there is provided a semiconductor memory system having a plurality of semiconductor memory elements, wherein a read / write operation of the semiconductor memory elements is controlled in accordance with a command from an externally provided CPU. Semiconductor memory device having input, output enable signal input, write enable signal input, address input, and data input / output, and performing high-speed data read / write through an interface via a bus connected to the address input and data input / output A semiconductor memory element that has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to read / write data; A controller for controlling read / write operations of each semiconductor memory element; It has, in the case where a predetermined mode for the controller is set, in which characterized in that A pass the controller is accessible directly to the semiconductor memory device.

  According to a second aspect of the present invention, there is provided a semiconductor memory system having a plurality of semiconductor memory elements, wherein a read / write operation of the semiconductor memory elements is controlled in accordance with a command from an externally provided CPU. A plurality of semiconductor memory elements having a select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performing different data read / write operations from the data input / output And a controller for controlling the reading / writing of each of the semiconductor memory elements. When accessing any of the semiconductor memory elements, a uniform command is used during the reading / writing operation via the controller. It is characterized by being executable.

  Further, a third invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled in accordance with a command from a CPU provided outside. Volatilization has a select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data at an interface via a bus connected to the address input and the data input / output A semiconductor memory device, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and a command is sent from the data input / output to read / write data. Nonvolatile semiconductor memory element to be read and reading / writing of each of the above semiconductor memory elements A controller for controlling only the operation, and automatically transferring data of a part or all of the non-volatile semiconductor memory element to the volatile semiconductor memory element when the power is turned on. It is a thing.

  Furthermore, a fourth invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled in accordance with a command from a CPU provided outside. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and a command is sent from the data input / output to perform a data read / write operation The semiconductor memory element and the read / write operation of each of the semiconductor memory elements are controlled. And when a command, a transfer destination address, a transfer source address and a data amount are given to the controller, data is transferred from the semiconductor memory element to another semiconductor memory element in the system. It is characterized by being transferable.

  Still further, a fifth invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled in accordance with a command from a CPU provided outside. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and a command is sent from the data input / output to perform a data read / write operation The semiconductor memory element and the read / write operation of each of the semiconductor memory elements are controlled. When reading data from one of the semiconductor memory elements, the data is written to an arbitrary address of another semiconductor memory element and the data is output from the controller to the outside. It is characterized by.

  Still further, a sixth invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled in accordance with a command from a CPU provided outside. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A volatile semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and read / write data by sending a command from the data input / output Nonvolatile semiconductor memory element that operates, and reading of each of the semiconductor memory elements A controller for controlling the write operation, and the controller performs the nonvolatile semiconductor memory element at a constant time interval with respect to data of a part or the whole area of the volatile semiconductor memory element. This data is written in the memory.

  Still further, a seventh invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled according to a command from an externally provided CPU. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A volatile semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and read / write data by sending a command from the data input / output Nonvolatile semiconductor memory element that operates, and reading of each of the semiconductor memory elements A controller for controlling the write operation, and by a command sent from the CPU to the controller, data in a part or all of the area of the volatile semiconductor memory element and the nonvolatile semiconductor memory Comparing with data of a part or all of the element region, reading data of a volatile semiconductor memory element for a region where the data is different, and writing the data to the nonvolatile semiconductor memory element It is what.

  Furthermore, an eighth invention of the present application is a semiconductor memory system having a plurality of semiconductor memory elements, wherein read / write operations of the semiconductor memory elements are controlled in accordance with a command from a CPU provided outside. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A volatile semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and read / write data by sending a command from the data input / output Nonvolatile semiconductor memory element that operates, and reading of each of the semiconductor memory elements A controller for controlling the write operation, the area of the volatile semiconductor memory element is divided into a predetermined number of areas, and an update flag is provided in each area, and the data in the area is updated. The update flag is set, and the controller reads the data of the volatile semiconductor memory element only for the area where the update flag is set, and writes the data to the nonvolatile semiconductor memory element. It is a feature.

  According to a first invention of the present application, in a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from an externally provided CPU. A semiconductor having a select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performing high-speed data read / write through an interface via a bus connected to the address input and the data input / output A semiconductor memory element having a memory element, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reading / writing data by sending a command from the data input / output And a controller for controlling the read / write operation of each semiconductor memory element. When a predetermined mode is set for the controller, it can pass through the controller and directly access and control each semiconductor memory element, so the conventional system can be applied. It is.

  According to the second invention of the present application, in the semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled in accordance with a command from an externally provided CPU. A plurality of semiconductors each having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sending different commands from the data input / output to perform data read / write operations A storage element and a controller for controlling reading / writing of each of the semiconductor storage elements, and when accessing any of the semiconductor storage elements, a unified read / write operation is performed via the controller. Multiple halves that can be executed with a command, i.e. need to be accessed with different commands Since even for body storage element is accessible by the same control method, it is possible to improve the convenience of the system.

  Furthermore, according to the third invention of the present application, in a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled in accordance with a command from an externally provided CPU. It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reads / writes data at a high speed through an interface connected to the address input and the data input / output. A volatile semiconductor memory device to perform, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and read / write data by sending a command from the data input / output Nonvolatile semiconductor memory element that operates, and reading of each of the semiconductor memory elements A controller for controlling the write operation, and when the power is turned on, data of a part or all of the non-volatile semiconductor memory element is automatically transferred to the volatile semiconductor memory element. When the program is turned on, the program can be immediately activated.

  Furthermore, according to the fourth invention of the present application, a semiconductor memory having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements being controlled in accordance with a command from an externally provided CPU. The system has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed data reading / reading through an interface via a bus connected to the address input and the data input / output. A semiconductor memory element for writing, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and a command is sent from the data input / output to read / write data Semiconductor memory device performing read / write operations of each of the above semiconductor memory devices And when the command, transfer destination address, transfer source address and data amount are given to the controller, data is transferred from the semiconductor memory element to another semiconductor memory element. Since data can be transferred without using the CPU bus, the convenience of the system can be improved.

  Still further, according to the fifth invention of the present application, the semiconductor memory has a plurality of semiconductor memory elements, and the read / write operation of the semiconductor memory elements is controlled in accordance with a command from an externally provided CPU. The system has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed data reading / reading through an interface via a bus connected to the address input and the data input / output. A semiconductor memory element for writing, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and a command is sent from the data input / output to read / write data Semiconductor memory device performing read / write operations of each of the above semiconductor memory devices When reading data from one of the semiconductor memory elements, the data is written to an arbitrary address of another semiconductor memory element and the data is output from the controller to the outside. Therefore, it is not necessary to write the same data again to another semiconductor memory element, data writing can be made efficient, and the time required for it can be shortened.

  Still further, according to the sixth invention of the present application, the semiconductor memory has a plurality of semiconductor memory elements, and the read / write operation of the semiconductor memory elements is controlled according to a command from an externally provided CPU. The system has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed data reading / reading through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element for writing, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reading data by sending a command from the data input / output / Nonvolatile semiconductor memory element performing write operation and each of the above semiconductor memory elements A controller for controlling a read / write operation, and the controller controls the nonvolatile semiconductor memory at a certain time interval with respect to data of a part or the whole area of the volatile semiconductor memory element. Since the data is written to the device, the controller can automatically back up the volatile semiconductor memory device to speed up the operation, and accordingly, the reliability of the data and the convenience of the system. Can be improved.

  Still further, according to the seventh invention of the present application, the semiconductor memory has a plurality of semiconductor memory elements, and the read / write operation of the semiconductor memory elements is controlled according to a command from an externally provided CPU. The system has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed data reading / reading through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element for writing, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reading data by sending a command from the data input / output / Nonvolatile semiconductor memory element performing write operation and each of the above semiconductor memory elements A controller that controls read / write operations, and a command sent from the CPU to the controller, data in a part or all of the area of the volatile semiconductor memory element, and the nonvolatile semiconductor Compare the data of a part or all of the area of the memory element, read the data of the volatile semiconductor memory element for the area where the data is different, and write the data to the nonvolatile semiconductor memory element, Access between the microcomputer and the semiconductor storage system is increased in speed, and data can be retained even when the power is turned off, improving the convenience of the system.

  Furthermore, according to the eighth invention of the present application, a semiconductor memory having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements being controlled in accordance with a command from a CPU provided outside. The system has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed data reading / reading through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element for writing, a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and reading data by sending a command from the data input / output / Nonvolatile semiconductor memory element performing write operation and each of the above semiconductor memory elements A controller for controlling the read / write operation, dividing the area of the volatile semiconductor memory element into a predetermined number of areas, further providing an update flag in each area, and updating the data in the area The update flag is set, and the controller reads the data of the volatile semiconductor memory element only for the area where the update flag is set, and writes the data to the nonvolatile semiconductor memory element. That is, the controller automatically detects the updated area in the volatile semiconductor memory element and writes only the data in the area to the nonvolatile semiconductor memory element, so that the backup work can be made more efficient. Accordingly, the reliability of data and the convenience of the system can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a semiconductor memory system and a CPU connected thereto according to Embodiment 1 of the present invention. This semiconductor memory system 1 has first and second semiconductor memory elements 3 and 4, and data read / write in each semiconductor memory element 3 and 4 is executed in accordance with a command from an externally provided CPU 10. Is done. Further, the semiconductor storage system 1 has a controller 2 interposed between the external CPU 10 and the first and second semiconductor storage elements 3 and 4. The semiconductor memory elements 3 and 4 are controlled.

  The first semiconductor memory element 3 has, as interface terminals with the controller 2, a chip select signal input “/ S”, an output enable signal input “/ OE”, an output enable signal input “/ W”, Address inputs “A0 to Am” and data inputs / outputs “DQ1 to DQ16” are provided. In the first semiconductor memory element 3, data is read / written at high speed through an interface via a bus connected to address input and data input / output.

  On the other hand, the second semiconductor memory element 4 has, as interface terminals with the controller 2, a chip select signal input “CE #”, an output enable signal input “OE #”, and a write enable signal input “WE #”. , Read protect signal input “RP #”, write protect signal input “WP #”, address inputs “A0 to An”, and data input / output “DQ0 to DQ15”. In the second semiconductor memory element 4, a command is sent from the data input / output to read / write data.

  The controller 2 uses a chip select signal output “/ MCS1” connected to “/ S” of the first semiconductor memory element 3 via the control bus 5a as an interface terminal with the first semiconductor memory element 3, and “ Output enable signal output “/ MOE1” connected to / OE via the control bus 5b, and write enable signal output “/ MWE1” connected to “/ W” via the control bus 5c. .

  On the other hand, the controller 2 serves as an interface terminal with the second semiconductor memory element 4 and outputs a chip select signal “/ MCS0” connected to “CE #” of the second semiconductor memory element 4 via the control bus 6a. ", Output enable signal output" / MOE0 "connected to" OE # "via the control bus 6b, and write enable signal output" / MWE0 "connected to" WE # "via the control bus 6c, The read protect signal output “/ MRP” is connected to “RP #” via the control bus 6d, and the write protect signal output “/ MWP” is connected to “WP #” via the control bus 6e. .

  Further, the controller 2 uses “A0 to Am” of the first semiconductor memory element 3 and “A0 to Am2” of the second semiconductor memory element 4 as a common interface with the first and second semiconductor memory elements 3 and 4. Data buses to address outputs “MAD1 to MADx” connected to “An” via the address bus 7, “DQ1 to DQ16” of the first semiconductor memory element 3, and “DQ0 to DQ15” of the second semiconductor memory element 4 8 and data input / output “MI / O0 to MI / O15”.

  Further, the controller 2 has, as an interface with the CPU 10 provided outside, a chip select signal input “/ CCS”, a write output enable signal input “/ CWE”, and an output enable signal input “/ COE”. Address inputs “CAD0 to CADx” and data input / output “CI / O0 to CI / O15”.

  On the other hand, the CPU 10 serves as an interface terminal for the controller 2 as a chip select signal output “CSn” connected to “/ CCS” via the control bus 11 a and to “/ CWE” via the control bus 11 b. Write signal output “/ WR” to be connected, read signal output “/ RD” to be connected to “/ COE” via the control bus 11 c, and address output “to be connected to“ CAD0 to CADx ”via the address bus 12“ MA0 to MAx ”and data inputs / outputs“ D0 to D15 ”connected to“ CI / O0 to CI / O15 ”via the data bus 13.

  FIG. 2 is a diagram conceptually showing the memory area of the semiconductor storage system 1. Although not particularly illustrated, the controller 2 has a control register which is a high-speed memory for various arithmetic processes. As can be seen from FIG. 2, the entire memory area in the semiconductor memory system 1 includes the area 16 (0000000h to XXXXXXh) by the first semiconductor memory element 3, the area 17 (ZZZZZZZh to SSSSSSSh) by the control register in the controller 2, and the second. Region 18 (YYYYYYYh to FFFFFFFh) of the semiconductor memory element.

  FIG. 3 shows a region 17 by a control register in the controller 2. This area 17 is composed of a register group for various kinds of arithmetic processing. The dual write control registers 17a, / RP and / WP control register 17b, address offset register 17c, first connection semiconductor memory element setting register 17d, second register Connection semiconductor memory element setting register 17e, transfer source address register 17f, transfer destination address register 17g, transfer data amount register 17h, data transfer control register 17i, simultaneous read / write control register 17j, write address register 17k, automatic backup control register 17l , A comparative update control register 17m.

  FIG. 4 shows an example of the input / output waveform of the controller 2. By using such a waveform, the same address is used for the first and second semiconductor memory elements 3 and 4 in one write operation. The same data can be written simultaneously. A write operation using such input / output waveforms will be described.

  First, “1” is written to the corresponding bits of the / RP and / WP control registers 17b in the controller 2, and the read protect signal output “/ MRP” and the write protect signal output “/ MWP” are set to “H”. . Next, a dual write command “4444h” is input from the CPU 10 to the dual write control register 17 a of the controller 2 via the data bus 13. At this time, the controller 2 writes the program command “4040h” only to the second semiconductor memory element 4.

  Subsequently, when the CPU 10 causes the controller 2 to set the write address to the address outputs “MAD1 to MDx” and sets the write data to the data input / output “MI / O0 to MI / O15”, both are written. It becomes possible to write the same data to the same address as that given by the CPU 10 to the semiconductor memory elements 3 and 4.

  In this way, it is possible to write to a plurality of semiconductor memory elements 3 and 4 having different control methods at the time of data reading / writing in one write operation, and the CPU 10 saves the trouble of writing separately for the semiconductor memory elements 3 and 4. The writing time can be shortened and the convenience can be improved.

Hereinafter, another embodiment of the present invention will be described. In the following description, the same reference numerals are given to the same components as those in the first embodiment, and further description is omitted.
Embodiment 2. FIG.
FIG. 5 is a block diagram showing a semiconductor memory system and a CPU connected thereto according to the second embodiment of the present invention. The semiconductor memory system 20 has substantially the same configuration as that in the first embodiment. In the second embodiment, the controller 22 outputs an address for each of the first and second semiconductor memory elements 3 and 4. “MAAD1 to MAADx” and “MBAD1 to MBADx” are provided, and these address outputs are address inputs “A0 to An” of the first and second semiconductor memory elements via the address buses 27A and 27B, respectively. "," A0 to Am ".

  FIG. 6 shows an example of the input / output waveform of the controller 22. By using such a waveform, the same data can be simultaneously applied to different addresses of the two semiconductor memory elements 3 and 4 by one write operation. Can write. A write operation using such input / output waveforms will be described. The controller 22 has a control register, which is a high-speed memory for various arithmetic processing, like the controller 2 in the first embodiment, and a controller as shown in FIG. 2 has a region 17 by the control register. In the second embodiment, in addition to the dual write control register 17a, the address offset register 17c, which is one configuration of the control register group shown in FIG. 3, is used for the write operation.

  First, “1” is written to the corresponding bits of the / RP and / WP control registers 17b in the controller 22, and the read protect signal output “/ MRP” and the write protect signal output “/ MWP” are set to “H”. . Next, an address to be written to the second semiconductor memory element 4 is input to the address offset register 17 c in the form of an offset address from the address to be written to the first semiconductor memory element 3. Therefore, the address written to the second semiconductor memory element 4 is the write address from the CPU + the offset address.

  Subsequently, as shown in FIG. 6, a dual write command (4444h) is input from the CPU 10 to the dual write control register 17a. At this time, the controller 22 writes the program command (4040h) only to the first semiconductor memory element 3.

  Next, the CPU 10 causes the controller 22 to set the write address to the address outputs “MAAD1 to MAADx” and “MBAD1 to MBADx” and sets the write data to the data input / output “MI / O0 to MI / O15”. As a result, the write address given by the CPU 10 to the first semiconductor memory element 3 and the write address plus the offset address given by the CPU 10 to the second semiconductor memory element 4 as a result. A write address is given, and the same data as that given by the CPU 10 can be written to both the semiconductor memory elements 3 and 4.

  As described above, the same data can be simultaneously written to different addresses of the semiconductor memory elements 3 and 4 having different control methods at the time of data reading / writing by one write operation. As a result, the CPU 10 can save the trouble of writing each of the semiconductor memory elements 3 and 4, shorten the writing time, and improve the convenience.

Embodiment 3 FIG.
FIG. 7 is a block diagram showing a semiconductor memory system and a CPU connected thereto according to Embodiment 3 of the present invention. The semiconductor storage system 30 has almost the same configuration as that in the first embodiment. In the third embodiment, in addition to the configuration, the controller 32 is used as an interface terminal for the CPU 31 provided outside. , Has a chip select signal input “CCS1”. Correspondingly, the CPU 31 has a chip select signal output “/ CSm” connected to “CCS1” via the control bus 35.

  Access to the semiconductor memory elements 3 and 4 in the semiconductor memory system 30 by the CPU 31 is performed in the same manner as described in the prior art. That is, when the CPU 31 accesses the first semiconductor memory element 3, “/ CSm” is set to “L” to select the first semiconductor memory element 3, and then the first semiconductor memory element 3 is used as an address input destination. When the address inputs “A0 to Am” are set and “/ RD” of the CPU 31 is set to “L”, data can be read from the first semiconductor memory element 3. On the other hand, if the address input “A0 to Am” is set as the address input destination, the data input / output “DQ1 to DQ16” is set as the data input destination, and “/ WR” of the CPU 31 is set to “L”, the first Data can be written into the semiconductor memory element 3.

  On the other hand, when the CPU 31 accesses the second semiconductor memory element 4, first, the read protection signal of the second semiconductor memory element 4 is used by using the / RP and / WP control register 17b described in the first embodiment. Both the input “RP #” and the write protect signal input “WP #” are set to “H”, the “/ CSn” of the CPU 31 is set to “L”, and the second semiconductor memory element 4 is selected.

  Then, a read command (Read Command) is set to the data bus 8, “/ WR” of the CPU 31 is set to “L”, the address bus 7 is set in the next cycle, and “/ RD” of the CPU 31 is set to “L”. If set to, data can be read from the second semiconductor memory element 4. On the other hand, a program command (Program Command) is set to the data bus, “/ WR” is set to “L”, the address bus 7 and the data bus 8 are set in the next cycle, and “/ WR” is set to “L”. In this case, data can be written to the second semiconductor memory element 4.

  Thus, since the semiconductor memory system 30 can control the semiconductor memory elements without using the controller in the system 30, a conventional system is applicable and excellent in convenience.

Embodiment 4 FIG.
FIG. 8 is a block diagram showing a semiconductor memory system and a CPU connected thereto according to Embodiment 4 of the present invention. The semiconductor memory system 40 includes a semiconductor memory element 43 that performs a read / write operation by command control instead of the first semiconductor memory element 3 described in the first to third embodiments as a first semiconductor memory element. Have. The first semiconductor memory element 43 has, as interface terminals with the controller 42, a chip select signal input “CE #”, an output enable signal input “OE #”, a write enable signal input “WE #”, It has a write protect signal input “WP #”, a reset signal input “RESET #”, and a READY / BUSY status signal output “RY / BY #”.

  Further, the controller 42 serves as an interface terminal with the first semiconductor memory element 43, and outputs a chip select signal “/ MCS1” connected to “CE #” of the first semiconductor memory element 43 via the control bus 45a. , Output enable signal output “/ MOE1” connected to “OE #” via control bus 45b, write enable signal output “/ MWE1” connected to “WE #” via control bus 45c, and “WP” Write protect signal output “/ MWP1” connected to the “#” via the control bus 45d, read protect signal output “/ MRP1” connected to the “RESET #” via the control bus 45e, and “RY / BY #” READY / BUSY status connected to control bus 45f It has a signal input “R / B”.

  FIGS. 9 and 10 are diagrams showing an external waveform and an internal waveform of the controller 42 when writing to the first and second semiconductor memory elements 4 and 43. In the fourth embodiment, the first connection semiconductor memory element setting register 17d and the second connection semiconductor memory element setting register 17e, which are one configuration of the control register group shown in FIG. 3, are used.

  The operation of the semiconductor storage system 40 will be described. First, the CPU 10 sets the types of the semiconductor storage elements 43 and 4 in the semiconductor storage system 40 connected thereto in the registers 17d and 17e. That is, the value for the semiconductor memory element connected to the first connected semiconductor memory element setting register 17d is set. Next, a value for the semiconductor memory element connected to the second connection semiconductor memory element setting register 17e is set.

  As a result, as shown in FIGS. 9 and 10, the internal waveform is changed to a waveform suitable for the control method of the respective semiconductor memory elements 43 and 4 even though the signal from the CPU 10 remains the same. It will be input in. At this time, “WP #”, “RP #”, and “RESET #” of the first semiconductor memory element 43 are set to “H” in advance by the / RP and / WP control register 17b.

  Thus, according to the semiconductor memory system 40, the semiconductor memory elements 43 and 4 having different control methods at the time of data reading / writing may have the same control method from the outside, and the control software is changed. Since it can be used without any problems, convenience is improved.

Embodiment 5. FIG.
FIG. 11 is a block diagram showing a semiconductor storage system and a CPU connected thereto according to the fifth embodiment of the present invention. The semiconductor storage system 50 has substantially the same configuration as that in the second embodiment. In the fifth embodiment, a voltage detection circuit 57 is further provided, and the controller 52 includes a first and a first. As the terminals for interfacing with the second semiconductor memory elements 3 and 4, the data outputs “MAI / O0 to MAI / O15” and “MBI / O0 to MBI / O15” are provided for each of the first and second semiconductor memory elements 3 and 4. "Is provided. Furthermore, in the fifth embodiment, in particular, the first semiconductor memory element 3 is a volatile memory, and the second semiconductor memory element 4 is a nonvolatile memory.

  The voltage detection circuit 57 has a reset signal output “RESET #” as an interface terminal with the controller 52, and has a voltage terminal “VDD” and a ground terminal “GND” connected to a power source as external terminals. is doing. Correspondingly, the controller 52 has a reset signal input “/ RST” connected to “RESET #” of the voltage detection circuit 57 via the control bus 59.

  The data outputs “MAI / O0 to MAI / O15” and “MBI / O0 to MBI / O15” of the controller 52 are respectively connected to the first and second semiconductor memory elements 3 via the data buses 58A and 58B. 4 data inputs “A0 to An” and “A0 to Am”.

FIG. 12 is a diagram illustrating an example of a waveform at power-on in the semiconductor storage system 50. The operation of the semiconductor storage system 50 will be described with reference to FIG.
First, when the power is turned on, the voltage detection circuit 57 detects it and generates a reset signal. From the next cycle after the reset signal is released, the second semiconductor memory element 4 enters a read operation for reading data in a range based on a predetermined address. At the same time, the address bus, control bus, and data bus are operated so that the same read data can be written to a predetermined address of the first semiconductor memory element 3.

  In this way, since the power-on is detected and the predetermined data is automatically transferred, the work using the data can be executed immediately without forcing the user to perform the data transfer work. Will improve. Further, since the data transfer work is also executed without going through the CPU 10, it is possible to reduce the load on the CPU 10 when the power is turned on. Further, in the seventh embodiment, when the power is turned on, the program can be immediately activated.

Embodiment 6 FIG.
The semiconductor storage system according to the sixth embodiment of the present invention has the same configuration as in the fifth embodiment, and will be described below with reference to FIG. FIG. 13 shows an internal waveform of the semiconductor memory system 50 at the time of data transfer. FIG. 14 is a diagram showing a memory area of the semiconductor storage system 50. In FIG. 14, the data of CCCC bytes (CCCCbytes in the figure) existing in the transfer source address AAAAAAh in the memory area 18 by the second semiconductor memory element 4 is stored in the memory area 16 by the first semiconductor memory element 3. Transferred to transfer destination address BBBBBBBh.
In the sixth embodiment, a transfer source address register 12f, a transfer destination address register 12g, a transfer data amount register 12h, and a data transfer control register 12i, which are one configuration of the control register group shown in FIG. 3, are used.

  The operation of the semiconductor storage system 50 will be described. As shown in FIG. 13, first, the CPU 10 writes the transfer source address in the transfer source address register 12f. Next, the CPU 10 writes the transfer destination address in the transfer destination address register 12g, and further writes the amount of data to be transferred in the transfer data amount register 12h. Then, a command (8080) for performing data transfer from the first semiconductor memory element 3 to the second semiconductor memory element 4 is written into the data transfer control register 12i. Thereby, the data transfer as shown in FIG. 13 is started while the internal bus in the semiconductor memory system 50 is used.

  Specifically, first, a read command (9090) is input to the first semiconductor memory element 3. Next, the number of bytes indicated in the transfer data amount register 12h is read in order from the transfer source address. At the same time, for the second semiconductor memory element 4, an operation of writing the read data as it is as the data amount designated from the transfer destination address is performed.

  In this way, if the transfer source address, the transfer destination address, and the transfer data amount are specified in various registers and a transfer command is input to the controller 52, the controller 52 transfers it internally separately from the CPU 10, thus reducing the load on the CPU 10. Since the CPU 10 bus is not used, other operations can be performed. Thereby, the convenience of the system can be improved.

Embodiment 7 FIG.
The semiconductor storage system according to the seventh embodiment of the present invention has the same configuration as that in the fifth embodiment, and will be described below with reference to FIG. FIG. 15 shows internal and external waveforms when the semiconductor memory system 50 reads data.
In the seventh embodiment, the simultaneous read / write control register 12j and the write address register 12k, which are one configuration of the control register group shown in FIG. 3, are used.

  An operation of the semiconductor storage system 50 will be described. First, the CPU 10 designates an address to be written in the write address register 17k. Next, a command (9999h) for reading data from the first semiconductor memory element 3 and simultaneously writing the same data to the second semiconductor memory element 4 is set in the simultaneous read / write control register 17j. Thus, based on the control register group as shown in FIG. 3, the read command is input to the first semiconductor memory element 3 and the data is read. The read data is transmitted from the MAI / O to the D10 to D15 of the CPU 10 via the CI / O. On the other hand, in the second semiconductor memory element 4, the same data is sequentially written to the addresses set as the write addresses simultaneously via the MAI / O and the MBI / O.

  Thus, by writing data to the semiconductor memory element at the same time as reading data, the trouble of transferring the data can be omitted when the same data is read next time, and convenience is improved.

Embodiment 8 FIG.
The semiconductor storage system according to the eighth embodiment of the present invention has the same configuration as in the fifth embodiment, and will be described below with reference to FIG. FIG. 16 is a diagram conceptually showing a memory area related to backup, which is a part of the memory area of the semiconductor storage system 50. As shown in FIG. 16, the area formed by the first semiconductor memory element 3 includes a volatile memory area 61 that performs backup, and the area formed by the second semiconductor memory element 4 includes A non-volatile memory area 62 is stored.

  FIG. 17 shows an internal waveform of the controller 10 of the semiconductor storage system 50. An operation of the semiconductor storage system 50 will be described. First, when the CPU 10 sets automatic backup in the automatic backup control register 12 l of the controller 10, backup is performed in the nonvolatile memory area 62 for the volatile memory area 61 at predetermined time intervals. As shown in FIG. 17, the internal waveform at the time of backup is to program data in the first semiconductor memory element 3 to which a program command (Program Command) has been input in advance simultaneously with the read operation of the second semiconductor memory element 4.

  As described above, since the controller 52 takes charge of the backup work for the first and second semiconductor memory elements 3 and 4 separately from the load on the CPU 10, the load on the CPU 10 can be reduced and the operation speed can be increased. As a result, improvement in performance can be expected.

Embodiment 9 FIG.
The semiconductor memory system according to the ninth embodiment of the present invention has the same configuration as that in the fifth embodiment, and will be described below with reference to FIG. FIG. 18 is a diagram conceptually showing the comparison update process performed in the memory area of the semiconductor storage system 50. FIG. 19 shows an internal waveform in the semiconductor storage system 50. In the ninth embodiment, a comparison / update control register 17m, which is one configuration of the control register group shown in FIG. 3, is used.

  An operation of the semiconductor storage system 50 will be described. When the CPU 10 sets a comparative update command (2222h) to the comparative update control register 17m, as shown in FIG. 19, in the semiconductor storage system 50, data is simultaneously transmitted from the first and second semiconductor storage elements 3 and 4. Are read out and data comparison is started. This comparison is executed within a preset range. If the contents of the two semiconductor memory elements 3 and 4 are equal as a result of the comparison, the comparison is executed for the next address within a preset range. On the other hand, if the contents of the two semiconductor memory elements 3 and 4 are different, the memory contents of the volatile semiconductor memory element 3 are stored in the nonvolatile semiconductor memory element 4 and the contents are updated. In this way, the comparison update operation is executed up to a preset range.

  As described above, since the controller 52 takes charge of the backup operation of the memory area in the semiconductor storage system 50 separately from the load on the CPU 10, the load on the CPU 10 can be reduced, and the performance of the system as a whole is expected to be improved. Further, since the comparison is performed by simultaneously reading data from the plurality of semiconductor memory elements 3 and 4, the time required for the comparison update can be shortened as compared with the case where the data is read and compared one by one. Further, in the ninth embodiment, access between the microcomputer and the semiconductor storage system 50 is accelerated, and data can be retained even when the power is turned off, thereby improving the convenience of the system. it can.

Embodiment 10 FIG.
The semiconductor storage system according to the tenth embodiment of the present invention has the same configuration as in the fifth embodiment, and will be described below with reference to FIG. FIG. 20 is a diagram conceptually showing a mode in which the memory area of the volatile semiconductor memory element 3 is divided and managed. FIG. 21 shows an update flag register (ZZZZZZZ + 20) h for the divided memory areas. 17 referring to the eighth embodiment further shows an internal waveform at the time of update in the semiconductor memory system 50. FIG.

  An operation of the semiconductor storage system 50 will be described. When the CPU 10 rewrites a part of the area of the volatile semiconductor storage element 3, for example, when the part of the third area in the volatile semiconductor storage element 3 is rewritten, as shown in FIG. Sets bit 2 of the update flag register and informs the controller 52 that this area has been updated. The controller 52 that has received the flag information reads data from the volatile semiconductor storage element 3 in the semiconductor storage system 50 and simultaneously writes data to the nonvolatile semiconductor storage element 4 as shown in FIG. Only the third area is updated.

  As described above, in the tenth embodiment, the controller 52 automatically detects the updated area in the volatile semiconductor memory element 3, and writes only the data in the area to the nonvolatile semiconductor memory element 4. Since the memory update work can be divided and executed, the time for one update work is completed in a short time, and the backup work can be made more efficient. Accordingly, the reliability of the data and the convenience of the system can be improved.

  Note that the present invention is not limited to the illustrated embodiments, and it goes without saying that various improvements and design changes are possible without departing from the scope of the present invention.

It is a figure which shows the semiconductor memory system which concerns on Embodiment 1 of this invention, and CPU connected to it. FIG. 3 is a diagram conceptually showing a memory area of the semiconductor storage system. It is a figure which shows the area | region by the control register in a controller which is a part of memory area in the said semiconductor memory system. It is a figure showing an example of the input-output waveform of the said controller. It is a figure which shows the semiconductor memory system which concerns on Embodiment 2 of this invention, and CPU connected to it. It is a figure showing an example of the input / output waveform of the controller in the semiconductor memory system concerning the above-mentioned Embodiment 2. It is a figure which shows the semiconductor memory system which concerns on Embodiment 3 of this invention, and CPU connected to it. It is a figure which shows the semiconductor memory system which concerns on Embodiment 4 of this invention, and CPU connected to it. It is a figure showing the external waveform at the time of the data writing to the 1st and 2nd semiconductor memory element in the semiconductor memory system concerning the said Embodiment 4. FIG. It is a figure showing the internal waveform at the time of the data writing to the 1st and 2nd semiconductor memory element in the semiconductor memory system concerning the said Embodiment 4. FIG. It is a figure which shows the semiconductor memory system which concerns on Embodiment 5 of this invention, and CPU connected to it. It is a figure showing the waveform at the time of power activation in the semiconductor memory system concerning the above-mentioned Embodiment 5. It is a figure showing the internal waveform at the time of the data transfer in the semiconductor memory system concerning Embodiment 6 of this invention. It is a figure showing the memory area of the semiconductor memory system concerning the said Embodiment 6. FIG. It is a figure showing the internal and external waveform at the time of data reading in the semiconductor memory system concerning Embodiment 7 of this invention. It is a figure which shows notionally the memory area relevant to backup which is a part of memory area in the semiconductor memory system concerning Embodiment 8 of this invention. It is a figure showing the internal waveform of the controller 10 in the semiconductor memory system concerning the said Embodiment 8. FIG. It is a figure which shows notionally the data comparison update process in the memory area of the semiconductor memory system based on Embodiment 9 of this invention. It is a figure showing an internal waveform in the semiconductor memory system concerning the above-mentioned Embodiment 9. In the semiconductor memory system which concerns on Embodiment 10 of this invention, it is a figure which shows notionally the aspect which divides | segments and manages the memory area of a volatile semiconductor memory element. It is a figure showing the update flag register with respect to the said memory area divided | segmented It is a figure which shows the conventional semiconductor memory system and CPU connected to it.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory system, 2 Controller, 3 1st semiconductor memory element, 4 2nd semiconductor memory element, 5a, 5b, 5c, 6a, 6b, 6c, 6d, 6e, 11a, 11b, 11c Control bus, 7, 12 address bus, 8 and 13 data bus, 10 CPU, 17 memory area by control register, 17a dual write control register, 17b / RP and / WP control register, 17c address offset register, 17d first connection semiconductor memory element, 17e first 2-connected semiconductor memory element, 17f transfer source address register, 17g transfer destination address register, 17h transfer data amount register, 17i data transfer control register, 17j simultaneous read / write register, 17k write address register, 17l automatic backup control register Data, 17m compared update control register, 57 voltage detection circuit.

Claims (8)

In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A semiconductor memory element;
A semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output; and sending / receiving a command from the data input / output;
A controller for controlling the read / write operation of each semiconductor memory element,
A semiconductor memory system characterized in that when a predetermined mode is set for the controller, each semiconductor memory element can be directly accessed through the controller. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
A plurality of semiconductor memories each having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performing data read / write operations by sending different commands from the data input / output Elements,
A controller for controlling reading / writing of each of the semiconductor memory elements,
Whatever the semiconductor memory element is accessed, a semiconductor memory system is characterized in that it can be executed with a unified command during a read / write operation via the controller. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element;
A nonvolatile semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation When,
A controller for controlling the read / write operation of each of the semiconductor memory elements,
A semiconductor memory system, wherein data of a part or all of the non-volatile semiconductor memory element is automatically transferred to the volatile semiconductor memory element when power is turned on. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A semiconductor memory element;
A semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation;
A controller for controlling the read / write operation of each of the semiconductor memory elements,
When a command, a transfer destination address, a transfer source address, and a data amount are given to the controller, data can be transferred from the semiconductor memory element to another semiconductor memory element in the system. Semiconductor storage system. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A semiconductor memory element;
A semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation;
A controller for controlling the read / write operation of each of the semiconductor memory elements,
When reading data from one of the semiconductor memory elements, the data is written to an arbitrary address of another semiconductor memory element, and at the same time, the data is output from the controller to the outside. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element;
A nonvolatile semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation When,
A controller for controlling the read / write operation of each of the semiconductor memory elements,
The semiconductor memory system, wherein the controller writes the data to the nonvolatile semiconductor memory element at a constant time interval with respect to data of a part or the whole area of the volatile semiconductor memory element. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element;
A nonvolatile semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation When,
A controller for controlling the read / write operation of each of the semiconductor memory elements,
Comparison between a part or all of the volatile semiconductor memory element data and a part or all of the non-volatile semiconductor memory element data by a command sent from the CPU to the controller And reading out data from a volatile semiconductor memory element in regions where the data are different, and writing the data into the nonvolatile semiconductor memory element. In a semiconductor memory system having a plurality of semiconductor memory elements, the read / write operation of the semiconductor memory elements is controlled according to a command from a CPU provided outside,
It has a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and performs high-speed reading / writing of data through an interface via a bus connected to the address input and the data input / output. A volatile semiconductor memory element;
A nonvolatile semiconductor memory element having a chip select signal input, an output enable signal input, a write enable signal input, an address input, and a data input / output, and sends a command from the data input / output to perform a data read / write operation When,
A controller for controlling the read / write operation of each of the semiconductor memory elements,
When the area of the volatile semiconductor memory element is divided into a predetermined number of areas, an update flag is provided in each area, and when the data in the area is updated, the update flag is set, and the controller A semiconductor memory system, wherein data of the volatile semiconductor memory element is read out only for an area in which an update flag is set, and the data is written into the nonvolatile semiconductor memory element.

Images