JP2007114625A - Display device and electronic apparatus with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that an area coverage modulation system has in relation to the mounting cost for an external IC and to solve the problem that a clock signal is delayed behind a start pulse signal when a signal is input from the external IC without providing a delay circuit to an input part of a driver. <P>SOLUTION: A display device has a pixel area where pixels including sub-pixels are arranged in a matrix, a source signal line driving circuit, a gate signal line driving circuit, and a control circuit, and is characterized in that the sub-pixels, source signal line driving circuit, gate signal line driving circuit, and control circuit have thin film transistors formed on a substrate and the control circuit has a circuit outputting signals for driving the source signal line driving circuit and gate signal line driving circuit with a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock signal input from outside the substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device having a pixel region in which pixels are arranged in a matrix. In particular, the present invention relates to a display device having a pixel region in which pixels having sub-pixels are arranged in a matrix.

  The area gray scale method, which is one of the gray scale display methods of display devices such as a liquid crystal display (LCD) and an electroluminescence (EL) display, is a binary light emission of pixels. Therefore, there is no need to mount a DA converter circuit for video signal processing. Further, it is not necessary to divide one frame seen in the time gray scale method into a plurality of subframes. Therefore, video signals can be sequentially input to the drive circuit and reflected in the display in the pixel area. Therefore, it is not necessary to mount a large-scale frame memory, and the display can be operated at a low frequency. Therefore, the area gradation method is a display method that can realize low power consumption and low cost.

  However, since the area gray scale method has a configuration including sub-pixels (also referred to as sub-pixels), there is a problem in that driving circuits and mounting costs increase due to an increase in the number of scanning lines.

Therefore, as shown in FIG. 18, the source line driver circuit (SD), the gate line driver circuit (GD), the respective buffer circuits (BUF), and the pixel matrix are formed on the same substrate (SUB). And the structure which has input the signal which controls a source line drive circuit and a gate line drive circuit from the control circuit (CTL) mounted outside the board | substrate is proposed (refer patent document 1).
Japanese Patent Laid-Open No. 10-068931

  In the area gradation method having a pixel region in which pixels having sub-pixels are arranged in a matrix, a simple configuration without mounting a D / A converter circuit and a large-scale frame memory is possible. However, according to the method described in Patent Document 1, there is a problem that an IC mounting cost is required by externally attaching a control circuit.

  Further, when a signal is input from an external IC via an external connection terminal or an FPC (Flexible Printed Circuit), the state of contact between the external connection terminal and the FPC or the influence of external noise until the signal is input to the drive circuit. As a result, the clock signal is delayed from the start pulse signal, the shift register circuit in the drive circuit malfunctions, and normal display cannot be performed. Therefore, it is necessary to provide a delay circuit at the input portion of the drive circuit. is there.

  In view of the above-described problems, the present invention can reduce the number of external connection terminals, reduce the number of external parts by simply forming a very simple circuit on the same substrate, reduce the cost, and reduce the delay of the clock signal. A display device capable of preventing the problem is provided.

One display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit outputs a signal for driving the source signal line driving circuit and the gate signal line driving circuit according to a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock signal inputted from the outside of the substrate. It was set as the structure which has.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal, an inverted clock signal, and a start pulse signal for driving the gate signal line driving circuit are output.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
A clock signal, an inverted clock signal, and a start pulse signal for driving the gate signal line driving circuit are output from a circuit having a JK flip-flop circuit, a D flip-flop circuit, and a plurality of inverter circuits.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the gate signal line driving circuit are a signal output from the D flip-flop circuit and an inverted signal of the signal output from the D flip-flop circuit, and the gate signal line The start pulse signal for driving the drive circuit is output from the JK flip-flop circuit.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the gate signal line driving circuit include a signal output from the D flip-flop circuit to which the inverted signal of the vertical synchronizing signal and the horizontal synchronizing signal are input, and the D flip-flop. A JK flip-flop to which an inverted signal of a signal output from the circuit and a start pulse signal for driving the gate signal line driving circuit is input to the vertical synchronization signal and the signal output from the D flip-flop circuit It was set as the structure output from a circuit.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the source signal line driving circuit are a signal based on the dot clock signal and an inverted signal of the dot clock signal, and the source signal line driving circuit The start pulse signal for driving is a signal based on the horizontal synchronization signal,
The clock signal and the inverted clock signal for driving the gate signal line driving circuit are a signal output from the D flip-flop circuit and an inverted signal of the signal output from the D flip-flop circuit, and the gate signal line The start pulse signal for driving the drive circuit is output from the JK flip-flop circuit.

Another display device of the present invention includes a pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit,
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the source signal line driving circuit are a signal based on the dot clock signal and an inverted signal of the dot clock signal, and the source signal line driving circuit The start pulse signal for driving is a signal based on the horizontal synchronization signal,
The clock signal and the inverted clock signal for driving the gate signal line driving circuit include a signal output from the D flip-flop circuit to which the inverted signal of the vertical synchronizing signal and the horizontal synchronizing signal are input, and the D flip-flop. A JK flip-flop to which an inverted signal of a signal output from the circuit and a start pulse signal for driving the gate signal line driving circuit is input to the vertical synchronization signal and the signal output from the D flip-flop circuit It was set as the structure output from a circuit.

  In the present invention, the start pulse signal for driving the source signal line driving circuit may be a signal from which the horizontal synchronizing signal is output via a JK flip-flop.

  In the present invention, the control circuit is integrally formed on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, thereby reducing the number of external connection terminals, reducing the mounting area of external components, and reducing the cost. Can be

  In the configuration of the first control circuit, it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

Note that in this specification, connection between elements indicates that they are electrically connected. For this reason, the elements having a connection relationship may be connected via a semiconductor element, a switching element, or the like.

In this specification, the source electrode and the drain electrode of a transistor are names used to distinguish electrodes other than the gate electrode for the sake of convenience in terms of the structure of the transistor. In the present invention, in the case of a structure that is not limited to the polarity of the transistor, the names of the source electrode and the drain electrode change in consideration of the polarity. Therefore, the source electrode or the drain electrode may be described as one of the one electrode and the other electrode.

(Embodiment 1)
In this embodiment, a basic configuration of a display device according to the present invention will be described. FIG. 1 is a schematic view of a display device.

  In FIG. 1, a source line driver circuit 101, a gate line driver circuit 102, a pixel region 106, and a control circuit 107 are formed on a substrate. In the pixel region 106, a plurality of pixels 105 are arranged in a matrix, and each pixel 105 includes a plurality of subpixels 108. The subpixels 108 are controlled by a source signal line 103 and a gate signal line 104. The In FIG. 1, two sub-pixels are used, but the present invention is not limited to this. It should be noted that three or more sub-pixels may be provided in one pixel.

  Note that in this specification, a pixel includes color elements constituting one image, and includes a plurality of subpixels each including a light emitting element and an element that drives the light emitting element (for example, a circuit including a thin film transistor). Shall be included. In this specification, a picture element is assumed to include a pixel constituting a color element for displaying one minimum image. Therefore, in the case of a full-color display device composed of R (red), G (green), and B (blue) color elements, a picture element is composed of pixels including R color elements, G color elements, and B color elements. It is assumed that In addition, each sub-pixel may have a different area size or shape, or may be the same.

  The source line driver circuit 101 sequentially outputs sampling pulses in a shift register circuit (sometimes abbreviated as SR) and a NAND circuit in response to input of a clock signal (SCK), a clock inversion signal (SCKB), and a start signal (SSP). To do. After that, the level shifter and the buffer are subjected to amplitude conversion or amplification, the video signal (Data) is sampled, and sequentially output to the source signal line. The output after the last stage of the shift register may be used as a pulse width control signal (PWC) of the gate line driver circuit. The source line driver circuit 101 includes a thin film transistor provided over a substrate.

  The gate line driver circuit 102 sequentially outputs row selection pulses in the SR and NAND circuits in response to input of a clock signal (GCK), a clock inversion signal (GCKB), and a start signal (GSP). After the pulse width of the row selection pulse is controlled, amplitude conversion or amplification is performed in a level shifter and a buffer, and gate signal lines in each row are sequentially selected. The gate line driver circuit 102 includes a thin film transistor provided over a substrate.

  The control circuit 107 receives a source line drive circuit start signal (SSP) and a source line drive circuit clock signal (SCK) in response to the input of a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a dot clock signal (DCK), which are video signals. The source line driver circuit clock inversion signal (SCKB), the gate line driver circuit start pulse signal (GSP), the gate line driver circuit clock signal (GCK), and the gate line driver circuit clock inversion signal (GCKB) are output. . The signal output unit of the control circuit 107 is arranged in the vicinity of the input ends of the source signal line driver circuit and the gate signal line driver circuit according to the type of signal, and the signal routing wiring is shortened.

FIG. 2 shows a first configuration of the control circuit. The control circuit 208 includes a D flip-flop circuit (hereinafter referred to as DFF) that is a flip-flop circuit, two J flip-flop circuits (hereinafter referred to as JKFF), a plurality of inverters, a plurality of buffers, and two NANDs. As a specific configuration of the J flip-flop circuit, the circuit shown in FIG. 3 may be employed. The specific configuration of the D flip-flop circuit may be the circuit shown in FIG.

  In FIG. 2, the HSYNC signal line is electrically connected to the CK terminal of the DFF 201. The QB terminal of the DFF 201 is electrically connected to the D terminal of the DFF 201. A VSYNC signal line is electrically connected to the PRESET terminal of the DFF 201 via an inverter 205. The Q terminal of the DFF is electrically connected to the GCK signal line of the gate line driving circuit 210 through the buffer 204. The Q terminal of the DFF 201 is electrically connected to the GCKB signal line of the gate line driving circuit 210 via the inverter 205 and the buffer 204.

  In FIG. 2, the GCK signal line is electrically connected to the CK terminal of the first JKFF 202. A VSYNC signal line is electrically connected to the first input terminal of the first NAND 206. A GCK signal line is electrically connected to the second input terminal of the first NAND 206. The output terminal of the first NAND 206 is electrically connected to the PRESET terminal of the first JKFF 202.

  In FIG. 2, the J terminal, the K terminal, and the Q terminal of the first JKFF 202 are electrically connected. The Q terminal of the first JKFF 202 is electrically connected to the GSP signal line of the gate line driver circuit through the buffer 204. The DCK signal line is electrically connected to the SCK signal line of the source line driver circuit 209 via the buffer 204. The DCK signal line is electrically connected to the SCK signal line of the source line driver circuit 209 via the inverter 205 and the buffer 204.

  In FIG. 2, the HSYNC signal line is electrically connected to the first input terminal of the second NAND 207. The second input terminal of the second NAND 207 is electrically connected to the SCK signal line. The output terminal of the second NAND 207 is electrically connected to the PRESET terminal of the second JKFF 203. The SCK signal line is electrically connected to the CK terminal of the second JKFF 203. The J terminal, K terminal, and Q terminal of the second JKFF 203 are electrically connected. The Q terminal of the second JKFF 203 is electrically connected to the SSP signal line of the source line driver circuit 209 through a buffer. The number of the above buffers is not particularly limited.

  In the control circuit shown in FIG. 2, a vertical synchronization signal VSYNC input from the outside is input to the PRESET terminal of the D flip-flop circuit 201 via the inverter circuit 205. A horizontal synchronization signal HSYNC input from the outside is input to the CK terminal of the D flip-flop circuit. The output terminal of the D flip-flop circuit 201 outputs a gate clock signal GCK input to the gate line driving circuit and an inverted gate clock signal GCKB output via an inverter.

  In the control circuit of FIG. 2, an output from the NAND circuit 206 to which the vertical synchronization signal VSYNC inputted from the outside and the gate clock signal GCK are inputted is inputted to the PRESET terminal of the JK flip-flop circuit 202. The gate clock signal GCK input from the outside is input to the CK terminal of the JK flip-flop circuit 202. The output terminal of the JK flip-flop circuit 202 outputs a gate start pulse signal GSP input to the gate line driving circuit.

  In the control circuit of FIG. 2, a dot clock signal DCK input from the outside is output as a source clock signal SCK to a source signal line driver circuit through a buffer circuit. The dot clock signal DCK input from the outside is output as an inverted source clock signal SCKB input to the source line driver circuit via the inverter circuit.

  In the control circuit of FIG. 2, the output from the NAND circuit 205 to which the horizontal synchronization signal HSYNC inputted from the outside and the dot clock signal DCK inputted from the outside are inputted is inputted to the PRESET terminal of the JK flip-flop circuit 203. The A dot clock signal DCK input from the outside is input to the CK terminal of the JK flip-flop circuit 203. The output terminal of the JK flip-flop circuit 203 outputs a source start pulse signal GSP input to the source line driver circuit.

  Next, FIG. 5 shows the operation of the control circuit.

SSP is output at approximately the same timing as HSYNC, SCK is output at approximately the same timing as DCK, and SCKB is output with logic inverted from SCK. At this time, the waveform is the same as that of the input signal, but SSP is delayed more than SCK.

At substantially the same time as the rise of the VSYNC H level 301, GCK becomes the H level 305 and keeps the H level. With respect to the H level 301 of VSYNC, GCK becomes L level almost simultaneously with the rise of the H level 302 of HSYNC. GCK becomes H level 306 almost simultaneously with the rise of the next HSYNC H level 303.

Assuming that the HSYNC high-level pulse 304 that rises simultaneously with the VSYNC high-level pulse 301 is the first, GCK goes low at the even-numbered (2m) high-level rising, and the odd-numbered (2m + 1) high-level rising. GCK goes to H level with increasing interest. GCKB is output with logic inverted from GCK.

Nearly simultaneously with the rise of the first H level 305 of GCK that rises almost simultaneously with the rise of the H level 301 of VSYNC, the GSP becomes the H level 308 and keeps the H level. With respect to the H level 301 of the VSYNC, the GCK becomes the L level almost simultaneously with the next rising of the H level 302 of the HSYNC, and keeps the L level until the next rising of the H level 307 of the VSYNC. At this time, the rise of the first H level 307 of GSP is delayed from the rise of the first H level 305 of GCK, and the first H level 307 of GSP is delayed from the rise of the second H level 306 of GCK. The falling edge is delayed.

  FIG. 6 shows a simple timing chart of the source line driver circuit 101 in FIG. 1, and the operation will be sequentially described below. In FIG. 6, the clock signals (SCK, SCKB), the start pulse (SSP), the digital video signal (Data) are input signals, and the first to fourth stages and the final stage sampling pulses (SROUT1 to 4) are output signals. , Last) and source signal line output (SLine1, SLine final).

First, the first line period (Period1) will be described. The shift register operates in accordance with the clock signal and the start pulse 501, and sequentially outputs the sampling pulse 503. Each sampling pulse 503 samples a digital video signal, holds data in a latch circuit, and is sequentially output to a source signal line.

Note that in the first line period, all the digital video signals 504 are input at the H level.

Here, the source signal line output is at the H level (period 507).

Next, the second line period (Period2) starts. Similar to the first line period, the sampling pulse 503 is sequentially output in accordance with the clock signal and the start pulse 502, and the digital video signal is sampled.

Note that in the second line period, all the digital video signals 505 are input at the L level.

At this time, the source signal line output is at the L level in all stages (period 508).

The output pulse 509 after the last stage of the shift register may be used as a PWC signal in the gate line driver circuit.

  FIG. 7 shows a timing chart of the gate line driver circuit 102 and the source line driver circuit 101, and their operations will be sequentially described below. In FIG. 7, clock signals (GCK, GCKB) and start pulses (GSP) are input signals to the gate line driving circuit, and first to fourth gate line output signals (GLlines 1 to 4) are output signals. Show.

The shift register operates in accordance with the clock signal and the start pulse, and the pulse width is adjusted using PWC, and then sequentially output to the gate signal line.

A row in which the source signal line output (SLine1, SLine final) is input to the sub-pixel is selected by the gate signal line output.

In the configuration of this embodiment, the rising edge and the falling edge of GSP are generated directly from the GCK signal line used in the shift register of the gate line driving circuit, so that GCK is generated from GSP. There is no delay.

In this embodiment, the rising edge and the falling edge of SSP are generated using the rising edge of SCK directly from the SCK signal line used in the shift register of the source line driver circuit, so that SCK is delayed from SSP. Never do.

Since the DFF used in the configuration of this embodiment operates as a T flip-flop (TFF) by connecting the D terminal and the QB terminal, it may be replaced with TFF.

In this embodiment, in order to reduce the number of external connection terminals, an output from the last stage of the shift register of the source line driver circuit may be used as a pulse width control signal (PWC) of the gate line driver circuit.

  As described above, this embodiment is a control circuit formed on a substrate, and a clock signal and an inverted clock signal for driving a source signal line driving circuit are converted into a signal based on a dot clock signal and a dot clock signal. Can be output as a signal generated internally as a signal based on the inverted signal. A start pulse signal for driving the source signal line driving circuit can be output as a signal generated internally as a signal based on the horizontal synchronizing signal. Further, the clock signal and the inverted clock signal for driving the gate signal line driving circuit are output as internally generated signals as signals output from the D flip-flop circuit to which the inverted signal of the vertical synchronizing signal and the horizontal synchronizing signal are input. be able to. The start pulse signal for driving the gate signal line driving circuit is a signal generated internally as a signal output from the JK flip-flop circuit to which the vertical synchronization signal and the signal output from the D flip-flop circuit are input. Can be output. The various signals output to the source signal line driving circuit and the gate signal line driving circuit in the control circuit described above are LCDs, ELs, etc., as long as the display device uses a digital video signal input and digital output type driver. In various display devices such as a display, the number of external connection terminals can be reduced.

Note that this embodiment mode can be implemented freely combining with any description in the embodiments or embodiment modes in this specification.

(Embodiment 2)
In the present embodiment, a configuration different from that of the first embodiment will be described. FIG. 8 shows the configuration of a control circuit that has fewer elements than the first configuration of the control circuit and can save the mounting area.

  The flip-flop circuit includes DFF and JKFF, a plurality of inverters 603, and a plurality of buffers 604, and the HSYNC signal line is electrically connected to the CK terminal of the DFF 601. The QB terminal of the DFF 601 is electrically connected to the D terminal. The VRESET signal line is electrically connected to the PRESET terminal of the DFF 601 via an inverter. The Q terminal of the DFF 601 is electrically connected to the GCK signal line of the gate line driver circuit through the buffer 604. The Q terminal of the DFF 601 is electrically connected to the GCKB signal line via the inverter 603 and the buffer 604. The GCK signal line is electrically connected to the CK terminal of JKFF602. The VSYNC signal line is electrically connected to the PRESET terminal of JKFF602. The J terminal, the K terminal, and the Q terminal of the JKFF 602 are electrically connected. The Q terminal of the JKFF 602 is electrically connected to the GSP signal line of the gate line driving circuit 607 through a buffer. The HSYNC signal line is electrically connected to the SCK signal line of the source line driver circuit 606 through the buffer 604. The HSYNC signal line is electrically connected to the SCKB signal line of the source line driver circuit 606 via the inverter 603 and the buffer 604, and the HSYNC signal line is connected to the SSP signal line of the source line driver circuit 606 via the buffer 604. Yes. The number of the above buffers is not particularly limited.

  In the control circuit shown in FIG. 8, the vertical synchronization signal VSYNC input from the outside is input to the PRESET terminal of the D flip-flop circuit 601 through the inverter circuit 603. A horizontal synchronization signal HSYNC input from the outside is input to the CK terminal of the D flip-flop circuit. The output terminal of the D flip-flop circuit 601 outputs a gate clock signal GCK input to the gate line driver circuit and an inverted gate clock signal GCKB output via an inverter.

In the control circuit of FIG. 8, the vertical synchronization signal VSYNC input from the outside is input to the PRESET terminal of the JK flip-flop circuit 202 via the inverter circuit 603. The gate clock signal GCK is input to the CK terminal of the JK flip-flop circuit 602. The output terminal of the JK flip-flop circuit 02 outputs a gate start pulse signal GSP input to the gate line driving circuit.

  In the control circuit of FIG. 8, the dot clock signal DCK input from the outside is output as a source clock signal SCK to the source signal line driver circuit via the buffer circuit. The dot clock signal DCK input from the outside is output as an inverted source clock signal SCKB input to the source line driver circuit via the inverter circuit.

  In the control circuit of FIG. 8, a dot clock signal DCK input from the outside is output as a source start pulse signal SSP to the source signal line driver circuit via the buffer circuit.

As in the first embodiment, the operation of the control circuit is shown using FIG.

SSP is output at approximately the same timing as HSYNC, SCK is output at approximately the same timing as DCK, and SCKB is output with logic inverted from SCK. The order of SSP and SCK timing at this time is unknown.
At substantially the same time as the rise of the VSYNC H level 301, GCK becomes the H level 305 and keeps the H level. With respect to the H level 301 of VSYNC, GCK becomes L level almost simultaneously with the rise of the H level 302 of HSYNC. GCK becomes H level 306 almost simultaneously with the rise of the next HSYNC H level 303.
Assuming that the HSYNC H level pulse 304 that rises simultaneously with the VSYNC H level pulse 301 is the first, GCK becomes L level at the even (2m) H level rise, and the odd (2m + 1) H level rise. GCK goes to H level with increasing interest. GCKB is output with logic inverted from GCK.

At almost the same time as the rise of the VSYNC H level 301, the GSP becomes the H level 308 and keeps the H level. With respect to the H level 301 of the VSYNC, the GCK becomes the L level almost simultaneously with the next rising of the H level 302 of the HSYNC and keeps the L level until the next rising of the H level 307 of the VSYNC. At this time, the fall timing of the first H level 307 of GSP is delayed rather than the rise of the second H level 306 of GCK.

In the second control circuit configuration, only the fall timing of GSP is delayed from the rise timing of GCK.

In the configuration of the present embodiment, the rising edge of GSP is generated using the rising edge of VSYNC, and the falling edge of GSP is generated using the rising edge of GCK.

In the configuration of the present embodiment, the fall timing of GSP is delayed from the rise timing of GCK.

The DFF used in the configuration of this embodiment operates as a TFF by connecting the D terminal and the QB terminal, and may be replaced with a TFF.

  Note that in this embodiment, the control circuit is integrally formed over the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, so that the number of external connection terminals is reduced and the mounting area of external components is reduced. Reduction and cost reduction. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

Note that this embodiment mode can be implemented freely combining with any description in the embodiments or embodiment modes in this specification.

  In the following, an example of manufacturing a thin film transistor over a substrate having an insulating surface in the display device of the present invention will be briefly described with reference to FIGS. The active matrix display device having the configuration shown in FIGS. 9 to 11 can realize a liquid crystal display device or a display device using an EL (Electro Luminescence) element.

  First, as shown in FIG. 9A, a silicon oxide film, silicon nitride is formed on a glass substrate 401 such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A blocking layer 402 made of an insulating film such as a film or a silicon oxynitride film is formed. For example, a silicon oxynitride film formed from SiH 4, NH 3, and N 2 O by plasma CVD is formed to have a thickness of 10 to 200 nm (preferably 50 to 100 nm). The layers are stacked to a thickness of ˜200 nm (preferably 100 to 150 nm). Although the blocking layer 402 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked.

  The semiconductor layers 403 to 406 divided into islands are formed by converting a semiconductor film having an amorphous structure into a semiconductor film having a crystal structure by a heat treatment using a laser annealing method or a furnace annealing furnace (hereinafter referred to as a crystalline semiconductor film). Form with. The island-shaped semiconductor layers 403 to 406 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  In order to manufacture a crystalline semiconductor film by a laser annealing method, a pulse oscillation type or continuous light emission type excimer laser, YAG laser, or YVO4 laser is used. Laser light output from the laser oscillator is collected in a linear form by an optical system and irradiated onto the semiconductor film. The conditions for annealing are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm 2 (typically 200 to 300 mJ / cm 2). . In the case of using a YAG laser, the second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm 2 (typically 350 to 500 mJ / cm 2). Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.

  Next, a gate insulating film 407 is formed to cover the island-shaped semiconductor layers 403 to 406. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film 407 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

  Then, a first conductive film 408 a and a second conductive film 408 b for forming a gate electrode are formed over the gate insulating film 407. In this embodiment, the first conductive film 408a is formed with tantalum nitride or titanium to a thickness of 50 to 100 nm, and the second conductive film 408b is formed with tungsten to a thickness of 100 to 300 nm. These materials are stable even in heat treatment at 400 to 600 ° C. in a nitrogen atmosphere, and the resistivity does not increase remarkably.

  Next, as shown in FIG. 9B, a resist mask 409 is formed, and a first etching process for forming a gate electrode is performed. There is no limitation on the etching method, but an ICP (Inductively Coupled Plasma) etching method is preferably used. CF4 and Cl2 are mixed in an etching gas, and 500 W of RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 0.5 to 2 Pa, preferably 1 Pa, to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF4 and Cl2 are mixed, etching can be performed at the same rate even in the case of a tungsten film, a tantalum nitride film, and a titanium film.

  Under the above etching conditions, the end portion can be tapered by the shape of the resist mask and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is set to 25 to 45 degrees. In order to etch without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to tungsten is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 410 to 415 (the first conductive films 410a to 415a and the second conductive films 410b to 415b) formed of the first conductive film and the second conductive film by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layer is etched and thinned by about 20 to 50 nm.

  Then, as shown in FIG. 9C, a first doping process is performed to dope n-type impurities (donors). Doping is performed by ion doping or ion implantation. The ion doping method is performed with a dose amount of 1 × 10 13 to 5 × 10 14 / cm 2. As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the acceleration voltage is controlled (for example, 20 to 60 keV), and the first shape conductive layer is used as a mask. Thus, first impurity regions 417 to 420 are formed. For example, the n-type impurity concentration in the first impurity regions 417 to 420 is formed in the range of 1 × 10 20 to 1 × 102 1 / cm 3.

  In the second etching process shown in FIG. 10A, similarly, using an ICP etching apparatus, CF 4, Cl 2, and O 2 are mixed in an etching gas, and RF power (500 W) is applied to a coil-type electrode at a pressure of 1 Pa. .56 MHz) to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the tungsten film is anisotropically etched to leave the tantalum nitride film or titanium film as the first conductive layer. Thus, second shape conductive layers 421 to 426 (first conductive films 421a to 426a and second conductive films 421b to 426b) are formed. The region of the gate insulating film that is not covered with the second shape conductive layers 421 to 426 is further etched by about 20 to 50 nm to be thinned.

  Next, a second doping process is performed. The n-type impurity (donor) is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is 1 × 10 13 / cm 2, and the second impurity region 427 is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 9C. ˜430. In this doping, the second shape conductive layers 423b to 426b are used as masks against the impurity element, and doping is performed so that the impurity element is added to the lower region of the second shape conductive layers 423a to 426a. In this impurity region, the second shape conductive layers 423a to 426a remain with substantially the same film thickness, so that the difference in concentration distribution in the direction along the second shape conductive layer is small, and 1 × 10 17. An n-type impurity (donor) is included at a concentration of ˜1 × 10 19 / cm 3.

  Then, as shown in FIG. 10B, a third etching process is performed, and an etching process for the gate insulating film is performed. As a result, the second shape conductive layers 421a to 426a are also etched, and the end portions recede and become smaller, so that the third shape conductive layers 431 to 436 (the first conductive films 431a to 436a and the second conductive layers are reduced). Films 431b-436b) are formed. Reference numeral 437 denotes a remaining gate insulating film, which may be further etched to expose the surface of the semiconductor layer.

  For the p-channel TFT, as shown in FIG. 10C, resist masks 438 and 439 are formed, and an island-shaped semiconductor layer for forming the p-channel TFT is doped with a p-type impurity (acceptor). To do. The p-type impurity (acceptor) is selected from elements belonging to Group 13, and typically boron (B) is used. The impurity concentration of the third impurity regions 440a to 440c is set to 2 × 1020 to 2 × 1021 / cm 3. Although phosphorus is added to the third impurity region, boron is added at a concentration higher than that to reverse the conductivity type.

  Through the above steps, impurity regions are formed in the semiconductor layer. In FIG. 10, the third shape conductive layers 433 to 435 serve as gate electrodes, and the third shape conductive layer 436 serves as a capacitor wiring. The third shape conductive layers 431 and 432 form wirings such as source lines.

  Next, in FIG. 11A, first, a first insulating film 441 made of a silicon nitride film (SiN: H) or a silicon oxynitride film (SiNxOy: H) is formed by a plasma CVD method. Then, a step of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. Activation is preferably performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can also be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 550 ° C. for 4 hours. Heat treatment is performed.

  Thereafter, a second insulating film 442 made of a silicon nitride film (SiN: H) or a silicon oxynitride film (SiNxOy: H) is formed over the first insulating film 441. And heat processing is performed at 350-500 degreeC. The semiconductor film is hydrogenated with hydrogen released from the second insulating film 442.

  Further, as shown in FIG. 11B, a third insulating film 443 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.

  Next, contact holes are formed in the third insulating film 443, the second insulating film 442, and the first insulating film 441, and aluminum (Al), titanium (Ti), tantalum (Ta), or the like is used. Connection electrodes 451 and source or drain wirings 444 to 447 are formed. In the pixel portion, a first pixel electrode 450, a gate wiring 449, and a connection electrode 448 are formed.

  Thus, a p-channel TFT 453 and an n-channel TFT 454 are formed on the same substrate. FIG. 11B shows only a cross-sectional view of a p-channel TFT 453 and an n-channel TFT 454. By using these TFTs, a thin film transistor included in a display device of the present invention can be formed over the same substrate. it can.

  The structure of the thin film transistor described in this embodiment is merely an embodiment, and is not necessarily limited to the manufacturing process and structure illustrated in FIGS. A thin film transistor included in the display device of the present invention can be formed over the same substrate by a known thin film transistor manufacturing method.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit formed of a thin film transistor on the substrate in order to delay the start pulse signal from the clock signal.

  In this embodiment, a process for manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 12, interlayer films 461 and 462 are formed on the substrate in the state of FIG. 11B, a second pixel electrode 463 is formed thereon, and an alignment film 551 is formed thereon. In this embodiment, a polyimide film is used as the alignment film. A transparent conductive film 553 and an alignment film 554 are formed over the counter substrate 552. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.

  Next, after forming an alignment film, a rubbing process is performed to adjust the liquid crystal molecules so that they are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion, the drive circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process.

  Thereafter, liquid crystal 555 is injected between both substrates and completely sealed with a sealing material (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 5 is completed.

  Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. The active matrix substrate includes a pixel portion 702, a gate side driver circuit 703, and a source side driver circuit 704 that are formed over a glass substrate 701. A pixel TFT 705 in the pixel portion is an n-channel TFT and is connected to the pixel electrode 706 and the storage capacitor 707.

  Further, the control circuit 713 of the present invention provided in the periphery is connected to the gate side driving circuit 703 and the source side driving circuit 704 through the FPC. The gate side driver circuit 703 and the source side driver circuit 704 are connected to the pixel portion 702 through a gate wiring 708 and a source wiring 709, respectively. The external input / output terminal 711 to which the FPC 710 is connected is provided with an input / output wiring (connection wiring) 712 for transmitting a signal to the control circuit 713. Reference numeral 614 denotes a counter substrate.

  The configuration of the active matrix liquid crystal display device described in this embodiment is merely an embodiment, and is not necessarily limited to the structure shown in FIGS. The display device of the present invention may be obtained by a known method for manufacturing an active matrix liquid crystal display device.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

  In this embodiment, an equivalent circuit of a pixel having a sub-pixel formed of a thin film transistor and its operation will be described. Here, a structure in which a pixel includes a light-emitting element typified by an EL element is described.

  FIG. 14 shows a light emitting element 2001, a signal line 2002 to which a video signal is input, a switching transistor 2003 for controlling input of the video signal to a pixel, and a driving transistor for controlling light emission or non-light emission of the light emitting element 2001. An equivalent circuit of a subpixel including a transistor 2004 and a capacitor 2005 for holding a potential of a video signal is shown. For the characteristics of each transistor, an enhancement type or a depletion type transistor can be used.

  In this embodiment mode, the switching transistor 2003 is an n-channel transistor, and the driving transistor 2004 is a p-channel transistor.

  The capacitor 2005 is not necessarily provided when the gate capacitance of the driving transistor 2004 is large and the leakage current from each transistor is within an allowable range.

  A connection relationship of such a pixel configuration is shown. A gate electrode of the switching transistor 2003 is connected to the scanning line 2006, a first electrode is connected to the signal line 2002, and a second electrode is connected to the gate electrode of the driving transistor 2004. A first electrode of the driving transistor 2004 is connected to the power supply line 2007, and a capacitor element 2005 is provided between the gate and the source of the driving transistor 2004. The capacitor element 2005 is connected so as to hold the potential difference between the gate and the source of the driving transistor 2004, that is, hold the potential of the video signal when the switching transistor 2003 is in a non-selected state (off state). Therefore, one electrode of the capacitor is connected to the gate electrode of the driving transistor 2004, and the other electrode is connected to the power supply line 2007.

  There are a large number of such sub-pixels, and area gradation display for controlling the light-emitting area from each light-emitting element is performed.

  Next, specific operation of each transistor in the sub-pixel will be described with reference to a timing chart shown in FIG. Note that FIG. 21A shows a timing chart when the vertical axis indicates scanning lines and the horizontal axis indicates time, and FIG. 15B shows timing charts for the j-th scanning line Gj.

  The display device normally has a frame frequency of about 60 Hz. In other words, the screen drawing is performed about 60 times per second, and the period in which the screen is drawn once is called one frame period (unit frame period). As shown in FIG. 15A, the sub-pixel performs a writing period Ta and a light emitting period Ts in one frame period.

  When the scanning line 2006 is sequentially selected in the writing period Ta, the switching transistor 2003 connected to the scanning line 2006 is turned on. When the switching transistor 2003 is turned on, electric charge is accumulated in the capacitor 2005 by a video signal input from the signal line. When this charge is equal to or higher than the threshold voltage Vth of the driving transistor 2004, the driving transistor 2004 is turned on and the light emitting element 2001 emits light.

  The light emitting element 2001 emits light with luminance corresponding to the supplied current, and the light emission period Ts.

  In the light emission period Ts, the switching transistor 2003 is turned off by controlling the potential of the scanning line 2006, and the potential of the video signal written in the writing period Ta is held by the capacitor 2005. As a result, the light emitting element 2001 continues to emit light.

  In the writing period Ta, when the driving transistor 2004 is turned off by a video signal input from the signal line, the capacitor 2005 does not hold a potential in the light emitting period Ts, and thus the light emitting element does not emit light. ing.

  That is, when the driving transistor 2004 is turned on in the writing period Ta, the video signal potential is held in the capacitor element 2005 in the light emission period Ts, and thus light emission continues. On the other hand, in the case where the driving transistor 2004 is turned off in the writing period Ta, the potential of the video signal is not held by the capacitor 2005 in the light emission period Ts and is not light emitting.

  In this manner, gradation display is performed by making the light emitting element emit light or not emit light. In particular, area gradation display is performed by making the light emitting element emit light or not emit light in a state where the light emitting area from the light emitting element in each sub-pixel is weighted.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

  In this embodiment, a top view corresponding to the pixel circuit shown in FIG. 14 will be described.

  FIG. 16A showing a top view corresponding to FIG. 14 shows a signal line 2401, a power supply line 2409, a scanning line 2408, a switching transistor 2403, a driving transistor 2404, and a light emitting element of the first subpixel. The first electrode 2407a, the light emitting element 2410a of the first subpixel, the first electrode 2407b of the light emitting element of the second subpixel, the light emitting element 2410b of the first subpixel, the capacitor elements 2406a and 2406b, and the ground line GND are shown. . FIG. 16B shows a circuit diagram corresponding to the strip view shown in FIG. Note that in this embodiment, the capacitor element has a plurality of capacitor elements 2406a and 2406b, but either one may be provided or may not be provided.

  In FIG. 16, when each transistor has a top gate structure, a film is formed in the order of a substrate, a semiconductor layer, a gate insulating film, a scanning line, an interlayer insulating film, and a signal line. In the case of the bottom gate structure, the film is formed in the order of the substrate, the scanning line, the gate insulating film, the semiconductor layer, the interlayer insulating film, and the signal line.

  In FIG. 24, a power supply line 2409 is formed in parallel with the signal line 2401. Therefore, the signal line 2408 and the power supply line 2409 are obtained by patterning the same conductive film.

  The switching transistor 2403 has a double gate structure in which two gate electrodes are provided for a semiconductor film, and part of the scanning line 2408 functions as these gate electrodes. The first electrode of the switching transistor 2403 is connected to the signal line 2401 through a contact hole, and the second electrode is connected to the capacitor elements 2406a and 2406b. Further, one electrode of the capacitor 2406b is formed using the same conductive film as the gate electrode of the driving transistor 2404, and a semiconductor film corresponding to the other electrode is connected to the power supply line 2409 through a contact hole.

  A gate electrode of the driving transistor 2404 is connected to a power supply line 2409 having a fixed potential through a contact hole, and a second electrode is connected to a wiring formed using the same conductive film as the signal line. The first electrodes 2407 and 2407b of the light emitting element are formed and connected to each other. The wiring and the anode may be connected via a contact hole.

  Note that although a double gate structure in which two channel formation regions of the switching transistor 2403 and the driving transistor 2404 are formed has been described, a single gate structure in which one channel formation region is formed or three channel formation regions are formed. A triple gate structure may be used. Alternatively, a dual gate type or other structure having two gate electrodes disposed above and below the channel formation region with a gate insulating film interposed therebetween may be used.

  The anode of the light-emitting element is formed of a transparent conductive film typified by ITO (indium tin oxide), and the area ratio thereof is 2407a: 2407b = 1: 2, provided on the anode. An electroluminescent layer and a cathode are formed. Then, based on the video signal input from the signal line 2401, the electroluminescent layer enters a light emitting state or a non-light emitting state. The light emission area is weighted 1: 2, and area gradation display is performed by selection.

  Note that the configuration of the wiring around the pixel of the display device of the present invention is wide-ranging and is not particularly limited to the configuration listed in this specification.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

  In this embodiment mode, an enlarged view of a cross section of a subpixel is shown. Note that in this embodiment, the case where a thin film transistor (TFT) including polycrystalline silicon is used as a transistor is described. Needless to say, in the display device of the present invention, the transistor is not limited to the one formed of polycrystalline silicon, but may be any compound having semiconductor characteristics such as amorphous silicon.

  As shown in FIG. 17A, a p-channel driver transistor 2801 provided over a substrate 2800 having an insulating surface includes a crystallization treatment by laser irradiation or heating, or a catalyst for a metal element such as nickel or titanium. A crystalline semiconductor film which has been crystallized by using the action; A gate electrode and a gate line are provided over the semiconductor film via a gate insulating film, and the semiconductor film under the gate electrode becomes a channel formation region. An impurity element such as boron is added to the semiconductor film in a self-aligning manner using the gate electrode as a mask, so that impurity regions to be a source region and a drain region are formed. A first insulating film is provided so as to cover the gate electrode, and a contact hole is formed in the first insulating film over the impurity region. A wiring is formed in the contact hole and functions as a source wiring and a drain wiring. A first electrode 2811 of the light emitting element is provided so as to be electrically connected to the drain electrode. Then, a second insulating film is provided so as to cover the first electrode 2811, and an opening is formed on the first electrode of the second insulating film. An electroluminescent layer 2812 is provided in the opening, and a second electrode 2813 of the light emitting element is provided so as to cover the electroluminescent layer and the second insulating film.

  The electroluminescent layer 2812 is stacked in the order of HIL (hole injection layer), HTL (hole transport layer), EML (light emitting layer), ETL (electron transport layer), and EIL (electron injection layer) in this order from the first electrode 2811 side. Has been. Typically, CuPc is used as HIL, α-NPD is used as HTL, BCP is used as ETL, and BCP: Li is used as EIL.

  In the case of full-color display as the electroluminescent layer 2812, materials that emit red (R), green (G), and blue (B) light are selected by an evaporation method using an evaporation mask, an inkjet method, or the like. It may be formed automatically. Specifically, CuPc or PEDOT is used as HIL, α-NPD is used as HTL, BCP or Alq3 is used as ETL, and BCP: Li or CaF2 is used as EIL. In addition, for example, EML may be Alq3 doped with a dopant corresponding to each emission color of R, G, and B (DCM for R, DMQD for G, etc.). Note that the present invention is not limited to the stacked structure of the electroluminescent layer.

  More specifically, in the case of forming the electroluminescent layer 2812 that emits red light, for example, after forming CuPc to 30 nm and α-NPD to 60 nm, the same mask is used to form a red light emitting layer 2812 that emits red light. Alq3 to which DCM2 and rubrene are added is 40 nm as the light emitting layer, BCP is 40 nm as the electron transport layer, and BCP to which Li is added is 1 nm as the electron injection layer. In the case of forming the electroluminescent layer 2812 that emits green light, for example, CuPc was 30 nm and α-NPD was 60 nm, and then coumarin 545T was added as a green light-emitting layer using the same vapor deposition mask. Alq3 is 40 nm, BCP is 40 nm as an electron transport layer, and BCP to which Li is added is 1 nm as an electron injection layer. In the case of forming the electroluminescent layer 2812 that emits blue light, for example, after CuPc is 30 nm and α-NPD is 60 nm, bis [2- (2-hydroxyphenyl) is used as the light-emitting layer using the same mask. Benzoxazolate] zinc: Zn (PBO) 2 is 10 nm, BCP is 40 nm as an electron transport layer, and BCP to which Li is added is 1 nm as an electron injection layer.

  As described above, among the electroluminescent layers of the respective colors, common CuPc and α-NPD can be formed on the entire surface of the pixel portion. The mask can also be shared by each color. For example, after forming a red electroluminescent layer, the mask can be shifted to form a green electroluminescent layer, and the mask can be shifted again to form a blue electroluminescent layer. . What is necessary is just to set suitably the order of the electroluminescent layer of each color to form.

  When an electroluminescent layer that emits white light is formed, full color display can be performed by separately providing a color filter or a color filter and a color conversion layer. The color filter and the color conversion layer may be attached after being provided over the second substrate.

  The material is selected in consideration of the work function with the first electrode. For example, the case where the first electrode is an anode and the second electrode is a cathode will be described.

  As the first electrode, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a high work function (work function 4.0 eV). Specific examples include ITO (indium tin oxide), indium oxide mixed with 2-20% zinc oxide (ZnO), IZO (indium zinc oxide), gold (Au), platinum (Pt), nickel. (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), or metal nitride (TiN), etc. Can be used.

  On the other hand, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a low work function (work function of 3.8 eV or less) as the second electrode. Specific materials include elements belonging to Group 1 or Group 2 of the element periodic rule, that is, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg: In addition to Ag, Al: Li) and compounds (LiF, CsF, CaF2), transition metals including rare earth metals can be used. However, since the second electrode has a light-transmitting property, the metal or an alloy including these metals is formed very thin and is formed by stacking with a metal (including an alloy) such as ITO.

These first electrode and second electrode can be formed by vapor deposition, sputtering, or the like.

  However, depending on the pixel configuration, both the first electrode and the second electrode can be an anode or a cathode. For example, the polarity of a driving transistor can be an n-channel type, the first electrode can be a cathode, and the second electrode and an anode.

  After that, a passivation film 2814 containing nitrogen is formed by a sputtering method or a CVD method to prevent moisture and oxygen from entering. In the space formed at this time, nitrogen may be sealed and a desiccant may be further disposed. Further, a resin having translucency and high water absorption may be filled. Furthermore, the first electrode, the second electrode, and other electrodes can cover the side surface of the display means to prevent oxygen and moisture from entering. After that, the sealing substrate 2815 is attached.

  In order to increase the contrast, a polarizing plate or a circular polarizing plate may be provided. For example, a polarizing plate or a circularly polarizing plate can be provided on one surface or both surfaces of the display surface.

  In the display device including the sub-pixel formed as described above, the first electrode 2811 and the second electrode 2813 have a light-transmitting property. Therefore, light is emitted from the light emitting element in the direction of the double arrow with a luminance corresponding to the video signal input from the signal line.

  As shown in FIG. 17A, an area gradation display that weights the light emitting area of a sub-pixel having a light emitting element, that is, the area of a transparent conductive film, in which light is emitted in both directions, is designed. The area of the transparent conductive film can be increased. As a result, the transmittance in a non-light emitting state can be increased, which is preferable.

  In FIG. 17B, the light emission direction is only on the sealing substrate 2815 side. Therefore, the first electrode 2811 is a light-transmitting conductive film, preferably a highly reflective conductive film, and the second electrode 2813 is a light-transmitting conductive film. The description of other structures is omitted because it is similar to that of FIG.

  In FIG. 17C, the light emission direction is only on the substrate 2800 side. Therefore, the first electrode 2811 is a light-transmitting conductive film, and the second electrode 2813 is a light-transmitting conductive film, preferably a highly reflective conductive film. The description of other structures is omitted because it is similar to that of FIG.

  As shown in FIGS. 17B and 17C, light can be effectively used by using a highly reflective conductive film for the electrode of the light-emitting element provided on the side not corresponding to the light emission direction. .

  In this embodiment, in order to obtain a light-transmitting conductive film, a light-transmitting conductive film is formed thin so as to have light-transmitting properties, and a light-transmitting conductive film is formed thereover. You may laminate.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

In this embodiment, a structural example of an electronic device having the display device of the present invention in a display portion will be described.

  Mobile devices such as television devices (TVs, television receivers), digital cameras, digital video cameras, mobile phone devices (mobile phones), PDAs, and the like as electronic devices using display devices having pixel regions including light-emitting elements Examples thereof include a terminal, a portable game machine, a monitor, a computer, an audio playback device such as a car audio, and an image playback device equipped with a recording medium such as a home game machine. The display device of the present invention can be applied to display portions of these electronic devices. A specific example of the electronic device will be described with reference to FIG.

  A portable information terminal using the display device of the present invention illustrated in FIG. 18A includes a main body 9201, a display portion 9202, and the like, and according to the present invention, the number of external connection terminals is reduced and the mounting area of external components is reduced. Cost can be reduced. A digital video camera using the display device of the present invention shown in FIG. 18B includes display portions 9701, 9702, etc., and the present invention reduces the number of external connection terminals and reduces the mounting area of external components. Cost can be reduced. A portable terminal using the display device of the present invention illustrated in FIG. 18C includes a main body 9101, a display portion 9102, and the like. According to the present invention, the number of external connection terminals is reduced, and the mounting area of external components is reduced. Cost can be reduced. A portable television device using the display device of the present invention illustrated in FIG. 18D includes a main body 9301, a display portion 9302, and the like, and according to the present invention, the number of external connection terminals is reduced and the mounting area of external components is reduced. Can be reduced and the cost can be reduced. A portable computer using the display device of the present invention illustrated in FIG. 18E includes a main body 9401, a display portion 9402, and the like. The number of external connection terminals is reduced, the mounting area of external components is reduced, and low cost is achieved. Can be made. A television set using the display device of the present invention illustrated in FIG. 18F includes a main body 9501, a display portion 9502, and the like, so that the number of external connection terminals is reduced, the mounting area of external components is reduced, and cost is reduced. Can do.

  Note that this embodiment can be implemented freely combining with any description in the other embodiments and examples in this specification. That is, by integrally forming the control circuit on the same substrate including the source line driver circuit, the gate line driver circuit, and the pixel matrix, the number of external connection terminals can be reduced, the mounting area of external components can be reduced, and the cost can be reduced. Further, the configuration of the first control circuit can provide an advantage that it is not necessary to provide a delay circuit on the TFT substrate in order to delay the start pulse signal from the clock signal.

The figure which shows one Embodiment of this invention. The figure which shows the 1st structure of a control circuit. The circuit diagram of a JK flip-flop circuit. A circuit diagram of a D flip-flop circuit. The figure which shows the timing chart of a control circuit. FIG. 11 is a timing chart of a source line driver circuit. FIG. 6 is a timing chart of a gate line driver circuit and a source line driver circuit. The figure which shows the 2nd structure of a control circuit. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. FIG. 6 illustrates a display device of the present invention. The perspective view in the display apparatus of this invention. FIG. 9 is a diagram illustrating a circuit diagram of a pixel of a display device of the present invention. FIG. 6 illustrates a display device of the present invention. FIG. 6 is a top view of a pixel in a display device of the present invention. FIG. 14 is a cross-sectional view of a pixel of a display device of the present invention. The figure of the electronic device of Example 5 of this invention. The figure explaining the prior art example of this invention.

Explanation of symbols

101 Source line driver circuit 102 Gate line driver circuit 103 Source signal line 104 Gate signal line 105 Pixel 106 Pixel area 107 Timing control circuit 108 Sub pixel 201 DFF
202 1st JKFF
203 2nd JKFF
204 Buffer 205 Inverter 206 First NAND
209 Source line driver circuit 210 Gate line driver circuit 301 H level 302 H level 303 H level 304 Pulse 305 H level 306 H level 307 H level 308 H level 401 Glass substrate 402 Blocking layer 403 Semiconductor layer 404 Semiconductor layer 405 Semiconductor layer 406 Semiconductor Layer 407 gate insulating film 408a first conductive film 408b second conductive film 409 mask 410 conductive layer 410a first conductive film 410b second conductive film 411 conductive layer 411a first conductive film 411b second conductive film 412 Conductive layer 412a first conductive film 412b second conductive film 413 conductive layer 413a first conductive film 413b second conductive film 414 conductive layer 414a first conductive film 414b second conductive film 415 conductive layer 415a first Conductive film 415b second conductive film 416 gate Edge film 417 First impurity region 418 First impurity region 419 First impurity region 420 First impurity region 421 Conductive layer 421a First conductive film 421b Second conductive film 422 Conductive layer 422a First conductive film 422b second conductive film 423 conductive layer 423a first conductive film 423b second conductive film 424 conductive layer 424a first conductive film 424b second conductive film 425 conductive layer 425a first conductive film 425b second conductive Film 426 conductive layer 426a first conductive film 426b second conductive film 427 second impurity region 428 second impurity region 429 second impurity region 430 second impurity region 431 conductive layer 431a first conductive film 431b Second conductive film 432 Conductive layer 432a First conductive film 432b Second conductive film 433 Conductive layer 433a First conductive film 433b Second Conductive film 434 Conductive layer 434a First conductive film 434b Second conductive film 435 Conductive layer 435a First conductive film 435b Second conductive film 436 Conductive layer 436a First conductive film 436b Second conductive film 437 Gate insulation Film 438 Resist mask 439 Resist mask 440a Third impurity region 440b Third impurity region 440c Third impurity region 441 First insulating film 442 Second insulating film 443 Third insulating film 444 Source or drain wiring 445 Source Or drain wiring 446 source or drain wiring 447 source or drain wiring 448 connection electrode 449 gate wiring 450 first pixel electrode 451 peripheral circuit 452 pixel portion 453 p-channel TFT
454 n-channel TFT
455 pixel TFT
456 Storage capacitor 461 Interlayer film 462 Interlayer film 463 Pixel electrode 501 Start pulse 502 Start pulse 503 Sampling pulse 504 Digital video signal 505 Digital video signal 506 Digital video signal 505
507 period 508 period 509 output pulse 601 DFF
602 JKFF
603 Inverter 604 Buffer 605 Timing control circuit 606 Source line drive circuit 607 Gate line drive circuit 551 Alignment film 552 Counter substrate 553 Transparent conductive film 554 Alignment film 555 Liquid crystal 601 Glass substrate 602 Pixel portion 603 Gate side drive circuit 604 Source side drive circuit 605 Pixel TFT
606 Pixel electrode 607 Retention capacitor 608 Gate wiring 609 Source wiring 610 FPC
611 External input / output terminal 612 Input / output wiring 613 Input / output wiring 614 Counter substrate 701 Glass substrate 702 Pixel portion 703 Gate side driving circuit 704 Source side driving circuit 705 Pixel TFT
706 Pixel electrode 707 Retention capacitor 708 Gate wiring 709 Source wiring 710 FPC
711 External input / output terminal 712 Input / output wiring 713 Control circuit 714 Counter substrate 2001 Light emitting element 2002 Signal line 2003 Switching transistor 2004 Driving transistor 2005 Capacitance element 2006 Scan line 2007 Power line 2401 Signal line 2403 Switching transistor 2404 Driving Transistor 2406a capacitor 2406b capacitor 2407a first electrode 2407b first electrode 2408 scanning line 2409 power supply line 2410a light emitting element 2410b light emitting element 2800 substrate 2801 transistor 2811 first electrode 2812 electroluminescent layer 2813 second electrode 2814 passivation film 2815 sealing Stop board 9101 Main body 9102 Display unit 9201 Main unit 9202 Display unit 9301 Main unit 9302 Display unit 9401 Main unit 94 Second display unit 9501 body 9502 display portion 9701 display unit 9702 display unit

Claims (9)

A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit outputs a signal for driving the source signal line driving circuit and the gate signal line driving circuit according to a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock signal inputted from the outside of the substrate. A display device comprising: A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A display device that outputs a clock signal, an inverted clock signal, and a start pulse signal for driving the gate signal line driver circuit. A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
A clock signal, an inverted clock signal, and a start pulse signal for driving the gate signal line driver circuit are output from a circuit having a JK flip-flop circuit, a D flip-flop circuit, and a plurality of inverter circuits. Display device. A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the gate signal line driving circuit are a signal output from the D flip-flop circuit and an inverted signal of the signal output from the D flip-flop circuit, and the gate signal line A display device, wherein a start pulse signal for driving a driving circuit is output from a JK flip-flop circuit. A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the gate signal line driving circuit include a signal output from the D flip-flop circuit to which the inverted signal of the vertical synchronizing signal and the horizontal synchronizing signal are input, and the D flip-flop. A JK flip-flop to which an inverted signal of a signal output from the circuit and a start pulse signal for driving the gate signal line driving circuit is input to the vertical synchronization signal and the signal output from the D flip-flop circuit A display device characterized by being output from a circuit. A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the source signal line driving circuit are a signal based on the dot clock signal and an inverted signal of the dot clock signal, and the source signal line driving circuit The start pulse signal for driving is a signal based on the horizontal synchronization signal,
The clock signal and the inverted clock signal for driving the gate signal line driving circuit are a signal output from the D flip-flop circuit and an inverted signal of the signal output from the D flip-flop circuit, and the gate signal line A display device, wherein a start pulse signal for driving a driving circuit is output from a JK flip-flop circuit. A pixel region in which pixels including sub-pixels are arranged in a matrix, a source signal line driver circuit, a gate signal line driver circuit, and a control circuit;
The sub-pixel, the source signal line driver circuit, the gate signal line driver circuit, and the control circuit have a thin film transistor formed on a substrate,
The control circuit includes a clock signal, an inverted clock signal, and a start pulse signal for driving the source signal line driving circuit based on a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal input from the outside of the substrate, and A clock signal for driving the gate signal line driving circuit, an inverted clock signal, and a start pulse signal;
The clock signal and the inverted clock signal for driving the source signal line driving circuit are a signal based on the dot clock signal and an inverted signal of the dot clock signal, and the source signal line driving circuit The start pulse signal for driving is a signal based on the horizontal synchronization signal,
The clock signal and the inverted clock signal for driving the gate signal line driving circuit include a signal output from the D flip-flop circuit to which the inverted signal of the vertical synchronizing signal and the horizontal synchronizing signal are input, and the D flip-flop. A JK flip-flop to which an inverted signal of a signal output from the circuit and a start pulse signal for driving the gate signal line driving circuit is input to the vertical synchronization signal and the signal output from the D flip-flop circuit A display device characterized by being output from a circuit.   8. The display device according to claim 6, wherein the start pulse signal for driving the source signal line driving circuit is a signal from which the horizontal synchronizing signal is output through a JK flip-flop.   An electronic apparatus comprising the display device according to any one of claims 1 to 8.

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