JP2007109918A - Transistor and its manufacturing method - Google Patents
Transistor and its manufacturing method Download PDFInfo
- Publication number
- JP2007109918A JP2007109918A JP2005299678A JP2005299678A JP2007109918A JP 2007109918 A JP2007109918 A JP 2007109918A JP 2005299678 A JP2005299678 A JP 2005299678A JP 2005299678 A JP2005299678 A JP 2005299678A JP 2007109918 A JP2007109918 A JP 2007109918A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- insulating film
- gate insulating
- transistor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Physical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
本発明は、同一の材料から構成される半導体層とゲート絶縁膜を有するトランジスタおよびその製造方法に関するものである。 The present invention relates to a transistor having a semiconductor layer and a gate insulating film made of the same material, and a method for manufacturing the same.
一般に液晶表示デバイスや有機ＥＬデバイスの駆動用等のトランジスタとして、アモルファスシリコンや多結晶シリコンを用いた薄膜トランジスタが広く使われてきた。
しかしながら、シリコンは可視光領域に光感度を有しているため、光によりキャリアが生成され導電率が上昇し、トランジスタ特性が大きく影響を受ける。
In general, thin film transistors using amorphous silicon or polycrystalline silicon have been widely used as transistors for driving liquid crystal display devices and organic EL devices.
However, since silicon has photosensitivity in the visible light region, carriers are generated by light, the conductivity is increased, and the transistor characteristics are greatly affected.
また、シリコンは２００℃以上の高温で成膜することで優れた特性を発揮するため低温成膜が難しく、耐熱温度が低い汎用のポリマーフィルム上には形成しにくいため、フレキシブルな表示装置の普及を阻んできた。 In addition, since silicon exhibits excellent characteristics when deposited at a high temperature of 200 ° C. or higher, it is difficult to form a film at low temperature, and it is difficult to form it on a general-purpose polymer film having a low heat-resistant temperature. Has been blocked.
そこで、シリコンに代わる半導体材料としてＺｎＯを用いて、電界効果型トランジスタを作製する試みが多くなされている。 Thus, many attempts have been made to produce field effect transistors using ZnO as a semiconductor material instead of silicon.
しかしながら、従来の技術では、ＺｎＯ膜内の酸素欠損や不純物を減らすことは極めて難しく、キャリア濃度を減らすことができないため、ノーマリーオフな電界効果型トランジスタを構成できない等の欠点がある。 However, in the conventional technique, it is extremely difficult to reduce oxygen vacancies and impurities in the ZnO film, and the carrier concentration cannot be reduced. Therefore, there is a disadvantage that a normally-off field effect transistor cannot be configured.
そこで近年、アモルファスＩｎ−Ｇａ−Ｚｎ−Ｏ材料を用いた電界効果型トランジスタが提案されている（非特許文献１参照）。 Therefore, in recent years, a field effect transistor using an amorphous In—Ga—Zn—O material has been proposed (see Non-Patent Document 1).
アモルファスＩｎ−Ｇａ−Ｚｎ−Ｏ材料を用いたアモルファス酸化物半導体を半導体層として用いることで、室温で、ＰＥＴ基板上に移動度１０ｃｍ２／Ｖｓ前後の優れた特性を持つ透明電界効果型トランジスタを作製することができる。
このような透明電界効果型トランジスタではゲート絶縁膜としては、酸化シリコン、窒化シリコン、酸化イットリウム、酸化ハフニウム、窒化ハフニウムシリケート等が用いられてきた。
しかしながら、半導体層、ゲート絶縁膜と種々の元素を含む材料をそれぞれ準備する必要があり、製造コストが大きく増加するという問題点があった（特許文献１参照）。
By using an amorphous oxide semiconductor using an amorphous In—Ga—Zn—O material as a semiconductor layer, a transparent field effect transistor having excellent characteristics of mobility of about 10 cm 2 / Vs on a PET substrate at room temperature can be obtained. Can be produced.
In such a transparent field effect transistor, silicon oxide, silicon nitride, yttrium oxide, hafnium oxide, hafnium nitride silicate, or the like has been used as a gate insulating film.
However, it is necessary to prepare a semiconductor layer, a gate insulating film, and materials containing various elements, respectively, and there is a problem that the manufacturing cost is greatly increased (see Patent Document 1).
本発明の課題は、半導体層およびゲート絶縁膜の形成に用いる材料を同一にすることにより、製造プロセスを簡略化し低コスト化した、界面順位の低い低オフ電流で、良好なオン／オフ特性、移動度、導電率を持つトランジスタを提供するものである。 An object of the present invention is to make a manufacturing process simple and low cost by using the same material used for forming a semiconductor layer and a gate insulating film, with a low off-state current with a low interface state, and a good on / off characteristic. A transistor having mobility and conductivity is provided.
請求項１に記載の発明は、絶縁性基板上に設けられた半導体層と、該半導体層に電気的に接触して配列されたソース電極と、前記半導体層に電気的に接触すると共に前記ソース電極に離隔して配列されたドレイン電極と、前記絶縁性基板を真上から見たときに前記ソース電極と前記ドレイン電極の間に位置する前記半導体層上に設けられたゲート絶縁膜と、該ゲート絶縁膜上に設けられたゲート電極とを備え、該ゲート電極に印加する電圧の有無によって、前記ソース電極と前記ドレイン電極との導通をオン又はオフするトランジスタであって、前記半導体層および前記ゲート絶縁膜がＩｎ、Ｇａ、Ｚｎ、Ｏから構成されることを特徴とするトランジスタである。 The invention according to claim 1 is a semiconductor layer provided on an insulating substrate, a source electrode arranged in electrical contact with the semiconductor layer, an electrical contact with the semiconductor layer, and the source A drain electrode arranged apart from the electrode, a gate insulating film provided on the semiconductor layer located between the source electrode and the drain electrode when the insulating substrate is viewed from directly above, A transistor that turns on or off conduction between the source electrode and the drain electrode depending on the presence or absence of a voltage applied to the gate electrode, the semiconductor layer and the semiconductor layer The transistor is characterized in that the gate insulating film is composed of In, Ga, Zn, and O.
請求項２に記載の発明は、前記半導体層の導電率が１×１０−１０Ｓ／ｃｍ以上１×１０−２Ｓ／ｃｍ以下、前記ゲート絶縁膜の導電率が１×１０−１１Ｓ／ｃｍ以下であることを特徴とする請求項１に記載のトランジスタである。 According to a second aspect of the present invention, the conductivity of the semiconductor layer is 1 × 10 −10 S / cm or more and 1 × 10 −2 S / cm or less, and the conductivity of the gate insulating film is 1 × 10 −11 S / cm. The transistor according to claim 1, wherein the transistor is equal to or less than cm.
請求項３に記載の発明は、絶縁性基板上に、酸化物半導体から構成される半導体層を形成する半導体層形成工程と、前記半導体層に電気的に接触すると共に、相互に離隔したソース電極とドレイン電極とを、前記半導体層上に配列するソース電極及びドレイン電極配列工程と、前記絶縁性基板を真上から見たときに前記ソース電極と前記ドレイン電極の間に位置する前記半導体層上にゲート絶縁膜を形成するゲート絶縁膜形成工程と、前記ゲート絶縁膜上にゲート電極を形成するゲート電極形成工程とを有するトランジスタの製造方法であって、前記半導体層形成工程および前記ゲート絶縁膜形成工程が、Ｉｎ、Ｇａ、Ｚｎ、Ｏからなるスパッタターゲットを不活性ガスまたは酸素の少なくとも一方でスパッタする工程であって、前記半導体層を形成する工程で用いるスパッタガスの酸素流量比が１０％以下であり、前記ゲート絶縁膜を形成する工程で用いるスパッタガスの酸素流量比が２０％以上であることを特徴とするトランジスタの製造方法である。 According to a third aspect of the present invention, there is provided a semiconductor layer forming step of forming a semiconductor layer made of an oxide semiconductor on an insulating substrate, and source electrodes that are in electrical contact with the semiconductor layer and spaced apart from each other A source electrode and a drain electrode arrangement step for arranging the gate electrode and the drain electrode on the semiconductor layer; and on the semiconductor layer positioned between the source electrode and the drain electrode when the insulating substrate is viewed from directly above. A method for manufacturing a transistor, comprising: a gate insulating film forming step of forming a gate insulating film on the gate electrode; and a gate electrode forming step of forming a gate electrode on the gate insulating film, wherein the semiconductor layer forming step and the gate insulating film The forming step is a step of sputtering a sputtering target made of In, Ga, Zn, and O with at least one of an inert gas and oxygen, and the semiconductor A method for manufacturing a transistor, wherein an oxygen flow rate ratio of a sputtering gas used in the step of forming the gate electrode is 10% or less and an oxygen flow rate ratio of the sputtering gas used in the step of forming the gate insulating film is 20% or more It is.
半導体層を形成する工程において、Ｉｎ、Ｇａ、Ｚｎ、Ｏからなるスパッタターゲットをスパッタして作製されるスパッタ膜の物性が、スパッタガスの酸素流量に極めて大きく左右されることを見い出した。 In the process of forming the semiconductor layer, it has been found that the physical properties of a sputtered film produced by sputtering a sputter target made of In, Ga, Zn, O are greatly influenced by the oxygen flow rate of the sputtering gas.
例えば、酸素流量を０％（アルゴン流量１００％）でアモルファス酸化物を作製すると１（Ｓ／ｃｍ）を超える導電率が得られるが、酸素流量を５０％とすると導電率が１×１０−１３（Ｓ／ｃｍ）以下の完全な絶縁体が得られる。
つまり、Ｉｎ、Ｇａ、Ｚｎ、Ｏからなるスパッタターゲットを用いスパッタガスの酸素流量を制御してスパッタすることで、従来困難であったゲート絶縁膜と半導体層を同一のスパッタターゲットから作製することが可能となり、同一真空槽内で半導体層とゲート絶縁膜を形成することができ、半導体層およびゲート絶縁膜の形成に際しての真空引きが１回で済み、低コストでトランジスタを製造することができる。
For example, when an amorphous oxide is produced with an oxygen flow rate of 0% (argon flow rate 100%), a conductivity exceeding 1 (S / cm) can be obtained, but when the oxygen flow rate is 50%, the conductivity is 1 × 10 −13. A complete insulator of (S / cm) or less is obtained.
That is, by using a sputtering target composed of In, Ga, Zn, and O and performing sputtering while controlling the oxygen flow rate of the sputtering gas, the gate insulating film and the semiconductor layer, which have been difficult in the past, can be manufactured from the same sputtering target. Therefore, the semiconductor layer and the gate insulating film can be formed in the same vacuum chamber, and the semiconductor layer and the gate insulating film can be evacuated once, so that a transistor can be manufactured at low cost.
本発明のトランジスタは、同一のスパッタターゲットからゲート絶縁膜および半導体層を作製し、製造プロセスを簡略化し低コスト化することができ、またゲート絶縁膜および半導体層が同一材料から形成されているため、界面準位の低い良好な電気的特性をもつトランジスタを提供することが可能となった。 In the transistor of the present invention, the gate insulating film and the semiconductor layer can be manufactured from the same sputter target, the manufacturing process can be simplified and the cost can be reduced, and the gate insulating film and the semiconductor layer are formed from the same material. Thus, it is possible to provide a transistor having a favorable electrical characteristic with a low interface state.
トランジスタの製造方法の例を図２を基にして説明する。 An example of a method for manufacturing a transistor will be described with reference to FIG.
まず、絶縁性基板１上に半導体層２を形成する（図２（ａ））。 First, the semiconductor layer 2 is formed on the insulating substrate 1 (FIG. 2A).
絶縁性基板１の材料としては、ガラス、石英、ＹＳＺ（イットリア安定化ジルコニア）、ＭｇＯ、ポリメチルメタクリレート、ポリカーボネート、ポリスチレン、ポリエチレンサルファイド、ポリエーテルスルホン、ポリオレフィン、ポリエチレンテレフタレート、ポリエチレンナフタレート、トリアセチルセルロース、ポリビニルフルオライドフィルム、エチレン−テトラフルオロエチレン共重合樹脂、耐候性ポリエチレンテレフタレート、耐候性ポリプロピレン、ガラス繊維強化アクリル樹脂フィルム、ガラス繊維強化ポリカーボネート、ポリイミド、透明性ポリイミド、フッ素系樹脂、環状ポリオレフィン系樹脂、ポリアクリル系樹脂などを用いることができるが、これらに限定されるわけではない。
これらは単独の基材として使用してもよいが、二種以上を積層した複合基材を使用することもできる。
また、絶縁性基板１の材料としては、可撓性、非可撓性のどちらでもよい。
Materials for the insulating substrate 1 include glass, quartz, YSZ (yttria stabilized zirconia), MgO, polymethyl methacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose. , Polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, transparent polyimide, fluorine resin, cyclic polyolefin resin Polyacrylic resin or the like can be used, but is not limited thereto.
These may be used as a single substrate, but a composite substrate in which two or more kinds are laminated can also be used.
The material of the insulating substrate 1 may be either flexible or inflexible.
半導体層２の形成方法としては、スパッタ法や、パルスレーザー蒸着法（ＰＬＤ法）を用いることができるが、スパッタ法が好ましい。
スパッタ法ではパルスレーザー蒸着法（ＰＬＤ法）と比較してより広い範囲で酸素濃度、キャリア濃度を制御可能でありかつ大面積に容易に成膜可能であるからである。
また、ここで述べるスパッタ法というのはＲＦマグネトロンスパッタ法、ＤＣスパッタ法双方の概念を含む物である。
As a method for forming the semiconductor layer 2, a sputtering method or a pulsed laser deposition method (PLD method) can be used, but a sputtering method is preferable.
This is because the sputtering method can control the oxygen concentration and the carrier concentration in a wider range than the pulse laser deposition method (PLD method) and can easily form a film over a large area.
Further, the sputtering method described here includes the concepts of both the RF magnetron sputtering method and the DC sputtering method.
半導体層２の材料としては、スパッタターゲットとして、ＩｎＡＭＢＺｎＣＯＤ（式中Ｍはガリウム及びアルミニウムのうち少なくとも一つの元素であり、
０．６＜ａ＜１．５
０．６＜ｂ＜１．５
０．６＜ｃ＜１．５
０≦ｄ≦５）からなるアモルファス酸化物材料を用いることができる。
０．９＜ａ＜１．１
０．９＜ｂ＜１．１
０．９＜ｃ＜１．１
３．８＜ｄ＜４．２であればより好ましい。
As a material of the semiconductor layer 2, as a sputter target, In A M B Zn C O D (where M is at least one element of gallium and aluminum,
0.6 <a <1.5
0.6 <b <1.5
0.6 <c <1.5
An amorphous oxide material consisting of 0 ≦ d ≦ 5) can be used.
0.9 <a <1.1
0.9 <b <1.1
0.9 <c <1.1
More preferably, 3.8 <d <4.2.
また、スパッタガスとしては、Ｈｅ、Ｎｅ、Ａｒ、Ｋｒ、Ｘｅ等の不活性ガス、もしくは、これらを混合した物と、スパッタガスの酸素流量比が２０％以下になるように、好ましくは１０％以下になるように酸素を混合したものを用いることができる。
価格等を考慮するとＡｒが好適に用いられる。
また酸素の代わりにオゾンもしくは酸素とオゾンの混合ガスを用いても構わない。
Further, as the sputtering gas, an inert gas such as He, Ne, Ar, Kr, or Xe, or a mixture thereof, and the oxygen flow rate ratio of the sputtering gas is preferably 10% so that the sputtering gas has an oxygen flow ratio of 20% or less. What mixed oxygen so that it may become below can be used.
Ar is preferably used in consideration of the price and the like.
In place of oxygen, ozone or a mixed gas of oxygen and ozone may be used.
半導体層２はＩｎＸＭＹＺｎＺＯＷ（式中Ｍはガリウムもしくはアルミニウムのうち少なくとも一つの元素であり、
０．７＜Ｘ／Ｙ＜１．４
０．７＜Ｚ／Ｙ＜１．７
３＜Ｗ＜５）
から構成されるアモルファス酸化物材料であり、
０．９＜Ｘ／Ｙ＜１．１
１．０＜Ｚ／Ｙ＜１．３
３．０＜Ｗ＜４．５であればより好ましい。
The semiconductor layer 2 is In X M Y Zn Z O W ( wherein M is at least one element selected from gallium or aluminum,
0.7 <X / Y <1.4
0.7 <Z / Y <1.7
3 <W <5)
An amorphous oxide material composed of
0.9 <X / Y <1.1
1.0 <Z / Y <1.3
More preferably, 3.0 <W <4.5.
半導体層２の導電率は１０−１０（Ｓ／ｃｍ）以上１０−３（Ｓ／ｃｍ）以下、好ましくは１０−９（Ｓ／ｃｍ）以上、１０−４（Ｓ／ｃｍ）以下が好ましい。
半導体層２の導電率が上記範囲内であれば、良好な移動度とオン／オフ特性を持つ。
The electrical conductivity of the semiconductor layer 2 is 10 −10 (S / cm) or more and 10 −3 (S / cm) or less, preferably 10 −9 (S / cm) or more and 10 −4 (S / cm) or less.
If the conductivity of the semiconductor layer 2 is within the above range, it has good mobility and on / off characteristics.
次に、前記半導体層２上にゲート絶縁膜３を形成する（図２（ｂ））。 Next, a gate insulating film 3 is formed on the semiconductor layer 2 (FIG. 2B).
ゲート絶縁膜３の形成方法としては、スパッタ法や、パルスレーザー蒸着法（ＰＬＤ法）を用いることができるが、スパッタ法が好ましい。
この時、パターニングはマスクを用いて行う。
As a method for forming the gate insulating film 3, a sputtering method or a pulsed laser deposition method (PLD method) can be used, but a sputtering method is preferable.
At this time, patterning is performed using a mask.
ゲート絶縁膜３の材料は、半導体層２と同じにする。
但し、スパッタガスの酸素流量比は２０％以上、好ましくは５０％以上の物を用いる。
スパッタガスの酸素流量比を５０％以上にすると、極めて低い導電率（１０−１２Ｓ／ｃｍ）のゲート絶縁膜３を得ることができる。
またゲート絶縁膜３の導電率が１０−１１Ｓ／ｃｍ以下であれば、良好な絶縁特性を発揮し、低いオフ電流、良好なオン／オフ特性を実現することができる。
The material of the gate insulating film 3 is the same as that of the semiconductor layer 2.
However, the oxygen flow rate ratio of the sputtering gas is 20% or more, preferably 50% or more.
When the oxygen flow rate ratio of the sputtering gas is 50% or more, the gate insulating film 3 having an extremely low conductivity (10 −12 S / cm) can be obtained.
Further, when the conductivity of the gate insulating film 3 is 10 −11 S / cm or less, good insulating characteristics can be exhibited, and a low off-current and good on / off characteristics can be realized.
ゲート絶縁膜３は、ＩｎＸＭＹＺｎＺＯＷ（式中Ｍはガリウムもしくはアルミニウムのうち少なくとも一つの元素であり、
０．７＜Ｘ／Ｙ＜１．４
０．７＜Ｚ／Ｙ＜１．７
３＜Ｗ＜５）
から構成されるアモルファス酸化物材料であり、
０．９＜Ｘ／Ｙ＜１．１
１．０＜Ｚ／Ｙ＜１．３
３．０＜Ｗ＜４．５であればより好ましい。
The gate insulating film 3, In X M Y Zn Z O W ( wherein M is at least one element selected from gallium or aluminum,
0.7 <X / Y <1.4
0.7 <Z / Y <1.7
3 <W <5)
An amorphous oxide material composed of
0.9 <X / Y <1.1
1.0 <Z / Y <1.3
More preferably, 3.0 <W <4.5.
最後に、半導体活性層２上にソース電極５およびドレイン電極６を、また、ゲート絶縁膜３上にゲート電極４を形成しトランジスタを得る（図２（ｃ））。 Finally, a source electrode 5 and a drain electrode 6 are formed on the semiconductor active layer 2 and a gate electrode 4 is formed on the gate insulating film 3 to obtain a transistor (FIG. 2C).
ソース電極５、ドレイン電極６およびゲート電極４の材料としては、インジウム（Ｉｎ）、アルミ（Ａｌ）、金（Ａｕ）、銀（Ａｇ）等の金属や、酸化インジウム（Ｉｎ２Ｏ３）、酸化スズ（ＳｎＯ２）、酸化亜鉛（ＺｎＯ）、酸化カドミウム（ＣｄＯ）、酸化インジウムカドミウム（ＣｄＩｎ２Ｏ４）、酸化カドミウムスズ（Ｃｄ２ＳｎＯ４）、酸化亜鉛スズ（Ｚｎ２ＳｎＯ４）等の酸化物材料を用いることができる。
また、これらの酸化物材料に不純物をドープしたものも好適に用いられる。
例えば、Ｉｎ２Ｏ３にスズ（Ｓｎ）やモリブデン（Ｍｏ）、チタン（Ｔｉ）をドープしたもの、ＳｎＯ２にアンチモン（Ｓｂ）やフッ素（Ｆ）をドープしたもの、ＺｎＯにインジウム、アルミニウム、ガリウム（Ｇａ）をドープしたもの等である。
ゲート電極、ソース電極及びドレイン電極の材料は、全て同じでもよく、異なっても良い。
As the material of the source electrode 5, the drain electrode 6 and the gate electrode 4, metals such as indium (In), aluminum (Al), gold (Au), silver (Ag), indium oxide (In 2 O 3 ), oxidation Oxidation of tin (SnO 2 ), zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn 2 O 4 ), cadmium tin oxide (Cd 2 SnO 4 ), zinc tin oxide (Zn 2 SnO 4 ), etc. Material materials can be used.
In addition, those oxide materials doped with impurities are also preferably used.
For example, In 2 O 3 doped with tin (Sn), molybdenum (Mo), titanium (Ti), SnO 2 doped with antimony (Sb) or fluorine (F), ZnO indium, aluminum, gallium For example, doped with (Ga).
The materials of the gate electrode, the source electrode, and the drain electrode may all be the same or different.
ソース電極５、ドレイン電極６およびゲート電極４の形成方法としては、スパッタ法とフォトリソグラフィー法の組み合わせた方法を用いることができる。 As a method for forming the source electrode 5, the drain electrode 6, and the gate electrode 4, a method in which a sputtering method and a photolithography method are combined can be used.
スパッタガスとしては、Ａｒおよび酸素を用いることができる。 Ar and oxygen can be used as the sputtering gas.
プラスチックフィルム上に薄膜トランジスタを形成する場合は連続巻取成膜法で成膜することが望ましい。
この場合、半導体層２、ゲート絶縁膜３および電極（ゲート電極４、ソース電極５、ドレイン電極６）の全ての層をスパッタ法で作製しても構わないし、半導体層２およびゲート絶縁膜３をスパッタ法で作製し、電極は蒸着法、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法、印刷法等で形成しても構わない。
When a thin film transistor is formed on a plastic film, it is desirable to form the film by a continuous winding film forming method.
In this case, all layers of the semiconductor layer 2, the gate insulating film 3, and the electrodes (gate electrode 4, source electrode 5, drain electrode 6) may be formed by sputtering, or the semiconductor layer 2 and the gate insulating film 3 may be formed. The electrode may be formed by sputtering, and the electrode may be formed by vapor deposition, CVD (Chemical Vapor Deposition), printing, or the like.
以下、本発明の実施例を説明するが、本発明は実施例に記載された構成および条件に限られるものではない。 Examples of the present invention will be described below, but the present invention is not limited to the configurations and conditions described in the examples.
表１に示した作製条件で、ＲＦマグネトロンスパッタ法においてガラス基板上に作製した。Ｉｎ−Ｇａ−Ｚｎ−Ｏ薄膜の導電率を図１に示す。
Ｉｎ−Ｇａ−Ｚｎ−Ｏ系の材料においては酸素流量を変えることで１４桁以上もの極めて広範囲において導電率を変化させることが可能であった。
この材料は半導体層２およびゲート絶縁膜３の双方として使用可能であることが確認された。
It was produced on a glass substrate by the RF magnetron sputtering method under the production conditions shown in Table 1. The conductivity of the In—Ga—Zn—O thin film is shown in FIG.
In an In—Ga—Zn—O-based material, it was possible to change the conductivity in an extremely wide range of 14 digits or more by changing the oxygen flow rate.
It was confirmed that this material can be used as both the semiconductor layer 2 and the gate insulating film 3.
まず、スパッタターゲットとしてＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガス（混合ガスの流量２０ＳＣＣＭ）を用い、ＲＦマグネトロンスパッタ法によってガラス製の絶縁性基板上に４０ｎｍの膜厚を有する半導体層を作製した。 First, a semiconductor having a film thickness of 40 nm on an insulating substrate made of glass by RF magnetron sputtering using InGaZnO 4 as a sputtering target and a mixed gas of Ar gas and oxygen gas (mixed gas flow rate 20 SCCM) as a sputtering gas. A layer was made.
上記の混合ガスにおいて、酸素ガスの流量を０．２ＳＣＣＭ〜２ＳＣＣＭ（酸素流量比で１％〜１０％）の範囲内で変化させることで、５×１０−１０〜１．８（Ｓ／ｃｍ）の導電率を持つ半導体層を作製した。
作製した半導体層は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
In the above mixed gas, by changing the flow rate of oxygen gas within the range of 0.2 SCCM to 2 SCCM (1% to 10% in oxygen flow ratio), 5 × 10 −10 to 1.8 (S / cm) A semiconductor layer having the following conductivity was manufactured.
The produced semiconductor layer was an amorphous film having an element ratio In: Ga: Zn = 1: 1: 0.9.
次に、半導体層を作製した真空槽内で大気開放せずに、スパッタターゲットとしては半導体層の作製で用いたものと同じＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガスにおいて、酸素ガスの流量を４ＳＣＣＭ〜１８ＳＣＣＭ（酸素流量比で２０％〜９０％）の範囲内で変化させて、ＲＦマグネトロンスパッタ法によって、１７０ｎｍの膜厚を有するゲート絶縁膜を半導体層上の一部にマスクを用いて形成した。
ゲート絶縁膜は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
Next, without opening to the atmosphere in the vacuum chamber in which the semiconductor layer was produced, the same InGaZnO 4 as that used for producing the semiconductor layer was used as the sputtering target, and oxygen gas was mixed in the mixed gas of Ar gas and oxygen gas as the sputtering gas. The gas flow rate is changed within the range of 4 SCCM to 18 SCCM (20% to 90% in oxygen flow ratio), and a gate insulating film having a film thickness of 170 nm is masked on a part of the semiconductor layer by RF magnetron sputtering. Formed using.
The gate insulating film was an amorphous film having an element ratio of In: Ga: Zn = 1: 1: 0.9.
次に、このゲート絶縁膜および半導体層上に、スパッタターゲットとしてＳｎを１０％ドープしたＩｎ２Ｏ３を用い、スパッタガスとして、Ａｒを流量２０ＳＣＣＭ、酸素を流量０．１ＳＣＣＭ用いてスパッタを行った後、フォトリソグラフィーでＳｎをドープした酸化インジウムでできたスパッタ膜をソース電極、ドレイン電極およびゲート電極の３領域に分離しトランジスタを形成した。
このとき形成されたＳｎドープ酸化インジウム（ＩＴＯ）からなる電極膜の導電率は４．０×１０３（Ｓ／ｃｍ）であった。
チャネル長は５０μｍ、チャネル幅は２００μｍであった。
Next, sputtering was performed on the gate insulating film and the semiconductor layer by using In 2 O 3 doped with 10% of Sn as a sputtering target, Ar at a flow rate of 20 SCCM, and oxygen at a flow rate of 0.1 SCCM. Thereafter, a sputtered film made of indium oxide doped with Sn was separated into three regions of a source electrode, a drain electrode, and a gate electrode by photolithography to form a transistor.
The conductivity of the electrode film made of Sn-doped indium oxide (ITO) formed at this time was 4.0 × 10 3 (S / cm).
The channel length was 50 μm and the channel width was 200 μm.
＜比較例１＞
まず、スパッタターゲットとしてＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガス（混合ガスの流量２０ＳＣＣＭ）を用い、ＲＦマグネトロンスパッタ法によってガラス製の絶縁性基板上に４０ｎｍの膜厚を有する半導体層を作製した。
<Comparative Example 1>
First, a semiconductor having a film thickness of 40 nm on an insulating substrate made of glass by RF magnetron sputtering using InGaZnO 4 as a sputtering target and a mixed gas of Ar gas and oxygen gas (mixed gas flow rate 20 SCCM) as a sputtering gas. A layer was made.
上記の混合ガスにおいて、酸素ガスの流量を０．２ＳＣＣＭ〜２ＳＣＣＭ（酸素流量比で１％〜１０％）の範囲内で変化させて、３×１０−１３〜１．８（Ｓ／ｃｍ）の導電率を持つ半導体層を作製した。
作製した半導体層は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
In the above mixed gas, the flow rate of oxygen gas is changed within the range of 0.2 SCCM to 2 SCCM (oxygen flow rate ratio of 1% to 10%), and 3 × 10 −13 to 1.8 (S / cm) A semiconductor layer having electrical conductivity was produced.
The produced semiconductor layer was an amorphous film having an element ratio In: Ga: Zn = 1: 1: 0.9.
次に、半導体層を作製した真空槽内で大気開放せずに、スパッタターゲットとしては半導体層の作製で用いたものと同じＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガスにおいて、酸素ガスの流量を０．２ＳＣＣＭ〜２ＳＣＣＭ（酸素流量比で１％〜１０％）の範囲内で変化させて、ＲＦマグネトロンスパッタ法によって、１７０ｎｍの膜厚を有するゲート絶縁膜を半導体層上の一部にマスクを用いて形成した。
ゲート絶縁膜は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
Next, without opening to the atmosphere in the vacuum chamber in which the semiconductor layer was produced, the same InGaZnO 4 as that used for producing the semiconductor layer was used as the sputtering target, and oxygen gas was mixed in the mixed gas of Ar gas and oxygen gas as the sputtering gas. A part of the gate insulating film having a thickness of 170 nm is formed on the semiconductor layer by RF magnetron sputtering by changing the gas flow rate within a range of 0.2 SCCM to 2 SCCM (1% to 10% in oxygen flow ratio). And using a mask.
The gate insulating film was an amorphous film having an element ratio of In: Ga: Zn = 1: 1: 0.9.
次に、このゲート絶縁膜および半導体層上に、スパッタターゲットとしてＳｎを１０％ドープしたＩｎ２Ｏ３を用い、スパッタガスとして、Ａｒを流量２０ＳＣＣＭ、酸素を流量０．１ＳＣＣＭ用いてスパッタを行った後、フォトリソグラフィーでＳｎをドープした酸化インジウムでできたスパッタ膜をソース電極、ドレイン電極およびゲート電極の３領域に分離しトランジスタを形成した。
このとき形成されたＳｎドープ酸化インジウム（ＩＴＯ）からなる電極膜の導電率は４．０×１０３（Ｓ／ｃｍ）であった。
チャネル長は５０μｍ、チャネル幅は２００μｍであった。
Next, sputtering was performed on the gate insulating film and the semiconductor layer by using In 2 O 3 doped with 10% of Sn as a sputtering target, Ar at a flow rate of 20 SCCM, and oxygen at a flow rate of 0.1 SCCM. Thereafter, a sputtered film made of indium oxide doped with Sn was separated into three regions of a source electrode, a drain electrode, and a gate electrode by photolithography to form a transistor.
The conductivity of the electrode film made of Sn-doped indium oxide (ITO) formed at this time was 4.0 × 10 3 (S / cm).
The channel length was 50 μm and the channel width was 200 μm.
＜比較例２＞
まず、スパッタターゲットとしてＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガス（混合ガスの流量２０ＳＣＣＭ）を用い、ＲＦマグネトロンスパッタ法によってガラス製の絶縁性基板上に４０ｎｍの膜厚を有する半導体層を作製した。
<Comparative example 2>
First, a semiconductor having a film thickness of 40 nm on an insulating substrate made of glass by RF magnetron sputtering using InGaZnO 4 as a sputtering target and a mixed gas of Ar gas and oxygen gas (mixed gas flow rate 20 SCCM) as a sputtering gas. A layer was made.
上記の混合ガスにおいて、酸素ガスの流量を４ＳＣＣＭ〜１０ＳＣＣＭ（酸素流量比で２０％〜５０％）の範囲内で変化させて、３×１０−１３〜１．８（Ｓ／ｃｍ）の導電率を持つ半導体層を作製した。
作製した半導体層は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
In the above mixed gas, the flow rate of oxygen gas is changed within the range of 4 SCCM to 10 SCCM (20% to 50% in oxygen flow ratio), and the conductivity is 3 × 10 −13 to 1.8 (S / cm). A semiconductor layer having was produced.
The produced semiconductor layer was an amorphous film having an element ratio In: Ga: Zn = 1: 1: 0.9.
次に、半導体層を作製した真空槽内で大気開放せずに、スパッタターゲットとしては半導体層の作製で用いたものと同じＩｎＧａＺｎＯ４を、スパッタガスとしてＡｒガスと酸素ガスの混合ガスにおいて、酸素ガスの流量を２ＳＣＣＭ〜１８ＳＣＣＭ（酸素流量比で１０％〜９０％）の範囲内で変化させて、ＲＦマグネトロンスパッタ法によって、１７０ｎｍの膜厚を有するゲート絶縁膜を半導体層上の一部にマスクを用いて形成した。
ゲート絶縁膜は元素比Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．９のアモルファス膜であった。
Next, without opening to the atmosphere in the vacuum chamber in which the semiconductor layer was produced, the same InGaZnO 4 as that used for producing the semiconductor layer was used as the sputtering target, and oxygen gas was mixed in the mixed gas of Ar gas and oxygen gas as the sputtering gas. The gas flow rate is changed within a range of 2 SCCM to 18 SCCM (10% to 90% in terms of oxygen flow ratio), and a gate insulating film having a thickness of 170 nm is masked on a part of the semiconductor layer by RF magnetron sputtering. Formed using.
The gate insulating film was an amorphous film having an element ratio of In: Ga: Zn = 1: 1: 0.9.
次に、このゲート絶縁膜および半導体層上に、スパッタターゲットとしてＳｎを１０％ドープしたＩｎ２Ｏ３を用い、スパッタガスとして、Ａｒを流量２０ＳＣＣＭ、酸素を流量０．１ＳＣＣＭ用いてスパッタを行った後、フォトリソグラフィーでＳｎをドープした酸化インジウムでできたスパッタ膜をソース電極、ドレイン電極およびゲート電極の３領域に分離しトランジスタを形成した。
このとき形成されたＳｎドープ酸化インジウム（ＩＴＯ）からなる電極膜の導電率は４．０×１０３（Ｓ／ｃｍ）であった。
チャネル長は５０μｍ、チャネル幅は２００μｍであった。
Next, sputtering was performed on the gate insulating film and the semiconductor layer by using In 2 O 3 doped with 10% of Sn as a sputtering target, Ar at a flow rate of 20 SCCM, and oxygen at a flow rate of 0.1 SCCM. Thereafter, a sputtered film made of indium oxide doped with Sn was separated into three regions of a source electrode, a drain electrode, and a gate electrode by photolithography to form a transistor.
The conductivity of the electrode film made of Sn-doped indium oxide (ITO) formed at this time was 4.0 × 10 3 (S / cm).
The channel length was 50 μm and the channel width was 200 μm.
効果を確認するため、作製した薄膜トランジスタの特性評価を行った。
成膜条件（酸素流量）、半導体層およびゲート絶縁膜の導電率、およびそれらを用いたトランジスタのＯＮ／ＯＦＦ比を表１に示す。
In order to confirm the effect, characteristics of the manufactured thin film transistor were evaluated.
Table 1 shows the film formation conditions (oxygen flow rate), the conductivity of the semiconductor layer and the gate insulating film, and the ON / OFF ratio of the transistor using them.
また、この結果をグラフにまとめたものを図３に示す。 FIG. 3 shows a summary of the results in a graph.
半導体の導電率が１×１０−３〜２×１０−９（Ｓ／ｃｍ）の範囲内、ゲート絶縁膜の導電率が１×１０−１１（Ｓ／ｃｍ）以下の範囲で、移動度０．８〜８．５ｃｍ２／Ｖｓ以上、ＯＮ／ＯＦＦ比７×１０５〜３×１０８の良好な特性を示している。
半導体層の導電率が上記の範囲内にあっても、絶縁層の導電率が５×１０−１０（Ｓ／ｃｍ）であれば、ＯＮ／ＯＦＦ比が８〜７００程度と低くトランジスタとしては使用できない。また上記の範囲外ではトランジスタの動作は確認できなかった。
When the conductivity of the semiconductor is in the range of 1 × 10 −3 to 2 × 10 −9 (S / cm) and the conductivity of the gate insulating film is in the range of 1 × 10 −11 (S / cm) or less, the mobility is 0. Good characteristics of 0.8 to 8.5 cm 2 / Vs or more and an ON / OFF ratio of 7 × 10 5 to 3 × 10 8 are shown.
Even if the conductivity of the semiconductor layer is within the above range, if the conductivity of the insulating layer is 5 × 10 −10 (S / cm), the ON / OFF ratio is as low as about 8 to 700, and it is used as a transistor. Can not. Outside of the above range, the operation of the transistor could not be confirmed.
本発明のトランジスタは液晶ディスプレー、有機ＥＬディスプレー、光書き込み型コレステリック液晶型ディスプレー、Ｔｗｉｓｔｉｎｇ Ｂａｌｌ 方式ディスプレー、トナーディスプレー方式ディスプレー、可動フィルム方式ディスプレー、ＲＦＩＤ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ Ｉｄｅｎｔｉｆｉｃａｔｉｏｎ）、センサーなどのデバイスに利用することができる。 The transistor of the present invention is used for devices such as liquid crystal displays, organic EL displays, optical writing cholesteric liquid crystal displays, Twisting Ball type displays, toner display type displays, movable film type displays, RFID (Radio Frequency Identification), and sensors. Can do.
１・・・絶縁性基板
２・・・半導体層
３・・・ゲート絶縁膜
４・・・ゲート電極
５・・・ソース電極
６・・・ドレイン電極
DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Source electrode 6 ... Drain electrode
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005299678A JP2007109918A (en) | 2005-10-14 | 2005-10-14 | Transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005299678A JP2007109918A (en) | 2005-10-14 | 2005-10-14 | Transistor and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2007109918A true JP2007109918A (en) | 2007-04-26 |
Family
ID=38035541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005299678A Pending JP2007109918A (en) | 2005-10-14 | 2005-10-14 | Transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2007109918A (en) |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009135380A (en) * | 2007-05-30 | 2009-06-18 | Canon Inc | Method for manufacturing thin film transistor using oxide semiconductor and display device |
| JP2010062549A (en) * | 2008-08-08 | 2010-03-18 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JPWO2008139860A1 (en) * | 2007-05-07 | 2010-07-29 | 出光興産株式会社 | Semiconductor thin film, semiconductor thin film manufacturing method, and semiconductor element |
| KR20100100659A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20100100673A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20100100671A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| KR20110015388A (en) | 2009-08-07 | 2011-02-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| JP2011150322A (en) * | 2009-12-24 | 2011-08-04 | Semiconductor Energy Lab Co Ltd | Display device and electronic device |
| JP2011181800A (en) * | 2010-03-03 | 2011-09-15 | Fujifilm Corp | Method of manufacturing igzo-based amorphous oxide insulating film and method of manufacturing field effect transistor using the same |
| JP2011249691A (en) * | 2010-05-28 | 2011-12-08 | Fujifilm Corp | Method for producing amorphous oxide thin film and method of manufacturing field effect transistor |
| JP2012019092A (en) * | 2010-07-08 | 2012-01-26 | Canon Inc | Electronic device, method of separating elements in electronic device, method of manufacturing electronic device, and display device having electronic device |
| JP2012114247A (en) * | 2010-11-25 | 2012-06-14 | Lg Display Co Ltd | Manufacturing methods of thin-film transistor and electrode substrate for display device |
| KR20120064626A (en) * | 2010-12-09 | 2012-06-19 | 엘지디스플레이 주식회사 | Oxide including film, and oxide semiconductor thin film transistor, and fabrication method of oxide semiconductor thin film transistor using the same |
| JP2012212714A (en) * | 2011-03-30 | 2012-11-01 | Toshiba Corp | Thin film transistor array substrate, method of manufacturing the same, and display device |
| US8324027B2 (en) | 2009-07-10 | 2012-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2013012751A (en) * | 2010-04-16 | 2013-01-17 | Semiconductor Energy Lab Co Ltd | Semiconductor device manufacturing method |
| JP2013175555A (en) * | 2012-02-24 | 2013-09-05 | Tohoku Univ | Method of manufacturing field effect type thin film transistor, and method of forming oxide semiconductor film |
| JP2013179276A (en) * | 2012-02-02 | 2013-09-09 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9257082B2 (en) | 2009-09-04 | 2016-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| JP2017135408A (en) * | 2012-03-14 | 2017-08-03 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| WO2018037335A1 (en) * | 2016-08-26 | 2018-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| JP2018093166A (en) * | 2016-08-03 | 2018-06-14 | 株式会社半導体エネルギー研究所 | Semiconductor device manufacturing method |
| CN108428730A (en) * | 2018-05-16 | 2018-08-21 | 京东方科技集团股份有限公司 | Oled display substrate and preparation method thereof, display device |
| KR20190122628A (en) * | 2009-02-06 | 2019-10-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of manufacturing the semiconductor device |
-
2005
- 2005-10-14 JP JP2005299678A patent/JP2007109918A/en active Pending
Cited By (97)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2008139860A1 (en) * | 2007-05-07 | 2010-07-29 | 出光興産株式会社 | Semiconductor thin film, semiconductor thin film manufacturing method, and semiconductor element |
| US9249032B2 (en) | 2007-05-07 | 2016-02-02 | Idemitsu Kosan Co., Ltd. | Semiconductor thin film, semiconductor thin film manufacturing method and semiconductor element |
| JP2009135380A (en) * | 2007-05-30 | 2009-06-18 | Canon Inc | Method for manufacturing thin film transistor using oxide semiconductor and display device |
| KR101685451B1 (en) | 2008-08-08 | 2016-12-12 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US8729547B2 (en) | 2008-08-08 | 2014-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US10205030B2 (en) | 2008-08-08 | 2019-02-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR101805381B1 (en) | 2008-08-08 | 2017-12-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US9793416B2 (en) | 2008-08-08 | 2017-10-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US9437748B2 (en) | 2008-08-08 | 2016-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR20160077022A (en) * | 2008-08-08 | 2016-07-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| JP2010062549A (en) * | 2008-08-08 | 2010-03-18 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| US9236456B2 (en) | 2008-08-08 | 2016-01-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US9166058B2 (en) | 2008-08-08 | 2015-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US8946703B2 (en) | 2008-08-08 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR20190122628A (en) * | 2009-02-06 | 2019-10-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of manufacturing the semiconductor device |
| KR102229569B1 (en) | 2009-02-06 | 2021-03-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of manufacturing the semiconductor device |
| US10686061B2 (en) | 2009-03-05 | 2020-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20220070403A (en) | 2009-03-05 | 2022-05-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US8461582B2 (en) | 2009-03-05 | 2013-06-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US11961894B2 (en) | 2009-03-05 | 2024-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US11955537B2 (en) | 2009-03-05 | 2024-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20180082385A (en) | 2009-03-05 | 2018-07-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US9941393B2 (en) | 2009-03-05 | 2018-04-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US8759206B2 (en) | 2009-03-05 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20180025312A (en) | 2009-03-05 | 2018-03-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20190016528A (en) | 2009-03-05 | 2019-02-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US10326008B2 (en) | 2009-03-05 | 2019-06-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20200006613A (en) | 2009-03-05 | 2020-01-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| US11233132B2 (en) | 2009-03-05 | 2022-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR20210090151A (en) | 2009-03-05 | 2021-07-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20210036335A (en) | 2009-03-05 | 2021-04-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20190069374A (en) | 2009-03-05 | 2019-06-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20190092360A (en) | 2009-03-05 | 2019-08-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20100100659A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20170036670A (en) | 2009-03-05 | 2017-04-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20170019401A (en) | 2009-03-05 | 2017-02-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20100100673A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20100100671A (en) | 2009-03-05 | 2010-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| US10916566B2 (en) | 2009-07-10 | 2021-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US9054138B2 (en) | 2009-07-10 | 2015-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US10522568B2 (en) | 2009-07-10 | 2019-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20160087401A (en) | 2009-07-10 | 2016-07-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| KR20180105263A (en) | 2009-07-10 | 2018-09-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| KR20210018551A (en) | 2009-07-10 | 2021-02-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| KR20190096445A (en) | 2009-07-10 | 2019-08-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| US8324027B2 (en) | 2009-07-10 | 2012-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US9754974B2 (en) | 2009-07-10 | 2017-09-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US9490277B2 (en) | 2009-07-10 | 2016-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US11374029B2 (en) | 2009-07-10 | 2022-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20140148483A (en) | 2009-07-10 | 2014-12-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| KR20220100086A (en) | 2009-07-10 | 2022-07-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| US8835920B2 (en) | 2009-07-10 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US8441011B2 (en) | 2009-07-10 | 2013-05-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US10157936B2 (en) | 2009-07-10 | 2018-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US8384085B2 (en) | 2009-08-07 | 2013-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR20110015388A (en) | 2009-08-07 | 2011-02-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| US10134912B2 (en) | 2009-09-04 | 2018-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| US11430899B2 (en) | 2009-09-04 | 2022-08-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| KR20230144506A (en) | 2009-09-04 | 2023-10-16 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| KR20180062443A (en) | 2009-09-04 | 2018-06-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| US11652174B2 (en) | 2009-09-04 | 2023-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| US10700215B2 (en) | 2009-09-04 | 2020-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| KR20220135226A (en) | 2009-09-04 | 2022-10-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| KR20200008001A (en) | 2009-09-04 | 2020-01-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| US9257082B2 (en) | 2009-09-04 | 2016-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| KR20220032542A (en) | 2009-09-04 | 2022-03-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| KR20210124128A (en) | 2009-09-04 | 2021-10-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
| US11069817B2 (en) | 2009-09-04 | 2021-07-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| US9047836B2 (en) | 2009-12-24 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| JP2011150322A (en) * | 2009-12-24 | 2011-08-04 | Semiconductor Energy Lab Co Ltd | Display device and electronic device |
| JP2011181800A (en) * | 2010-03-03 | 2011-09-15 | Fujifilm Corp | Method of manufacturing igzo-based amorphous oxide insulating film and method of manufacturing field effect transistor using the same |
| JP2016213499A (en) * | 2010-04-16 | 2016-12-15 | 株式会社半導体エネルギー研究所 | Insulation film manufacturing method |
| US9698008B2 (en) | 2010-04-16 | 2017-07-04 | Semiconductor Energy Laboratory Co., Ltd. | Deposition method and method for manufacturing semiconductor device |
| US10529556B2 (en) | 2010-04-16 | 2020-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Deposition method and method for manufacturing semiconductor device |
| US8518761B2 (en) | 2010-04-16 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Deposition method and method for manufacturing semiconductor device |
| JP2013012751A (en) * | 2010-04-16 | 2013-01-17 | Semiconductor Energy Lab Co Ltd | Semiconductor device manufacturing method |
| US9006046B2 (en) | 2010-04-16 | 2015-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Deposition method and method for manufacturing semiconductor device |
| JP2011249691A (en) * | 2010-05-28 | 2011-12-08 | Fujifilm Corp | Method for producing amorphous oxide thin film and method of manufacturing field effect transistor |
| TWI485775B (en) * | 2010-05-28 | 2015-05-21 | Fujifilm Corp | Method for producing amorphous oxide thin-film, method for producing field-effect transistor |
| KR101523125B1 (en) * | 2010-05-28 | 2015-05-26 | 후지필름 가부시키가이샤 | Method for manufacturing amorphous oxide thin film and method for manufacturing field effect transistor |
| JP2012019092A (en) * | 2010-07-08 | 2012-01-26 | Canon Inc | Electronic device, method of separating elements in electronic device, method of manufacturing electronic device, and display device having electronic device |
| JP2012114247A (en) * | 2010-11-25 | 2012-06-14 | Lg Display Co Ltd | Manufacturing methods of thin-film transistor and electrode substrate for display device |
| KR20120064626A (en) * | 2010-12-09 | 2012-06-19 | 엘지디스플레이 주식회사 | Oxide including film, and oxide semiconductor thin film transistor, and fabrication method of oxide semiconductor thin film transistor using the same |
| KR101970548B1 (en) | 2010-12-09 | 2019-04-19 | 엘지디스플레이 주식회사 | oxide including film, and oxide semiconductor thin film transistor, and fabrication method of oxide semiconductor thin film transistor using the same |
| JP2012212714A (en) * | 2011-03-30 | 2012-11-01 | Toshiba Corp | Thin film transistor array substrate, method of manufacturing the same, and display device |
| JP2013179276A (en) * | 2012-02-02 | 2013-09-09 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9812582B2 (en) | 2012-02-02 | 2017-11-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2013175555A (en) * | 2012-02-24 | 2013-09-05 | Tohoku Univ | Method of manufacturing field effect type thin film transistor, and method of forming oxide semiconductor film |
| JP2017135408A (en) * | 2012-03-14 | 2017-08-03 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2018093166A (en) * | 2016-08-03 | 2018-06-14 | 株式会社半導体エネルギー研究所 | Semiconductor device manufacturing method |
| US11404016B2 (en) | 2016-08-26 | 2022-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device having neural network for calculating set values of luminance and color tone |
| WO2018037335A1 (en) * | 2016-08-26 | 2018-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| US10733946B2 (en) | 2016-08-26 | 2020-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device |
| CN108428730A (en) * | 2018-05-16 | 2018-08-21 | 京东方科技集团股份有限公司 | Oled display substrate and preparation method thereof, display device |
| US11348987B2 (en) | 2018-05-16 | 2022-05-31 | Beijing Boe Display Technology Co., Ltd. | OLED display substrate having large aperture ratio, method of manufacturing the same, and display device |
| CN108428730B (en) * | 2018-05-16 | 2021-01-26 | 京东方科技集团股份有限公司 | OLED display substrate, manufacturing method thereof and display device |
| WO2019218993A1 (en) * | 2018-05-16 | 2019-11-21 | 京东方科技集团股份有限公司 | Oled display substrate and manufacturing method therefor, and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2007109918A (en) | Transistor and its manufacturing method | |
| KR101263538B1 (en) | Semiconductor thin film method for producing same and thin film transistor | |
| JP5386179B2 (en) | Semiconductor device, image display apparatus, thin film transistor manufacturing method, and thin film transistor substrate | |
| JP5213458B2 (en) | Amorphous oxide and field effect transistor | |
| JP5250929B2 (en) | Transistor and manufacturing method thereof | |
| KR101398332B1 (en) | Semiconductor thin film and method for manufacturing same, and thin film transistor | |
| JP5538797B2 (en) | Field effect transistor and display device | |
| US9991135B2 (en) | Method for fabricating a metal oxide thin film transistor | |
| JP5339792B2 (en) | Thin film field effect transistor, method of manufacturing the same, and display device using the same | |
| JP2010040552A (en) | Thin film transistor and manufacturing method thereof | |
| KR20110073536A (en) | Thin film transistor and method for manufacturing same | |
| KR20080087744A (en) | Thin film field effect transistor and display | |
| JPWO2008099863A1 (en) | Semiconductor, semiconductor device and complementary transistor circuit device | |
| KR20100097002A (en) | Top gate type field effect transistor, manufacturing method thereof, and display device comprising the same | |
| JP2009260254A (en) | Composition for oxide semiconductor thin film, field-effect transistor using it, and its method for manufacturing | |
| JP2010074061A (en) | Thin-film field effect transistor | |
| JP2010186860A (en) | Field effect transistor, and method of manufacturing the same | |
| US20170317195A1 (en) | Method for fabricating metallic oxide thin film transistor | |
| WO2015119385A1 (en) | Thin-film transistor having active layer made of molybdenum disulfide, method for manufacturing same, and display device comprising same | |
| JP5098152B2 (en) | Thin film transistor manufacturing method | |
| JP5274165B2 (en) | Thin film field effect transistor and method of manufacturing the same | |
| KR101132989B1 (en) | Method for producing thin film transistor and method for producing electronic optical device | |
| JP2007123661A (en) | Thin-film transistor and method of manufacturing same | |
| KR101417932B1 (en) | Thin film transistor having double layered semiconductor channel and method of manufacturing the thin film transistor | |
| JP2010045159A (en) | Thin film field effect transistor and process of fabricating the same |