JP2007065246A - Exposure mask, mask pattern correction method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge a depth of focus by considering a method for disposing an auxiliary pattern according to the pattern possession density, relating to an exposure mask, a mask pattern correction method and a semiconductor device. <P>SOLUTION: An auxiliary pattern corresponding to a certain pattern such as a memory pattern is formed in a different type of an auxiliary pattern from auxiliary patterns for other patterns. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an exposure mask, a mask pattern correction method, and a semiconductor device, and particularly to an auxiliary pattern in an exposure mask for manufacturing a semiconductor device for expanding a manufacturing margin of a desired pattern shape. The present invention relates to an exposure mask, a mask pattern correction method, and a semiconductor device.

  The demand for miniaturization of semiconductor devices is constantly evolving, and in recent years, a pattern having a line width equal to or shorter than the wavelength of an exposure light source used in the semiconductor device manufacturing process has been required.

  Along with this, illumination conditions that can achieve higher resolving power even in fine patterns, for example, a method using annular illumination such as oblique incidence is adopted, and a proximity effect is produced when manufacturing a reticle for manufacturing an actual semiconductor device. Correction processing is performed.

Here, a manufacturing process of a conventional semiconductor device will be described with reference to FIG.
See FIG.
First, an SiO ₂ film 32 is deposited on the semiconductor substrate 31, and a resist 33 is applied thereon, and then illumination 42 is irradiated on the reticle 41, and light transmitted through a light transmission portion provided on the reticle 41 is projected onto the projection lens 43. Then, the light irradiation part 34 of the resist 33 is cured by exposing the resist 33.

Next, after removing the light irradiation portion 34 cured by performing development processing to form a resist pattern 35, the SiO ₂ film 32 is etched using the resist pattern 35 as a mask to form a contact hole 36. Finally, The resist pattern 35 is removed by ashing.

  In such a semiconductor device manufacturing process, in addition to the reduction of the focus margin due to the miniaturization of the device, it is necessary to consider that the state of the device and the unevenness of the substrate itself vary to some extent. This will be described with reference to FIG.

See FIG.
FIG. 9 is an explanatory diagram of a focus shift caused by the apparatus. For example, due to a change in the focal length of the projection lens 43 due to a change in atmospheric pressure, the focus is deviated from the resist 33 and defocus Δz is generated.

See FIG.
FIG. 10 is an explanatory diagram of a focus shift due to the warpage of the substrate. In the manufacturing process of the semiconductor device, the semiconductor substrate 31 may warp in order to stack various thin films having different stresses.
In this case, when the best focus is set near the center of the semiconductor substrate 31, defocus Δz occurs in the peripheral portion of the semiconductor substrate 31.

See FIG.
FIG. 11 is an explanatory view of the focus shift due to the unevenness of the substrate. After the MOSFET structure is formed on the semiconductor substrate 51, an interlayer insulating film 58 is provided, and the interlayer insulating film 58 is provided with respect to the source / drain regions 57 and the gate electrode 54. When forming contact holes, if there are irregularities due to the gate electrode 54 or the like, irregularities are also formed on the surface of the resist 59 provided on the interlayer insulating film 58.
In this case, if the best focus is set at the position of the gate electrode 54, defocus Δz occurs at the position of the source / drain region 57.

  Accordingly, when the depth of focus (DOF) is shallow, when the defocus shown in FIGS. 9 to 11 occurs, the resist pattern has a dimension different from the design value, which ultimately causes a product defect. .

  In particular, the annular illumination used in conjunction with pattern miniaturization has a strong resolving power, but it has a feature such as that a sufficient depth of focus cannot be achieved for a specific design pitch. The pattern dependence of the focal depth will be described with reference to FIGS.

  The pattern layout of a semiconductor device includes a repetitive pattern of a specific cell layout represented by SRAM and various randomly arranged patterns represented by logic LSI. In many cases, the SRAM cell layout is a design of a corresponding generation. Often designed with the most critical values of the rules.

On the other hand, the logic LSI has many dimensions based on the design rule, such as the minimum line width, but when expressed in terms of line & space, the space is not always the minimum space defined by the design rule.
In other words, the SRAM layout shows a high pattern occupancy, while one logic LSI shows a relatively gradual pattern occupancy.

  In light of this fact and situation, the actual lithography process technology needs to ensure a certain process margin for patterns existing from high to low occupancy rates.

See FIG. 12 and FIG.
FIG. 12 shows a CD-FOCUS curve of a dense pattern and a sparse pattern, and FIG. 13 is an arrangement diagram showing an example of a dense pattern and a sparse pattern made up of openings provided in the reticle in order to obtain this CD-FOCUS curve.

  This CD-FOCUS curve shows the focus shift at the time of exposure on the X-axis and the resist dimensions are plotted on the Y-axis. From this CD-FOCUS curve, the influence of the CD on the focus fluctuation can be seen, and its inclination is The slower the depth of focus, the wider the depth of focus DOF, and the greater the focus margin. Conversely, when the inclination is steep, it means that the depth of focus is very narrow.

The focus value that hits the apex of the parabola is called the best focus, and in many cases, the largest resist dimension is indicated.
For the Y axis, the resist dimension value at the time of best focus is normalized to 100% and graphed.
Further, here, as in the general depth of focus, a method is used in which a focus shake amount indicating a dimension of 90% or more of the dimension value indicated at the time of the best focus is compared as an effective depth of focus.

  As apparent from the CD-FOCUS curve shown in FIG. 12, the dense pattern has a sufficient depth of focus, whereas the focal depth of the sparse pattern is much narrower than that of the dense pattern.

See FIGS. 14 and 15
14 and 15 are light intensity distribution diagrams of projected images on a resist having a dense pattern and a sparse pattern, the horizontal axis indicates the position on the resist, the vertical axis indicates the light intensity, FIG. 14 shows the distribution during best focus, and FIG. 15 shows the distribution during defocus.

In the figure, the curve I _a is the light intensity distribution of the dense pattern, and the curve I _b is the light intensity distribution of the sparse pattern. When the resist exposed with such a light intensity distribution is developed, the critical value I ₀ A resist pattern is formed in which a portion exposed by exposure light having an intensity exceeding 1 is an opening.

At the best focus shown in FIG. 14, the difference in the depth of focus between the dense pattern and the sparse pattern has little influence on the width of the opening formed in the resist pattern, and W _a = W _b .
On the other hand, at the time of defocusing shown in FIG. 15, since the focal depth of the sparse pattern becomes shallower than the focal depth of the dense pattern, W _a > W _b , causing a product defect.

  Therefore, as described above, in the oblique incidence illumination that has been frequently used in recent years, the focus depth tends to decrease as the pattern density decreases.

  Therefore, as an example of a method for increasing the depth of focus, it has been proposed to arrange an auxiliary pattern called an assist pattern or a scattering bar (SB) in the periphery of the main pattern (see, for example, Patent Document 1). Here, the auxiliary pattern according to the above proposal will be described with reference to FIGS.

See FIG.
FIG. 16 is a plan view of the main part of the reticle when the auxiliary pattern is provided in the sparse pattern. The auxiliary pattern SB _z is provided so as to face the four sides of the main pattern M _{b with} respect to the main pattern M _b. Yes.
The auxiliary pattern SB _z in this case is a square pattern with α = β, and is formed in a size that is not resolved by the exposure apparatus.

See FIG.
FIG. 17 shows a CD-FOCUS curve of a sparse pattern provided with such an auxiliary pattern, which is superimposed on the CD-FOCUS curve shown in FIG.
As can be seen, the slope of the parabola becomes gentle, it can be seen that the depth of focus is enlarged by providing the auxiliary patterns SB _z.

See FIG.
FIG. 18 is an explanatory diagram of resist dimensions for determining the depth of focus. The resist dimensions in the CD-FOCUS curve of FIG. 17 are defined by the hole diameters as shown in FIG.
JP 2002-122976 A

However, the improvement of the focal depth of the sparse pattern by providing the auxiliary pattern SB _z in the above proposal is about 15%, which is not sufficiently deep compared to the focal depth of the dense pattern. It's hard to say.

Therefore, the present inventor provided a plurality of rows of auxiliary patterns SB _{a1 so as} to _face each side of the main pattern M _b , forms a rectangular pattern, and sets a square auxiliary pattern SB _a2 on the diagonal of the main pattern M _b. It is proposed to provide (see Japanese Patent Application No. 2005-159077 if necessary).

Another arrangement example of the auxiliary pattern aiming at the same kind of effect as the auxiliary pattern will be described with reference to FIGS. 19 and 20.
See FIG.
FIG. 19 uses a square pattern SB _a2 whose long side is the same as or shorter than one side of the main pattern or a rectangular pattern SB _a1 close to a square as the auxiliary pattern. The main pattern M is regularly arranged two-dimensionally. Five types of arrangement states A to E are shown according to the density of _b .

See FIG.
FIG. 20 uses linear patterns SB _b1 and SB _b2 whose long sides are longer than one side of the main pattern as auxiliary patterns. In this case as well, there are five types A to E depending on the density of the main pattern M _b. The arrangement state of is shown.

  However, although the auxiliary pattern group shown in FIG. 19 and the auxiliary pattern group shown in FIG. 20 are provided in order to achieve the same effect, they should never be formed simultaneously using one generation rule (script). I can't.

For example, even in the comparison of the E type indicating the rudimentary shape, the inner auxiliary pattern SB _{b1 in} FIG. 20 is longer than the main pattern M _{b in} the long side direction by three times or more, and the outer auxiliary pattern SB. _{Whereas b2} is about 5 times, the long sides of the auxiliary patterns SB _a1 and SB _a2 in FIG. 19 are the same as or shorter than the main pattern M _{b in} the long side direction of the main pattern M _b. is there.
On the other hand, regarding the length in the short side direction, the relationship is reversed, and the auxiliary patterns SB _b1 and SB _b2 in FIG. 20 are narrower than the auxiliary patterns SB _a1 and SB _a2 shown in FIG. is there.

In order to generate such an auxiliary pattern, a method of defining and generating and arranging a distance (space) from the main pattern M _b is generally used. Furthermore, a space between the main pattern M _b and its own pattern are used. Depending on the size, it should be placed within a range that does not interfere with the process.

Therefore, when the auxiliary patterns are arranged (inserted) in the limited space between the main patterns, when the auxiliary patterns SB _a1 and SB _a2 having the shape shown in FIG. 19 are inserted, the arrangement number is small. When the auxiliary patterns SB _b1 and SB _b2 having the shape shown in FIG. 20 are inserted, the number of arrangement is greater than the number possible with the auxiliary patterns SB _a1 and SB _a2 shown in FIG.

  For example, when comparing with B type or C type auxiliary patterns, the B type and the C type have the same main pattern space, but the difference in the auxiliary pattern size and the allowable auxiliary pattern and the space between the auxiliary patterns. The number of auxiliary patterns to be inserted is different because of the difference.

See FIG.
FIG. 21 is a graph comparing the effects of the difference in the shape of the auxiliary pattern. The horizontal axis indicates the pitch of the design pattern, and the vertical axis plots the resist dimensions.
However, the value on the vertical axis indicates a value normalized with the value at the best focus as 100%, and indicates that the resist size decreases when defocused. This is shown in FIGS. 14 and 15. Street.

Therefore, when comparing the CD behavior at the time of defocusing between the case surrounded by the auxiliary pattern SB _a and the case surrounded by the auxiliary pattern SB _b by the through pitch, the auxiliary pattern SB _a is more than the auxiliary pattern SB _b. However, it can be seen that there are pitch regions that vary as a plot.

  This phenomenon indicates that the auxiliary pattern effect depends on the pitch. The occurrence occurs at a pitch that changes the placement rule, and occurs because the position relative to the main pattern moves away from the optimum position. This phenomenon itself is difficult to avoid because it follows the fundamental principle of SB technology.

However, in the sense of optimizing the arrangement rule, it is possible to keep the CD fluctuation at the time of defocusing at a high level without depending on the pitch and also keep the CD attenuation amount constant without depending on the pitch. The smoothness curve can be drawn at the time of defocusing by suppressing the amount of undulations, and this is a measure of the degree of completion of the auxiliary pattern technology.
Looking at such a point of view, who mask surrounded by the auxiliary patterns SB _b shown in FIG. 20 can be determined to be in a high perfection throughout the pitch.

Therefore, the auxiliary pattern SB _a and the auxiliary pattern SB _b are arranged in a specific circuit pattern and the effects are compared, and this will be described with reference to FIGS.
See FIG.
Figure 22 is an explanatory view of an arrangement example of applying the assist patterns SB _a logic LSI pattern, there is a region where the auxiliary pattern is not disposed in the central portion as shown in FIG.

See FIG.
FIG. 23 is an explanatory diagram of an arrangement example in which the auxiliary pattern SB _b is applied to the logic LSI pattern. As shown in the figure, a thin auxiliary pattern SB _b is also combined in the central portion.

See FIG.
FIG. 24 is an explanatory diagram of an arrangement example in which the auxiliary pattern SB _a is applied to the SRAM layout, and a plurality of auxiliary patterns SB _a are arranged inside the cell as shown in the figure.

See FIG.
FIG. 25 is an explanatory diagram of an arrangement example in which the auxiliary pattern SB _b is applied to the SRAM layout. As shown in the figure, only one thin auxiliary pattern SB _b is arranged at the center.

See FIG.
FIG. 26 is an explanatory diagram of dimensions at the time of defocusing of the main patterns L ₁ , L ₂ , L ₃ , S ₁ and S ₂ extracted from the pattern layouts of FIGS. 22 to 25, and the value on the vertical axis represents the best focus. The value normalized by assuming the value at 100% as 100% is shown.

As is apparent from the figure, in the case of the main patterns L ₁ , L ₂ , and L ₃ in the logic LSI layout that is a sparse pattern, it is more effective to arrange the linear auxiliary pattern SB _b than the auxiliary pattern SB _a. It can be seen that it is.
On the other hand, in the case of the main patterns S ₁ and S ₂ in the SRAM layout which is a dense pattern, it can be seen that it is more effective to arrange the rectangular auxiliary pattern SB _a than the auxiliary pattern SB _b .

As described above, as a result of intensive studies by the present inventors, the phenomenon that an optimal arrangement method and arrangement shape can exist depending on the pattern layout has been confirmed.
That is, it is still insufficient to use a uniquely defined arrangement rule for various patterns that can exist in a chip, and there is a problem that it is difficult to say that the technique is in view of stable mass production.

  Accordingly, an object of the present invention is to increase the depth of focus by taking advantage of the characteristics of an illumination system having resolution and considering an auxiliary pattern arrangement method according to the pattern occupancy density or the like.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
See FIG. 1 In order to solve the above-mentioned problem, according to the present invention, in an exposure mask, an auxiliary pattern for a certain pattern and an auxiliary pattern for a pattern other than the other patterns are different types of auxiliary patterns. Features.

  In this way, appropriate auxiliary patterns are appropriately arranged in accordance with the pattern layout, and for example, auxiliary patterns for high-density pattern layouts such as memories such as SRAM, and other relatively random logics such as random logic. For patterns with a low occupancy rate, the shape and arrangement method of auxiliary patterns optimized according to the layout is implemented, and various auxiliary patterns are produced in such a way that the maximum effect can be obtained for various patterns that may exist in the device chip. Since it is arranged, the depth of focus can be effectively expanded.

  In this case, the auxiliary pattern for the memory pattern is a rectangular pattern in which the length of the side facing the side of each memory pattern is the same as or shorter than the length of the side of the memory pattern, and other than the memory pattern The auxiliary pattern for this pattern is preferably a fine linear pattern having a ratio of the long side to the short side of 5 or more.

  Further, as a mask pattern correction method, in the proximity effect correction process, a memory pattern and other patterns are distinguished and extracted from design data, and the extracted memory pattern and other patterns are different types. It is sufficient to generate an auxiliary pattern, and thereby an auxiliary pattern optimized according to the layout can be provided.

  Note that the memory pattern and other patterns may be distinguished depending on the presence or absence of a memory frame surrounding the memory pattern in the design data.

  In this case, as an auxiliary pattern for the memory pattern, a rectangular pattern whose length opposite to the side of each memory pattern is equal to or shorter than the length of the side of the memory pattern is a high-density pattern layout. It is suitable for widening the depth of focus.

  On the other hand, as an auxiliary pattern for patterns other than the memory pattern, a fine linear pattern having a ratio of the long side to the short side of 5 or more is suitable for increasing the depth of focus of the low-density pattern layout.

  In addition, by using the above-described exposure mask in a manufacturing process of a semiconductor device, a semiconductor device having a circuit pattern faithful to design can be manufactured stably with high reproducibility.

  According to the present invention, due to the proximity effect brought about by lithography, the depth of focus of the illumination condition can be made wider than ever, regardless of the pattern layout, so it can be applied to patterns existing in a wide variety of arrangements. Therefore, a large process margin can be obtained, which greatly contributes to stable manufacturing of the semiconductor device.

  In the proximity effect correction process, for example, the memory pattern and the other pattern are distinguished and extracted from the design data based on the presence or absence of a memory frame surrounding the memory pattern in the design data. As an auxiliary pattern of a different type with respect to the pattern, for example, an auxiliary pattern for the memory pattern, the length of the side opposite to the side of each memory pattern is equal to or less than the length of the side of the memory pattern. As the auxiliary pattern for the rectangular pattern having a length and a pattern other than the memory pattern, a fine linear pattern having a ratio of the long side to the short side of 5 or more is generated.

Here, with reference to FIG. 2 thru | or FIG. 7, the manufacturing process of the reticle of Example 1 of this invention is demonstrated.
See FIG. 2 and FIG.
FIG. 2 is a flowchart showing a reticle manufacturing procedure according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the main part of the reticle during manufacturing. FIG. 2 is a flowchart of FIG. However, the basic steps other than the details of the proximity effect correction process to be described later are exactly the same as the conventional reticle manufacturing process.

  Note that the reticle generally refers to a substrate in which a metal thin film pattern is formed on a quartz glass substrate, and is a kind of photomask. The pattern of the metal thin film on the reticle is the same as that of a semiconductor device. In many cases, it is composed of patterns for forming circuit patterns for one chip to several chips.

First, in the design data creation step of step S1, design data D ₀ of a device pattern formed on a semiconductor substrate, for example, data including the position and size of a device pattern such as a contact hole, is used for the reduction ratio of reduced projection exposure. reciprocal only by similar enlargement creates design data D ₁ as the pattern of the metal thin film on the reticle.

Then, the design data verification process in step S2, verifying whether the design data D ₁ is created as designed rules.
Here, the design rule refers to restrictions on forming the pattern of the metal thin film on the reticle. For example, there are restrictions on ensuring the minimum line width of the metal thin film pattern and eliminating the minimum pattern interval. is there.

When the design data D ₁ satisfies the design rule, the process proceeds to the proximity effect correction process at the next step S3. On the other hand, when the design data D ₁ does not satisfy the design rule, the process proceeds to the design data correction process at step S8. , design data D ₁ that has been modified is repeated until satisfying the design rule.
The design data correction step, the design data portion does not satisfy the design rule, to fit the design rule, a step of modifying the design data D _1.

Then, although details of the proximity effect correction process in step S3 will be described later, in the proximity correction step, while deforming the design data D ₁ in consideration of the optical proximity effect, thereby generating an auxiliary pattern for improving the depth of focus .

  That is, when the reticle is illuminated, a projection image of the metal thin film pattern on the reticle is obtained, and when this projection image is passed through the lens, a reduced projection image is obtained. However, the size of the metal thin film pattern on the reticle is When approaching the wavelength of light, the reduced projection image is not completely similar to the metal thin film pattern due to the so-called proximity effect of light.

  Therefore, it is necessary to correct the design data for forming the metal thin film pattern before deformation so that the metal thin film pattern on the reticle is deformed and the reduced projection image becomes similar to the metal thin film pattern before deformation. .

Then, the proximity correction verification process of step S4, if the design data D ₃ corrected to verify whether it is appropriate to obtain a reduced projection imaging was scheduled, the correction of the design data is appropriate, On the other hand, the process proceeds to the exposure pattern forming process in step 5. On the other hand, if the design data D ₃ is not appropriate, the process proceeds to the correction parameter correction process in step 9 and is repeated until the corrected design data D ₃ becomes appropriate design data.

Then, in the exposure pattern forming process of step 5, using the design data D ₃ which was corrected by operating an electron beam drawing apparatus, as shown in FIG. 3, Cr or on the quartz glass substrate 11 A resist pattern 15 is formed by drawing and developing a pattern with an electron beam 14 on an electron beam resist film 13 provided via a metal thin film 12 such as MoSi ₂ .

  Next, in the line width verification process of step 6, the line width of the resist pattern 15 is verified using a length measuring device such as a CD-SEM. If the line width of the resist pattern 15 is within the standard value, step 7 is performed. The process proceeds to the metal thin film formation process by etching.

On the other hand, if the line width of the resist pattern 15 is not within the standard value, the process proceeds to the exposure condition changing step in Step 10.
This exposure condition changing step is a step of changing the electron beam exposure conditions of the electron beam exposure apparatus in order to keep the line width of the resist pattern 15 formed in the exposure pattern forming step within the standard value.

  However, when it is determined that the line width of the resist pattern 15 cannot be kept within the standard value only by the electron beam exposure conditions, the process goes back up to the correction parameter correction step in step S9, and again the proximity effect. A correction process is performed.

  Next, in the metal thin film pattern forming process by etching in Step 7, the metal thin film 12 is etched using the resist pattern 15 determined to be within the standard value as a mask to form the metal thin film pattern 16, and finally Further, by removing the resist pattern 15 by ashing, the reticle 10 is completed and all the steps are completed.

Next, with reference to FIG. 4 to FIG. 7, the proximity effect correction process of step 3 which is a characteristic point of the first embodiment of the present invention will be described in detail.
See Figure 4
FIG. 4 is a flowchart showing details of the proximity effect correction step of step 3 shown in FIG.
First, in the initial step of the design data in step S3 _1, performs initial processing of the design data D ₀ of the device pattern, after the design data D _1, in the extraction process of the subject graphic in step S3 _2, and corrected The figure which becomes is extracted sequentially.

Note that the initial processing includes the following processing.
Since design data for manufacturing an LSI generally includes not only data for one element or one layer but also design data for all elements or all layers that can be established as an LSI, these data This is a step for selecting and setting the reticle to be processed from a variety of data, in other words, only the target layer is processed.

Then, in the determination process of extraction result in step S3 _3, or extracted figure is a memory pattern such as SRAM, or it is determined whether the pattern other than the memory pattern in the logic LSI pattern or the like, the memory pattern In this case, the process proceeds to the S system processing step, and in cases other than the memory pattern, the process proceeds to the L system processing process.
Note that this determination is made based on the presence or absence of a memory frame such as an SRAM frame in the design data.

See also FIG.
In L system, first, in a fine linear SB generating process of step S3 _41, the extracted design data D _1, design data D ₁ by the main pattern M ₁ of each 3 lines shape so as to surround the four sides An auxiliary pattern SB ₁ is generated.
Incidentally, the linear assist patterns SB _b1, when one side of the main pattern M ₁ according to the design data D ₁ and 0.1 [mu] m, for example, a size of 0.1 [mu] m × 0.06 .mu.m, and sizes that are not resolved during exposure To do.

Then, whether or not in the inspection step in step S3 _42, linear assist patterns SB _b1 between the projected image of that caused, or the projected image of the main by the design data D ₁ pattern M ₁ and the linear auxiliary patterns SB _b1 interferes It performed Kano space checking, to generate new linear assist patterns SB _b1 so as not to interfere with the interfere, if no interference, the operation proceeds to the next step S3 ₄₃ minute linear SB stretching step.

In the figure, three fine linear auxiliary patterns SB _b1 are generated, but this number may be determined from the relationship between the working time and the effect of improving the depth of focus, which are in a trade-off relationship. In the case of a book, the throughput is improved, but the effect of improving the depth of focus is low. On the other hand, when the number is four or more, the effect of improving the depth of focus is increased, but the throughput is greatly reduced.

Then, the fine linear SB stretching step of the step S3 _43, by stretching a linear auxiliary patterns SB _b1 that is generated, for example, a 0.5 [mu] m × fine linear aid of 0.06μm patterns SB _b2 and SB _b3 .
At this time, if the distance between the opposing SB _b2 and SB _b3 is not resolved in the exposure ECR, SB _b2 and SB _b3 may intersect or be combined during the stretching process.

Then, in the inspection step in step S3 _44, performed whether the space checking the projected image of the fine line-like auxiliary which is generated patterns SB _b2 and SB _b3 interfere with each other, the fine lines of the size that does not interfere with interfere to generate Jo auxiliary patterns SB _b2 and SB _b3, if no interference, the operation proceeds to the next step S3 ₆ of the OPC process.
Note that when the projection images of the fine linear auxiliary patterns SB _b2 and SB _b3 interfere with each other, the exposure amount at the interference portion increases, and the auxiliary pattern that should not be resolved is resolved and causes product defects. .

See also FIG.
On the other hand, in the S-system, first, in the pre-bias process of step S3 _51, after obtaining the design data D ₂ by extending the four sides of the design data D _1, in the orthogonal quadrature SB generating process of step S3 _52, designed generating a respective two rectangular auxiliary patterns SB _a1 so as to face the respective sides of the main pattern M ₂ by the data D _2.
Incidentally, the rectangular auxiliary patterns SB _a1 in this case, when one side of the main pattern M ₂ according to the design data D ₂ and 0.1 [mu] m, for example, a size of 0.12 .mu.m × 0.10 .mu.m, not resolved during exposure Magnitude.

Then, in the inspection step in step S3 _53, rectangular auxiliary patterns SB _a1 between the projected image of that caused, or the projected image of the main pattern M ₂ according to the design data D ₂ rectangular auxiliary patterns SB _a1 of whether interference A space check is performed, and if there is interference, a rectangular auxiliary pattern SB _a1 having a size narrowed so as not to interfere or having a shorter short side is generated. If there is no interference, the next step S3 _{54 is performed.} Proceed to the guideline frame generation process.

Then, the pointer frame generation process at step S3 _54, the size around the main pattern M ₂ according to the design data D ₂ generates the variable pointer frame F.

See also FIG.
Then, in the oblique SB generation process in step S3 _55, it generates a rectangular auxiliary patterns SB _a2 square sharing this guidance frame F and 1 vertex inside the guide frame F.
The rectangular auxiliary pattern SB _a2 has a size of, for example, 0.11 μm × 0.11 μm.

Then, in the inspection step in step S3 _56, rectangular auxiliary patterns SB _a2 and the rectangular auxiliary patterns SB _a1 between the projected image of the caused, or the projected image of the main by the design data D ₂ pattern M ₂ and the rectangular auxiliary patterns SB _a2 is performed whether space check interfering, back to the pointer frame generation process of step S3 ₅₄ when interfere, or increase the size of the pointer frame F, or change the size of the rectangular auxiliary patterns SB _a2, repeated until the interference does not occur, if not interfere, the process proceeds to the next step S3 ₆ of the OPC process.
Note that the OPC process of Step S3 _6, will be described S-system, the basic flow and processing principles also L lines are the same.

Then, in the OPC process of Step S3 _6, only the enlargement processing to the main pattern M ₂ according to the design data D ₂ so that the projection image by the main pattern M ₂ according to the design data D ₂ coincides with the plane shape of the device pattern to the target and carried out the design data D _3.
Note that enlargement processing is not performed on the rectangular auxiliary patterns SB _a1 and SB _a2 .
In the case of the L system, enlargement processing is not performed for SB _b2 and SB _b3 .

Then, in the inspection step in step S3 _7, the design data D _3, rectangular auxiliary patterns SB _a1, SB design data D _a1 also include location information of _a2, D _a2, L line of the design data D ₄ for the main pattern, and fine The design data D _{b1 and} D _b2 including the positional information of the linear auxiliary patterns SB _b1 and SB _b2 are data that can guarantee dimensions in the actual manufacturing process of the reticle, and a desired resist dimension can be obtained by exposure. Whether it is data or not is determined by simulation.

If the result of determination is that it is the dimensions guarantee proceeds to output data extraction step of the next step S3 _8, whereas, if it can not have dimensions guarantee returns to OPC process of Step S3 _6, OPC until a size guarantees Repeat the process.

Next, in the output data extraction process in step S3 ₈ , design data D ₃ , D ₄ , D _a1, D _a2 , D _{b1, and} D _b2 whose dimensions can be guaranteed are extracted, and a series of proximity effect corrections in step S3 The process ends, and the process proceeds to the proximity effect correction verification process of step S4 shown in FIG.

The OPC process in S3 ₆ is a process of sizing the main patterns M ₁ and M ₂ , and the subsequent S3 ₇ process checks whether or not the actual desired dimension has been corrected to a shape or size after sizing. It is a process.

Further, S4 is the proximity correction when creating the reticle, i.e., S3 ₆ when the processing object is transferred to the resist on the wafer, the resist is process that aims to put the desired dimensions, S4 Is a step of performing a process for the reticle 10 itself having a metal thin film on the quartz glass substrate to obtain a desired dimension in the reticle production process.

As described above, in the first embodiment of the present invention, as an auxiliary pattern for a high-density pattern such as SRAM, a square or rectangular shape having a long side that is the same as or shorter than the side of the main pattern. Since the rectangular auxiliary pattern SB _a is used and the fine linear auxiliary pattern SB _b having a longer side than the side of the main pattern is used as an auxiliary pattern for a low density pattern such as a logic LSI, the device Various auxiliary patterns can be arranged in such a way as to maximize the effect on the various patterns that may exist on the chip, thereby effectively increasing the depth of focus.
Incidentally, the long sides and the ratio of the short side of the fine line-shaped auxiliary patterns SB _b is desirably 5 or more.

  In addition, since the presence / absence of a memory frame such as an SRAM frame in the design data is used in the target graphic extraction process, it is possible to uniquely and easily determine which auxiliary pattern is to be generated.

Next, referring to FIG. 8, a manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described.
Refer again to FIG.
First, after depositing the SiO ₂ film 32 on the semiconductor substrate 31 and coating the resist 33 thereon, different auxiliary patterns are provided depending on whether the L system or the S system created by the method of the first embodiment. The reticle 41 is irradiated with illumination 42, the light transmitted through the light transmission portion provided on the reticle 41 is condensed by the projection lens 43, and the resist 33 is exposed to cure the light irradiation portion 34 of the resist 33. .

Next, after removing the light irradiation portion 34 cured by performing development processing to form a resist pattern 35, the SiO ₂ film 32 is etched using the resist pattern 35 as a mask to form a contact hole 36. Finally, The resist pattern 35 is removed by ashing.

  At this time, since the reticle created by the method of Example 1 is used, a circuit pattern (contact hole in the case of FIG. 8) faithful to the design is formed. In such a series of photolithography processes, By using a combination of various reticles created by the method of Embodiment 1, a semiconductor device having a fine circuit pattern can be formed with good reproducibility and stability.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments and can be variously modified. For example, the rectangular auxiliary pattern and the fine line The size and shape of the auxiliary pattern are appropriately changed according to the wavelength of the exposure light source used, the sensitivity of the photoresist, or the like.

  Each of the above embodiments is based on the premise that a binary mask is used in a KrF light source exposure apparatus that has been frequently used in recent years. However, in the ArF light source exposure apparatus that will start to be frequently used in the future, and further in the immersion type ArF exposure apparatus, the phase shift is performed. Even when a mold mask, for example, a halftone mask is used, the effect is sufficiently exhibited, which is more preferable.

  In each of the above embodiments, the reticle is described as an SRAM. However, the present invention is not limited to the SRAM, and various semiconductor devices having memory cell regions in which regular patterns such as DRAM, FeRAM, and ROM are arranged. Applies to

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Supplementary note 1) An exposure mask, wherein an auxiliary pattern for a certain pattern and an auxiliary pattern for other patterns are different types of auxiliary patterns.
(Supplementary note 2) The above-mentioned pattern is a memory parameter, and the auxiliary pattern for the memory pattern is such that the length of the side facing the side of each memory pattern is equal to or shorter than the length of the side of the memory pattern. 2. The exposure mask according to appendix 1, wherein the auxiliary pattern for the pattern other than the memory pattern is a fine linear pattern having a ratio of a long side to a short side of 5 or more.
(Supplementary Note 3) In the proximity effect correction process, a process of distinguishing and extracting a memory pattern and other patterns from design data, and different types of auxiliary patterns for the extracted memory pattern and other patterns. A mask pattern correcting method comprising: generating a mask pattern.
(Additional remark 4) The mask pattern correction method according to Additional remark 3, wherein the memory pattern is distinguished from other patterns by the presence or absence of a memory frame surrounding the memory pattern in the design data.
(Additional remark 5) The auxiliary pattern with respect to the said memory pattern consists of a rectangular pattern in which the length of the edge | side which opposes the edge | side of each memory pattern is the same as or less than the length of the edge of the said memory pattern. The mask pattern correction method according to appendix 3 or 4, (Supplementary note 6) The mask pattern according to any one of supplementary notes 3 to 5, wherein the auxiliary pattern for the pattern other than the memory pattern is a fine linear pattern having a ratio of a long side to a short side of 5 or more. Correction method.
(Additional remark 7) It has a circuit pattern formed using the exposure mask of Additional remark 1 or 2, The semiconductor device characterized by the above-mentioned.

  As a practical example of the present invention, SRAM is typical, but it is also applied to a reticle for manufacturing various memory devices such as DRAM, FeRAM, MRAM, ROM, etc. The present invention is also applicable to other exposure masks such as a proximity exposure mask other than the reticle.

It is explanatory drawing of the fundamental structure of this invention. It is a flowchart showing the manufacture procedure of the reticle of Example 1 of this invention. It is a schematic principal part sectional drawing in the middle of manufacture of a reticle. FIG. 3 is a flowchart showing details of a proximity effect correction process in step 3 shown in FIG. 2. FIG. It is explanatory drawing of the auxiliary | assistant pattern generation process in L system | strain. It is explanatory drawing of the auxiliary | assistant pattern generation process to the middle in S system | strain. It is explanatory drawing of the auxiliary | assistant pattern generation process and OPC process after FIG. 6 in S system | strain. It is explanatory drawing of the manufacturing process of the conventional semiconductor device. It is explanatory drawing of the focus shift resulting from an apparatus. It is explanatory drawing of the focus shift | offset | difference by the curvature of a board | substrate. It is explanatory drawing of the focus shift | offset | difference by the unevenness | corrugation of a board | substrate. It is a CD-FOCUS curve of a dense pattern and a sparse pattern. FIG. 5 is an arrangement diagram showing an example of a dense pattern and a sparse pattern made of openings provided in a reticle for obtaining a CD-FOCUS curve. It is the light intensity distribution figure of the projection image on the resist of the dense pattern and sparse pattern at the time of the best focus. It is the light intensity distribution figure of the projection image on the resist of the dense pattern and sparse pattern at the time of a defocus. It is a principal part top view of a reticle at the time of providing an auxiliary pattern in a sparse pattern. It is a CD-FOCUS curve of a sparse pattern provided with an auxiliary pattern. It is explanatory drawing of the resist dimension which determines a depth of focus. It is explanatory drawing of the arrangement _| positioning state of rectangular auxiliary pattern _SBa1 , SBa2. It is explanatory drawing of the arrangement _| positioning state of linear auxiliary pattern _SBb1 , SBb2. It is explanatory drawing of the effect by the difference in the shape of an auxiliary pattern. The logic LSI pattern is an explanatory view of an arrangement example of applying the assist patterns SB _a. The logic LSI pattern is an explanatory view of an arrangement example of applying the assist patterns SB _b. Is an explanatory view of an arrangement example of applying the assist patterns SB _a to SRAM layout. It is an explanatory view of an arrangement example of applying the assist patterns SB _b to SRAM layout. 22 to the main pattern L ₁ extracted from the pattern layout of FIG. 25, L _2, L _3, an illustration of S _1, S ₂ of the defocus at the time dimension.

DESCRIPTION OF SYMBOLS 10 Reticle 11 Quartz glass substrate 12 Metal thin film 13 Electron beam resist film 14 Electron beam 15 Resist pattern 16 Metal thin film pattern 31 Semiconductor substrate 32 SiO ₂ film 33 Resist 34 Light irradiation part 35 Resist pattern 36 Contact hole 41 Reticle 42 Illumination 43 Projection lens 51 Semiconductor substrate 52 Element isolation region 53 Gate insulating film 54 Gate electrode 55 Extension region 56 Side wall 57 Source / drain region 58 Interlayer insulating film 59 Resist

Claims (6)

An exposure mask, wherein an auxiliary pattern for a certain pattern and an auxiliary pattern for other patterns are different types of auxiliary patterns. In the proximity effect correction step, a step of distinguishing and extracting a memory pattern and other patterns from the design data, and a step of generating different types of auxiliary patterns for the extracted memory pattern and the other patterns A mask pattern correction method comprising: 3. The mask pattern correction method according to claim 2, wherein the memory pattern is distinguished from other patterns by the presence or absence of a memory frame surrounding the memory pattern in the design data. The auxiliary pattern for the memory pattern is a rectangular pattern having a side length opposite to a side of each memory pattern equal to or shorter than a side length of the memory pattern. 4. The mask pattern correction method according to 2 or 3. 5. The mask pattern correction method according to claim 2, wherein the auxiliary pattern for the pattern other than the memory pattern is a fine linear pattern having a ratio of a long side to a short side of 5 or more. . A semiconductor device having a circuit pattern formed using the exposure mask according to claim 1.

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