JP2004040039A - Selecting method of exposing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a selecting method of an exposing method in which selection of an exposing technique corresponding to a real chip layout design is realized and required gate line width control is attained, when the exposing method is selected to perform pattern transfer for a mask pattern by the selected exposing method. <P>SOLUTION: The exposing method used when a pattern of 0.1μm of a line width is transferred to a resist film on a wafer is selected. First, in a step S<SB>1</SB>, a plurality of exposing methods are specified as candidates to be selected. For example, two exposing methods of a first exposing method using a half tone phase mask and a second exposing method using a Levenson phase mask are specified. In a step S<SB>2</SB>, an exposing condition for each exposing method selected in the step S<SB>1</SB>is set. In a step S<SB>3</SB>, an exposure simulation for using the first and second exposing methods is performed for all pattern of the mask patterns, to check the degree of a process margin (process tolerance). In a step S<SB>4</SB>, the exposing method including the exposing condition is decided based on the degree of the process tolerance. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an exposure method selection method, and more particularly, to an exposure method and an exposure condition capable of selecting an exposure method corresponding to an actual chip layout design and achieving required gate line width control.
[0002]
[Prior art]
A photomask used in a photolithography process in a semiconductor device manufacturing process has a structure in which a light-shielding film having a pattern opening is provided on a glass substrate.
In the process of manufacturing a semiconductor device, for example, when patterning a wiring layer, a resist film is formed on the wiring layer of the wafer, and then the resist film is projected and exposed through a photomask to provide a light-shielding film. The pattern opening is transferred onto the resist film and patterned to form an etching mask made of the resist film. Next, a predetermined wiring is formed by etching the wiring layer using an etching mask.
When manufacturing a photomask, CAD data of a design wiring pattern of a semiconductor device is converted into drawing data for a photomask drawing device, and a light mask is faithfully patterned based on the drawing data to form a photomask. .
[0003]
2. Description of the Related Art As the integration density and miniaturization of semiconductor devices increase, the line width of patterns has become finer. Therefore, in the photolithography process performed in the manufacturing process of the semiconductor device, as the line width of the pattern becomes smaller and approaches the vicinity of the exposure wavelength, the light interference effect becomes remarkable, and a difference occurs between the design pattern and the transfer resist pattern. The optical proximity effect is a problem.
The optical proximity effect is an effect that thin patterns and corners of the patterns become insufficiently exposed due to scattering of exposure light such as electron beams in the resist, resulting in poor dimensional accuracy and rounded corners of rectangular patterns. In addition, there is an effect that a portion outside the pattern is exposed by electrons or light scattered from the two patterns when the patterns are arranged close to each other, and the resist pattern is distorted.
In other words, the optical proximity effect appears as a phenomenon such as a line width difference between the isolated line and the repetition line, a line end shrinkage, and the like, resulting in deterioration of gate line width controllability and a decrease in alignment margin.
[0004]
In the etching process following the photolithography process, as in the photolithography process, the line width of the etching bottom differs due to the difference in the taper angle according to the distance between the patterns, and the phenomenon that the gate line width controllability deteriorates I do.
[0005]
As a result, variations in transistor characteristics are increased, and ultimately the chip yield and the speed yield are reduced, which has a significant adverse effect on the design margin for production efficiency and chip performance.
Since this problem has become remarkable in a 0.18 μm generation logic circuit chip that requires high integration, it is necessary to determine a space-dependent correction value for each pattern in advance and perform the correction over the entire chip. Therefore, it has been studied to improve the gate line width controllability. This is called Optical Proximity Effect Correction (OPC) or Process Proximity Effect Correction (PPC).
[0006]
From the 0.13 μm generation onwards, a model-based OPC method that predicts a two-dimensional pattern shape after pattern transfer and wiring layer etching by a sampling function, and performs high-speed correction calculation in which the predicted shape matches the design pattern as much as possible. Has been generally applied.
As confirmation of the correction accuracy of the optical proximity effect correction by the OPC / PPC, a corrected EPE (Edge Placement Error) is simulated at a gate line width measurement position of a desired pattern, for example, at an edge portion, and the corrected EPE of the entire chip It is possible to identify a place where is extremely large or to verify the distribution of EPE. However, in that case, it is important to sufficiently check the reliability of the sampling and the simulation itself.
[0007]
[Problems to be solved by the invention]
Although OPC / PPC is a technique for matching the optimum exposure amount for each pattern, it cannot improve the process margin itself.
As a technique for improving the process margin, there is a super-resolution exposure technique using deformed illumination or diffracted light interference by spatial frequency modulation.
The super-resolution exposure technology is a lithography technology corresponding to a design rule that is equal to or smaller than the exposure wavelength, and, of course, must be effective in all desired pattern formations on an actual high-integrated device circuit layout. In addition, the combination with the optimal exposure amount matching by OPC / PPC is also important.
[0008]
Until now, however, process design for super-resolution exposure technology has mainly been performed only with a simple lithography performance monitor, and verification has been performed by printing it on an actual chip.If a problem actually occurs, the process design has to be repeated from the beginning. Was. This is not enough to support process design.
As a result, the actual chip prototype TAT has been lengthened, the chip shipment time has been delayed, and business opportunities have been missed.
[0009]
Therefore, an object of the present invention is to select an exposure method, and when performing pattern transfer of a mask pattern by the selected exposure method, it is possible to select an exposure technique corresponding to an actual chip layout design, and to control gate line width required. Is to provide a method of selecting an exposure method that can achieve the following.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the inventor first performed a half-width simulation of a line width of 0.15 μm and a gate length variation of 0.10 μm on a real layout chip (7.5 million gates) as described below. We conducted the tone phase shift method and the Levenson phase shift method, and studied the change in process margin depending on the type of exposure method and exposure conditions.
With reference to FIGS. 2 to 4, the relationship between the gate length variation simulation on the actual layout chip (7.5 million gates) and the process margin will be described.
[0011]
FIGS. 2A and 2B are KrF scanners using a halftone phase shift mask with NA = 0.60, σ _in = 0.375 / σ _out = 0.75, and 6% transmittance, respectively. This is a simulation result on an actual chip layout when a pattern having a line width of 0.15 μm is transferred, and proximity effect correction is performed by OPC using a 2.5 nm correction grid.
FIG. 2A is a graph showing the relationship between the EPE (nm) when focused and the standard deviation (%), while FIG. 2B is the EPE (nm) when the focus range is 0.10 μm. 4 is a graph showing the relationship between the standard deviation (%).
[0012]
FIGS. 3A and 3B are KrF scanners using a halftone phase shift mask with NA = 0.60, σ _in = 0.375 / σ _out = 0.75, and 6% transmittance. This is a simulation result on a real chip layout when a pattern having a line width of 0.10 μm is transferred, and proximity effect correction is performed by OPC of a 2.5 nm correction grid.
FIG. 3A is a graph showing the relationship between the EPE (nm) and the standard deviation (%) when focused, and FIG. 2B is a graph showing the relationship between the EPE (nm) when the focus range is 0.10 μm. It is a graph which shows a relationship with a standard deviation (%).
[0013]
FIGS. 4A and 4B show the actual chip layout when a pattern having a line width of 0.10 μm is transferred by the Levenson phase shift method with NA = 0.53 and σ = 0.75 using a KrF scanner, respectively. This is a simulation result, and proximity effect correction is performed by OPC of a 2.5 nm correction grid.
FIG. 4A is a graph showing the relationship between the EPE (nm) and the standard deviation (%) when focusing, and FIG. 4B is a graph showing the relationship between the EPE (nm) and the standard when the focus range is 0.10 μm. It is a graph which shows a relationship with a deviation (%).
[0014]
When comparing FIGS. 2A and 2B with FIGS. 3A and 3B, FIG. 3 shows that, compared to FIG. 2, the standard deviation in the variation distribution taking into account the in-shot variation is larger. Understand. In particular, the EPE (nm) when the focus range is 0.10 μm is large over a wide range.
This is the result of using a halftone phase shift mask with NA = 0.60, σ _in = 0.375 / σ _out = 0.75, and 6% transmittance _in the KrF scanner, and the focus range is 0.1 μm. In the pattern transfer with a line width of 0.15 μm under the process conditions described above, there is no change in the standard deviation of the variation on the actual layout chip. However, in the pattern transfer with a line width of 0.10 μm, the variation on the actual layout chip does not. The standard deviation increases, indicating that there is a problem in the process design using the actual layout chip.
[0015]
On the other hand, as can be seen from FIGS. 5A and 5B, when the variation when the focus range on the actual chip layout by the Levenson phase shift method is 0.10 μm is simulated on the actual layout chip, the variation is shown. It can be seen that it is suppressed within ± 5 nm, and the increase in variation is hardly evident.
From this simulation result, it is understood that the Levenson phase shift method is effective for pattern transfer with a line width of 0.10 μm in order to satisfy the requirement of the process margin on the actual layout chip.
[0016]
In order to achieve the above object, based on the above findings, the method for selecting an exposure method according to the present invention, when selecting an exposure method, when performing a pattern transfer of a mask pattern by the selected exposure method,
Select at least a part of patterns of various shapes provided as a mask pattern,
An exposure simulation in which the space dependence of the pattern and the exposure process conditions are fitted is performed on all of the selected patterns, and the magnitude of the process margin (process margin) is calculated for each exposure method.
The exposure method and the exposure parameter are determined according to the magnitude of the process margin obtained by the calculation.
[0017]
In the method of the present invention, at least a part of patterns having various shapes provided as mask patterns is selected, for example, 70% or 80% is selected, and exposure simulation is performed on all of the selected patterns. And the process margin is determined, and the exposure method and exposure conditions are selected according to the magnitude of the process margin, so that the exposure method corresponding to the actual chip layout design can be selected, and the required gate line width control can be performed. Can be achieved.
In the method of the present invention, the fitting of "exposure simulation in which the space dependence of the pattern and the exposure process conditions are fitted" means that coefficient values in a multidimensional multiple function are determined from experimental values to enable a desired simulation. Say
[0018]
It is naturally preferable that the exposure simulation is performed for all of the patterns.
That is, in a preferred embodiment of the method of the present invention, all of the patterns of various shapes provided as mask patterns are selected, and an exposure simulation in which the space dependency of the pattern and the exposure process conditions are fitted is performed on all of the patterns. Do it.
[0019]
Specifically, the method of the present invention comprises the steps of: identifying a plurality of exposure methods as candidates to be selected;
Setting exposure conditions for each selected exposure method;
Performing an exposure simulation by each exposure method on all of the patterns of the mask pattern under the set exposure conditions, and confirming a magnitude of a process margin (process margin);
Determining the exposure method including the exposure conditions according to the magnitude of the process latitude.
[0020]
In the method of the present invention, since the exposure method is determined including the exposure conditions according to the process margin, it is possible to select the exposure technique corresponding to the actual chip layout design, and to achieve the required gate line width control. Further, it becomes possible to design a chip in consideration of both the design margin and the process margin.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings by way of example embodiments.
Embodiment Example This embodiment is an example of an embodiment of a method of selecting an exposure method according to the present invention, and FIG. 1 is a flowchart showing a procedure when applying the method of this embodiment. is there.
In the present embodiment, an exposure method for transferring a pattern having a line width of 0.1 μm to a resist film on a wafer is selected.
First, as shown in FIG. 1, in step S _1, identifies a plurality of candidates for the exposure method as the exposure method of choice. In the present embodiment, two exposure methods, for example, a first exposure method using a halftone phase mask and a second exposure method using a Levenson phase mask are specified.
[0022]
Then, in step S _2, sets the exposure conditions for each exposure method selected in step S _1. In this embodiment, a halftone phase shift mask having NA = 0.60, σ _in = 0.375 / σ _out = 0.75, and 6% transmittance with a KrF scanner as exposure conditions of the first exposure method. Is used. Further, as an exposure condition of the second exposure method, a Levenson phase shift mask is used with a KrF scanner at NA = 0.53 and σ = 0.75.
[0023]
Then, in step S _3, and an exposure simulation when using the first and second exposure method for all patterns of the mask pattern, to check the magnitude of the process margin (process tolerance). In the present embodiment, the results are as shown in FIGS.
[0024]
Subsequently, in step S _4, the magnitude of the process tolerance, for determining the exposure method including the exposure conditions.
In the present embodiment, the second exposure method is selected. As can be seen from a comparison between FIG. 3 and FIG. 4, when the variation when the focus range on the real chip layout using the Levenson phase shift mask is 0.10 μm is simulated on the real layout chip, the variation is obtained. Is found to be kept within ± 5 nm, and the increase in variation hardly appears.
[0025]
【The invention's effect】
According to the method of the present invention, at least a part, and preferably all, of patterns having various shapes provided as mask patterns are selected, and an exposure simulation in which the space dependency of the turn and the exposure process conditions are fitted is selected. The process is performed for all the patterns, and the magnitude of the process margin (process margin) is calculated for each exposure method, and the exposure method and the exposure parameters are determined according to the magnitude of the process margin obtained by the calculation.
As a result, it is possible to select an exposure technique corresponding to an actual chip layout design, and to achieve required gate line width control. In addition, it is possible to design a chip in consideration of both the design margin and the process margin, and it is possible to supply a chip that satisfies the customer sufficiently. Further, the optical proximity effect correction accuracy and the process proximity effect correction accuracy can be clarified, and the specifications relating to the wafer dimensional controllability can be clarified, so that unnecessary man-hours required for trial production can be reduced.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a procedure of a method of selecting an exposure method according to an embodiment.
FIGS. 2 (a) and (b) are halftone phase shifts of NA = 0.60, σ _in = 0.375 / σ _out = 0.75, 6% transmittance with a KrF scanner, respectively. It is a simulation result on an actual chip layout when a pattern having a line width of 0.15 μm is transferred using a mask.
FIGS. 3 (a) and (b) are halftone phase shifts of NA = 0.60, σ _in = 0.375 / σ _out = 0.75, 6% transmittance with a KrF scanner, respectively. It is a simulation result on an actual chip layout when a pattern having a line width of 0.10 μm is transferred using a mask.
FIGS. 4 (a) and 4 (b) show actual results when a pattern having a line width of 0.10 μm is transferred by a Levenson phase shift method using a KrF scanner at NA = 0.53 and σ = 0.75, respectively. It is a simulation result on a chip layout.

Claims (3)

Select the exposure method, when performing the pattern transfer of the mask pattern by the selected exposure method,
Select at least a part of patterns of various shapes provided as a mask pattern,
An exposure simulation in which the space dependency of the pattern and the exposure process conditions are fitted is performed on all of the selected patterns, and the magnitude of a process margin (process margin) is calculated for each exposure method.
A method of selecting an exposure method, wherein an exposure method and an exposure parameter are determined according to the magnitude of the process margin obtained by the calculation. An exposure simulation in which all of the patterns of various shapes provided as the mask pattern are selected and the space dependency of the pattern and an exposure process condition are fitted is performed on all of the patterns. Item 1. A method for selecting an exposure method according to Item 1. Identifying a plurality of exposure methods as candidates to be selected;
Setting exposure conditions for each of the selected exposure methods,
Performing an exposure simulation by each exposure method on all of the mask patterns under the set exposure conditions, and confirming the magnitude of the process margin (process margin);
3. The method according to claim 2, further comprising: determining an exposure method including an exposure condition according to the magnitude of the process latitude.

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