JP2007041811A - Information processing system, information processor and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing system with which processing can be efficiently achieved. <P>SOLUTION: This information processing system is provided with a first external memory control means 130 to which addresses on a first address space are assigned for controlling first external memories 140 to 143, a first buffer memory 124 to which an address on a second address space is assigned and a first transfer permitting means 123 for, when it is determined that a command address on the first address designated by the command is included in a first address range corresponding to the first external memories 140 to 143, permitting the transfer of data from the first external memories 140 to 143 to the first buffer memory 124. When the transfer of data is permitted, the external memory control means 130 reads the data corresponding to the command address from the first external memories 140 to 143, and stores the read data in a first buffer memory 124. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing system including a computing means and a memory bus composed of a plurality of channels, an information processing apparatus connected to the computing means via a memory bus composed of a plurality of channels, and an information processing method. It is.

  Conventionally, DIMMnet-2 (for example, refer to “Non-patent Document 1”), an information processing device (for example, refer to “Patent Document 1”) attached to a memory bus or a memory slot, is one main information processing device (master device). On the other hand, it was assumed to operate independently. For example, Patent Document 1 discloses a network interface device equipped with a memory bus. One apparatus is mounted on one CPU.

JP 2004-272576 A Tanabe, Ando, Hakozaki, Toi, Nakajo, Amano: Acceleration of indirect referencing on a PC using a memory module with a preload function, IPSIS 2005, ISSN-1344-0640, pp. 17-24 (May 2005)

  However, when an information processing device such as the above-mentioned DIMMnet-2 is simply mounted on a master device having a dual-channel memory bus that has become widespread in recent years, there is a drawback that it can only operate as a single-channel memory bus.

  Therefore, the master device having a dual channel memory bus has a problem that the processing efficiency cannot be improved.

  The present invention has been made in view of the above, and provides an information processing system capable of efficiently performing processing even when mounted on a master device having a dual channel memory bus. Objective.

  In order to solve the above-described problems and achieve the object, the present invention provides a computing means, a memory bus composed of a plurality of channels, and a first information processing apparatus and a second information processing apparatus connected to the memory bus. The first information processing apparatus is a memory to which an address in a first address space is assigned, and a memory for storing information used by the computing means. A first external memory control means for controlling the first external memory and an address on the second address space used by the calculation means are allocated, and data read from the first external memory is temporarily held. A first buffer memory and a command issued by the arithmetic means are acquired via the memory bus, and the first address space designated in the command is acquired. First address range determining means for determining whether or not the command address is included in the first address range corresponding to the first external memory, and the command address is determined by the first address range determining means to be in the first address range. And a first transfer permission means for permitting transfer of data from the first external memory to the first buffer memory when it is determined that the first external memory control means includes the first external memory control means. When transfer of the data is permitted by one transfer permission means, data corresponding to the command address is read from the first external memory, the read data is stored in the first buffer memory, and the second information processing apparatus Is a memory assigned an address in the first address space, and stores information used by the computing means A second external memory control means for controlling a second external memory, which is a memory to be stored, and a second external memory controller which is assigned an address on the second address space and temporarily holds data read from the second external memory The buffer memory and the command issued by the computing means are acquired via the memory bus, and the command address in the first address space designated in the command corresponds to the second external memory. A second address range determining unit that determines whether or not the address range is included, and the second external address range when the command address is determined to be included in the second address range by the second address range determining unit. Second transfer permission means for permitting transfer of data from the memory to the second buffer memory, and the second external memory control means Reads data corresponding to the command address from the second external memory and stores the read data in the second buffer memory when transfer of the data is permitted by the second transfer permission means. And

  According to another aspect of the present invention, there is provided an information processing apparatus connected to an arithmetic means via a memory bus composed of a plurality of channels, wherein the memory is assigned an address on a first address space, An external memory control means for controlling an external memory which is a memory for storing information used by the computing means, and an address on the second address space used by the computing means are assigned and read from the external memory A buffer memory that temporarily holds data and a command issued by the arithmetic means are acquired via the memory bus, and a command address in the first address space specified in the command corresponds to the external memory Address range determination means for determining whether or not the address range is included, and the address range determination means Transfer permission means for permitting transfer of data from the external memory to the buffer memory when it is determined that a command address is included in the address range, and the external memory control means includes: When the transfer of the data is permitted, the data corresponding to the command address is read from the external memory, and the read data is stored in the buffer memory.

  According to another aspect of the present invention, there is provided an information processing system including a calculation unit and a memory bus composed of a plurality of channels, wherein the second address is connected to the memory bus and used by the calculation unit. A first memory bus interface having a first buffer memory which is assigned an address on the space and temporarily holds data read from the external memory; and an address on the second address space is assigned to the external memory A second memory bus interface having a second buffer memory for temporarily holding data read from the memory; and an address on the first address space connected to the first memory bus interface and the second memory bus interface Is stored in the external memory and used by the computing means Read data from the external memory, characterized by comprising an external memory control means for storing the data to the first buffer memory and the second buffer memory.

  According to another aspect of the present invention, there is provided an information processing method in an information processing system including a calculation unit and a memory bus composed of a plurality of channels, wherein a command issued by the calculation unit is transmitted to the memory bus. And a command address on the first address space designated in the command is a memory to which an address on the first address space is assigned, and is used by the computing means. A first address range determining step for determining whether or not the first address range corresponding to a first external memory, which is a memory for storing information, and the command address in the first address range determining step; When it is determined to be included in the address range, it is used by the calculation means from the first external memory. A first buffer memory to which an address in a two-address space is assigned, wherein the first buffer memory permits the transfer of data to the first buffer memory that temporarily holds data read from the first external memory When transfer of the data is permitted in the transfer permission step and the first transfer permission step, the data corresponding to the command address is read from the first external memory, and the read data is stored in the first buffer memory A first external memory control step; a second acquisition step of acquiring the command issued by the computing means via the memory bus; and the command address specified in the command is stored on the first address space. An address-assigned memory that stores information used by the computing means A second address determination step for determining whether or not the second address range corresponding to the second memory, which is a storage memory, and the command address is included in the second address range in the second address range determination step A second buffer memory to which an address in the second address space is assigned from the second external memory, the data read from the second external memory is temporarily stored A second transfer permission step for permitting the transfer of data to the second buffer memory to be held; and when the transfer of the data is permitted in the second transfer permission step, the second external memory to the command address Second external memory control step for reading data and storing the read data in the second buffer memory It is characterized by having.

  According to another aspect of the present invention, there is provided an information processing method in an information processing apparatus connected to a calculation means via a memory bus composed of a plurality of channels, wherein a command issued by the calculation means is transmitted via the memory An acquisition step to acquire the information, and a command address in the first address space designated in the command is a memory to which an address in the first address space is assigned, and stores information used by the computing means An address range determination step for determining whether the command address is included in the address range in the address range determination step, and an address range determination step for determining whether the command address is included in the address range. A buffer memory to which an address in the second address space is allocated from the memory. A transfer permission step for permitting transfer of data to a buffer memory that temporarily holds data read from the external memory, and when the transfer of the data is permitted in the transfer permission step, A buffer memory from which data corresponding to the command address can be read from a memory, and the arithmetic means can read data by designating an address in the address space, and is mapped to an address space used by the arithmetic means And an external memory control step for storing the read data in the buffer memory that temporarily holds the information read from the external memory.

  According to another aspect of the present invention, there is provided an information processing method in an information processing system including a calculation unit and a memory bus composed of a plurality of channels. The information processing method is connected to the memory bus and used by the calculation unit. A first memory bus interface having a first buffer memory for temporarily storing data read from the external memory and an address on the second address space. The external memory connected to a second memory bus interface having a second buffer memory for temporarily holding data read from the external memory and assigned an address on a first address space, And external memory control connected to the external memory for storing information used by the computing means A stage that reads data from the external memory and stores the data in the first buffer memory and the second buffer memory; and the computing means includes the first buffer memory and the second buffer in the storage step. And a reading step of reading data stored in the buffer memory.

  According to the information processing system of the present invention, when the command address specified by the command issued by the computing unit is determined to be included in the first address range by the first address range determining unit, the first external memory When the data read from the second external memory is transferred to the first buffer memory and the command address is determined to be included in the second address range by the second address range determination means, the data read from the second external memory is Since the data is transferred to the second buffer memory, the calculation means can acquire the data stored in the first buffer memory and the second buffer memory. As described above, the arithmetic means can access the first external memory and the second external memory by issuing one command even when it is mounted on a master device having a dual channel memory bus. There is an effect that processing can be performed efficiently.

  Hereinafter, embodiments of an information processing system, an information processing apparatus, and an information processing method according to the present invention will be described in detail based on the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a diagram showing the overall configuration of the information processing system 1. The information processing system 1 includes a CPU 11, a north bridge 12, a south bridge 13, a first main memory 14, a second main memory 15, a first memory bus 16, a second memory bus 17, and a first memory. A module 100 and a second memory module 200 are provided.

  The first memory module 100 includes a first information processing device 150 and a plurality of first external memories 140 to 143. The first information processing apparatus 150 includes a first network control unit 110, a first memory bus interface 120, and a first external memory control unit 130. The first memory bus interface 120 includes a first address generation unit 121, a first address range determination unit 122, a first transfer permission unit 123, and a first buffer memory 124.

  The second memory module 200 includes a second information processing device 250 and a plurality of second external memories 240 to 243. The second information processing apparatus 250 includes a second network control unit 210, a second memory bus interface 220, and a second external memory control unit 230. The second memory bus interface 220 includes a second address generation unit 221, a second address range determination unit 222, a second transfer permission unit 223, and a second buffer memory 224.

  Each part of the first information processing apparatus is provided on one electronic circuit board. The second information processing apparatus is provided on an electronic circuit board different from the electronic circuit board of the first information processing apparatus.

  The CPU 11 performs calculations using data in the first external memories 140 to 143 and the second external memories 240 to 243. The north bridge 12 and the south bridge 13 mediate between the CPU 11 and other devices. A first memory bus 16 and a second memory bus 17 are connected to the north bridge 12. The first main memory 14 and the first memory module 100 are connected to the first memory bus 16. The second main memory 15 and the second memory module 200 are connected to the second memory bus 17. The north bridge 12 directly accesses the first main memory 14 and the first memory module 100 via the first memory bus 16. The north bridge 12 also directly accesses the second main memory 15 and the second memory module 200 via the second memory bus 17.

  Next, the configuration and processing of the first memory module 100 will be described. The configuration and processing of each unit of the second memory module 200 are the same as the configuration and processing of each corresponding unit of the first memory module 100.

  The first external memories 140 to 143 of the first memory module 100 store data used by the CPU 11. The first information processing apparatus 150 controls access to the first external memories 140 to 143 and the network. The first memory bus interface 120 of the first information processing device 150 manages data to be sent to the first memory bus 16.

  The first address generation unit 121 of the first memory bus interface 120 acquires a preload command from the CPU 11 via the first memory bus 16. Here, preloading means that data corresponding to the maximum data capacity of the buffer memory 122 is stored in the buffer memory 122. For example, when the buffer memory 122 has a 64-bit capacity, it is determined that preloading is completed when 64-bit data is stored.

  When acquiring the preload command, the first address generation unit 121 generates a command address sequence that is an array of command addresses indicating the address of data specified in the preload command, based on the preload command. Here, the command address is an address on the I / O space that can be accessed by the first external memory control unit 130 of the first memory module 100. The first external memories 140 to 143 are mapped in the I / O space. The I / O space will be described later.

  The first address range determination unit 122 holds the first address range. Here, the first address range is an address range of the memory managed by the first memory module 100, that is, the first external memories 140 to 143. Then, the first address range determination unit 122 determines whether each command address included in the command address sequence generated by the first address generation unit 121 is an address within the first address range.

  The first transfer permission unit 123 permits access to the command address when the first address range determination unit 122 determines that the command address is an address within the first address range. When the transfer is permitted by the first transfer permission unit 123, the first external memory control unit 130 accesses the first external memories 140 to 143 specified by the command address based on the preload command.

  The first buffer memory 124 temporarily stores data read from the first external memories 140 to 143 by the first external memory control unit 130. When data of a predetermined size is stored in the first buffer memory 124, the data for that size, that is, in units of data blocks, is collectively transferred to the CPU 11 by read access from the CPU 11. Here, the size of the buffer memory 124 is preferably the line size of the lowest layer cache of the CPU.

  As described above, the first memory module 100 performs the process for the preload command only when the command address generated from the preload command is an address within the first address range, and thus the CPU 11 performs processing for the first external memories 140 to 143 and the first 2 Even when one preload command including access to both of the external memories 240 to 243 is issued, the first memory module 100 can only perform processing for the first external memories 140 to 143 managed by itself. it can.

  As described above, the first memory module 100 and the second memory module 200 are in charge of only processing for the addresses of the external memories 140 to 143 and 240 to 243 managed by the CPU 11 among the preload commands issued by the CPU 11. That is, the first memory bus interface 120 and the second memory bus interface 220 perform processing in cooperation.

  FIG. 2 is a diagram for explaining processing of the first external memory control unit 130. The first external memories 140 to 143 are mapped to a huge address space such as an I / O space. The first external memory control unit 130 sequentially accesses a plurality of data existing in discontinuous areas in the I / O space by the command address generated by the first address generation unit 121, and stores the data in the order of access. The data is stored in the first buffer memory 124. As shown in FIG. 2, when the first buffer memory 124 has a 64-bit size, for example, 64-bit data is stored in the order of command addresses.

  As described above, the first external memory control unit 130 reads predetermined data by the command address generated from the preload command issued by the CPU 11 and writes it in the first buffer memory 124.

  The first external memory control unit 130 accesses the first external memories 140 to 143 in units of data, and writes necessary data in the first buffer memory 124. When data corresponding to the size of the first buffer memory 124 is stored, the data stored in the first buffer memory 124 is transferred to the CPU 11 in response to a read request from the CPU 11. At this time, the data in the first buffer memory 124 is batch transferred in units of data corresponding to the size of the first buffer memory 124, that is, data blocks.

  When the CPU 11 reads data via the first memory bus 16 in units of cache lines, necessary data may be stored only in a part of one cache line. However, even in this case, the entire cache line must be read. For this reason, transfer in units of cache lines is inefficient.

  On the other hand, the information processing system 1 according to the present embodiment transfers the data in the first buffer memory 124 in units of data blocks after the preload is completed in the first buffer memory 124, so that only necessary data is the first data. It is sent to the memory bus 16. Therefore, transfer efficiency can be improved.

  FIG. 3 is a diagram for explaining a CPU address space accessed by the CPU 11. As shown in FIG. 3, in the CPU address space, a 128-bit address range is assigned to the first buffer memory 124 and the second buffer memory 224. The upper 4 bits of the addresses assigned to the first buffer memory 124 and the second buffer memory 224 are the same. The first buffer memory 124 and the second buffer memory 224 are identified in the lower 4 bits. Specifically, the first buffer memory 124 is assigned to the address area 0-7 determined by the lower 4 bits, and the second buffer memory 224 is assigned to the address area 8-15. As described above, the first buffer memory 124 and the second buffer memory 224 are mapped to continuous areas on the CPU address space.

  The CPU 11 can access data stored in the first buffer memory 124 and the second buffer memory 224 mapped on the CPU address space. Incidentally, the first external memories 140 to 143 and the second external memories 240 to 243 are mapped to the I / O space, but are not mapped to the CPU address space. Since the upper limit of the 32-bit CPU 11 is 4 GB, the entire capacity of the 8 GB external memories 140 to 143 and the external memories 240 to 243 cannot be mapped as the main memory on the CPU address space accessible from the CPU 11 directly. is there. Therefore, the CPU 11 cannot directly access the first external memories 140 to 143 and the second external memories 240 to 243.

  That is, for example, in order to acquire data stored in the first external memories 140 to 143, the CPU 11 first writes data from the first external memories 140 to 143 to the first buffer memory 124 by a preload command. Then, after data corresponding to the data size of the first buffer memory 124 is stored, read access is performed, and data is acquired from the first buffer memory 124 in units of data blocks. As described above, the CPU 11 obtains data of the first external memories 140 to 143 indirectly from the first buffer memory 124.

  The timing specifications of the first memory module 100 connected to the first memory bus 16 and the second memory module 200 connected to the second memory bus 17 are set to be the same.

  For example, assume that the first memory bus 16 and the second memory bus 17 each have a data width of 64 bits. At this time, the north bridge 12 sets the two memory buses 16 and 17 to operate in the dual channel lock step mode via the BIOS. In this case, the two memory buses 16 and 17 operate as if they were one 128-bit memory bus for the CPU 11.

  If different timing specifications are set for the first memory module 100 and the second memory module 200, the two memory buses 16 and 17 operate as if they were one 64-bit memory bus for the CPU 11. That is, the processing efficiency is lower than when the timing specifications are the same. That is, when the timing specifications are the same, the processing efficiency can be improved as compared with the case where the timing specifications are different.

  Here, the timing specifications are, for example, timing specifications such as capacity written in an SPD (Serial Presence Detect) ROM and CAD latency. That is, the same timing specification means that the memory capacity and timing are the same when viewed from the north bridge side.

  As described above, since the first memory module 100 and the second memory module 200 have the same timing specifications, it is possible to operate in the dual channel lock step mode. This makes it possible to supply the CPU with a bandwidth twice that of the 64-bit width memory bus. Therefore, it is possible to prevent a decrease in processing speed of a program that operates only with the main memory.

  The first network control unit 110 of the first memory module 100 accesses the first external memories 140 to 143 to read / write data related to transmission / reception. Further, the CPU 11 reads / writes control data from / to the first network control unit 110, so that the first network control unit 110 executes communication instructed by the CPU 11 while accessing the first external memories 140-143. By doing so, it functions as a network interface.

  FIG. 4 is a flowchart showing preload processing by the information processing system 1. In the preload process, the preload command issued by the CPU 11 is transferred to the first memory module 100 and the second memory module 200. The processing of the first memory module 100 and the second memory module 200 after acquiring the preload command is the same. Therefore, here, the processing of the first memory module 100 will be described. A case where a vector load command is issued as a preload command will be described.

  When the vector load command is issued by the CPU 11 (step S100), the vector load command is transferred to the first memory module 100 via the north bridge 12 and the first memory bus 16 (step 102).

  In the first memory module 100, a vector load command is activated, and a command address to be accessed in the vector load command is generated. The first address range determination unit 122 of the first memory bus interface 120 determines whether or not the command address generated from the vector load command is an address within the first address range.

  When it is determined that the command address is an address within the first address range (step S110, Yes), the first transfer permission unit 123 permits data transfer for the command address (step S112). Then, the first external memory control unit 130 reads data from the area specified by the command address in the first external memories 140 to 143, and stores the data in the first buffer memory 124 (step S114). At this time, the first external memory control unit 130 arranges corresponding data in the first buffer memory 124 in the order of command addresses.

  On the other hand, if it is determined in step S110 that the command address is not within the first address range (step S110, No), the first transfer permission unit 123 prohibits data transfer for the command address.

  Since the vector load command issued by the CPU 11 includes access to the second external memories 240 to 243, a command address corresponding to the second external memories 240 to 243 is included. In the case of such a command address, it is determined that the address is not within the first address range. In this case, since the corresponding data is not stored in the first external memories 140 to 143 managed by the device, data transfer processing is not performed.

  The first memory module 100 performs the above processing for all command addresses generated from the vector load command.

  On the other hand, the CPU 11 monitors whether or not preloading is completed in the first buffer memory 124 of the first memory bus interface 120 (step S120). If the CPU 11 determines that preloading is complete (step S122, Yes), it issues a read command (step S124).

  Specifically, a flag is provided for each partial data block (for example, 8 bytes) in the first buffer memory 124. This flag indicates whether or not preloading has been completed. By reading this flag, the CPU 11 monitors whether or not preloading of each data block is completed, that is, whether or not data is stored in the data block.

  When it is confirmed that the value indicates completion of preloading, an actual read command is issued to obtain a corresponding data block. By monitoring the completion of the preload in this way, it is possible to prevent a read command from being issued before the preload is completed. That is, even when the preload completion is delayed, it can be flexibly dealt with.

  In this case, the first buffer memory 124 is preferably mounted with a flag, for example, by a register disposed at a close position on the first memory bus interface 120 so that the CPU 11 can read the flag. Furthermore, it is preferable that a plurality of (for example, 64 bits) flag states can be acquired by one read access.

  As described above, the CPU 11 issues a read command (step S124), and transfers the read command to the first memory module 100 via the north bridge 12 and the first memory bus 16 (step S126). When acquiring the read command, the first memory module 100 returns data corresponding to the read command to the CPU 11 (step S1128). That is, the data stored in the first buffer memory 124 is transferred to the CPU 11. Thus, the preload process in the information processing system 1 is completed.

  In the data block acquired by the CPU 11, data of addresses corresponding to the first external memories 140 to 143 among the command addresses generated from the vector load command are arranged in the order of the command addresses in the vector load command. That is, the CPU 11 can acquire data corresponding to the first external memories 140 to 143 in the order of command addresses.

  FIG. 5 is a diagram schematically illustrating an example of continuous command addresses generated from the vector load command issued by the CPU 11. The command addresses shown in FIG. 4 are the first external memory 140, the second external memory 240, the first external memory 141, the second external memory 241, the first external memory 142, the second external memory 242, the first external memory 143, and This is a continuous address for accessing the second external memory 243 in order.

  In the information processing system 1 according to the present embodiment, processing for one vector load command including access to the external memories 140 to 143 and 240 to 243 connected via the different memory buses 16 and 17 as described above. It can be performed. When the vector load command shown in FIG. 4 is issued, each of the first memory module 100 and the second memory module 200 performs only the processing for the external memory managed by itself.

  When the vector load command shown in FIG. 4 is acquired, the first memory module 100 accesses the first external memory 140, the first external memory 141, the first external memory 142, and the first external memory 143 in this order. The second memory module 200 accesses the second external memory 240, the second external memory 241, the second external memory 242, and the second external memory 243 in this order.

  As described above, the CPU 11 issues a vector load command including access to the first external memories 140 to 143 and the second external memories 240 to 243 once, thereby reading the data in the order corresponding to the access order. can do. Further, as described above, the two 64-bit memory buses 16 and 17 operate like one 128-bit memory bus.

  On the other hand, if the information processing system 1 according to the present embodiment does not have a function of determining the address range to be processed by each memory module, it is desired to acquire data in the order of command addresses as shown in FIG. In this case, it is necessary to issue a vector load command for each of the external memories 140 to 143 and 240 to 243. That is, it is necessary to issue the vector load command eight times. Accordingly, the processing efficiency is reduced. On the other hand, the information processing system 1 according to the present embodiment only needs to issue one vector load command, and the processing efficiency can be improved.

  As described above, the present invention has been described using the embodiment, but various changes or improvements can be added to the above embodiment.

(Embodiment 2)
FIG. 6 is a block diagram of an overall configuration of the information processing system 1 according to the second embodiment. In the information processing system 1 according to the second exemplary embodiment, the first network control unit 110 and the second network control unit 210 are connected by a cable 300.

  The cable 300 transfers the data of the first external memories 140 to 143 of the first memory module 100 and the data of the first memory bus interface 120 to the second memory module 200, and the second external memory 240 of the second memory module 200. The data of ˜243 and the data of the second memory bus interface 220 are transferred to the first memory module 100. As described above, the cable 300 performs remote data transfer between the first memory module 100 and the second memory module 200. As described above, the first network control unit 110 and the second network control unit 210 function as a first transfer unit and a second transfer unit, respectively.

  For example, when two 64-bit width memory buses 16 and 17 are set to operate in the dual channel lockstep mode, command addresses are allocated to the first memory bus 16 and the second memory bus 17 every 8 bytes. .

  Therefore, when the command address generated by the preload command issued by the CPU 11 is concentrated on only one of the first memory module 100 and the second memory module 200, the memory bus connected to the other is effective. It is not used, and the processing efficiency decreases.

  Therefore, in the information processing system 1 according to the second embodiment, for example, a command address generated by a preload command acquired by the first memory bus interface 120 is an address for the first external memories 140 to 143 in the first memory module 100. If it is not included in the range, that is, the first address range, the first network control unit 110 performs remote read access to the second external memories 240 to 243 via the cable 300 or the like, and sends a command to its own first buffer memory 124 The data for the address is loaded.

  Similarly, when the command address generated by the preload command acquired by the second memory bus interface 220 is not included in the address range for the second external memories 240 to 243 in the second memory module 200, that is, the second address range. The second network control unit 210 performs remote read access to the first external memories 140 to 143 via the cable 300 or the like, and loads data into its own second buffer memory 224.

  FIG. 7 is a flowchart of the preload process performed by the information processing system 1 according to the second embodiment. In the preload process, the preload command issued by the CPU 11 is transferred to the first memory module 100 and the second memory module 200. The processing of the first memory module 100 and the second memory module 200 after acquiring the preload command is the same. Therefore, here, the processing of the first memory module 100 will be described. A case where a vector load command is issued as a preload command will be described.

  In the second embodiment, when a vector load command is transferred as a preload command to the first memory module 100 (step S102), the vector load command is activated and a command address is generated. The first address range determination unit of the first memory bus interface 120 determines whether or not the command address is an address within the first address range.

  When it is determined that the command address is an address within the first address range (step S110, Yes), the first transfer permission unit 123 permits data transfer for the command address (step S112). Then, the process proceeds to step S114.

  On the other hand, if it is determined in step S110 that the command address is not within the first address range (step S110, No), the first network control unit 110 performs remote read access to the second external memories 240 to 243. Is performed (step S116).

  FIG. 8 is a flowchart showing detailed processing of the first memory module 100 and the second memory module 200 in the remote read access processing (step S116). In the remote read access process (step S116), first, in the first memory module 100, the first network control unit 110 issues an access request to the second external memories 240 to 243 via the cable 300, that is, a remote read access request. The data is sent to the second memory module 200 (step S140). Note that the remote read access request includes a command address.

  When the second network control unit 210 of the second memory module 200 acquires the remote read access request, the second external memory control unit 230 transmits data corresponding to the command address range included in the remote read access request to the second external memory 240. To 243 (step S142). Then, the second network control unit 210 transfers the data read from the second external memories 240 to 243 to the first memory module 100 via the cable 300 (step S144).

  When acquiring the data from the second memory module 200, the first network control unit 110 of the first memory module 100 stores the acquired data in the first buffer memory 124 (step S146). Thus, the remote read access process (step S116) is completed.

  As described above, in the information processing system 1 according to the second embodiment, when the first address range determination unit 122 determines that the command address range is not included in the first address range, the second external memories 240 to 243 are included. Since the data is accessed and the data is read, the processing efficiency can be improved.

  Further, the data read from the second external memories 240 to 243 is stored in the first buffer memory 124 in the order of command addresses in the vector load command. Therefore, since the CPU 11 can acquire data in the order of the vector load command, the data rearrangement operation becomes unnecessary. That is, processing efficiency can be improved.

  FIG. 9 is a diagram schematically illustrating an example of continuous command addresses generated from the vector load command issued by the CPU 11. The addresses shown in FIG. 9 are the first external memory 140, the first external memory 141, the first external memory 142, the first external memory 143, the second external memory 240, the second external memory 241, the second external memory 242, and This is a continuous address for accessing the second external memory 243 in order.

  In the command address shown in FIG. 9, the first four accesses out of the eight accesses are accesses to the first memory module 100, and the latter four accesses are accesses to the second memory module 200. . In the information processing system 1 according to the second exemplary embodiment, the first memory module 100 has an odd-numbered access out of such a total of eight accesses, that is, the first external memory 140, the first external memory 142, the second Access to the external memory 240 and the second external memory 242 is assigned.

  When the first memory module 100 starts a vector load command for the second external memories 240 and 242 that are not its own external memory, the first memory module 100 acquires corresponding data from the second memory module 200 via the first network control unit 110. And stored in the first buffer memory 124.

  The second memory module 200 is assigned even-numbered access among the eight accesses, that is, access to the first external memory 141, the first external memory 143, the second external memory 241, and the second external memory 243. Similarly to the first memory module 100, when a vector load command for the first external memories 141 and 143 that are not its own external memory is activated, the first memory module 100 responds via the second network control unit 210. Data is acquired and stored in the second buffer memory 224.

  As described above, even when access is concentrated on one of the first memory module 100 and the second memory module 200, the first memory bus 16 and the second memory bus 17 are used for the first memory module. Since the module 100 and the second memory module 200 process in cooperation, the processing efficiency can be improved.

  That is, for example, data is set to be loaded into the first buffer memory 124 of the first memory module 100 and the second buffer memory 224 of the second memory module 200 every 8 bytes, and remote read access to each other is possible. As a result, even when access is concentrated on one of the first memory module 100 and the second memory module 200, both the first memory module 100 and the second memory module 200 perform processing, thereby improving processing efficiency. Can be achieved.

  The remaining configuration and processing of the information processing system 1 according to the second embodiment are the same as the configuration and processing of the information processing system 1 according to the first embodiment.

  As described above, the present invention has been described using the embodiment, but various changes or improvements can be added to the above embodiment.

  As such a first modification, in the information processing system 1 according to the second embodiment, the first network control unit 110 and the second network control unit 210 perform data transfer via the cable 300, that is, the dedicated line. However, as another example, the first network control unit 110 and the second network control unit may perform data transfer via a network.

  FIG. 10 is a diagram illustrating an overall configuration of the information processing system 1 according to the second modification. The first memory bus interface 120 of the information processing system 1 according to the second modification example further includes a first buffer memory determination unit 126. The second memory bus interface 220 further includes a second buffer memory determination unit 226.

  The first buffer memory determination unit 126 of the first memory bus interface 120 determines which command address is allocated to itself. Similarly, the second buffer memory determination unit 226 of the memory bus interface 220 determines which command address is allocated to itself.

  When command addresses included in the command address string are allocated to the first memory bus 16 and the second memory bus 17 every 8 bytes, the command addresses allocated to the first memory bus 16, that is, the corresponding data are For a command address to be stored in one buffer memory 124, the first buffer memory determination unit 126 determines that the command address is to be processed by itself.

  If the first buffer memory determination unit 126 determines that the command address is not to be processed by itself, data is written to the second buffer memory 224 by remote writing.

  Further, the command address following the 8-byte command address determined by the first buffer memory determination unit 126 as the command address to be processed by itself is allocated to the second memory bus 17. This is a command address where the corresponding data is to be stored in the second buffer memory 224. Therefore, the second buffer memory determination unit 226 determines that the command address is to be processed by itself.

  When it is determined in the second buffer memory 226 that the command address is not to be processed, the second network control unit 210 writes data into the first buffer memory 114 by remote writing.

  As described above, the first buffer memory determination unit 126 and the second buffer memory determination unit 226 each process the command address included in the command address string alternately by a predetermined length unit such as 8 bytes. Judge as. That is, according to a predetermined condition, it is determined whether or not it is a command address to be processed.

(Embodiment 3)
FIG. 11 is a block diagram of an overall configuration of the information processing system 1 according to the third embodiment. The information processing system 1 according to the third embodiment includes a CPU 11, a north bridge 12, a south bridge 13, a first main memory 14, a second main memory 15, a first memory bus 16, and a second memory bus. 17, a first memory bus interface 120, a second memory bus interface, an external memory control unit 400, and eight external memories 421 to 428. The first memory bus interface 120, the second memory bus interface, and the external memory controller 400 are formed on separate electronic circuit boards.

  The first memory bus interface 120 has a first buffer memory 124. The second memory bus interface 220 has a second buffer memory 224. The external memory control unit 400 includes an address generation unit 410, a transfer control unit 412, and a buffer memory determination unit 414.

  When the address generation unit 410 acquires the preload command issued by the CPU 11 via the first memory bus interface 120, the address generation unit 410 generates an address based on the preload command.

  The transfer control unit 412 accesses the external memories 421 to 428 based on the address generated by the address generation unit 410. Then, the transfer control unit 412 stores the data acquired from the external memories 421 to 428 in the first buffer memory 124 of the first memory bus interface 120 or the second buffer memory 224 of the second memory bus interface.

  The buffer memory determination unit 414 designates the first buffer memory 124 or the second buffer memory 22 as a write destination to which the transfer control unit 412 should write data.

  In the CPU address space, as described with reference to FIG. 3 in the first embodiment, a 128-bit address range is allocated to the first buffer memory 124 and the second buffer memory 224. The first buffer memory 124 and the second buffer memory 224 are identified in the lower 4 bits. Specifically, the first buffer memory 124 is assigned to the address area 0-7 determined by the lower 4 bits, and the second buffer memory 224 is assigned to the address area 8-15.

  The transfer control unit 412 stores the data acquired from the external memories 421 to 428 in the order of the command address in the address of the lower bits in the order of the command address based on the designation of the buffer memory determination unit 414. That is, first, data is stored in the areas of the addresses 0 to 7 of the first buffer memory 124 in order, and when data corresponding to the data size of the first buffer memory 124 is stored, the address 8 of the second buffer memory 224 is then stored. Data is stored in the areas of -15 in order. As described above, the buffer memory determination unit 414 determines an area in which data is to be stored next in accordance with a predetermined condition according to the data storage state in the first buffer memory 124 and the second buffer memory 224.

  FIG. 12 is a flowchart of the preload process performed by the information processing system 1 according to the third embodiment. When the vector load command is issued by the CPU 11 (step S200), the vector load command is transferred to the external memory control unit 400 via the north bridge 12, the first memory bus 16, and the first memory bus interface 120 (step S200). 202).

  In external memory control unit 400, a vector load command is activated, and a command address to be accessed in the vector load command is generated (step S204). Next, the data transfer destination is determined (step S206). Specifically, it is designated in which of the first buffer memory 124 and the second buffer memory 224 the data acquired from the external memories 421 to 428 is stored.

  Then, the transfer control unit 412 stores the data read from the external memories 421 to 428 in the determined transfer destination (step S208). The above processing is performed for all command addresses generated from the vector load command.

  The CPU 11 monitors whether the preload is completed. If the CPU 11 determines that preloading is complete (step S210, Yes), it issues a read command (step S212). Specifically, the CPU 11 determines that the preload is completed when the preload in the first buffer memory 124 is completed and the preload in the second buffer memory 224 is completed.

  The read command is transferred to the first memory bus interface 120 and the second memory bus interface 220 (step S214). The first memory bus interface 120 transfers the data stored in the first buffer memory 124 in units of blocks. Similarly, the second memory bus interface 220 transfers the data stored in the second buffer memory 224 in units of blocks (step S216). Thus, the preload process in the information processing system 1 is completed.

  As described above, according to the information processing system 1 according to the third embodiment, the first memory bus interface 120, the second memory bus interface 220, and the external memory control unit 400 are formed on separate LSIs, respectively. The entire processing system 1 can be reduced in size. The external memory control unit 400 continuously stores data in the first buffer memory 124 and the second buffer memory 224 mapped to continuous address areas on the CPU 11 address space, and stores these data in units of data blocks. Since it can transfer to CPU11, transfer efficiency can be improved.

  The other configuration and processing of the information processing system 1 according to the third embodiment are the same as the configuration and processing of the information processing system 1 according to the other embodiments.

  As described above, the present invention has been described using the embodiment, but various changes or improvements can be added to the above embodiment.

1 is a diagram illustrating an overall configuration of an information processing system 1. FIG. It is a figure for demonstrating the process of the 1st external memory control part. It is a figure for demonstrating CPU address space which CPU11 accesses. 3 is a flowchart showing preload processing by the information processing system 1; It is a figure which shows typically an example of the continuous command address produced | generated from the vector load command issued in CPU11. It is a block diagram which shows the whole structure of the information processing system 1 concerning Embodiment 2. FIG. 6 is a flowchart showing preload processing by the information processing system 1 according to the second exemplary embodiment; It is a flowchart which shows the detailed process of the 1st memory module 100 and the 2nd memory module 200 in a remote read access process (step S116). It is a figure which shows typically an example of the continuous command address produced | generated from the vector load command issued in CPU11. It is a block diagram which shows the whole structure of the information processing system 1 concerning the 2nd modification of Embodiment 2. FIG. FIG. 4 is a block diagram showing an overall configuration of an information processing system 1 according to a third embodiment. 10 is a flowchart showing preload processing by the information processing system 1 according to the third exemplary embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing system 12 North bridge 13 South bridge 14 1st main memory 15 2nd main memory 16 1st memory bus 17 2nd memory bus 100 1st memory module 110 1st network control part 120 1st memory bus interface 121 1st Address generation unit 122 First address range determination unit 123 First transfer permission unit 124 First buffer memory 130 First external memory control unit 140 to 143 First external memory 150 First information processing device 200 Second memory module 210 Second network Control unit 220 Second memory bus interface 221 Second address generation unit 222 Second address range determination unit 223 Second transfer permission unit 224 Second buffer memory 230 Second external memory control unit 240 to 243 Second external memory control unit 250 The information processing apparatus 300 cable 400 external memory control unit 410 address generator 412 transfers the control unit 414 the buffer memory judging unit 421 to 428 external memory

Claims (23)

An information processing system comprising a computing means, a memory bus composed of a plurality of channels, and a first information processing device and a second information processing device connected to the memory bus,
The first information processing apparatus
First external memory control means for controlling a first external memory, which is a memory to which an address in a first address space is assigned and which stores information used by the computing means;
A first buffer memory which is assigned an address on a second address space used by the arithmetic means and temporarily holds data read from the first external memory;
Whether the command issued by the computing means is acquired via the memory bus, and the command address in the first address space specified in the command is included in the first address range corresponding to the first external memory First address range determination means for determining whether or not,
A first transfer permission for permitting transfer of data from the first external memory to the first buffer memory when the first address range determining means determines that the command address is included in the first address range; Means,
The first external memory control means reads data corresponding to the command address from the first external memory when transfer of the data is permitted by the first transfer permission means, and reads the read data to the first buffer. Store it in memory,
The second information processing apparatus
Second external memory control means for controlling a second external memory which is a memory to which an address in the first address space is assigned and which stores information used by the computing means;
A second buffer memory which is assigned an address on the second address space and temporarily holds data read from the second external memory;
The command issued by the computing means is acquired via the memory bus, and the command address on the first address space specified in the command is included in a second address range corresponding to the second external memory. Second address range determination means for determining whether or not
A second transfer permission for permitting data transfer from the second external memory to the second buffer memory when the second address range determining means determines that the command address is included in the second address range; Means,
The second external memory control means reads data corresponding to the command address from the second external memory when transfer of the data is permitted by the second transfer permission means, and reads the read data to the second buffer. An information processing system characterized by being stored in a memory.   The arithmetic means designates an address on the second address space, and reads the data stored in the first buffer memory and the data stored in the second buffer memory. The information processing system according to claim 1.   3. The information processing system according to claim 1, wherein timings when the first information processing apparatus and the second information processing apparatus are accessed from the arithmetic unit are the same. 4. The first external memory control means generates a command address string on the first address space by the command issued by the arithmetic means,
In the first information processing apparatus, a data write destination corresponding to each command address included in the command address sequence generated by the first external memory control means is based on a predetermined condition. And first buffer memory determining means for determining which of the second buffer memory and the second buffer memory,
The first external memory control means writes data corresponding to the command address determined by the first buffer memory determination means to be data write destination to the first buffer memory. The information processing system according to any one of claims 1 to 3.   The first buffer memory determining means selects a command address arranged in a predetermined order in the address string as a command address corresponding to the data to be written to the first buffer memory. The information processing system according to claim 4. The command address determined by the first buffer memory determining means as the data write destination is the first buffer memory is determined not to be included in the first address range by the first address determining means. A first transfer means for transferring the command address to the second information processing apparatus,
The second information processing apparatus acquires the command address from the first information processing apparatus, and reads data corresponding to the command address read from the second external memory by the second external memory control unit. A second transfer means for transferring to the information processing apparatus;
6. The first transfer unit of the first information processing apparatus acquires data for the command address from the second transfer unit, and stores the acquired data in the first buffer memory. Information processing system described in 1. The first information processing apparatus transfers the command address to the second information processing apparatus when the first address determination unit determines that the command address is not included in the first address range. Further comprising a transfer means,
The second information processing apparatus acquires the command address from the first information processing apparatus, and reads data corresponding to the command address read from the second external memory by the second external memory control unit. A second transfer means for transferring to the information processing apparatus;
2. The first transfer unit of the first information processing apparatus acquires data corresponding to the command address from the second transfer unit, and stores the acquired data in the first buffer memory. Information processing system described in 1.   The information according to claim 7, wherein the first transfer unit of the first information processing apparatus and the second transfer unit of the second information processing apparatus transfer the data via a dedicated line. Processing system.   8. The information processing according to claim 7, wherein the first transfer unit of the first information processing apparatus and the second transfer unit of the second information processing apparatus transfer the data via a network. system.   The said calculating means reads the data of the said block from the said 1st buffer memory, when the block data of a predetermined | prescribed block size are stored in the said 1st buffer memory. The information processing system according to one item.   The information processing system according to any one of claims 1 to 10, wherein the first information processing apparatus and the second information processing apparatus are formed on independent electronic circuit boards, respectively. . An information processing apparatus connected to a calculation means via a memory bus composed of a plurality of channels,
An external memory control means for controlling an external memory which is a memory to which an address on the first address space is assigned and which stores information used by the arithmetic means;
A buffer memory that is assigned an address on a second address space used by the arithmetic means and temporarily holds data read from the external memory;
The command issued by the arithmetic means is acquired via the memory bus, and it is determined whether or not the command address in the first address space specified in the command is included in the address range corresponding to the external memory. Address range determination means to perform,
Transfer permission means for permitting transfer of data from the external memory to the buffer memory when the address range determination means determines that the command address is included in the address range;
The external memory control means reads the data corresponding to the command address from the external memory and stores the read data in the buffer memory when the transfer of the data is permitted by the transfer permission means. A characteristic information processing apparatus.   Transfer means for acquiring data for the command address from the outside and storing the acquired data in the buffer memory when the address range determination means determines that the command address is not included in the address range The information processing apparatus according to claim 12, comprising the information processing apparatus. An information processing system comprising a computing means and a memory bus composed of a plurality of channels,
A first memory bus having a first buffer memory connected to the memory bus, assigned an address on a second address space used by the computing means, and temporarily holding data read from the external memory Interface,
A second memory bus interface having a second buffer memory that is assigned an address on the second address space and temporarily holds data read from the external memory;
Data from an external memory connected to the first memory bus interface and the second memory bus interface and assigned an address in a first address space and storing information used by the computing means An information processing system comprising: external memory control means for reading and storing the data in the first buffer memory and the second buffer memory.   The external memory control means includes a bit width of a first memory bus connected to the first buffer memory and data read from the external memory and a second memory bus connected to the second buffer memory. The information processing system according to claim 14, wherein the information is stored in the first buffer memory and the second buffer memory by switching for each bit width. The external memory control means generates a command address string on the first address space by a command issued by the arithmetic means,
In the first information processing apparatus, the write destination of data corresponding to each command address in the address string generated by the external memory control means is based on a predetermined condition. Buffer memory determination means for determining which of the buffer memories is,
16. The information processing system according to claim 14, wherein the external memory control unit writes data corresponding to the command data in a write destination determined by the buffer memory determination unit.   The buffer memory determining unit selects a command address arranged in a predetermined order in the address string as a command address corresponding to the data to be written to the first buffer memory. 16. The information processing system according to 16. The arithmetic means transfers a preload command indicating reading of data from the external memory to the first memory bus interface,
External memory control means
Command acquisition means for acquiring a preload command via the first memory bus interface;
Command address generation means for generating a command address that is an address on the first address space based on the preload command acquired by the command acquisition means;
Transfer control means for accessing the external memory based on the command address generated by the command address generating means and transferring the data read from the external memory to the first buffer memory and the second buffer memory; The information processing system according to claim 14, further comprising:   The computing means stores data for the data size of the first buffer memory in the first buffer memory, and stores data for the data size of the second buffer memory in the second buffer memory. The information processing system according to any one of claims 14 to 18, wherein data in the first buffer memory and the second buffer memory is read.   20. The first memory bus interface, the second memory bus interface, and the external memory control unit are formed on three independent electronic circuit boards, respectively. The information processing system described. An information processing method in an information processing system comprising a computing means and a memory bus composed of a plurality of channels,
A first acquisition step of acquiring a command issued by the computing means via the memory bus;
A first external address which is a memory in which a command address in the first address space designated in the command is assigned an address in the first address space and which stores information used by the computing means A first address range determination step for determining whether or not the first address range corresponding to the memory is included;
When it is determined in the first address range determination step that the command address is included in the first address range, an address on the second address space used by the calculation means is allocated from the first external memory. A first transfer permission step of permitting transfer of data to the first buffer memory, which temporarily holds data read from the first external memory,
First external memory control for reading data corresponding to the command address from the first external memory and storing the read data in the first buffer memory when transfer of the data is permitted in the first transfer permission step Steps,
A second acquisition step of acquiring the command issued by the computing means via the memory bus;
The command address specified in the command is a memory to which an address in the first address space is assigned, and corresponds to a second memory corresponding to a second memory that stores information used by the computing means. A second address determination step of determining whether or not the address range is included;
A second buffer memory to which an address in the second address space is allocated from the second external memory when it is determined in the second address range determining step that the command address is included in the second address range; A second transfer permission step for permitting transfer of data to the second buffer memory that temporarily holds data read from the second external memory;
Second external memory control for reading data corresponding to the command address from the second external memory and storing the read data in the second buffer memory when transfer of the data is permitted in the second transfer permission step And an information processing method. An information processing method in an information processing apparatus connected to a calculation means via a memory bus composed of a plurality of channels,
An acquisition step of acquiring the command issued by the computing means via the memory;
The command address in the first address space specified in the command is a memory to which an address in the first address space is assigned, and is stored in an external memory that is a memory for storing information used by the arithmetic means. An address range determination step for determining whether or not it is included in the corresponding address range;
When it is determined in the address range determination step that the command address is included in the address range, the buffer memory is allocated from the external memory with an address in the second address space, and is read from the external memory. A transfer permission step for permitting the transfer of data to a buffer memory that temporarily holds the received data;
A buffer from which data corresponding to the command address is read from the external memory when the data transfer is permitted in the transfer permission step, and the arithmetic means designates an address in the address space and can read the data An external memory control step for storing the read data in the buffer memory which is a memory and is mapped to an address space used by the computing means and temporarily holds information read from the external memory; An information processing method characterized by comprising: An information processing method in an information processing system comprising a computing means and a memory bus composed of a plurality of channels,
A first memory bus having a first buffer memory connected to the memory bus, assigned an address on a second address space used by the computing means, and temporarily holding data read from the external memory An interface and an address on the second address space are allocated and connected to a second memory bus interface having a second buffer memory for temporarily holding data read from the external memory, and on the first address space External memory control means connected to the external memory that stores the information used by the computing means and that reads the data from the external memory, and stores the data in the external memory Storage step for storing in the first buffer memory and the second buffer memory ,
The information processing method characterized in that the computing means includes a reading step of reading data stored in the first buffer memory and the second buffer memory in the storing step.

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