JP2006011926A - Serial data transfer system, serial data transfer device, serial data transfer method and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To use a plurality of serial memory devices to which the same address is allocated. <P>SOLUTION: A serial data transfer system comprises n serial memory devices 2, 3, 4 allocated to the same address and each having a serial interface with a clock terminal SCL and a data terminal SDA; and a serial data transfer device 1 having one clock terminal SCL and n data terminals SDA0-SDA2, with the data terminals SDA of the n serial memory devices 2, 3, 4 connected to the n data terminals SDA0-SDA2 and the clock terminals SCL of the serial memory devices 2, 3, 4 commonly connected to the one clock terminal SCL. A serial clock line to which the clock terminals is connected is shared and a separate data line to which the data terminals is connected is used for each serial memory device, whereby it is made possible to connect a plurality of general-purpose, space-saving serial memory devices 2, 3, 4 allocated to the same address. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a serial data transfer system, a serial data transfer device, a serial data transfer method, and an image forming apparatus such as an MFP (multifunction peripheral) including the serial data transfer system.

  As for the serial data transfer method, for example, Patent Document 1 proposes a transfer method in which serial data is transferred from a microcomputer to a plurality of devices and the number of serial ports of the microcomputer is smaller than the number of devices. .

  Here, the serial data transfer is not limited to a personal computer (PC) or the like but is required for image data development processing or the like even in an image forming apparatus such as an MFP that handles a large amount of image data.

JP-A-5-324858

  When an attention is paid to a serial memory device as an expansion device used for this type of serial data transfer, for example, there is a DIMM (Dual In-Line Memory Module). This DIMM has a large size suitable for a desktop PC (for example, package dimensions: W133.55 × H35 × D4.5 mm) and a small size suitable for a notebook PC (for example, package dimensions: W67.6 ×). H31.75 × D3.8 mm).

  For example, a configuration example of a desktop SDRAM module configured by connecting a desktop DIMM as a device having different addresses on an I2C bus that is one of the interface bus standards and has low speed, low cost, and high expandability is shown in FIG. Shown in That is, a master (serial data transfer device) 102 that performs transfer control with respect to the I2C bus 101 using the serial clock SCL line and the serial data SDA line, and a plurality of, for example, three desktops as slaves to the master. It is configured by connecting the DIMMs 103, 104, and 105. These three desktop DIMMs 103, 104, and 105 are devices capable of addressing lower 3 bits of E0, E1, and E2, and differ depending on, for example, addresses 1, 2, and 3 in order as shown in the figure. The device has an address, and by outputting an address signal from the master 102 to perform data transfer, even if a plurality of desktop DIMMs 103, 104, 105 are connected, the desired desktop DIMMs 103, 104, 105 Can transfer data between them.

  As a serial data transfer system in the MFP, a desktop SDRAM module configured by connecting desktop DIMMs as shown in FIG. 18 may be used. However, unlike a desktop PC with less space restrictions, the MFP In the case of an image forming apparatus such as a small-sized machine, in particular, the area and space for a control board are limited. Therefore, a large desktop DIMM is not suitable for an image forming apparatus such as an MFP. In the case of the configuration example of FIG. 18, data transfer can be performed only with one addressed device, and simultaneous transfer with all devices is impossible. , It takes time to clear the memory for all devices.

  Therefore, it is conceivable to use a notebook PC DIMM for space saving as a serial data transfer system in the MFP. As shown in FIG. 18, as shown in FIG. 19, a master (serial data transfer device) 112 that performs transfer control for the I2C bus 111 using the serial clock SCL line and the serial data SDA line. And a plurality of, for example, three notebook PC DIMMs 113, 114, and 115 as slaves to the master.

  However, these DIMMs 113, 114, and 115 developed for notebook PCs differ from the DIMMs 103, 104, and 105 in which addressing is possible, and the addresses of the lower 3 bits E0, E1, and E2 in the device are, for example, As shown, it is fixed at 0. That is, the DIMMs 113, 114, and 115 have the same address allocation configuration, and the configuration shown in FIG. 19 cannot be used because the addresses of the DIMMs 113, 114, and 115 cannot be distinguished. This is presumably because the amount of data handled in a notebook PC is not so large, and it is sufficient that one notebook PC DIMM can be expanded and mounted, and no distinction between devices is originally required.

  However, in a MFP that handles a large amount of image data, the use of a notebook PC DIMM is effective for the desire to use a small memory within a limited space, and a single notebook PC DIMM. Therefore, it is important to construct a serial data transfer system that can use a plurality of DIMMs for notebook PCs having the same address assignment.

  In this case, simply, as shown in FIG. 20, the serial data transfer device ASIC 116 corresponding to the master 112 applies serial clock terminals SCL, SCL0 to SCL2 and SDA0 to SDA2 to the DIMMs 113, 114, and 115, respectively. This can be realized by providing a serial data terminal SDA separately and connecting it to the I2C bus 111.

  However, with such a configuration, the number of pins of the serial data transfer device ASIC 116 increases, resulting in an increase in cost.

  In the case of Patent Document 1, the microcomputer corresponding to the serial data transfer device ASIC 116 has a large number of pins.

  An object of the present invention is to provide an image of a serial data transfer system, a serial data transfer device, a serial data transfer method, and an MFP (multifunction peripheral) equipped with the serial data transfer system, which can use a plurality of serial memory devices with the same address assignment. A forming apparatus is provided.

  A serial data transfer system according to a first aspect of the present invention includes n serial memory devices having the same address assignment configuration each having a serial interface having a clock terminal and a data terminal, one clock terminal and n data terminals. The n data terminals are connected to the data terminals of the n serial memory devices, and the clock terminals of the n serial memory devices are commonly used for one clock terminal. And a connected serial data transfer device.

  According to a second aspect of the present invention, in the serial data transfer system according to the first aspect, the serial data transfer device includes means for simultaneously transferring write data to a plurality of connected serial memory devices.

  According to a third aspect of the present invention, in the serial data transfer system according to the second aspect, the means for transferring is means for transferring different write data for each serial memory device.

  According to a fourth aspect of the present invention, in the serial data transfer system according to the second aspect, the means for transferring is means for transferring the same write data to a plurality of the serial memory devices.

  According to a fifth aspect of the present invention, in the serial data transfer system according to the fourth aspect, the same write data is erase data.

  According to a sixth aspect of the present invention, in the serial data transfer system according to the first aspect, the serial data transfer device has means for simultaneously transferring read data from a plurality of connected serial memory devices.

  The invention according to claim 7 is the serial data transfer system according to claim 1, wherein the serial data transfer device transfers write data to a plurality of connected serial memory devices at the same time, or is connected. Means for simultaneously transferring read data from the plurality of serial memory devices.

  According to an eighth aspect of the present invention, in the serial data transfer system according to any one of the second to seventh aspects, the data size of the data transferred simultaneously by the transferring means is the same.

  According to a ninth aspect of the present invention, in the serial data transfer system according to any one of the first to eighth aspects, the serial data transfer device preliminarily stores a memory space of the n connected serial memory devices in a system memory. Memory mapping in space.

  According to a tenth aspect of the present invention, in the serial data transfer system according to the ninth aspect, the serial data transfer device also includes a simultaneous memory space for simultaneously accessing the n serial memory devices connected thereto. Memory mapping is performed in advance in the system memory space.

  The serial data transfer device according to an eleventh aspect of the present invention is the serial data transfer device, wherein each of the clock terminals of the n serial memory devices having the same address assignment configuration each having a serial interface having a clock terminal and a data terminal is connected in common. A clock terminal; and n data terminals to which the data terminals of each of the n serial memory devices are connected.

  A twelfth aspect of the present invention is the serial data transfer device according to the eleventh aspect, further comprising means for simultaneously transferring write data to the plurality of serial memory devices connected thereto.

  According to a thirteenth aspect of the present invention, in the serial data transfer device according to the twelfth aspect, the means for transferring is means for transferring different write data for each serial memory device.

  According to a fourteenth aspect of the present invention, in the serial data transfer device according to the twelfth aspect, the means for transferring is means for transferring the same write data to a plurality of the serial memory devices.

  According to a fifteenth aspect of the present invention, in the serial data transfer device according to the fourteenth aspect, the same write data is erase data.

  A sixteenth aspect of the present invention is the serial data transfer device according to the eleventh aspect, further comprising means for simultaneously transferring read data from the plurality of connected serial memory devices.

  According to a seventeenth aspect of the present invention, in the serial data transfer device according to the eleventh aspect, write data is simultaneously transferred to a plurality of connected serial memory devices, or from a plurality of connected serial memory devices. Means for transferring read data simultaneously.

  According to an eighteenth aspect of the present invention, in the serial data transfer device according to any one of the twelfth to seventeenth aspects, the data sizes transferred simultaneously by the transferring means have the same data size.

  According to a nineteenth aspect of the present invention, in the serial data transfer device according to any one of the eleventh to eighteenth aspects, the memory space of the n serial memory devices to be connected is preliminarily mapped to the system memory space.

  According to a twentieth aspect of the present invention, in the serial data transfer device according to the nineteenth aspect of the present invention, a memory mapping for simultaneously accessing the n serial memory devices to be connected is also previously mapped to the system memory space. Keep it.

  A serial data transfer method according to a twenty-first aspect of the present invention is directed to n serial memory devices having the same address assignment configuration each having a serial interface having a clock terminal and a data terminal, and one clock terminal and n data terminals. The data terminals of the n serial memory devices are connected to the n data terminals, and the serial data transfer devices of the n serial memory devices are connected to one clock terminal. The clock terminals are connected in common, the serial clock signals are shared by the n serial memory devices, and the serial data transfer device and each serial memory device are connected to each other using data lines between the individually connected data terminals. The write data or read data is transferred between the two.

  According to a twenty-second aspect of the present invention, in the serial data transfer method according to the twenty-first aspect, write data is simultaneously transferred in accordance with a serial clock signal to the plurality of connected serial memory devices.

  A thirteenth aspect of the present invention is the serial data transfer method according to the twenty-second aspect, wherein different write data is transferred for each serial memory device.

  According to a twenty-fourth aspect of the present invention, in the serial data transfer method according to the twenty-second aspect, the same write data is transferred to the plurality of serial memory devices.

  According to a twenty-fifth aspect of the present invention, in the serial data transfer method according to the twenty-fourth aspect, the same write data is erase data.

  According to a twenty-sixth aspect of the present invention, in the serial data transfer method according to the twenty-first aspect, read data is simultaneously transferred in accordance with a serial clock signal from the plurality of connected serial memory devices.

  According to a twenty-seventh aspect of the present invention, in the serial data transfer method according to the twenty-first aspect, write data is simultaneously transferred or connected to a plurality of connected serial memory devices in accordance with a serial clock signal. The read data is transferred simultaneously from the plurality of serial memory devices.

  According to a twenty-eighth aspect of the present invention, in the serial data transfer method according to any one of the twenty-second to twenty-seventh aspects, data to be transferred simultaneously has the same data size.

  A twenty-ninth aspect of the present invention is the serial data transfer method according to any one of the twenty-first to twenty-eighth aspects, wherein a memory space of the n serial memory devices connected is preliminarily defined as a system memory space of the serial data transfer device. The memory is mapped in advance, and addressing is performed using the memory address of the system memory space in which the memory mapping is performed.

  A thirty-third aspect of the invention is the serial data transfer method according to the twenty-ninth aspect, wherein a simultaneous memory space for simultaneously accessing the n connected serial memory devices is also stored in the system memory space in advance. In the case where n serial memory devices are simultaneously accessed, addressing is performed using the memory address of the memory space for simultaneous use of the system memory space mapped.

  An image forming apparatus according to a thirty-first aspect includes a scanner for reading image data of a document, a printer for performing an image forming operation based on the image data, image data read by the scanner, or image data for image formation by the printer. The serial data transfer system according to any one of claims 1 to 10, or the data transfer system according to any one of claims 1 to 10, wherein data transfer processing for writing or reading the image data from or to the serial memory device is performed. A serial data transfer device according to claim 1.

  Since the serial clock line to which the clock terminal is connected is made common and the data line to which the data terminal is connected is individually divided for each serial memory device, Multiple serial memory devices with the same address assignment configuration for space saving can be connected, and as a serial data transfer device, it is possible to reduce the number of pins as much as possible, and it is also easy to simultaneously transfer to and from multiple serial memory devices This makes it possible to obtain a merit such as speeding up the memory erasing operation.

  According to the second, twelfth, and twenty-second aspects of the present invention, write data is transferred to a plurality of serial memory devices at the same time. Therefore, in the serial transfer method having a low transfer speed, the data transfer process in the entire system can be accelerated. Can be planned.

  According to the third, thirteenth and twenty-third aspects of the present invention, different write data is transferred simultaneously for each serial memory device, so that the data transfer processing in the entire system can be speeded up in a serial transfer method with a low transfer speed. Can do.

  According to the fourth, fourteenth and twenty-fourth aspects of the present invention, since the same write data is simultaneously transferred to a plurality of serial memory devices, the data transfer processing in the entire system can be speeded up in the serial transfer method having a low transfer speed. For example, if the same write data is erased data as in the fifth, fifteenth and twenty-fifth aspects of the invention, memory erasure can be processed at a high speed in an erasing time required for one serial memory device. it can.

  According to the sixth, sixteenth and twenty-sixth aspects of the present invention, read data is simultaneously transferred from a plurality of serial memory devices, so that the data transfer processing in the entire system can be speeded up in a serial transfer method with a low transfer speed. Can do.

  According to the seventh, seventeenth and twenty-seventh aspects of the present invention, write data or read data is simultaneously transferred to and from a plurality of serial memory devices. Can be speeded up.

  According to the invention described in claims 8, 18 and 28, since the data sizes of the data to be transferred simultaneously are the same, the performance of the write operation or the write / read operation can be improved.

  According to the ninth, nineteenth and twenty-ninth aspects of the present invention, since the memory space of the n serial memory devices is preliminarily mapped to the system memory space, it is possible to access a plurality of serial memory devices having the same address assignment configuration. As in the case of accessing a normal memory, the address can be easily accessed only by addressing using the memory address of the system memory space mapped with the memory.

  According to the tenth, twentieth and thirty aspects of the invention, the simultaneous memory space for simultaneously accessing n serial memory devices is also preliminarily mapped to the system memory space, so that n pieces of erase data and the like are simultaneously received. Addressing when transferring data to a serial memory device is facilitated and can be easily accessed.

  According to the invention described in claim 31, since the serial data transfer system according to any one of claims 1 to 10 or the serial data transfer device according to any one of claims 11 to 20 is mounted, space saving. Large image data can be handled without hindering the conversion.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[First embodiment]
This embodiment is one of the interface bus standards. The I2C bus having a low speed, a low cost, and a high expandability is connected to the serial data transfer device ASIC and n, for example, three of the same address allocation configuration. An example of application to a serial data transfer system configured by connecting a notebook PC DIMM as a serial memory device will be described.

  FIG. 1 shows a schematic configuration example of this serial data transfer system. First, the serial data transfer device 1 having an ASCII configuration includes one clock terminal SCL and n, in this case, three data terminals SDA0, SDA1, and SDA2. In addition, n, here, three DIMMs for notebook PCs, which are three serial memory devices, are configured with, for example, package dimensions: W67.6 × H31.75 × D3.8 mm. The lower 3 bits of addresses E0, E1, and E2 are fixed to 0 in the device, for example, so that they are the same as the DIMMs 113, 114, and 115 for notebook PCs to which the same address is assigned. Each has a clock terminal SCL and a data terminal SDA. The serial data transfer device 1 and the DIMMs 2, 3, 4 are connected to the three data terminals SDA 0, SDA 1, SDA 2 of the serial data transfer device 1 via the I2C bus 5. The clock terminals SCL of the DIMMs 2, 3, and 4 are commonly connected to one clock terminal SCL of the serial data transfer apparatus 1. That is, the serial clock line is shared, and the data line is individually divided for each of DIMMs 2, 3, and 4.

FIG. 2 shows an example of the internal configuration of the serial data transfer apparatus 1 according to the I2C standard when reading / writing DIMMs 2, 3, and 4 in units of one. That is, an IO selector 11 for switching input / output is provided for each of the clock terminal SCL and the data terminals SDA0, SDA1, and SDA2. Further, an interface 13 of the I2C standard that switches input / output of clock and data is connected to the control unit 12 that controls the operation of the serial data transfer apparatus 1. Specifically, for the clock terminal SCL, SCL I selects the serial clock i2cclki for reading and SCL The serial clock i2cclkko for writing is selected by O. A selector 16 having an input gate circuit 14 and an output gate circuit 15 is interposed between the selector 11 on the data terminals SDA0, SDA1, and SDA2 side and the interface 13. Either one of the input gate circuit 14 and the output gate circuit 15 is selected according to enable [1: 0], and the inside of the input gate circuit 14 and the output gate circuit 15 is mode-selected. Signal sda Three types of data i2cdatai0 to i2cdatai2 and i2cdatao0 to i2cdatao2 are selected according to sel [1: 0].

Thus, for example, the SCL at the interface 13 O selects the serial clock i2cclkko for output and sends it to the I2C bus 5 from the clock terminal SCL, and also selects i2cdatao0 in the output gate circuit 15 to write data SDA. If o is sent from the data terminal SDA0 onto the I2C bus 5, the address data and write data SDA are sent to the DIMM 2 connected to the data terminal SDA0.
o can be transferred. The same applies to the case where address data and write data are transferred to the other DIMMs 3, 4, and when the read data is transferred from these DIMMs 2, 3, 4, the interface 13 and the input gate circuit 14 are switched. Is possible as well.

  Therefore, according to the present embodiment, the serial clock line to which the clock terminal SCL is connected is basically shared, and the data line to which the data terminal SDA is connected is individually divided for each of DIMMs 2, 3, and 4. Therefore, a plurality of DIMMs 2, 3, and 4 for a notebook PC having the same address allocation configuration that is general purpose and space-saving can be connected, and the serial data transfer device 1 can be inexpensive with a minimum number of pins.

  Here, another embodiment in which the same data can be simultaneously written with respect to the selector 16 in the serial data transfer apparatus 1 is shown in FIG. The selector 16 of this embodiment has individual select terminals 0, 1, and 2 for the DIMMs 2, 3, and 4 in the output gate circuit 15 as well as a simultaneous write select terminal 3, and each individual terminal. The simultaneous write select terminal 3 is commonly connected to the OR gates 17, 18, 19 provided between 0, 1, 2 and the data terminals SDA0, SDA1, SDA2. On the other hand, even in the input gate circuit 14, each of the DIMMs 2, 3, 4 has individual select terminals 0, 1, 2, and any of the DIMMs 2, 3, 4 indicates a write failure in the write operation. A select terminal 3 is provided for determining a write failure when NAK (H level) is returned via the OR gate 20.

According to the selector 16 having such a configuration, the serial data transfer device 1 selects the individual select terminals 0, 1 and 2 in the output gate circuit 15 so that data is individually recorded for each of the DIMMs 2, 3 and 4. In addition, it is possible to select the simultaneous write select terminal 3 to select address data or write data SDA. If o is given, the same data can be simultaneously transferred to the DIMMs 2, 3, and 4 to perform the write operation.

  FIG. 4 is a schematic diagram showing an operation example at the time of simultaneous writing of the same data. In the figure, white portions indicate transmission (transfer) from the serial data transfer apparatus 1, and hatched portions indicate transmission (transfer) from the devices (DIMMs 2, 3, 4). “S” is Start Condition, “P” is Stop Condition, “A” is Acknowledge, and “/ A” is Not Acknowledge. First, set the start condition, specify the address where the data is to be written, and transfer the “/ W” command, which means writing, to all devices (DIMMs 2, 3, 4) through the simultaneous write select terminal 3 After receiving Ack from these devices (DIMM2, 3, 4), all the devices (DIMM2) receive the actual write data by a predetermined number of bits through the simultaneous write select terminal 3, such as Data00, Data01,. , 3, 4), each time receiving an Ack from these devices (DIMMs 2, 3, 4) and finally a response “A // A” indicating whether or not the writing of these data was successful Wait for "and complete the phase by setting a stop condition.

  Therefore, according to such a configuration, since the same write data is simultaneously transferred to a plurality of devices (DIMMs 2, 3, 4), the high-speed data transfer processing in the entire system can be achieved in the serial transfer method having a low transfer speed. Can be achieved. In particular, if the same write data is used as erasure data, parallel processing can be performed, so that memory erasure can be processed at high speed in an erasure time required for one device.

FIG. 5 shows another embodiment of the serial data transfer device 1 that enables simultaneous writing of different data. The serial data transfer apparatus 1 according to the present embodiment omits the output gate circuit 15, and the interface 13 has a dedicated data output terminal SDA0 for each data terminal, and thus for each of DIMMs 2, 3, and 4. o ~ SDA2 o is set.

Therefore, these data output terminals SDA0 are synchronized with the serial clock. o ~ SDA2
If different data are output from o at the same timing, different data can be simultaneously transferred to DIMMs 2, 3, and 4. FIG. 6 is a schematic diagram showing an operation example at the time of simultaneous writing of such different data. The notation and the like in the figure are the same as those in FIG. As described above, different write data is transferred simultaneously for each of DIMMs 2, 3, and 4, so that the data transfer processing in the entire system can be speeded up in the serial transfer method having a low transfer speed.

  In this case, if the selection operation on the input gate circuit 14 side is used together, the DIMMs 2, 3, and 4 can be simultaneously read / written with the same data size. FIG. 7 is a schematic diagram showing an operation example at the time of reading / writing at the same time when, for example, the individual select terminal 1 of the input gate circuit 14 is selected and the DIMM 3 is set to the read mode. Also in this case, the notation and the like in the figure are the same as those in FIG. In this case, regarding the read operation, first, a start condition is set, an address from which data is to be read is designated, and an “R” command meaning read is transferred to the DIMM 3 through the individual select terminal 1. After receiving the Ack from the DIMM 3, the read data is successively transferred from the DIMM 3 in order of a predetermined number of bits such as Data10, Data11,..., Data1N. In addition to returning Ack, a response “A // A” indicating whether or not the writing of these data has finally been successful is also returned, and the phase is completed by setting a stop condition.

[Second Embodiment]
The present invention is not limited to an I2C compatible serial memory, but can be applied to a serial compatible memory including a serial interface having a clock terminal and a data terminal. Therefore, the present embodiment is one of the interface bus standards, and there is no upper limit of speed, and the SPI for high speed and large capacity (for example, the data sheet M95256 “256 Kbit Serial SPI Bus of STMicroelectronics GROUP OF COMPANIES (Refer to “EEPROM With High Speed Clock” March 2004).

  In other words, the present embodiment is directed to a serial data transfer system configured by connecting a serial data transfer device ASIC and n, for example, three, SPI-compatible memories having the same address assignment configuration. An application example is shown.

FIG. 8 shows a schematic configuration example of this serial data transfer system. First, the serial data transfer device 21 having an ASCII configuration has one clock terminal CLK and chip select terminals CS0 N to CS2 corresponding to n, here, three data terminals. N, an output terminal Q, and an input terminal D. In addition, n, here three, SPI-compatible memories 22, 23, 24 are small ones having a small package size according to DIMMs 2, 3, 4, etc., and assigned the same address. And a chip select terminal CS corresponding to one clock terminal CLK and one data terminal, respectively. N, a serial input terminal SI, and a serial output terminal SO. These serial data transfer device 21 and SPI-compatible memories 22, 23, 24 are connected to the three chip select terminals CS0 of the serial data transfer device 1. N to CS2 N is a chip select terminal CS of each SPI-compatible memory 22, 23, 24 N is connected, the clock terminal CLK of each of the SPI corresponding memories 22, 23, 24 is commonly connected to one clock terminal CLK of the serial data transfer device 21, and each SPI corresponding memory 22 is further connected to the output terminal Q. , 23 and 24 are connected in common, and the serial output terminal SO of each of the SPI-compatible memories 22, 23 and 24 is connected to the input terminal D in common. That is, the serial clock line is shared, and the chip select line corresponding to the data line is individually divided for each of the SPI-compatible memories 22, 23, and 24.

In such a configuration, the chip select signal CSx output from the serial data transfer device 21. The SPI corresponding memories 22, 23, and 24 in which N (x = 0, 1, 2) is active (L level) are selected. That is, the SPI-compatible memories 22, 23 and 24 have a feature that only the device selected by the chip select signal operates.

  Here, the case where the SPI corresponding memories 22, 23 and 24 are individually read / written and simultaneously written will be described in order.

FIG. 9 shows an example of a time chart during individual writing, and FIG. 10 shows an example of a time chart during individual reading. As described above, in the SPI standard, the chip select terminal CSx of the device to be accessed The device is accessed after N is activated. When individual reading / writing is performed, only one target chip select terminal needs to be activated. For example, in the individual write, as shown in FIG. 9, after issuing a 1-byte write enable command, a 1-byte write command is issued, and a 3-byte length address is designated (2 bytes). In the case of a device corresponding to a length, it is only necessary to output only 2 bytes of the address (the same applies hereinafter), and each byte of data is actually transferred for n bytes. In the individual read, as shown in FIG. 10, after issuing a read command, an address of 3 bytes length is specified, and n bytes of data from the target device (SPI compatible memory) are received one byte at a time.

FIG. 10 shows an example of a time chart for simultaneous writing. In simultaneous writing, a chip select signal CSx for devices (SPI-compatible memories 22, 23, 24) that are accessed simultaneously.
Make all N active. By the way, if writing to two devices at the same time, the chip select signal CSx for the two target devices. N may be activated. After this, it is the same as that for individual writing. After issuing a 1-byte write enable command, issue a 1-byte write command, and then specify a 3-byte address and specify each byte. N bytes of data are actually transferred.

  In the serial data transfer system of the present embodiment, in order to enable not only individual read / write and simultaneous write but also simultaneous read / write, for example, as shown in FIG. In common, the input terminal Q and the output terminal D may be Q0 to Q2 and D0 to D2 so as to be individual for each of the SPI-compatible memories 22, 23, and 24.

[Third embodiment]
A third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a memory mapping technique is used in order to perform the memory access operation in the above-described embodiment more simply and at high speed.

  First, in the case of the configuration example described above, a more practical configuration example for memory access will be described with reference to FIG. For example, serial memory 32, 33, 34 as serial memory devices corresponding to DIMMs 2, 3, 4 are connected to a serial memory controller 31 having an ASIC structure corresponding to serial data transfer device 1 in accordance with the I2C standard as described above. This is an example applied to a data transfer system, and a CPU 35 for instructing access to the serial memories 32, 33, 34, etc. is actually connected to the serial memory controller 31. For example, a DDR (Double Data Rate) memory 36 is also connected to the CPU 35.

  The serial memory controller 31 is provided with various registers for receiving access settings from the CPU 35 in order to access the serial memories 32, 33, and 34. That is, a “Device CLK Mode” register for setting a data transfer clock frequency (speed) according to a device, for example, which of three devices (serial memories 32, 33, 34) is selected is selected. "Device Address" register for setting, "Device Memory Address" register for setting address in memory, "Device Read / Write" register for setting either read / write, actual read / A "Device Data" register for setting the data to be written, a "Device Data Length" register for setting the data length, and a "Device Exec" register for executing an operation by triggering. Therefore, in order to access the serial memories 32, 33 and 34, the CPU 35 needs to access each of the registers in the serial memory controller 31 on the basis of software and set the registers one by one in order. is there.

  In this regard, in the present embodiment, by using a memory mapping technique for accessing the serial memories 32, 33, and 34, the software setting of each register as described above becomes unnecessary, and the normal steps are performed. Can be greatly simplified.

  FIG. 14 schematically shows an example of memory mapping set by the hardware of the serial memory controller 31. Here, it is assumed that the serial memories 32, 33, and 34 all have addresses 0000h to FFFFh. For example, with respect to the system memory space 41 consisting of addresses 00000000h to FFFFFFFFh, the memory space of the serial memory 32 is mapped to the addresses 80000000h to 8000FFFFh as the serial compatible memory 32a, and the memory space of the serial memory 33 is similarly converted to the serial compatible memory. 33a is mapped to addresses 80010000h to 8001FFFFh, and the memory space of the serial memory 34 is mapped to addresses 800100000h to 8002FFFFh as serial-compatible memory 34a. On 41, each has a unique address. Thus, even if the same address 1234h is used, for example, 80001234h for the serial memory 32, 80011234h for the serial memory 33, and 80012234h for the serial memory 34, the distinction is made. Note that the memory space for the DDR memory 36 is memory-mapped after address A0000000h, for example.

  As described above, if the serial correspondence memories 32a, 33a, and 34a are mapped in the system memory space 41, the CPU 35 can access the serial memories 32, 33, and 34 based on software in the same manner as a normal memory access. Become. That is, in the present embodiment, in order to access the serial memories 32, 33, and 34, it is necessary to set the “Device CLK Mode” register as usual in order to set the speed. The memory space of the serial correspondence memories 32a, 33a, and 34a may be accessed in advance in accordance with software and in the same manner as normal memory access (that is, simply specifying an address). When the memory space of the serial correspondence memories 32a, 33a, and 34a is accessed, the serial memory controller 31 makes the remaining register settings except for the speed setting ("Device Address" register to "Device Exec" in accordance with the memory mapped address). "Register" is automatically performed, and the corresponding addresses of the serial memories 32, 33, and 34 can be directly accessed as they are. For example, if the address 80011234h in the system memory space 41 is designated, the register setting for accessing the address 1234h of the serial memory 33 is automatically performed, and the read or write operation for the address 1234h of the serial memory 33 is immediately performed. Can be executed.

  By the way, in the present embodiment, in addition to the memory mapping described above, a simultaneous memory space for simultaneously accessing the serial memories 32, 33, and 34 is set as the serial memory 3 space 42 on the system memory space 41 at addresses 8003000h to 8003FFFFh. As memory mapping. As shown in FIG. 15, the serial memory 3 space 42 is obtained by duplicating the addresses of the memory spaces of the serial memories 32, 33, and 34 using the identity of these addresses. By designating the internal address, the same address of these serial memories 32, 33, and 34 is accessed simultaneously. Therefore, when simultaneously writing the same data to these serial memories 32, 33 and 34, the serial memory can be simultaneously written only by designating an address (for example, address 8003234h) in the serial memory 3 space 42 on the system memory space 41. 32, 33, and 34 can be accessed at the same address (for example, address 1234h). Therefore, for example, when performing a memory erasing operation on these serial memories 32, 33, 34, an address in the serial memory 3 space 42 can be designated on the system memory space 41 and a write operation can be executed with the erasing data. For example, the erase operation for all devices can be completed in the time required for erasing one device.

  Next, the simultaneous read operation from the serial memories 32, 33 and 34 using the serial memory 3 space 42 will be described with reference to FIG. When an address in the serial memory 3 space 42 is designated with a read command, actual addresses of the serial memories 32, 33, and 34 are generated and data is read from the address location. The data read from each serial memory 32, 33, 34 is temporarily allocated to the internal register 43 in the serial memory controller 31 according to the memory mapped address for each serial memory 32, 33, 34 and temporarily stored. Is done. After this storage, reading from the corresponding memory space becomes possible. For example, when it is desired to read data from the serial correspondence memory 32a, the data can be read from the internal register 43 using an address on the system memory space 41 to which the serial correspondence memory 32a is mapped. In this case, reading from the internal register 43 takes less time than reading from the serial memory 32 itself. The same applies to the other serial-compatible memories 33a and 34a.

  In other words, the simultaneous read operation from the serial memories 32, 33, and 34 requires two readings. However, since the access speed of the serial memory is usually slow, the serial memories 32, 33, and 34 are individually read in order. Rather than accessing, the memory is accessed at the same time, and thereafter, high-speed reading from the internal register is performed, so that apparent memory access can be improved.

[Fourth embodiment]
The present embodiment shows an application example to a small MFP (multi-function peripheral) that is an image forming apparatus as a preferred implementation example of the serial data transfer system as described above. FIG. 17 is a schematic block diagram showing an extremely simplified configuration example relating to the MFP including the serial data transfer system. The serial data transfer device 1 (or 21 or 31) having an ASIC configuration is connected to a scanner 51, a plotter (printer) 52, and a main ASIC 53 to which a CPU 35 is connected via an interface. The scanner 51 photoelectrically reads the image data of the document, and the printer 52 performs an image forming operation based on the image data. Generally, the scanner 51 has a laser printer configuration using an electrophotographic process. In addition to the CPU 35, the ASIC 53 is connected to the HDD 54 via the HDD interface, and further to the DDR memory 36 and the like. Further, a plurality of serial memories 32, 33, and 34 (actually DIMMs 2, 3, and 4 and SPI memories 22, 23, and 24) are connected to the ASIC-structured serial data transfer device 1 to form a serial data transfer system. ing. In addition to having a USB terminal, it is also connected to a network via an Ethernet physical layer (Ethernet is a registered trademark) 55, for example.

  Here, the serial data transfer device 1 having the ASIC configuration is mounted on the controller board inside the MFP together with the CPU 35, the serial memories 32, 33, 34, the ASIC 53, etc. In the case of a desktop PC or the like as described above. Unlike space limitations, there is a desire to use a compact one. In addition, since the amount of image data handled by the MFP is large, when using a small serial memory, it is desired to use a plurality of serial memories. In this regard, the serial data transfer system according to the present invention as described above meets these demands, and mounting in an MFP is a suitable application example.

1 is a connection diagram illustrating a schematic configuration example of a serial data transfer system according to a first embodiment of this invention. It is a schematic block diagram which shows the internal structural example of the serial data transfer apparatus. It is a schematic block diagram which shows the some modification. It is a schematic diagram which shows the operation example at the time of simultaneous writing of the same data. It is a schematic block diagram which shows another modification of the internal structure of the serial data transfer apparatus. It is a schematic diagram which shows the operation example at the time of simultaneous writing of different data. It is a schematic diagram which shows the operation example at the time of simultaneous reading / writing. It is a connection diagram which shows the example of schematic structure of the serial data transfer system of 2nd embodiment of this invention. It is a time chart which shows the operation example at the time of individual writing. It is a time chart which shows the operation example at the time of individual reading. It is a time chart which shows the operation example at the time of simultaneous writing. It is a connection diagram which shows the schematic structural example of the modification of a serial data transfer system. It is a schematic block diagram. It is a schematic diagram which shows the example of memory mapping of 3rd embodiment of this invention. It is explanatory drawing regarding the simultaneous write operation using the memory space for simultaneous. It is explanatory drawing regarding the simultaneous read-out operation | movement using the memory space for simultaneous. It is a schematic block diagram which shows the structural example of MFP of the 4th Embodiment of this invention. It is a connection diagram which shows the structural example for desktops which connected the device with a different address to an I2C bus. It is a connection diagram which shows the example of a connection which cannot be implemented at the time of using DIMM for space saving. It is a connection diagram which shows a prior art example.

Explanation of symbols

1 Serial Data Transfer Device 2, 3, 4 Serial Memory Device 21 Serial Data Transfer Device 22, 23, 24 Serial Memory Device 31 Serial Data Transfer Device 32, 33, 34 Serial Memory Device 51 Scanner 52 Printer

Claims (31)

N serial memory devices of the same address assignment configuration each comprising a serial interface having a clock terminal and a data terminal;
1 clock terminal and n data terminals, the data terminals of each of the n serial memory devices are connected to n data terminals, and n clock terminals are connected to n clock terminals. A serial data transfer device in which the clock terminals of the serial memory device are connected in common;
A serial data transfer system comprising:   2. The serial data transfer system according to claim 1, wherein said serial data transfer device has means for transferring write data simultaneously to a plurality of connected serial memory devices.   3. The serial data transfer system according to claim 2, wherein the means for transferring is means for transferring different write data for each serial memory device.   3. The serial data transfer system according to claim 2, wherein said means for transferring is means for transferring the same write data to a plurality of said serial memory devices.   5. The serial data transfer system according to claim 4, wherein the same write data is erase data.   2. The serial data transfer system according to claim 1, wherein the serial data transfer device has means for transferring read data simultaneously from a plurality of connected serial memory devices.   The serial data transfer device has means for transferring write data simultaneously to a plurality of connected serial memory devices, or transferring read data simultaneously from a plurality of connected serial memory devices, The serial data transfer system according to claim 1.   8. The serial data transfer system according to claim 2, wherein the data transferred simultaneously by the transferring means have the same data size.   The serial data transfer device according to any one of claims 1 to 8, wherein the serial data transfer device previously maps a memory space of the n connected serial memory devices into a system memory space. Data transfer system.   2. The serial data transfer device according to claim 1, wherein a simultaneous memory space for simultaneously accessing the n serial memory devices connected to the serial data transfer device is previously mapped in the system memory space. 9. The serial data transfer system according to 9.   One clock terminal to which the clock terminals of n serial memory devices having the same address allocation configuration each having a serial interface having a clock terminal and a data terminal are connected in common, and each of the n serial memory devices. A serial data transfer device comprising: n data terminals to which the data terminals are connected.   12. The serial data transfer device according to claim 11, further comprising means for simultaneously transferring write data to a plurality of connected serial memory devices.   13. The serial data transfer apparatus according to claim 12, wherein the transfer means is means for transferring different write data for each serial memory device.   13. The serial data transfer apparatus according to claim 12, wherein the transfer means is means for transferring the same write data to a plurality of the serial memory devices.   15. The serial data transfer apparatus according to claim 14, wherein the same write data is erase data.   12. The serial data transfer device according to claim 11, further comprising means for simultaneously transferring read data from the plurality of serial memory devices connected thereto.   12. The means for transferring write data to a plurality of connected serial memory devices at the same time or transferring read data from a plurality of connected serial memory devices at the same time. Serial data transfer device.   18. The serial data transfer device according to claim 12, wherein the data transferred simultaneously by the transferring means have the same data size.   19. The serial data transfer device according to claim 11, wherein the memory space of the n serial memory devices to be connected is previously mapped to a system memory space.   20. The serial data transfer device according to claim 19, wherein a simultaneous memory space for simultaneously accessing the n serial memory devices to be connected is also previously mapped to the system memory space. N serial memory devices having the same address assignment configuration each including a serial interface having a clock terminal and a data terminal are compared with a serial data transfer device having one clock terminal and n data terminals. Connecting the data terminals of each of the n serial memory devices to the data terminals, and commonly connecting the clock terminals of the n serial memory devices to one clock terminal,
A serial clock signal is shared by the n serial memory devices, and write data or read data is transferred between the serial data transfer device and each serial memory device using a data line between the individually connected data terminals. A serial data transfer method characterized in that the data is transferred.   22. The serial data transfer method according to claim 21, wherein write data is transferred simultaneously to a plurality of connected serial memory devices in accordance with a serial clock signal.   23. The serial data transfer method according to claim 22, wherein different write data is transferred for each serial memory device.   23. The serial data transfer method according to claim 22, wherein the same write data is transferred to a plurality of said serial memory devices.   25. The serial data transfer method according to claim 24, wherein the same write data is erase data.   22. The serial data transfer method according to claim 21, wherein read data is transferred simultaneously from a plurality of connected serial memory devices in accordance with a serial clock signal.   Write data is simultaneously transferred to a plurality of connected serial memory devices in accordance with a serial clock signal, or read data is simultaneously transferred from a plurality of connected serial memory devices. 22. The serial data transfer method according to claim 21, wherein:   28. The serial data transfer method according to claim 22, wherein the data transferred simultaneously have the same data size.   The memory space of the n connected serial memory devices is preliminarily mapped to the system memory space of the serial data transfer device, and is addressed using the memory address of the system memory space mapped. 29. The serial data transfer method according to any one of claims 21 to 28, wherein:   In the case where the simultaneous memory space for simultaneously accessing the n serial memory devices connected is also mapped in advance in the system memory space and the n serial memory devices are accessed simultaneously. 30. The serial data transfer method according to claim 29, wherein addressing is performed using a memory address of a simultaneous memory space of said system memory space that is memory-mapped. A scanner that reads the image data of the document;
A printer that performs an image forming operation based on image data;
11. The image data read by the scanner or the image data to be formed by the printer is handled, and data transfer processing for writing or reading the image data from or to the serial memory device is performed. Any one of the serial data transfer systems or the serial data transfer device according to any one of claims 11 to 20;
An image forming apparatus comprising:

Images