CN110765060B - MDIO bus-to-parallel bus conversion method and device, equipment and medium - Google Patents
MDIO bus-to-parallel bus conversion method and device, equipment and medium Download PDFInfo
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Abstract
The application relates to a method, a device, equipment and a readable storage medium for converting an MDIO bus into a parallel bus, wherein the method comprises the following steps: the first CPU is used as a main device of the MDIO, and the second CPU is used as a slave device of the MDIO. Enabling the MDIO to parallel bus bridging function. The first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface of a parallel bus, and after the parallel bus is accessed, a result is sent back to the first CPU in an MDIO response mode. Thus, the first CPU indirectly accesses the DSP processor chip of the parallel interface in an MDIO mode. The MDIO driving of the first CPU does not need to be modified, the second CPU does not need to realize the support of the MDIO driving, and the conversion from MDIO to parallel buses can be realized only by the bridging function of the chip; the invention has simple realization and convenient operation.
Description
Technical Field
The present invention relates to the field of embedded driving, and in particular, to a method, an apparatus, a device, and a readable storage medium for converting an MDIO bus to a parallel bus.
Background
The computer bus is divided into a parallel bus and a serial bus, the parallel bus is provided with independent multiple address lines and multiple data lines, the external access speed is high, and the support of driving software is not needed. And the serial bus has few signal lines basically, and the CPU needs the support of driving software for accessing the peripheral equipment. In short, the software realizes a simple interface, and the hardware is complex; the simple interface of the hardware interface has certain requirements on the software drive. Many CPUs are now not provided with parallel bus interfaces in order to save chip costs.
Some special chips can only be accessed by a parallel bus, and if the current main control chip cannot provide a parallel interface, how to meet the design requirement of a product becomes a urgent need of a product developer.
Accordingly, the prior art is in need of improvement.
Disclosure of Invention
The invention provides a method for converting an MDIO bus into a parallel bus, a device, equipment and a readable storage medium, which are used for providing a method for indirectly accessing a DSP processor (digital signal processing) by using an MDIO (management data input output) bus to communicate with a second CPU with a parallel interface and transferring an MDIO request by the second CPU; the MDIO to parallel bus conversion can be realized only by the bridging function of the chip; the invention has simple realization and convenient operation.
An MDIO bus to parallel bus conversion method, wherein the method comprises:
connecting the first CPU with a second CPU, and connecting the second CPU with a DSP processor;
setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus;
the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode.
The MDIO bus-to-parallel bus conversion method, wherein the step of connecting the first CPU with the second CPU and the second CPU with the DSP processor comprises the following steps:
the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO respectively;
the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively.
The method for converting MDIO bus to parallel bus, wherein the first CPU accesses the MDIO expansion space of the second CPU through MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to the interface access DSP processor of the parallel bus, and when the parallel bus access is completed, the second CPU sends the result back to the first CPU in an MDIO response mode, the method comprises the following steps:
when the first CPU needs to indirectly access the DSP processor, firstly writing the internal address of the DSP processor into a parallel bus address register of the second CPU, and then reading the parallel bus data register of the second CPU through MDIO;
the second CPU knows the offset address of the first CPU to access the DSP processor from the parallel bus address register, takes out the register value of the offset address from the DSP processor, stores the register value into the parallel bus data register, and the first CPU starts the MDIO reading time sequence once again, thus obtaining the register value of the DSP processor.
The method for converting MDIO bus to parallel bus, wherein the step of setting the attribute of the slave device of the MDIO controller of the second CPU further comprises:
the MDIO controller provides two indirect registers for accessing the parallel bus, one parallel bus address register and one parallel bus data register.
The method for converting the MDIO bus into the parallel bus, wherein the step of setting the first CPU as the main device of the MDIO and the second CPU as the auxiliary device of the MDIO comprises the following steps:
configuring the width of an MDIO bus address bit of the second CPU, and selecting one of the three modes of 8/16/32;
the address range of the second CPU parallel bus chip select signal CS is set to 0xF 000-0000-0 xF000-FFFF, and the on-chip addressing space of the chip select CS is set to 0x10000 bytes.
The MDIO bus-to-parallel bus conversion method comprises the following steps of, when the input password is inconsistent with the preset password:
setting the bridging function enabling of the MDIO and the CS of the second CPU, wherein the address brought by the MDIO only needs to be the on-chip address of the CS.
An MDIO bus to parallel bus conversion device, wherein the device comprises: the system comprises a first CPU, a second CPU and a DSP processor;
the first CPU is connected with the second CPU, and the second CPU is connected with the DSP processor;
setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus;
the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode.
The MDIO bus-to-parallel bus conversion device is characterized in that the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO respectively;
the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively.
An apparatus comprising a memory storing a computer program and a processor, wherein the processor implements the steps of any of the methods when executing the computer program.
A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of any of the methods.
Compared with the prior art, the embodiment of the invention has the following advantages:
according to the method provided by the embodiment of the invention, the first CPU can only output one MDIO interface, the MDIO is provided with two signal lines, one is a clock MDC, and the other is a bidirectional data line MDIO. The second CPU is connected with the first CPU through MDIO, and the chip selection CS is connected with a DSP processor, wherein the DSP processor is 16-bit data width. The first CPU is used as a main device of the MDIO, and the second CPU is used as a slave device of the MDIO. The MDIO controller slave device attribute of the second CPU is set to enable the accessed address space to be covered to the chip selection space of the parallel bus, and meanwhile, the bridging function from the MDIO to the parallel bus is enabled. The first CPU accesses the MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space onto an interface of the parallel bus, and after the parallel bus is accessed, the result is sent back to the first CPU in an MDIO response mode.
Thus, the first CPU indirectly accesses the DSP processor chip of the parallel interface in an MDIO mode. The MDIO driving of the first CPU does not need to be modified, the second CPU does not need to realize the support of the MDIO driving, and the conversion from MDIO to parallel buses can be realized only by the bridging function of the chip; the invention has simple realization and convenient operation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a schematic diagram of an MDIO bus to parallel bus conversion device in the embodiment of the present invention.
Fig. 2 is a flow chart of a method for converting an MDIO bus to a parallel bus in an embodiment of the present invention.
Fig. 3 is a schematic diagram of MDIO timing sequence of an MDIO bus-to-parallel bus conversion method according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a second CPU initializing MDIO/parallel bus bridging flow of an MDIO bus to parallel bus conversion method according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a process of reading a DSP register R by a first CPU in an MDIO bus to parallel bus conversion method according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a process of writing a DSP register R by a CPU a in an MDIO bus to parallel bus conversion method according to an embodiment of the present invention.
Fig. 7 is an internal structural diagram of the apparatus in the embodiment of the present invention.
Detailed Description
In order to make the present invention better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The inventor finds that some existing special chips can only be accessed by a parallel bus, and if the current main control chip cannot provide a parallel interface, how to meet the design requirement of a product becomes a necessary thing for a product developer.
In order to solve the above-mentioned problems, in the embodiment of the present invention, a method is provided in which a first CPU without a parallel bus interface communicates with a second CPU with a parallel interface by using an MDIO (management data input output) bus, and the second CPU forwards an MDIO request to indirectly access a DSP processor (digital signal processing).
Various non-limiting embodiments of the present invention are described in detail below with reference to the attached drawing figures.
The implementation of the invention provides an MDIO bus to parallel bus conversion device, as shown in fig. 1, the device comprises: the system comprises a first CPU, a second CPU and a DSP processor;
the first CPU is connected with the second CPU, and the second CPU is connected with the DSP processor;
in the embodiment of the present invention, as shown in fig. 1, the first CPU is connected to the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO, respectively; the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively. Among them, MDIO (Management Data Input/Output), serial communication bus is called Management Data Input Output (MDIO).
In the embodiment of the invention, a first CPU is set as a main device of MDIO, and a second CPU is set as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus; in an embodiment of the invention, the MDIO controller provides two indirect registers for accessing the parallel bus, one is a parallel bus address register and the other is a parallel bus data register.
The first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode.
In the embodiment of the invention, when a first CPU needs to indirectly access a DSP processor, the internal address of the DSP processor is written into a parallel bus address register of a second CPU, and then the parallel bus data register of the second CPU is read through MDIO;
the second CPU knows the offset address of the first CPU to access the DSP processor from the parallel bus address register, takes out the register value of the offset address from the DSP processor, stores the register value into the parallel bus data register, and the first CPU starts the MDIO reading time sequence once again, thus obtaining the register value of the DSP processor.
Referring to fig. 2, fig. 2 shows a method for converting an MDIO bus to a parallel bus according to an embodiment of the present invention, where the method includes:
s1, connecting a first CPU with a second CPU, wherein the second CPU is connected with a DSP processor;
for example, the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected with the second CPU through a clock MDC line and a bidirectional data line MDIO respectively; the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively. The correct hardware connection is an important precondition for ensuring the proper functioning of the software protocol.
S2, setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; the MDIO controller slave device attribute of the second CPU is set to enable the accessed address space to be covered to the chip selection space of the parallel bus, and meanwhile, the bridging function from the MDIO to the parallel bus is enabled. The step sets the MDIO function of the second CPU correspondingly, so that the MDIO function of the second CPU can complete the function of automatic conversion.
S3, the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode. Thus, the MDIO bus to parallel bus function is completed.
When the first CPU needs to indirectly access the DSP processor, firstly writing the internal address of the DSP processor into a parallel bus address register of the second CPU, and then reading the parallel bus data register of the second CPU through MDIO;
the second CPU knows the offset address of the first CPU to access the DSP processor from the parallel bus address register, takes out the register value of the offset address from the DSP processor, stores the register value into the parallel bus data register, and the first CPU starts the MDIO reading time sequence once again, thus obtaining the register value of the DSP processor.
In one embodiment, the parallel bus bit width is typically three of 8 bits/16 bits/32 bits, a standard I2C timing is typically an address out with 8 bits at a time, an MDIO bus timing, a device address of 5 bits, and a register address of 5 bits, as shown in FIG. 3. The register of the parallel bus is typically 32 bits, but if only its on-chip offset address is taken, 8 or 16 bits are also required, depending on the size of the on-chip space. If 256 address spaces are inside the chip, only 8 bit offset addresses are needed, if 64KB address space is available, 16 bit offset addresses are needed, and above 64KB 32 bit addresses are needed.
The MDIO protocol is shown in fig. 3, where one 16-bit register can be read and written at a time. The 16-bit register data is treated as an address of the parallel bus, so that the access to the parallel bus can be realized only through two MDIOs. The MDIO controller provides two indirect registers for accessing the parallel bus, one parallel bus address register and one parallel bus data register.
The following is illustrated by specific examples:
when the first CPU needs to indirectly access the DSP, the internal address of the DSP is written into the parallel bus address register of the second CPU, which is 16 bits, and then the parallel bus data register of the second CPU is read through MDIO. The second CPU knows the offset address of the first CPU to access the DSP from the parallel bus address register, immediately takes out the register value of the offset address from the DSP, stores the register value into the parallel bus data register, and the first CPU starts the MDIO reading time sequence once again, thus obtaining the register value of the DSP.
Configuring the width of an MDIO bus address bit of the second CPU, selecting one of three modes 8/16/32, and configuring the mode as a 16-bit address mode currently;
setting the address range of the second CPU parallel bus chip selection CS1 to be 0xF 000-0000-0 xF000-FFFF, and setting the on-chip addressing space of the chip selection CS1 to be 0x10000 bytes, namely 64KB;
setting the bridging function between the MDIO of the second CPU and the CS1 to enable, wherein the address carried by the MDIO only needs to be the on-chip address of the CS1, namely, 0-0 xffff, and the address carried by the MDIO in the timing diagram 3 is carried twice;
the first CPU reads and writes all registers in the 0-0 xffff address space in the DSP with the MDIO timing in FIG. 3 above.
In the specific implementation, as shown in fig. 4, fig. 5 and fig. 6;
as shown in fig. 4, a bridging flow chart of the MDIO/parallel bus is initialized for the second CPU (CPU B);
as shown in figure 4 of the drawings,
step S41, initializing and starting a second CPU (CPU B); the initialization stage in the starting process is required to perform the following relevant configuration operations;
step S42, setting an MDIO slave address addr_dev; the address is used for communication with the first CPU;
step S43, setting the MDIO offset address of the parallel bus address register as addr_1; for specifying a DSP address bus;
step S44, setting the MDIO offset address of the parallel bus data register as addr_2; for specifying a DSP data bus;
step S45, setting the address range of the second CPU parallel bus chip selection CS1 to be 0 xF000-0000-0 xF000-FFFF, wherein the on-chip addressing space of the chip selection CS1 is 0x10000 bytes, namely 64KB; the register space of the DSP is mapped to the address range of 0xF 000-0000-0 xF000-FFFF of the second CPU;
step S46, enabling the bridging function from the MDIO to the chip selection CS 1; the address accessed is within this range, i.e. corresponds to accessing the DSP;
step S47, the initialization of the second CPU (CPU B) is completed, and the configuration work in the earlier stage is completed.
Fig. 5 is a schematic diagram of a process of reading a DSP register R by a first CPU in an MDIO bus to parallel bus conversion method according to an embodiment of the present invention.
The first CPU (CPU a) reads the DSP register R, and the flow thereof is shown in fig. 5;
step S51, a first CPU (CPU A) reads an R entry of a DSP register; the step is mainly used for calling the interface;
step S52, the first CPU (CPU A) writes the register of the second CPU (CPU B) through MDIO, wherein the device address addr_dev, the offset address addr_1 and the written data are 16-bit numerical values R; the first CPU accesses the second CPU through an MDIO protocol;
step S53, the second CPU (CPU B) receives the MDIO write command of the first CPU (CPU A) and writes the 16-bit numerical value R into a register addr_1; the second CPU processes according to the MDIO protocol;
step S54, the first CPU (CPU A) writes the register of the second CPU (CPU B) through MDIO, wherein the device address addr_dev and the offset address addr_2; the first CPU accesses the second CPU through an MDIO protocol read protocol;
in step S55, the second CPU (CPU B) receives the read request from the first CPU (CPU a) and finds the addr_1 register address, and requests the parallel bus timing sequence, and sends the value of the DSP register R back to the MIDO bus, and transmits the value to the first CPU (CPU a). The second CPU accesses the DSP according to the operation and returns the result to the first CPU;
when the first CPU is to write the DSP register R, the flow is shown in fig. 6;
step 61: the first CPU (CPU A) writes the entry of the DSP register R; calling an interface;
step 62: the first CPU writes a register of the second CPU (CPU B) through MDIO, wherein the device address addr_dev, the offset address addr_1 and the written data are 16-bit numerical values R; accessing a second CPU through an MDIO protocol;
step 63, the second CPU (CPU B) receives the MDIO write command of the first CPU (CPU A) and writes the 16-bit numerical value R into a register addr_1; the second CPU processes according to the MDIO protocol;
step 64, the first CPU writes the register of the second CPU (CPU B) through MDIO, wherein the device address addr_dev, the offset address addr_2 and the written data are 16-bit value; the first CPU accesses the second CPU through an MDIO protocol read protocol;
step 65, the second CPU (CPU B) writes the value into the register addr_2. And meanwhile, the current command is an MDIO write command, the parallel bus time sequence is requested, and the value is written into the DSP register R. The second CPU writes the value to the DSP register according to the operation;
step 65, the first CPU (CPU A) successfully writes the value into the DSP register R.
From the above, the present invention provides a method for a first CPU without parallel bus interface to communicate with a second CPU with parallel interface by using an MDIO (management data input output) bus, and for the second CPU to transfer an MDIO request to indirectly access a DSP processor (digital signal processing). Thus, the first CPU indirectly accesses the DSP processor chip of the parallel interface in an MDIO mode. The MDIO driving of the first CPU does not need to be modified, the second CPU does not need to realize the support of the MDIO driving, and the conversion from MDIO to parallel buses can be realized only by the bridging function of the chip; the invention has simple realization and convenient operation.
In one embodiment, the present invention provides a device, which may be a computer device, having an internal architecture as shown in FIG. 7. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a method of generating a natural language model. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the block diagram of fig. 7 is merely a partial structure related to the present application and does not constitute a limitation of the computer device to which the present application is applied, and that a specific computer device may include more or less components than those shown in the drawings, or may combine some components, or have a different arrangement of components.
The embodiment of the invention provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the following steps when executing the computer program:
connecting the first CPU with a second CPU, and connecting the second CPU with a DSP processor;
setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus;
the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode.
Wherein, the step of connecting the first CPU with the second CPU, and the second CPU with the DSP processor comprises:
the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO respectively;
the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively.
The step of the first CPU accessing the MDIO expansion space of the second CPU through the MDIO protocol, the MDIO inside the second CPU automatically mapping the read-write of the expansion space to the interface access DSP processor of the parallel bus, and after the parallel bus access is completed, the second CPU sending the result back to the first CPU in an MDIO response mode comprises the following steps:
when the first CPU needs to indirectly access the DSP processor, firstly writing the internal address of the DSP processor into a parallel bus address register of the second CPU, and then reading the parallel bus data register of the second CPU through MDIO;
the second CPU knows the offset address of the first CPU to access the DSP processor from the parallel bus address register, takes out the register value of the offset address from the DSP processor, stores the register value into the parallel bus data register, and the first CPU starts the MDIO reading time sequence once again, thus obtaining the register value of the DSP processor.
Wherein, the step of setting the attribute of the MDIO controller slave device of the second CPU further includes:
the MDIO controller provides two indirect registers for accessing the parallel bus, one parallel bus address register and one parallel bus data register.
The step of setting the first CPU as the main device of the MDIO and the second CPU as the auxiliary device of the MDIO comprises the following steps:
configuring the width of an MDIO bus address bit of the second CPU, and selecting one of the three modes of 8/16/32;
the address range of the second CPU parallel bus chip select signal CS is set to 0xF 000-0000-0 xF000-FFFF, and the on-chip addressing space of the chip select CS is set to 0x10000 bytes.
Wherein, when the input password is inconsistent with the preset password, the method comprises the following steps:
setting the bridging function enabling of the MDIO and the CS of the second CPU, wherein the address brought by the MDIO only needs to be the on-chip address of the CS.
In summary, compared with the prior art, the embodiment of the invention has the following advantages:
the method, the device, the equipment and the readable storage medium for converting the MDIO bus into the parallel bus provided by the embodiment of the application, wherein the method for converting the MDIO bus into the parallel bus comprises the following steps: receiving a password detection identifier; after receiving the password detection identifier, judging whether the input password is consistent with a preset password; when the input password is consistent with the preset password, the serial port input function is opened; and under the condition that the input password is inconsistent with the preset password, the serial port input function is closed. The serial port is controlled by the method, the safety of equipment is greatly improved, the protection of equipment information is enhanced, and the serial port information is prevented from being acquired by unauthorized personnel, so that the leakage of the equipment information is caused.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (7)
1. An MDIO bus to parallel bus conversion method, the method comprising:
connecting the first CPU with a second CPU, and connecting the second CPU with a DSP processor;
the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO respectively;
the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively;
setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus;
the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO in the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode;
when the first CPU needs to indirectly access the DSP processor, firstly writing the internal address of the DSP processor into a parallel bus address register of the second CPU, and then reading the parallel bus data register of the second CPU through MDIO;
the second CPU obtains the offset address of the DSP processor to be accessed by the first CPU from the parallel bus address register, takes out the register value of the offset address from the DSP processor, stores the register value into the parallel bus data register, and then starts an MDIO reading time sequence once again by the first CPU, so that the register value of the DSP processor can be obtained;
the first CPU reads and writes all registers in the 0-0 xffff address space in the DSP at MDIO timing.
2. The MDIO bus to parallel bus conversion method according to claim 1, wherein said step of setting an MDIO controller slave attribute of the second CPU further includes:
the MDIO controller provides two indirect registers for accessing the parallel bus, one parallel bus address register and one parallel bus data register.
3. The MDIO bus to parallel bus conversion method according to claim 1, wherein said step of setting the first CPU as a master device of the MDIO and the second CPU as a slave device of the MDIO includes:
configuring the width of an MDIO bus address bit of the second CPU, and selecting one of the three modes of 8/16/32;
the address range of the second CPU parallel bus chip select signal CS is set to 0xF 000-0000-0 xF000-FFFF, and the on-chip addressing space of the chip select CS is set to 0x10000 bytes.
4. The MDIO bus to parallel bus conversion method according to claim 1, wherein a password detection identifier is received; after receiving the password detection identifier, judging whether the input password is consistent with a preset password, and if not, including:
setting the bridging function enabling of the MDIO and the CS of the second CPU, wherein the address brought by the MDIO only needs to be the on-chip address of the CS.
5. An MDIO bus to parallel bus conversion apparatus, the apparatus comprising: the system comprises a first CPU, a second CPU and a DSP processor;
the first CPU is connected with the second CPU, and the second CPU is connected with the DSP processor;
the first CPU is connected with the second CPU through an MDIO interface, and the first CPU is connected to the second CPU through a clock MDC line and a bidirectional data line MDIO respectively;
the chip selection signal CS of the second CPU is connected with the DSP processor, and the second CPU is connected with the DSP processor through an address line addr, a data line data, the chip selection signal CS and a read-write control pin signal WE respectively;
setting a first CPU as a main device of MDIO and a second CPU as a slave device of MDIO; setting the attribute of the slave device of the MDIO controller of the second CPU, enabling the accessed address space to be covered to the chip selection space of the parallel bus, and enabling the bridging function from the MDIO to the parallel bus;
the first CPU accesses an MDIO expansion space of the second CPU through an MDIO protocol, the MDIO inside the second CPU automatically maps the read-write of the expansion space to an interface access DSP processor of a parallel bus, and after the parallel bus access is completed, the second CPU sends a result back to the first CPU in an MDIO response mode.
6. An apparatus comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any one of claims 1 to 4 when the computer program is executed.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7246192B1 (en) * | 2003-01-10 | 2007-07-17 | Marvell International Ltd. | Serial/parallel ATA controller and converter |
| CN103226533A (en) * | 2013-03-29 | 2013-07-31 | 福建星网锐捷通讯股份有限公司 | Device for extending MDIO (management data input/output) interface through parallel buses and realizing method thereof |
| CN109391604A (en) * | 2017-08-14 | 2019-02-26 | 深圳市中兴微电子技术有限公司 | A kind of bridge-set and management system managing data input and output agreement |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006101435A (en) * | 2004-09-30 | 2006-04-13 | Mitsubishi Electric Corp | Optical communication module |
| US7376780B2 (en) * | 2005-10-31 | 2008-05-20 | Lsi Corporation | Protocol converter to access AHB slave devices using the MDIO protocol |
| KR102584438B1 (en) * | 2017-11-13 | 2023-10-05 | 삼성전자주식회사 | Device for adjusting path of power and operation method thereof |
-
2019
- 2019-10-09 CN CN201910952365.7A patent/CN110765060B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7246192B1 (en) * | 2003-01-10 | 2007-07-17 | Marvell International Ltd. | Serial/parallel ATA controller and converter |
| CN103226533A (en) * | 2013-03-29 | 2013-07-31 | 福建星网锐捷通讯股份有限公司 | Device for extending MDIO (management data input/output) interface through parallel buses and realizing method thereof |
| CN109391604A (en) * | 2017-08-14 | 2019-02-26 | 深圳市中兴微电子技术有限公司 | A kind of bridge-set and management system managing data input and output agreement |
Non-Patent Citations (1)
| Title |
|---|
| I~2C Slave器件内部结构设计及VLSI实现;王岗等;《计算机工程与应用》;20070101(第01期);全文 * |
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