JP2007034668A - Layout method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a design required time by simplifying timing convergence for the design change(ECO) of a circuit after the layout of clock wiring. <P>SOLUTION: In a layout process S2, a library LIB1 including a driver 20 is used for layout. In a layout process S5, a driver LIB2 including a driver 30A whose output terminal Y2 is set as wiring inhibition is used for replacing the driver 20 in the final stage with the driver 30A. Afterwards, in a layout process S7, a library LIB3 including the driver 30B whose output terminal Y2 is set as wiring permission is used for replacing the driver 30A in the final stage with the driver 30B. Two types of available LIB2 and LIB3 are used for switching the reading of the available LIB2 and LIB3 according to the purpose of an ECO so that the layout of clock wiring can be set. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a layout method for laying out (placement and routing) clock wiring in a semiconductor integrated circuit such as a large-scale semiconductor integrated circuit (hereinafter referred to as “LSI”) using layout software, and in particular, to change the design of a circuit after layout ( The present invention relates to a clock wiring layout method in which a desired correction is performed while maintaining an existing timing relationship by reducing the correction range as much as possible when executing Engineering Change Order (hereinafter referred to as “ECO”). .

  For example, in LSI layout design, clock wiring is an important layout process that affects timing. Various methods of clock wiring have been studied, but recently, clock tree synthesis (Clock Tree Synthesis, hereinafter referred to as “CTS”) prepared by layout software is used. Has become the mainstream.

FIG. 13 is a circuit diagram showing an example of a clock connection state after a conventional CTS.
As shown in FIG. 13, for example, the CTS drives the clock signal CLK by the clock drivers 1, 2, and 3, while the terminal flip-flop circuits (hereinafter referred to as “F / F”) 4-1 to 4. -4 clock terminals 1, 2 and 3 are arranged in a tree structure (tree shape) to minimize the clock skew (Clockskew, phase shift) between F / Fs 4-1 to 4-4. Wiring. The number of fanouts (Fanout, hereinafter referred to as “F / O”) of the driver 3 that drives the terminal F / Fs 4-1 to 4-4 in FIG.

  This process is optimized by the layout software, and when performing ECO such as F / F addition generated after layout, it is necessary to perform automatic wiring by the layout software or manually correct the wiring. Although it is possible to implement ECO with minor modifications, timing convergence is difficult when performing ECO related to clock wiring, and the entire layout may be re-executed, greatly affecting design man-hours and costs.

  As a technique related to such a layout method, for example, there are those described in the following documents.

JP 2001-308186 A

The conventional layout method as shown in FIG. 13 has a problem as shown in FIG.
FIG. 14 is a circuit diagram showing an example of a clock connection state after ECO in FIG.

  In the conventional layout method, for example, as shown in FIG. 14, when ECO such as F / F addition after layout is performed, it is necessary to perform automatic wiring or manual wiring correction by layout software. In particular, when wiring to the added F / F 4-5, since the corrected clock wiring 5 is newly extended from the nearby clock driver 3 and connected, the timing that has been passed so far (OK). However, there is a case in which a failure (NG) occurs due to an increase in F / O (4 + 1) of the driver 3 due to the addition of F / F 4-5. If this happens, it will be necessary to perform subtle timing adjustments around the added F / F4-5, and it will be necessary to re-execute CTS and redo the worst layout, such as adjusting the drive capability of the related driver 3. The time required (Turn Around Time, hereinafter referred to as “TAT”) was greatly affected.

  The present invention provides a layout library data including a first driver and a second driver in a layout method in which clock wiring is performed by layout software, and includes a first layout step and a second layout step. And a correction process.

  Here, the first driver has a first input terminal and a first output terminal, and drives a clock signal input from the first input terminal and is a driven clock signal delayed by a predetermined time t. Are output from the first output terminal. The second driver includes a second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and one corresponding to the second output terminal or A plurality of third output terminals, and driving the clock signal input from the second input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the second output terminal and the second output terminal; The signals are output from the third output terminals.

  Then, in the first layout step, the first drivers are arranged at a plurality of locations based on the first circuit diagram data, and the first input terminals and the first drivers in the plurality of first drivers are arranged. The second circuit diagram data is created by performing the clock wiring in a tree shape using one output terminal. In the second layout step, in the second circuit diagram data, the first driver at the final stage in the vicinity of a place where an element that operates by the clock signal is expected to be added is changed by the second driver. Based on the replaced third circuit diagram data, a fourth circuit diagram data is created by performing the clock wiring in a tree shape using the second input terminal and the second output terminal in the second driver. To do. Thereafter, in the correction step, when the element needs to be added, the second driver located in the vicinity of the element is searched, and the corrected clock wiring is searched from the third output terminal of the second driver. Is pulled out and connected to the element.

  In another layout method of the present invention, the following processing is performed in the second layout step and the correction step. That is, in the second layout step, the second driver replaces the first driver in the second circuit diagram data in the vicinity of a place where an element to be operated by the clock signal is expected to be added. Based on the third circuit diagram data, the fourth wiring diagram data is created by performing the clock wiring in a tree shape using the second input terminal and the second output terminal in the second driver. . Thereafter, in the correction step, when the element needs to be added, the second driver located in the vicinity of the element is searched, and the corrected clock wiring is connected from the third output terminal of the second driver. Pull out and connect to the element.

  According to the layout method of the present invention, when an element needs to be added, the second driver in the final stage located in the vicinity of this element is searched for and corrected from the third output terminal of the second driver. The clock wiring is drawn out and connected to the element. Therefore, when the correction related to the clock wiring is performed after the layout is completed, the timing convergence can be realized with a short TAT.

  According to another layout method of the present invention, when an element needs to be added, a second driver at an arbitrary stage located in the vicinity of the element is searched, and a third output of the second driver is obtained. The corrected clock wiring is drawn from the terminal and connected to the element. Therefore, after the layout is completed, if the correction required is related to the clock wiring, the second driver in the final stage is not used, but any stage (in the vicinity of the additional element) ( For example, since the clock wiring is performed using the second driver located at the upper stage), it is possible to achieve timing convergence with a short TAT while shortening the delay time. .

  The best mode for carrying out the present invention is to prepare layout library data including a first driver and a second driver in a layout method in which clock wiring is performed by layout software. Here, the first driver has a first input terminal and a first output terminal, and drives a clock signal input from the first input terminal and is a driven clock signal delayed by a predetermined time t. Is output from the first output terminal. The second driver has a second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and a first output terminal corresponding to the second output terminal. Two or more third output terminals, and driving the clock signal input from the second input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the second output terminal And the third output terminal.

  First, in the first layout step, based on the first circuit diagram data, the first drivers are arranged at a plurality of locations, and each of the first input terminals and each of the plurality of first drivers are arranged. The clock wiring is performed in a tree structure using the first output terminal to generate second circuit diagram data. Next, in the second layout step, in the second circuit diagram data, the first driver in the vicinity of a place where an element that operates by the clock signal is expected to be replaced is replaced with the second driver. Based on the third circuit diagram data, the fourth wiring diagram data is created by performing the clock wiring in a tree shape using the second input terminal and the second output terminal in the second driver. . Thereafter, in the correction step, when the element needs to be added, the second driver located in the vicinity of the element is searched, and the corrected clock wiring is connected from the third output terminal of the second driver. It is pulled out and connected to the element.

(Device of Example 1)
FIG. 3 is a schematic configuration diagram showing the layout apparatus used in the first embodiment of the present invention.

  The layout apparatus 10 includes a layout apparatus body 11 configured by a central processing unit (hereinafter referred to as “CPU”) that executes layout software including CTS. The layout apparatus main body 11 includes a library storage means 12 such as a hard disk (hereinafter referred to as “HD”) for storing layout library data, and a netlist storage such as an HD for storing a netlist which is circuit diagram data. Means 13, an input device 14 such as a keyboard and a mouse for inputting data, a display device 15 for displaying data, and the like are connected.

  4A to 4C are schematic circuit diagrams illustrating the clock driver used in the first embodiment of the present invention.

  The first driver 20 for clock shown in FIG. 4A has a first input terminal A and a first output terminal Y1, and two input terminals A and B are provided between the input terminal A and the output terminal B. Signal inversion inverters 21 and 22 are connected in series. The driver 20 is a circuit that inverts and drives the clock signal CLK input from the input terminal A by the inverter 21 and further inverts and drives it by the inverter 22 and outputs a driven clock signal delayed by a predetermined time t from the output terminal Y1. The library data for layout of this circuit is stored in the library storage means 12 of FIG.

  The second driver 30A for clock shown in FIG. 4B has a second input terminal A, a second output terminal Y1, and a third output terminal Y2 set to wiring prohibition. Two signal inverting inverters 31 and 32 are connected in series between the terminal A and the output terminal Y1, and further, the signal inverting inverter 33 is connected between the output terminal of the inverter 31 and the output terminal Y2. Is a 1-input 2-output driver. The driver 30A inverts and drives the clock signal CLK input from the input terminal A by the inverter 31 and further inverts and drives it by the inverters 32 and 33, and outputs the driven clock signal delayed by a predetermined time t to each output terminal. This is a circuit given to Y1 and Y2, and the library data for layout of this circuit is stored in the library storage means 12 of FIG.

  In the driver 30A, the transmission delay time t of the clock signal CLK from the input terminal A to the output terminal Y1 and the transmission delay time t of the clock signal CLK from the input terminal A to the output terminal Y2 are from the input terminal A in the driver 20. It is designed to be the same as the transmission delay time t of the clock signal CLK to the output terminal Y1. The position of the output terminal Y1 of the driver 30A in the layout is designed to be the same position as the output terminal Y1 of the driver 20. Also, the area of the driver 30A in the layout is designed to be the same as the area of the driver 20. For the output terminal Y2 set to wiring prohibition, for example, a wiring prohibition object is set so as to cover the output terminal Y2 portion, and the layout tool executes wiring there to prevent erroneous wiring and the like. I can't do it.

  The third driver 30B for clock shown in FIG. 4C has a third input terminal A, a fourth output terminal Y1, and a fifth output terminal Y2 set to allow wiring. Two signal inverting inverters 31 and 32 are connected in series between the terminal A and the output terminal Y1, and further, the signal inverting inverter 33 is connected between the output terminal of the inverter 31 and the output terminal Y2. Is a 1-input 2-output driver. The driver 30B has a circuit configuration similar to that of the driver 30A, but differs from the driver 30A only in that the output terminal Y2 is set to permit wiring, and the layout library data of this circuit is the library storage means 12 of FIG. Stored in For example, the output terminal Y2 set to permit wiring in the driver 30B is obtained by removing the wiring prohibition object that covers the output terminal Y2 portion in the driver 30A, so that wiring to the output terminal Y2 can be executed by the layout tool. It has become.

  The feature of the first embodiment is that the drivers 20, 30A, 30B are prepared, and the output terminals Y1 of the drivers 20, 30A are used in the normal layout, and the elements (for example, F / F) generated after the layout whose timing is determined. For the correction by adding, the correction clock wiring to the additional F / F can be automatically corrected by the layout software or manual correction to the additional F / F using the output terminal Y2 of the driver 30B. It is possible to make corrections without affecting other timings. Thereby, the area increases due to the configuration of the drivers 30A and 30B, but when there is an ECO related to the clock wiring, there is an advantage that the timing convergence becomes easy and the design TAT is shortened.

(Layout Method of Example 1)
FIG. 1 is a flowchart showing a clock wiring layout method according to the first embodiment of the present invention. 5 is a circuit diagram showing an example of the netlist Net2 in FIG. 1, FIG. 6 is a circuit diagram showing an example of the netlist Net3 in FIG. 1, and FIG. 7 is an example of the netlist Net5 in FIG. FIG.

  In the clock wiring layout method according to the first embodiment, layout processing (steps S1 to S8) is performed under the control of the layout apparatus main body 11 that executes layout software.

  When the layout process is started, the layout apparatus body 11 reads the first netlist Net1 which is the circuit diagram data stored in the netlist storage unit 13 (step S1) and stores it in the library storage unit 13. The layout library LIB1 including the driver 20 of FIG. 4 is read out, and the first layout step S2 is performed. In this layout step S2, placement is executed according to the netlist Net1 (step S2-1), and then CTS is performed (step S2-2). The CTS execution result is output as a second netlist Net2 which is an example of circuit diagram data as shown in FIG. 5 reflecting this (step S3) and stored in the netlist storage means 13.

  In the netlist Net2 of FIG. 5, the input terminals A of the plurality of drivers 20 in the second stage are connected to the output terminal Y1 of the driver 20 in the first stage that drives the clock signal CLK, and each of the drivers 20 in the second stage is connected. Clock wiring is formed in a tree shape such that the output terminals Y1 are connected to the input terminals A of a plurality of drivers 20 in the third stage. A plurality of elements (for example, F / F) 40-1 to 40-4,... Operated by the clock signal CLK are respectively connected to the output terminals Y1 of the plurality of drivers 20 of the final stage EN1 surrounded by a one-dot chain line. It is connected. For example, the number of F / 0s of the final stage driver 20 that supplies the clock signal CLK to the four F / Fs 40-1 to 40-4 in FIG.

  The netlist Net2 is modified as shown in FIG. 6 by referring to the structure information of the CTS so that the layout device body 11 replaces the plurality of drivers 20 in the final stage EN1 shown in the netlist Net2 of FIG. 5 with the driver 30A. Then, the modified third netlist Net3 of FIG. 6 is stored in the netlist storage means 13. The netlist Net3 is layout circuit diagram data obtained by replacing and correcting the netlist Net2 output from the layout process (step S2) from the driver 20 at the final stage to the driver 30A. The reason for replacing only the final stage driver 20 is that it is likely to be used after the layout is completed. Even if it is desired to apply to other CTS levels based on past experience or the like, it is possible to perform similar net correction at the necessary CTS level.

  Next, in the second layout step (step S5), the layout apparatus body 11 stores the library LIB2 including the drivers 20 and 30A of FIG. 4 stored in the library storage unit 12 and the netlist storage unit 13. The net list Net3 is read (step S5-1), and detailed wiring is performed (step S5-2). In the driver 30A added here, since the output terminal Y2 is prohibited from wiring, wiring from the output terminal Y1 to the F / Fs 40-1 to 40-4,... Is performed. Since the output terminal Y1 is at the same position as the output terminal Y1 of the replaced driver 20, there is no difference in the detailed wiring plan in the layout, so that there is no difference in timing. The wiring result of this layout step (step S5) is output as the fourth netlist Net4 and stored in the netlist storage means 13 (step S6).

  After the netlist Net4 is stored, the layout device body 11 performs a third layout process (step S7). In the layout process (step S7), the layout apparatus body 11 determines whether or not the operator has requested the ECO process from the input device 14 (step S7-1). When the determination result is no request, a standard delay format (Standard Delay Format, hereinafter referred to as “SDF”), which is timing information, is output, and the layout processing by the layout apparatus body 11 ends.

  When the determination result in step S7-1 is requested, the layout device main body 11 replaces the driver 30A described in the netlist Net4 with a driver 30B considering ECO (step S7-2). The replaced fifth netlist Net5 as shown in FIG. 7 is stored in the netlist storage means 13. The difference between the driver 30A and the driver 30B is that the wiring attribute of the output terminal Y2 is prohibited in the driver 30A, and the wiring attribute of the output terminal Y2 is permitted in the driver 30B. This is because the output terminal Y2 of the driver 30B is used as a new driver output at the time of correction after completion of the layout.

  The layout apparatus body 11 determines whether or not an F / F has been added from the input device 14 by the operator (step S7-3). When no determination result is added, SDF data as timing information is output, and the layout processing by the layout apparatus body 11 ends.

  When the determination result in step S7-3 is added, the layout apparatus body 11 causes the library LIB3 including the driver 20 and the driver 30B stored in the library storage unit 13 and the netlist stored in the netlist storage unit 13 to be included. Net5 is read and an ECO process as a correction process is performed (step S7-4). In the ECO processing, the driver 30A that is the same in the layout structure is replaced with the driver 30B, and correction processing is performed. When the driver 30A is replaced with the driver 30B, other layout data is not affected. As the final layout result, the sixth netlist Net6 and the SDF data as timing information are output (step S8), and the layout process ends.

  2 is a flowchart showing the ECO processing in FIG. 1, and FIG. 8 is a diagram showing timing adjustment of the ECO processing in FIG. Note that steps S14 and S15 in FIG. 2 and the delay adjustment element 50 in FIG. 8 constitute a delay adjustment means.

  When the ECO processing (step S7-4) in FIG. 2 is started, the layout apparatus main body 11 reads the library LIB3 stored in the library storage means 13 and the netlist Net5 stored in the netlist storage means 13. Then, the driver 30A that is the same in the layout structure is replaced with the driver 30B (step S10). When a new F / F needs to be added, the layout apparatus main body 11 searches (searches) the ECO spare F / F 40-5 shown in FIG. The CTS driver 30B that uses the clock signal CLK is searched (step S12). The layout apparatus body 11 calculates the delay time when the F / F 40-5 added by ECO is connected using the found ETS output terminal Y2 of the CTS driver 30B, and the calculated value satisfies the timing constraint. It is confirmed whether or not (steps S12 and S13). When the timing constraint is satisfied (step S13), the ECO process is terminated.

  When the timing constraint is not satisfied (step S13), it is determined whether or not the delay time is larger than the allowable value (step S14). When the determination result is large, the process returns to step S11. When the determination result is small, delay adjustment is performed by using spare cells such as nearby drivers and inverters embedded in advance as the delay adjustment element 50 (step S15), and the process returns to step S13 to determine whether timing constraints are satisfied. Determine whether. When the tamming constraint is satisfied, the ECO process ends.

  As described above, when a new F / F needs to be added around the F / F connection in the CTS configuration diagram, the corrected clock wiring 35 is drawn out from the output terminal Y2 of the driver 30B in the vicinity to add the F / F 40. Connect to -5 clock terminal. When delay adjustment is performed at this time, it can be performed only with this wiring, so that it does not affect the other F / Fs 40-1 to 40-4,.

(Effect of Example 1)
According to the first embodiment, there are the following effects (a) to (d).

  (A) Since the F / F addition correction related to the clock wiring after the layout is completed is connected to the additional F / F 40-5 using the output terminal Y2 of the driver 30B of the last stage replaced. It is possible to achieve timing convergence with a short TAT without affecting the other F / Fs 40-1 to 40-4,.

  (B) Since the delay adjustment during the ECO processing is performed by using a spare cell such as a driver or an inverter embedded in the vicinity of the ECO correction location as the delay adjustment element 50, the delay adjustment can be easily performed. it can.

  (C) After laying out using the library LIB1 including the driver 20 and replacing the final stage driver 20 with the driver 30A using the library LIB2 including the driver 30A in which the output terminal Y2 is set to wiring prohibition, the output terminal Since the last stage driver 30A is replaced by the driver 30B using the library LIB3 including the driver 30B in which Y2 is set to permit wiring, erroneous wiring or the like at the output terminal Y2 can be prevented. In addition, two types of library LIB2 including a driver 30A in which the output terminal Y2 is set to wiring prohibition and library LIB3 including a driver 30B in which the output terminal Y2 is set to wiring permission are prepared. Since the clock wiring layout is performed by switching the reading of LIB2 and LIB3, the drivers 30A and 30B can be easily replaced using layout software with a simple configuration.

  (D) As another method of the first embodiment, if the wiring prohibition setting and the wiring permission setting are switched by the layout software or the like for the output terminal Y2 of the driver 30A, one type of driver 30A is used. Thus, the last stage driver 20 can be replaced, so that the number of layout steps can be reduced.

(Equipment of Example 2)
The second embodiment of the present invention uses the layout device 10 and the libraries LIB1, LIB2, and LIB3 of the first embodiment and executes a layout method different from that of the first embodiment to perform a clock wiring layout method. .

  That is, in the first embodiment, the driver 20 in FIG. 4A at the final stage of the CTS is replaced with the driver 30A in FIG. 4B. However, in the second embodiment, a driver of any level of the CTS is used. 20 is replaced by a driver 30A to further facilitate delay adjustment.

(Layout Method of Example 2)
9 is a circuit diagram showing an example of the netlist Net3 in FIG. 1 according to the second embodiment of the present invention. FIG. 10 is a circuit diagram showing an example of the netlist Net5 in FIG. 1 according to the second embodiment of the present invention. is there.

  In the layout method of the second embodiment, in the flowchart of FIG. 1, any of the drivers 20 in the second stage and the final stage is compared with the netlist Net2 in FIG. 5 showing the CTS result of the first layout step S2. The driver 20 is replaced with a driver 30A as shown in FIG. 9 to create a netlist Net3.

  Next, as in the first embodiment, the second layout step S5 is performed, and it is determined whether or not ECO processing is necessary in the third layout step S7 for the netlist Net4 output as a result ( Step S7-1) When the ECO processing is necessary, as shown in FIG. 10, the driver 30A is replaced with the driver 30B to create a netlist Net5 (step S7-2). Thereafter, it is determined whether or not an F / F is added (step S7-3), and when there is an addition, an ECO process is performed (step S7-4).

  FIG. 11 is a flowchart showing the ECO process (step S7-4) in FIG. 1 according to the second embodiment of the present invention. Elements common to the elements in FIG. ing. FIG. 12 is a diagram illustrating timing adjustment of the ECO process (step S7-4) in FIG. 1 according to the second embodiment of the present invention. Note that steps S14, S15, and S20 in FIG. 11 and the delay adjustment element 51 in FIG. 12 constitute a delay adjustment means.

  The ECO process (step S7-4) of FIG. 11 of the second embodiment is different only in that step S20 is added to FIG. 2 of the first embodiment.

  That is, when the ECO process (step S7-4) in FIG. 11 is started, the library LIB3 stored in the library storage means 13 and the netlist storage means 13 are stored by the layout apparatus body 11 as in FIG. The read netlist Net5 is read, and the driver 30A that is the same in the layout structure is replaced with the driver 30B (step S10). When it is necessary to add a new F / F, the layout apparatus main body 11 searches for an ECO spare F / F 40-5 near the final stage shown in FIG. The CTS driver 30B using the clock signal CLK is searched (step S12). The layout apparatus body 11 calculates the delay time when the F / F 40-5 added by ECO is connected using the found ETS output terminal Y2 of the CTS driver 30B, and the calculated value satisfies the timing constraint. It is confirmed whether or not (steps S12 and S13). When the timing constraint is satisfied (step S13), the ECO process is terminated.

  When the timing constraint is not satisfied (step S13), it is determined whether or not the delay time is larger than the allowable value (step S14). When the determination result is large, the CTS driver 30B that is one level higher in the vicinity of the correction point is selected. Search and return to the process of step S11. When the determination result is small, delay adjustment is performed using a spare cell such as a nearby driver or inverter embedded in advance as the delay adjustment element 51 (step S15), and the process returns to step S13 to determine whether the timing constraint is satisfied. Determine whether. When the tamming constraint is satisfied, the ECO process ends.

  As described above, in the second embodiment, when the delay at the time of ECO correction is large, the CTS driver 30B that is one level higher than the CTS driver 30B in the final stage is used instead of the CTS driver 30B in the final stage. The corrected clock wiring 36 is connected from the output terminal Y2 to the clock terminal of the additional F / F 40-5.

(Effect of Example 2)
The second embodiment has the following effects (a) to (c).

  (A) In the first embodiment, the F / F addition correction related to the clock wiring after the layout is completed is connected to the additional F / F 40-5 using the output terminal Y2 of the driver 30B at the last stage replaced. ing. However, if the output of the last stage driver 30B is used, it may be difficult to make it shorter than the conventional clock delay to the end. The reason is that when the F / F 40-5 to be added is not near the correction portion, the F / F located far away is used, so that the delay from the final stage driver 30B increases. is there. In this case, as in the second embodiment, if the corrected clock wiring 36 is connected from the driver 30B one level higher than the final stage, the delay that cannot be achieved in the final stage can be shortened, and the TAT can be shortened. Timing convergence can be realized.

  (B) As another method of the second embodiment, if the modified clock wiring 36 is connected from the driver 30B at an arbitrary level instead of the driver 30B one level higher than the final stage, the effect is greater.

(C) As another method of the second embodiment, as in the first embodiment, if the wiring prohibition setting and the wiring permission setting are switched by the layout software or the like for the output terminal Y2 of the driver 30A, Since the driver 20 can be replaced by using one type of driver 30A, the number of layout processes can be reduced.

  In addition, this invention is not limited to the said Example 1, 2, The various deformation | transformation is possible. Examples of this modification include the following (1) to (3).

(1) The drivers 30A and 30B are not limited to the one-input and two-output type, and may be one having a structure that outputs three or more by one input, thereby further improving the degree of freedom in design. To do. Further, the configuration of the drivers 20, 30A, 30B is not limited to two inverter stages, but may be configured in other stages, or may be configured using other elements such as a buffer gate.
(2) The element driven by the clock signal CLK may be an element other than the F / F.
(3) The processing of FIGS. 1, 2, and 11 may be changed to other processing contents.

It is a flowchart which shows the layout method of the clock wiring of Example 1 of this invention. It is a flowchart which shows the ECO process in FIG. It is a schematic block diagram which shows the layout apparatus used in Example 1 of this invention. 1 is a schematic circuit diagram illustrating a clock driver used in Embodiment 1 of the present invention. It is a circuit diagram which shows an example of netlist Net2 in FIG. It is a circuit diagram which shows an example of netlist Net3 in FIG. It is a circuit diagram which shows an example of netlist Net5 in FIG. It is a figure which shows the timing adjustment of the ECO process in FIG. It is a circuit diagram which shows an example of netlist Net3 in FIG. 1 of Example 2 of this invention. It is a circuit diagram which shows an example of netlist Net5 in FIG. 1 of Example 2 of this invention. It is a flowchart which shows the ECO process in FIG. 1 of Example 2 of this invention. It is a figure which shows the timing adjustment of the ECO process in FIG. 1 of Example 2 of this invention. It is a circuit diagram which shows an example of the clock connection state after the conventional CTS. It is a circuit diagram which shows an example of the clock connection state after ECO of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Layout apparatus 11 Layout apparatus main body 12 Library storage means 13 Net list storage means 14 Input device 15 Display device 20, 30A, 30B Driver 40-1 to 40-5 F / F

Claims (7)

In the layout method in which clock wiring is performed by layout software,
A first input terminal and a first output terminal are provided, a clock signal input from the first input terminal is driven, and a driven clock signal delayed by a predetermined time t is output from the first output terminal. A first driver;
A second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and one or more third output terminals corresponding to the second output terminal And driving the clock signal input from the second input terminal to delay the plurality of driven clock signals delayed by the predetermined time t from the second output terminal and the third output terminal, respectively. A second driver to output;
Prepare library data for layout that includes
Based on the first circuit diagram data, the first drivers are arranged in a plurality of places, and each of the first input terminals and the first output terminals in the plurality of first drivers is used to form a tree structure. A first layout step of generating second circuit diagram data by performing the clock wiring,
In the second circuit diagram data, third circuit diagram data obtained by replacing the first driver in the final stage in the vicinity of a portion where an element to be operated by the clock signal is expected to be added with the second driver. And a second layout step of creating fourth circuit diagram data by performing the clock wiring in a tree structure using the second input terminal and the second output terminal in the second driver, ,
When it is necessary to add the element, the second driver located in the vicinity of the element is searched, and the corrected clock wiring is drawn from the third output terminal of the second driver and connected to the element. A correction process to
A layout method characterized by comprising: In the layout method in which clock wiring is performed by layout software,
A first input terminal and a first output terminal are provided, a clock signal input from the first input terminal is driven, and a driven clock signal delayed by a predetermined time t is output from the first output terminal. A first driver;
A second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and one corresponding to the second output terminal and set to wiring prohibition or A plurality of third output terminals, and driving the clock signal input from the second input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the second output terminal and the second output terminal; A second driver applied to each of the third output terminals;
A third input terminal corresponding to the second input terminal, a fourth output terminal corresponding to the second output terminal, and one corresponding to the third output terminal and set to wiring permission or A plurality of fifth output terminals, and driving the clock signal input from the third input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the fourth output terminal and the A third driver that outputs from each of the fifth output terminals;
Prepare library data for layout that includes
Based on the first circuit diagram data, the first drivers are arranged in a plurality of places, and each of the first input terminals and the first output terminals in the plurality of first drivers is used to form a tree structure. A first layout step of generating second circuit diagram data by performing the clock wiring,
In the second circuit diagram data, third circuit diagram data obtained by replacing the first driver in the final stage in the vicinity of a portion where an element to be operated by the clock signal is expected to be added with the second driver. And a second layout step of creating fourth circuit diagram data by performing the clock wiring in a tree structure using the second input terminal and the second output terminal in the second driver, ,
It is determined whether or not a design change is necessary. When the determination result indicates that the design is not necessary, the layout processing is terminated. When the determination result indicates that the design is necessary, the second driver in the fourth circuit diagram data is determined. Based on the fifth circuit diagram data replaced by the third driver, it is determined whether or not the element is added. When the determination result indicates that there is no addition, the layout process is terminated, and the determination result indicating that there is an addition. In this case, the clock wiring is performed in a tree structure using the third input terminal and the fourth output terminal in the third driver, and the third driver located in the vicinity of the element is searched. A third layout step of creating sixth circuit diagram data in which the modified clock wiring is drawn out from the fifth output terminal of the third driver and connected to the element;
A layout method characterized by comprising:   The second driver is a one-input two-output driver, and has an area the same as that of the first driver, and the second output terminal is the first driver of the first driver. The layout method according to claim 1, wherein the layout method is arranged at the same position as the one output terminal. In the layout method in which clock wiring is performed by layout software,
A first input terminal and a first output terminal are provided, a clock signal input from the first input terminal is driven, and a driven clock signal delayed by a predetermined time t is output from the first output terminal. A first driver;
A second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and one or more third output terminals corresponding to the second output terminal And driving the clock signal input from the second input terminal to delay the plurality of driven clock signals delayed by the predetermined time t from the second output terminal and the third output terminal, respectively. A second driver to output;
Prepare library data for layout that includes
Based on the first circuit diagram data, the first drivers are arranged in a plurality of places, and each of the first input terminals and the first output terminals in the plurality of first drivers is used to form a tree structure. A first layout step of generating second circuit diagram data by performing the clock wiring,
In the second circuit diagram data, based on third circuit diagram data in which the first driver in the vicinity of a place where an element that operates by the clock signal is expected to be added is replaced by the second driver. A second layout step of creating fourth circuit diagram data by performing the clock wiring in a tree structure using the second input terminal and the second output terminal in the second driver;
When it is necessary to add the element, the second driver located in the vicinity of the element is searched, and the corrected clock wiring is drawn from the third output terminal of the second driver and connected to the element. A correction process to
A layout method characterized by comprising: In the layout method in which clock wiring is performed by layout software,
A first input terminal and a first output terminal are provided, a clock signal input from the first input terminal is driven, and a driven clock signal delayed by a predetermined time t is output from the first output terminal. A first driver;
A second input terminal corresponding to the first input terminal, a second output terminal corresponding to the first output terminal, and one corresponding to the second output terminal and set to wiring prohibition or A plurality of third output terminals, and driving the clock signal input from the second input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the second output terminal and the second output terminal; A second driver applied to each of the third output terminals;
A third input terminal corresponding to the second input terminal, a fourth output terminal corresponding to the second output terminal, and one corresponding to the third output terminal and set to wiring permission or A plurality of fifth output terminals, and driving the clock signal input from the third input terminal to drive the plurality of driven clock signals delayed by the predetermined time t to the fourth output terminal and the A third driver that outputs from each of the fifth output terminals;
Prepare library data for layout that includes
Based on the first circuit diagram data, the first drivers are arranged in a plurality of places, and each of the first input terminals and the first output terminals in the plurality of first drivers is used to form a tree structure. A first layout step of generating second circuit diagram data by performing the clock wiring,
In the second circuit diagram data, based on third circuit diagram data in which the first driver in the vicinity of a place where an element that operates by the clock signal is expected to be added is replaced by the second driver. A second layout step of creating fourth circuit diagram data by performing the clock wiring in a tree structure using the second input terminal and the second output terminal in the second driver;
It is determined whether or not a design change is necessary. When the determination result indicates that the design is not necessary, the layout processing is terminated. When the determination result indicates that the design is necessary, the second driver in the fourth circuit diagram data is determined. Based on the fifth circuit diagram data replaced by the third driver, it is determined whether or not the element is added. When the determination result indicates that there is no addition, the layout process is terminated, and the determination result indicating that there is an addition. In this case, the clock wiring is performed in a tree structure using the third input terminal and the fourth output terminal in the third driver, and the third driver located in the vicinity of the element is searched. A third layout step of creating sixth circuit diagram data in which the modified clock wiring is drawn out from the fifth output terminal of the third driver and connected to the element;
A layout method characterized by comprising: The second driver is a one-input two-output driver, and has an area the same as that of the first driver, and the second output terminal is the first driver of the first driver. 1 is arranged at the same position as the output terminal,
The third driver is a one-input two-output driver, and has the same area as the second driver, and the fourth and fifth output terminals are the second driver. 6. The layout method according to claim 4, wherein the layout method is arranged at the same position as the second and third output terminals.   7. An adjustment means for calculating a clock signal transmission delay time up to the element connected to the corrected clock wiring and adjusting the delay with respect to the calculated value is provided. The layout method according to the item.

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