JP2007011243A - Method of controlling display on multiple screens - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the development cost of equipment by enabling the software designing, without having to consider the timing, by simplifying the circuit configurations in an image display device with multiple screens and improving their operation speed. <P>SOLUTION: The image memory is built in hardware and stores fixed image data. This image memory is automatically divided into addresses on the X-axis an Y-axis, to enable display of multiple images at the same time. The driver of this image memory is connected to various display units. The overall images and the divided images in the memory are displayed, as desired, by taking into consideration their applications to game machines. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a configuration and a control method for efficiently and inexpensively displaying multi-screen images such as information home appliances, OA devices, game machines, and toys.

  Electronic displays are not just devices, but now constitute systems and modules that include drive circuits, light sources or optical systems. For this reason, there are a wide variety of display evaluation methods.

  Examples include mechanical structure, display contents, optical characteristics, display method, reliability and life, electrical drive characteristics, and interactive characteristics. The interaction characteristic is a user interface and includes a light pen, a touch entry, and a voice response.

  The electronic display has a display content memory, a drive circuit, and a CPU (Central Processing Unit). The CPU is configured with an image memory and a driver circuit for each display unit. When a plurality of images are displayed, a video output device is required for each display device in order to cause each display device to output an image.

  In recent years, various types of high-quality electronic displays are used for information appliances, game machines, and game machines. Both are the reasons for being in the main industry in Japan. It is a medium that conveys letters, numbers, pictures, images, symbols, etc. to our users.

  Looking at the development of electronic displays, historically, the theory of atomic and molecular theory and the development of solid-state electronic theory, followed by the discovery of the principle of operation, was technically realized. As a display method, direct view, projection (prOjection), and holography are typical.

  The classification according to the operation mechanism of the display includes a light emitting type (emissive, active) and a non-light emitting type (passive). The light emitting type includes CRT (CRT), LED (light emitting diode), PDP (plasma panel), ELP (electroluminescence) and the like. A typical example of the non-light emitting type is an LCD (liquid crystal display).

In recent years, remarkable progress of electronic displays has exerted great effects on information home appliances, OA equipment, game machines, and toys. Especially in game machines and game machines, the electronic display is an important product factor.
JP 2002-277958 A "Transistor Technology February 2004 issue", CQ Publisher

  The problem to be solved is that when these electronic displays are applied to a game machine or a game machine, the number of the displays increases, and accordingly, peripheral circuit devices increase and the cost increases.

  Furthermore, there are the following problems. When an electronic display is used, the circuit functions including the CPU, the display unit, and the timing must be accurately defined. The content of the display changes from moment to moment, and the design of the circuit function corresponding to this changes becomes complicated.

  In addition, since there are many display units depending on the game device, setting of the circuit device and the synchronization timing requires a lot of delicate work including a program.

  In the present invention, in order to solve the above-described problem, the contents of an image to be displayed are stored in one place in hardware. The image hardware further stores the image by dividing it into a plurality of addresses by addressing in the X-axis and Y-axis directions.

  If necessary, the stored image can be displayed on a display unit that specifies only a part of the stored image. The display unit and the driver unit of the image memory storing the images are fixedly connected. The entire image can be displayed to create a sense of realism, or only a part can be emphasized and divided.

  In the automatic image division control device according to the present invention, a fixed image is stored in an image memory constituted by one piece of hardware. This image is basically fixed although the circuit configuration can be freely changed by resetting the function like hardware, for example ROM (read only Memory) or FPGA (field programmable gate array). The speed is fast because it is a dedicated LSI.

  In addition, images stored inside can be automatically divided. Since the image fixed by hardware is addressed in the X and Y axis directions, the image can be divided and output. Since a part of the image can be emphasized on the specified display portion, the interest can be improved.

  By fixing the connection between the display unit and the image memory, it is possible to design without considering the delicate timing between the image memory and the circuit configuration device of the display unit, thereby reducing the burden of product development. There may be only one IO (input / output) chip in the memory unit. Therefore, the overall configuration is simplified, improving reliability and reducing costs.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. FIG. 1 shows the overall configuration of this embodiment. In FIG. 1, 11 is an internal bus of the circuit configuration unit, and 12 is a CPU for controlling the whole. Reference numeral 13 denotes a program memory having this configuration, and reference numeral 14 denotes a RAM (random access memory).

  Reference numeral 15 denotes a memory for temporarily storing calculation results necessary for control of the circuit device and data fetched from the outside. Reference numeral 16 denotes an image memory, which stores image contents in hardware such as an FPGA. Reference numeral 17 denotes a chip having a function of writing the contents of 16 images on the display unit 19.

  A timing controller 18 receives display information from 17 and controls the display timing of the display information on the display unit 19. The display unit 19 includes an X-axis driver and a Y-axis driver (not shown). The image is accurately displayed at 19 in synchronization with 18. Even if there are a plurality of display panels 19, one image controller device of 21 is sufficient.

  Reference numeral 20 denotes a bus line for connecting 21 image controllers. Use serial or parallel bus lines as needed. A connection line 22 between the image display unit 19 and the image controller 21 uses a serial or parallel line.

  FIG. 2 shows the configuration of the display unit. As an example, the internal configuration of a direct matrix liquid crystal display panel (LCD) will be described. FIG. 2 (a) shows the internal structure of the LCD panel, and an X electrode and a Y electrode are provided on two glass substrates sandwiching a liquid crystal layer (not shown).

  As shown in FIG. 2A, the intersection of the XY electrodes is used as a display pixel. For driving the element, as shown in FIG. 2B, the X electrodes are sequentially scanned, the signal electrodes corresponding to the scanned X electrodes are sequentially scanned, and the signal voltage corresponding to the scanned X electrodes is set to Y. Line sequential scanning applied to the electrodes is used.

  There are two driving methods for the direct matrix LCD: a cumulative response type and a sequential writing type. In the former, the scanning voltage pulse width ts is set shorter than the response time tr of the liquid crystal. In the latter case, on the contrary, tr is set longer than ts, and is mainly used for a liquid crystal panel having a memory property such as a ferroelectric liquid crystal.

  In order to improve the contrast of the image, the drive applied voltage is averaged to solve the problem of crosstalk. In general, the liquid crystal is bidirectional with respect to the voltage, and is the same as the state in which + 1V is applied and the state in which -1V is applied. The voltage averaging method is used for the liquid crystal simple matrix display.

  On the other hand, there is an active matrix method. In order to manufacture a simple matrix type LCD, wiring may be provided in a matrix on two pieces of glass. In contrast, an active matrix LCD uses a semiconductor process.

  Various liquid crystal modes can be used in the active matrix method. The switch is made possible by incorporating a transistor in the pixel. The active matrix includes scanning lines, signal lines, and thin film transistors (TFTs).

  The TFT plays the role of a switch. The TFT has the same structure as a MOSFET (Metal Oxide Field Effect Transistor). The gate electrode, i.e. the scan line, is below the channel layer. Inverted stagger structure. The inverted staggered structure blocks light from the backlight using scanning lines.

  FIG. 3 is a diagram for explaining the relationship among the CPU 31, the I / O 32, the image memory 33, the driver device 34, and the displays 35 to 37mn. When an event occurs and the CPU 31 enters an operation for displaying an image, the CPU 31 issues an image output command from the 33 storing the image via the I / O 32.

  Reference numeral 33 denotes a fixed memory that stores images. Images can be divided and output. 33 X-axis and Y-axis are addressed. If the address of the XY axis is designated, the image there can be output to the designated display panel.

  34 driver devices are connected to each display. An image is output to the connected panel according to an image output instruction. At this time, since the 33 image memories are fixed and the connection between the display 34 and the displays 35 to 37 mn is fixed, there is no need to consider timing or state transition. There is little burden on the design including software.

  The image memory 33 is also an image dividing device. When one picture is stored in 33, the part or the whole of the picture can be displayed on an arbitrary display by the address designation of the XY axes from the 31 CPU. A part of the whole can be arbitrarily displayed by the occurrence of an event as in a game machine.

  For example, the event mentioned here is a phenomenon that gives a sense of realism, joy and fun to the person who is playing the game, such as a win on a game machine, a lot of numerical values that match like a throttle machine, etc. Say what happened.

  FIG. 4 is a diagram for explaining the operation of image division. 33 shows how the fixed image stored in 33 is divided and displayed and the whole image is displayed. Conventionally, a drawing command is received from the CPU, and the result is written in a video memory 33. The current video chip is a graphics accelerator specialized for GUI (graphical user interface).

  Actual screen display is performed by a RAMDAC (Random Access Memory Digital-to-Analog Converter) that converts data in the video memory into an analog signal. Since the video memory 33 of the present invention is a fixed memory by hardware, high-speed transfer is possible.

  In general, an image control apparatus employs a technique of transferring data from a main memory to a video memory at high speed without using a CPU by using a graphics accelerator.

  The driver devices 33 and 34 are connected by 37, and the driver device 34 and the display unit are connected by 38 connection lines. In this example, a liquid crystal panel LCD is used. The LCD n1 displays the entire image in 33. In LCDn2, the left ear of the animal character in 33 is enlarged, and LCDn3 shows the right ear enlarged.

  LCDn4 shows only the background of the animal character, LCDn5 shows the animal character's face enlarged, and OLCDn6 shows the animal character's neck enlarged. The images on the LCDn1 to LCDn6 are an example.

  The number of display portions of the LCD can be increased or decreased depending on the application. In any case, when an event occurs, the image portion can be reduced and enlarged, or the entire image can be reduced or enlarged to display a sense of reality. In addition, since all processing is performed by hardware, there is a feature that an image can be displayed at a higher speed than a graphics accelerator.

  The display units of the LCDs n1 to LCDn6 include a driver device on the image receiving side XY axes (not shown). The data is displayed on the LCD in synchronization with the driver device 34 on the output side. There is no problem in software design and timing even if the designer is not involved in any synchronization.

  When the 38 connection lines are serial, a serial-parallel conversion unit is provided on the display unit LCD side, and a buffer memory is provided on the XY axes of the display unit as necessary. Depending on the event, the image and picture stored in the 33 image memory units are enlarged or reduced. In 33 memories, images are recorded by a bit pattern by hardware.

  Enlarging and reducing can be performed by manipulating the 33 X-axis and Y-axis bits. Use this to create an effect that creates a sense of reality. A score can be given by the image that has appeared on the display unit to enhance the game. For example, when the whole image comes out enlarged, the score is increased, and when the image is small, the score is decreased.

  The score is determined when only the background appears, or when the left-side image, upper-side, lower-side, and right-side images appear. Such a game sensation stimulates the game. Since the present invention is configured by hardware, it is faster than a video accelerator and is easy to design.

  FIG. 5 is a flowchart associated with image control according to the present invention. The game machine is described as an example. In FIG. 5, S101 first stores the display information of the image in 33 of FIG. In the case of an FPGA or ROM, images are stored in advance. The display contents can be rewritten from the CPU 12 of FIG. 1 according to the application if it is an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and read only memory).

  S102 waits for an event to occur. The event in this case means that, for example, a pachinko ball has entered a specific location, or the throttle machine number has reached a specific value. An event occurred in S103. In step S104, display information corresponding to the event is sent to the designated display unit.

  S105 displays the information sent to LCDnm0. S106 waits for the next event. In step S107, it is checked whether an event has occurred. Since a new event has occurred in S108, the next display content is sent from 33 in FIG.

  In S109, a big hit event occurred. All display units are lit. In this case, the same specific image of FIG. 433 may be displayed all at once. In order to enhance the sense of reality, the display image may be blinked to emit music and sound.

  In S110, it waits for the next new event. An event occurred in S111. In step S112, display information corresponding to the event that has occurred is sent. In step S113, the display unit LCDnm1 is displayed. In step S114, an image is displayed on the display unit specified to send display information corresponding to events that occur one after another. These operations are repeated.

  As described above, the display control according to the present invention displays the contents of the image memory configured by hardware on a specific display unit according to the occurrence of an event. In the image memory 33, images and pictures are drawn on hardware such as FPGA, EPROM, and EEROM.

  Therefore, it is possible to display at higher speed than the conventional video controller, and there is no need to synchronize timing. Since the display unit and the driver device are fixed, it is not necessary to provide a driver device for each display unit.

  For such image display, a conventional video card is provided in a computer device. VGA (video graphic array) is the name of the graphics chip and is the standard for video cards. 16 colors out of 262,144 colors can be simultaneously developed with a resolution of 640 dots × 480 dots.

  According to the present invention, the circuit configuration is simplified and the cost is reduced. Since the contents of the image memory are drawn by hardware, high-speed display becomes possible. In addition, since it is not necessary to design software in consideration of synchronization such as timing, the burden on device design can be reduced. Note that the description of the display unit according to the present invention is given by taking an LCD as an example, but other display elements LED, organic EL, inorganic EL, CRT, and the like can be applied.

  It is a figure of embodiment which shows the system configuration | structure of this invention.   It is a figure which shows the structure of a LCD display part.   It is a figure which shows the relationship between an image memory, a driver, and a display part.   It is a figure which shows the relationship between both image memories and image division, and a display example.   It is a flowchart which shows the process of an image display.

Explanation of symbols

11 Internal bus line 12, 31 CPU
13 ROM, program memory 14 RAM
15 Data memory 16, 33 Image memory 17 Display controller 18 Timing controller 19, 35, 36, 37 mn Display unit 20, 22, 38 Connection line 21, 34 Display driver device 32 I / O unit LCDn1, LCDn2, LCDn3
LCDn4, LCDn5, LCDn6 Display device examples

Claims (6)

In a device provided with an image display device, means for dividing an image by providing a memory for storing an image to be displayed and a driver device for outputting the image to the display device, addressing the image memory in the X-axis and Y-axis directions,
A display control method for a plurality of screens, wherein the contents of the image memory are displayed on a plurality of image display devices. 2. The display control method for a plurality of screens according to claim 1, wherein the image stored in the image memory is arbitrarily divided and a partial display or an entire image display is displayed on a plurality of image display devices. 2. The display control method for a plurality of screens according to claim 1, wherein the image memory and the driver device have a function of an automatic image dividing device. The image memory and display driver device according to claim 1 can be connected to a plurality of display devices with a single image memory and driver device.
A display control method for a plurality of screens, wherein a circuit device is simplified by omitting provision of an image display driver device for each display device. 5. The display control method for a plurality of screens according to claim 4, wherein the image output to the plurality of display devices does not require synchronization timing control by an image display driver, the plurality of display devices, and fixed connection means. An image stored in the image memory, comprising: means for automatically dividing and displaying an image when a certain event occurs in a device transition state.

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