JP2008077007A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of reducing the number of output terminals of a gate driver for the number of gate lines of a display panel and the number of connection lines with the gate driver. <P>SOLUTION: The gate lines G1 to G800 are divided into two blocks and the gate lines which are divided into the blocks are wired to the gate driver 20 in multi-layer. Therein, a selection switches Tr11, Tr12 and non-selection switches Tr21, Tr22 are disposed between respective output terminals of the gate driver 20 and respective gate lines, the state of the selection switches Tr11, Tr12 is switched in accordance with the output state of a scanning signal from the gate driver 20 to select the block and the scanning signal is sequentially supplied to the gate line of the selected block. Further, a gate line of non-selected block is made to be non-selection level VGL by the non-selection switches Tr21, Tr22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device such as a liquid crystal display device, and more particularly to an active matrix display device.

  Conventionally, an active matrix type display panel is known as a display panel used in a liquid crystal display device. In this active matrix display panel, a plurality of scanning lines (gate lines) and a plurality of signal lines (source lines) are arranged in a display area on the display panel so as to be orthogonal to each other, and these gate lines and source lines are arranged. A pixel electrode is disposed in the vicinity of the intersection with a thin film transistor (hereinafter referred to as TFT) via a thin film transistor, and a liquid crystal is filled between the counter electrode disposed opposite to the pixel electrode to display a pixel. Is configured. Then, by applying a voltage between the pixel electrode and the counter electrode by a display driving device (gate driver and source driver) for driving such a display panel, the alignment state of the liquid crystal layer filled between both electrodes Display is performed by changing.

As one configuration of such a liquid crystal display device, for example, in Patent Document 1, a display panel is formed on a glass substrate, and a display drive device is placed on a non-display area on one side of the display area on the glass substrate. On Glass) The configuration to be implemented is described.
JP 2006-71814 A

  Here, in the conventional gate driver mounting method as disclosed in Patent Document 1, each scanning line is individually connected to the output terminal of the gate driver, and the routing wiring that connects each scanning line and each output terminal of the gate driver. Is formed in the non-display area on the other side of the display area of the glass substrate. In this case, the number of routing lines to be formed on the glass substrate and the number of output terminals of the gate driver are required to be the same as the number of gate lines of the display panel.

  Here, when the number of gate lines is increased in order to increase the resolution of the display panel, the number of routing wirings to be formed in the non-display area of the glass substrate also increases. For this reason, in the conventional method, for example, if the number of gate lines is doubled, the number of routing lines needs to be doubled. For this reason, the width of the non-display area for forming the lead wiring increases. Further, since the number of gate output terminals increases as the number of gate lines increases, the size of the gate driver tends to increase.

  The present invention has been made in view of the above circumstances, and provides a display device capable of reducing the number of output terminals of a gate driver and the number of wiring lines connected to the gate driver with respect to the number of gate lines of a display panel. With the goal.

  In order to achieve the above object, a display device according to claim 1 of the present invention includes a plurality of scanning lines and a plurality of signal lines formed on a display panel, and each of the scanning lines and the signal lines. Display means having a plurality of display pixels arranged in a matrix in the vicinity of the intersection, wherein the plurality of scanning lines are divided into a plurality of blocks, and the number of scanning lines in one block in the plurality of blocks, A scanning side driving unit that has at least the same number of output terminals and sequentially outputs scanning signals from the output terminal; and is provided between each of the output terminals of the scanning side driving unit and the plurality of scanning lines. The plurality of blocks are sequentially selected according to the output state of the scanning signal from the side driving means, and the scanning lines in the selected block and the output terminals of the scanning side driving means are electrically connected Characterized by comprising selection means for connecting, the.

  According to a second aspect of the present invention, in the display device according to the first aspect, the selection means is formed on the display panel.

  According to a third aspect of the present invention, in the display device according to the second aspect, the selection means includes an amorphous silicon thin film transistor.

  According to a fourth aspect of the present invention, in the display device according to the first aspect, the selection unit is configured to apply the scanning signal to all the scanning lines in one selected block in the plurality of blocks. The selection of the block is canceled and another block is selected.

  According to a fifth aspect of the present invention, in the display device according to the first aspect, the selection unit includes a switching unit that switches the potential of the scanning line in the unselected block to a non-selection level potential. It is characterized by.

  According to a sixth aspect of the present invention, in the display device according to the first aspect, the number of the scanning lines in each of the plurality of blocks is the same.

  According to the present invention, a plurality of scan lines for display pixels arranged in a matrix are divided into a plurality of blocks, which are sequentially selected for each block, and the scan lines in the selected block and the output of the scan driving means are output. The number of output terminals of the scan driving means can be reduced by connecting the terminals to sequentially input the scanning signals to the respective scanning lines, and for connecting the scanning lines and the scanning driving means. The wiring area can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an overall configuration of a display device, particularly a display panel module, according to an embodiment of the present invention. In the display panel module shown in FIG. 1, a display panel unit (display unit) 10 is formed on a glass substrate 1, and a gate driver (scanning side driving unit) 20 and a source driver 30 are mounted on one side of the glass substrate 1. Configured.

  The display panel unit 10 is, for example, an active matrix liquid crystal (LCD) panel, and includes a plurality of scanning lines (gate lines) arranged in the row direction and a plurality of signal lines (source lines) arranged in the column direction. ) And display pixels are provided in the vicinity of each intersection of the gate line and the source line. In addition, a plurality of lead wires 2 connecting the output terminal of the gate driver 20 and the gate line of the display panel unit 10 on the other side orthogonal to the one side on which the gate driver 20 and the source driver 30 of the glass substrate 1 are mounted. Is provided.

  FIG. 2 is a diagram showing an equivalent circuit of one display pixel provided in the display panel unit 10. The gate line G shown in FIG. 2 is connected to the gate electrode of the thin film transistor (TFT) 11, and the source line S is connected to the source electrode of the TFT 11. Further, a pixel electrode 12 of a liquid crystal capacitor and a storage capacitor 14 are connected to the drain electrode of the TFT 11. The counter electrode 13 and the storage capacitor 14 of the liquid crystal capacitor are connected to the common signal line C. Further, liquid crystal is filled between the pixel electrode 12 and the counter electrode 13 to constitute a liquid crystal layer. Actually, the glass substrate 1 is composed of an active substrate and a counter substrate disposed so as to face the active substrate through a liquid crystal layer. The TFT 11, the pixel electrode 12, and the storage capacitor are disposed on the active substrate side. One electrode 14 is formed, and the other electrode of the counter electrode 13 and the storage capacitor 14 is formed on the counter substrate side to constitute a display pixel.

  Here, the display panel section 10 of FIG. 1 shows a display panel section having 1440 source lines (480 lines × 3 colors) and 800 gate lines. The numbers of source lines and gate lines shown in FIG. 1 are merely examples.

  In the display pixel having such a configuration, when a voltage is applied between the pixel electrode 12 and the counter electrode 13, the liquid crystal filled between the pixel electrode 12 and the counter electrode 13 according to the value of the voltage is used. The alignment state changes and the light transmittance in the liquid crystal layer changes. Thereby, the transmission state of light from a light source (not shown) arranged on the back surface of the display pixel shown in FIG. 2 is changed, and image display is performed.

  The source driver 30 is connected to the source line S of the display panel unit 10. Then, the source driver 30 receives a horizontal control signal output from a controller (not shown), takes in display data of each color of RGB in units of one row, selects a gradation voltage corresponding to the fetched display data, and handles it. Supply to each source line S. Note that the number of output terminals of the source driver 30 is the same as the number of source lines S.

  The gate driver 20 receives a vertical control signal from a controller (not shown), sequentially supplies a scanning signal for turning on the TFT 11 to each gate line G, turns the TFT 11 into a selected state (on state), and crosses the source line S. The gradation voltage supplied from the source driver 30 via the source line S is applied to the pixel electrode 12 in the display pixel at the position.

  Here, in this embodiment, the gate line is divided into a plurality of blocks, and the gate driver 20 has the number of output terminals equal to or larger than the number obtained by dividing the number of gate lines by the number of divisions. Then, by driving the gate lines of each block in a time-sharing manner, all the gate lines can be sequentially driven as in the conventional case. For this purpose, as shown in FIG. 1, a selection unit 10a as a selection unit is formed in the non-display area of the display panel unit 10 on the side where the gate driver 20 is selected.

  In this case, for example, as shown in FIG. 1, when the gate line of the display panel unit 10 is divided into two blocks, the number of output terminals of the gate driver 20 is set to ½ of the number of gate lines of the display panel unit 10. The gate driver 20 can be made smaller than before. In addition, since the number of the routing wirings 2 is reduced, the width of the non-display area in which the routing wirings 2 are formed can be made narrower than the conventional one.

  FIG. 3 is a diagram for illustrating a detailed configuration of the selection unit 10a. The selection unit 10a shown in FIG. 3 includes selection switches Tr11 and Tr12 and non-selection switches (switching means) Tr21 and 22. Note that these switches can be configured as amorphous silicon TFT switches in the non-display area of the display panel unit 10. Here, Gout1 to Gout400 are output terminals of the gate driver 20.

As shown in FIG. 3, at least a part of the wiring connecting each output terminal of the gate driver 20 and the selection switch Tr12 in the routing wiring 2 is a wiring connecting each output terminal of the gate driver 20 and the selection switch Tr11. It is configured so as to form a multilayer wiring intersecting with an insulating film (not shown). Further, the gate lines G1 to G800 of the display panel unit 10 and the output terminals Gout1 to Gout400 of the gate driver 20 are individually connected, and for example, two routing wirings 2 are provided at each output terminal of the gate driver 20, for example. You may make it connect. In this case, since the timing of the signal applied to the two routing wirings 2 connected to one output terminal is the same, a multilayer wiring in which these two wirings are stacked at the top and bottom can be formed. For this reason, even in this case, the width of the non-display area in which the routing wiring 2 is formed does not increase.

  Here, in the following example, an example in which the 800 gate lines shown in FIG. 1 are divided into two blocks will be described. The number of gate lines in each block is the same. That is, one block includes 400 gate lines, and the number of output terminals of the gate driver 20 is 400. In the following description, of the two blocks shown in FIG. 3, the upper block (the block consisting of gate lines G1 to G400) is the block 1, and the lower block (the block consisting of gate lines G401 to G800) is the block 2. Called.

  As shown in FIG. 3, the gate lines G1 to G400 of the block 1 are connected to the output terminals G1, G401 to G400, and G800 of the gate driver 20 through the non-select switch Tr21 and the select switch Tr11, respectively. The selection control signal SW1 is input from the gate driver 20 to the selection switch Tr11 and the non-selection switch Tr21. The gate lines G401 to G800 of the block 2 are connected to the output terminals G1, G401 to G400, and G800 of the gate driver 20 common to the block 1 through the non-select switch Tr22 and the select switch Tr12, respectively. The selection control signal SW2 is input from the gate driver 20 to the selection switch Tr12 and the non-selection switch Tr22.

  The selection switch Tr11 and the non-selection switch Tr21 are both turned on when the selection control signal SW1 from the gate driver 20 is at a high level (Hi), so that the gate lines G1 to G400 and the gate driver 20 are in a conductive state. Is low level (Lo), the selection switch Tr11 is turned off to be in the release state, the non-selection switch Tr21 is connected to the off level VGL, and the gate lines G1 to G400 are set to the off level VGL. Further, the selection switch Tr12 and the non-selection switch Tr22 are both turned on when the selection control signal SW2 from the gate driver 20 is Hi to make the gate lines G401 to G800 and the gate driver 20 conductive, and SW2 is Lo. In this case, the selection switch Tr12 is turned off to be in the released state, the non-selection switch Tr22 is connected to the off level VGL, and the gate lines G401 to G800 are set to the off level VGL.

  FIG. 4 is a timing chart showing the timing of gate scanning of the display device of this embodiment.

  First, when the selection control signals SW1 and SW2 are both Lo, the selection switches Tr11 and Tr12 are turned off, and the gate lines G1 to G800 are set to the off level VGL by the non-selection switches Tr21 and Tr22. When the vertical synchronization signal Vsync is input to the gate driver 20 from a controller (not shown), the gate driver 20 sets the selection control signal SW1 to Hi, the selection control signal SW2 to Lo, and sequentially outputs scanning signals from the output terminal Gout1. Output. Here, in the configuration of FIG. 3, the scanning signal from the gate driver 20 is output toward both the gate lines G1 and G401, but the selection switch Tr11 is on and the selection switch Tr12 is off. The output terminals Gout1 to Gout400 of the driver 20 and the gate lines G1 to G400 of the block 1 are connected, the scanning signal is supplied only to the gate line G1, and the gate lines G2 to G400 other than the gate line G1 become the off level VGL. Further, the gate lines G401 to G800 of the block 1 are at the off level VGL by the non-select switch Tr22. As a result, only the display pixels connected to the gate line G1 are selected.

  Thereafter, the scanning signals are sequentially output from the output terminals of the gate driver 20 while the selection control signal SW1 and the selection control signal SW2 remain unchanged until the scanning of each gate line in the block 1 is completed. Are sequentially supplied to the gate lines G1 to G400.

  After the scanning in the block 1 is completed, that is, after the scanning signal is output from the output terminal Gout400 of the gate driver 20 and the gate line G400 is selected, the gate driver 20 sets the selection control signal SW1 to Lo and the selection control. The signal SW2 is set to Hi and the scanning signal is output from the output terminal G1 again. In this case, since the selection switch Tr11 is off and the selection switch Tr12 is on, the output terminals Gout1 to Gout400 of the gate driver 20 and the gate lines G401 to G800 of the block 2 are connected, and the scanning signal is applied to the gate line G401. Only the gate lines G402 to G800 other than the gate line G401 are at the off level VGL. Further, the gate lines G1 to G400 of the block 1 are at the off level VGL by the non-select switch Tr21. As a result, only the display pixels connected to the gate line G401 are selected.

Thereafter, the scanning signals are sequentially output from the output terminals of the gate driver 20 with the selection control signal SW1 and the selection control signal SW2 kept in the same state until the scanning of each gate line in the block 2 is completed.
As described above, an image for one frame is displayed.

  According to the display device of the present embodiment as described above, the gate lines are divided into a plurality of blocks, and the gate lines of each block are driven in a time division manner, whereby all the gate lines can be driven sequentially. Since the number of output terminals of the gate driver can be reduced, the gate driver can be reduced in size. In addition, since the number of routing wirings can be reduced, the routing wiring forming area in the non-display area can be reduced, and the size of the glass substrate can also be reduced.

  Further, in the configuration of FIG. 3, the selection switches Tr11 and Tr12 and the non-selection switches Tr21 and Tr22 are configured to be turned on and off all at once. With such a configuration, the transistor size for configuring each switch can be increased, and the speed of the switch operation can be increased.

  Although the present invention has been described based on the above embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention. For example, in the example of FIG. 3, an example in which the gate line is divided into two blocks has been described, but it may be divided into three or more blocks. For example, if each block is divided into three blocks and driven in a time division manner, the number of gate output terminals and the number of gate wirings can be reduced to 1/3 of the number of gate lines.

  In the example of FIG. 1, the gate driver 20 and the source driver 30 are mounted only on one side of the display panel unit 10, but the present invention is not limited to this. For example, the gate driver 20 may be provided on the side of the display panel unit 10 and the source driver 30 may be provided on the lower side of the display panel unit 10.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

It is a figure which shows the whole structure of the display apparatus which concerns on one Embodiment of this invention especially the display panel module. It is a figure which shows the equivalent circuit of one display pixel provided in a display panel part. It is a figure for showing the detailed structure of a selection part. 4 is a timing chart showing gate scanning timing of the display device according to the embodiment of the present invention.

Explanation of symbols

  G1 to G800: gate line, Tr11, Tr12 ... selection switch, Tr21, Tr22 ... non-selection switch, 1 ... glass substrate, 10 ... display panel unit, 10a ... selection unit, 20 ... gate driver, 30 ... source driver

Claims (6)

A plurality of scanning lines and a plurality of signal lines formed on the display panel; and a plurality of display pixels arranged in a matrix in the vicinity of each intersection of the scanning lines and the signal lines. Display means in which the line is divided into a plurality of blocks;
Scanning-side driving means having at least the same number of output terminals as the number of scanning lines in one block in the plurality of blocks, and sequentially outputting scanning signals from the output terminals;
Provided between each of the output terminals of the scanning side driving means and the plurality of scanning lines, the plurality of blocks are sequentially selected and selected according to the output state of the scanning signal from the scanning side driving means Selecting means for electrically connecting each scanning line in the block and each output terminal of the scanning side driving means;
A display device comprising:   The display device according to claim 1, wherein the selection unit is formed on the display panel.   The display device according to claim 2, wherein the selection unit includes an amorphous silicon thin film transistor.   The selection unit is configured to cancel the selection of the block and select another block after the scanning signal is applied to all the scanning lines in the selected block in the plurality of blocks. The display device according to claim 1.   The display device according to claim 1, wherein the selection unit includes a switching unit that switches a potential of the scanning line in the unselected block to a non-selection level potential.   The display device according to claim 1, wherein the number of the scanning lines in each of the plurality of blocks is the same.

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