JP2006337668A - Method for manufacturing semiconductor device, and production program of layout pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which whether a design layout pattern is good or not can be discriminated and a clear guideline for correction is presented. <P>SOLUTION: A tendency of inducing wiring failures in a design layout pattern of a semiconductor device by lithography and processing is quantified as a score; whether the design layout pattern is good or not is discriminated by the score; and if the pattern is discriminated as good, a transfer layout pattern transferred from the design layout pattern is formed on a semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for creating a layout method used in a method for manufacturing a semiconductor device.

  Semiconductor devices are being miniaturized. An important element in a manufacturing process for manufacturing a miniaturized semiconductor device is a lithography (exposure) step of transferring a design layout pattern of the semiconductor device onto a semiconductor substrate. However, the current situation is that the resolution of the exposure apparatus that performs the lithography process cannot keep up with the dimensions required for miniaturization.

  Attempts have been made to improve resolution using phase shift mask techniques such as the Levenson method and optical proximity correction (OPC). However, in generations where the line and space width of the design layout pattern is 90 nm or 65 nm, the lithography margin tends to be surely reduced even if these phase shift mask technologies are used. Therefore, there is a need to create a design layout pattern using only a layout pattern that can be processed in a lithography process with strict design restrictions according to design rules of the design layout pattern.

Since such design constraints change complicatedly depending on the relative position (topology) of existing layout patterns and dimensions such as distance and thickness, the design constraints are complicated and cannot be defined exhaustively. Due to this problem, a compliance check for checking the workability of the layout has been devised by lithography / process simulation and OPC trial (see, for example, Patent Document 1). Since the design layout pattern is changed from the original design, the design constraints are simplified and the design layout pattern can be freely designed. This is a cause of worsening TAT.
JP 2004-079586 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can determine whether a design layout pattern is good or not and has a clear correction guideline.

  Another object of the present invention is to provide a layout pattern creation program capable of presenting a design guideline pattern pass / fail judgment and a clear correction guideline.

  The first feature of the present invention for solving the above-described problems is that the probability of occurrence of wiring defects in a design layout pattern of a semiconductor device by lithography and process is quantified as a score, and the design layout pattern is based on the score. In the method of manufacturing a semiconductor device, a transfer layout pattern formed by transferring a design layout pattern is formed on a semiconductor substrate.

  A second feature of the present invention is a modified layout pattern creation program executed by a computer that can use a transfer layout pattern from a simulator that creates a transfer layout pattern based on lithography and a process using a design layout pattern of a semiconductor device. In order to cause a computer to execute a procedure for quantifying, as a score, the likelihood of a design layout pattern defect due to lithography and a process based on a transfer layout pattern, and a procedure for determining the quality of a design layout pattern based on the score There is a modified layout pattern creation program.

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor device with a clear design layout pattern and a clear guideline for correction.

  Furthermore, according to the present invention, it is possible to provide a layout pattern creation program that can determine whether a design layout pattern is good or not and can present a clear correction guideline.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  As shown in FIG. 1, the layout pattern creation apparatus 1 according to the embodiment includes an OPC unit 2, a simulator 3, a deformation unit 4, a quantification unit 5, an optimization unit 6, a division unit 7, a search unit 8, and an extraction unit. Unit 9, composition unit 10, design layout pattern storage unit 11, semiconductor device specification / spec storage unit 12, OPC layout pattern storage unit 13, transfer layout pattern storage unit 14, modified layout pattern storage unit 15, database storage unit 16 and a database creation unit 17. The OPC unit 2 and the simulator 3 may be external devices of the layout pattern creation device 1 that can be operated by the layout pattern creation device 1.

  The layout pattern creation apparatus 1 may be a computer, and the layout pattern creation apparatus 1 may be realized by causing a computer to execute a procedure written in a program.

  The semiconductor device manufacturing method according to the first embodiment is performed using the layout pattern creating apparatus 1 shown in FIG. In the method of manufacturing a semiconductor device according to the first embodiment, first, in step S1 of FIG. 2, a design layout pattern D1 of the semiconductor device as shown in FIG. 3 is input and stored in the design layout pattern storage unit 11.

  In step S2 of FIG. 2, the OPC unit 2 of FIG. 1 performs OPC on the design layout pattern D1, and generates an OPC-made layout pattern D2 as shown in FIG. The OPC layout pattern D2 is stored in the OPC layout pattern storage unit 13.

  In step S3 in FIG. 2, the quantification unit 5 in FIG. 1 performs the disconnection short circuit failure in the transfer layout pattern D3 of the design layout pattern D1 of the semiconductor device or the OPC layout pattern D2 by the lithography process and the manufacturing process before and after the lithography process. The probability of occurrence is quantified as a score Zm. As the score Zm, the transfer layout pattern at the inter-surface distance Z with the standard deviation of the inter-surface distance Z variation between the surface of the semiconductor substrate on which the semiconductor device is formed and the image plane of the transfer layout pattern in lithography as a distance unit The minimum inter-surface distance Z that causes a disconnection short circuit can be used. That is, when the inter-plane distance Z is zero, the transfer layout pattern forms an image on the semiconductor substrate, and the outline of the transfer layout pattern formed on the semiconductor substrate is clear. As the inter-plane distance Z increases from zero, the transfer layout pattern does not form an image on the semiconductor substrate, and the outline of the transfer layout pattern formed on the semiconductor substrate becomes blurred and blurred. The blurring of the outline causes a disconnection short circuit defect in the transfer layout pattern. In the manufacturing process, the inter-surface distance Z cannot always be zero, and the inter-surface distance Z varies. The standard deviation σ can be calculated from this variation distribution. By dividing the inter-surface distance Z by the standard deviation σ, the inter-surface distance Z can be normalized from the viewpoint of variation distribution. The inter-plane distance Z is the inter-plane distance between the surface of the semiconductor substrate on which the semiconductor device is formed and the imaging plane of the transfer layout pattern in lithography. The surface of the semiconductor substrate on which the semiconductor device is formed can be visually recognized, but the image plane of the transfer layout pattern in lithography cannot be visually recognized. Therefore, the image plane is indirectly recognized. First, it is considered that the distance between the imaging plane and the lens of the lithography apparatus that images the transfer layout pattern is constant. When the transfer layout pattern is transferred and developed on the semiconductor substrate by moving the lens up and down with respect to the surface of the semiconductor substrate, the semiconductor substrate is positioned at the position of the lens where the developed transfer layout pattern has the sharpest outline. It is thought that the image plane coincides with the surface of Accordingly, the inter-surface distance can be considered as a distance from the lens position to the lens position where the contour of the developed transfer layout pattern becomes the clearest. Further, the variation in the inter-surface distance can be considered as the variation in the lens position.

  Here, there is almost no case where the interplanar distance Z deviates from the variation distribution such as 5 (σ), and the interplanar distance Z takes a value such as 5 (σ) in the lithography process. If there is no disconnection short circuit defect in the transfer layout pattern D3, as long as the design layout pattern D1 that is the origin of the transfer layout pattern D3 or the OPC layout pattern D2 is used, no matter how the inter-plane distance Z varies. The transfer layout pattern D3 does not cause a disconnection short circuit defect. Such a design layout pattern D1 or an OPC layout pattern D2 can be said to be a layout pattern that hardly causes a disconnection short circuit defect.

  Conversely, in the distribution of variations such that the inter-surface distance Z is 1 (σ), the inter-surface distance Z may take a value such as 1 (σ) in the lithography process. If a disconnection short circuit defect occurs in the pattern D3, the inter-plane distance Z is changed by more than 1 (σ) as long as the design layout pattern D1 or the OPC layout pattern D2 that is the basis of the transfer layout pattern D3 is used. As a result, a disconnection short circuit defect occurs in the transfer layout pattern D3. Such a design layout pattern D1 or an OPC layout pattern D2 can be said to be a layout pattern that easily causes a disconnection short circuit defect.

  From these facts, it can be seen that the susceptibility to occurrence of the disconnection short-circuit defect in the design layout pattern D1 or the OPC layout pattern D2 can be expressed by the presence or absence of the disconnection short-circuit defect at the inter-plane distance Z. That is, the difficulty of occurrence of disconnection short-circuit failure can be quantified by the fact that the minimum inter-surface distance Z at which disconnection short-circuit failure occurs in the transfer layout pattern is large. The reason why the minimum inter-plane distance Z is defined in this way is that it is based on the yield model of the integrated circuit of the semiconductor device.

  Specifically, in step S13 of FIG. 2, the simulator 3 of FIG. 1 performs a simulation when the inter-surface distance Z is 5 (σ) as shown in FIG. 5C to generate the transfer layout pattern D3. And stored in the transfer layout pattern storage unit 14. The simulator 3 may be any simulator as long as simulation capable of reproducing lithography / process behavior is possible. In the description of the transfer layout pattern D3, the transfer layout pattern D3 and the design layout pattern D1 are all overlapped thereafter. This clearly shows the change from the shape of the design layout pattern D1 to the shape of the transfer layout pattern D3.

  In step S4, the quantifying unit 5 in FIG. 1 determines whether a disconnection short circuit defect has occurred in the transfer layout pattern D3 when the inter-plane distance Z in FIG. 5C is 5 (σ). In the determination, if there is no part that violates the specification of the pattern width of the specification / spec D5 of the semiconductor device and the specification of the pattern interval, it is determined that no defect has occurred. If there is a part that violates the specification, it is determined that a defect has occurred. In the transfer layout pattern D3 in the case where the inter-plane distance Z in FIG. 5C is 5 (σ), there are violation points P1 to P4 where the pattern widths w1 to w4 are narrower than the specifications, and a defect has occurred. It was determined.

  Since the occurrence of a defect was confirmed, the value of the inter-surface distance Z for simulation is set to 3 (σ) smaller than 5 (σ). A bisection method can be used as a method for setting the value of the inter-surface distance Z for simulation. If no failure is confirmed, the value of the inter-surface distance Z for performing the simulation may be set larger than 5 (σ).

  Returning to step S13, the simulator 3 performs a simulation when the inter-surface distance Z is 3 (σ) as shown in FIG. 5B, generates a transfer layout pattern D3, and stores it in the transfer layout pattern storage unit 14. Let

  Again, in step S4, the quantification unit 5 determines whether a disconnection short circuit defect has occurred in the transfer layout pattern D3 when the inter-plane distance Z in FIG. 5B is 3 (σ). In the transfer layout pattern D3 in the case where the inter-plane distance Z in FIG. 5B is 3 (σ), there are violation points P1 and P2 in which the pattern widths w1 and w2 are narrower than the specifications, and a defect has occurred. It was determined. Since the occurrence of a defect was confirmed, the value of the inter-surface distance Z for simulation is set to 1 (σ) smaller than 3 (σ).

  Returning to step S13 again, the simulator 3 performs a simulation when the inter-surface distance Z is 1 (σ) as shown in FIG. 5A to generate the transfer layout pattern D3, and the transfer layout pattern storage unit 14 Remember me.

  Again, in step S4, the quantification unit 5 determines whether a disconnection short circuit defect has occurred in the transfer layout pattern D3 when the inter-plane distance Z in FIG. 5A is 1 (σ). For the transfer layout pattern D3 in the case where the inter-plane distance Z in FIG. 5A is 1 (σ), no violating part was detected and it was determined that no defect occurred.

  From the above, the quantification unit 5 calculates 3 (σ) as the score Zm that is the minimum inter-surface distance Z at which a defect occurs. If there is a surplus power, the inter-surface distance Z with the inter-surface distance Z exceeding 1 (σ) and less than 3 (σ) may be set in the simulator 3 to increase the accuracy of the score Zm.

  In step S5 in FIG. 2, the optimization unit 6 in FIG. 1 determines pass / fail of the design layout pattern D1 or the OPC layout pattern D2 based on the score Zm. A good criterion Zo is set so that the score Zm is 5 (σ) or more. Since the score Zm is 3 (σ) and not 5 (σ) or more, the design layout pattern D1 or the OPC layout pattern D2 is determined to be NO.

  In step S5, whether the quality is good or not is judged as negative. Therefore, as shown in FIGS. 6 and 7, the deforming unit 4 in FIG. 1 is changed so that the score Zm, which is a direction in which defects are less likely to occur, changes. However, the design layout pattern D1 or the OPC layout pattern D2 is deformed. In the modification, the modification is performed so as to satisfy that the criterion of step S5, the score Zm is 5 (σ) or more. In other words, the transfer layout pattern D3 in the case where the inter-plane distance Z in FIG. 5C is 5 (σ) is deformed so that the violation points P1 to P5 are not detected. Next, the deformation procedure will be described in detail.

  First, the violation points P1 to P4 in FIG. 5C are overlaid on the design layout pattern D1 or the OPC layout pattern D2, as shown in FIG. Circular regions c1 to c4 centering on the violation points P1 to P4 are set. The radii of the regions c1 to c4 are within a range where the effect of OPC is exerted, and can be appropriately set within a range of 300 nm or less. Next, the sides s1 to s7 of the design layout pattern D1 or the OPC layout pattern D2 that overlaps the areas c1 to c4 are extracted. As shown in FIG. 7, the sides s1 to s7 are moved by distances d1 to d7. The distances d1 to d7 are set in advance within a range equal to or less than half the line width or line interval of the design layout pattern D1. Then, the distances d1 to d7 are optimized by the bisection method or the like while rotating the loop of steps S2 to S6 or the loop of steps S3 to S6 in FIG.

  By going around the loop, the quality determination in step S5 of FIG. 2 becomes good, and the process proceeds to step S7. A transfer layout pattern D3 obtained by transferring the design layout pattern D1 or the OPC layout pattern D2 is formed on the semiconductor substrate. As shown in FIG. 8, the transfer layout pattern D3 transferred to the semiconductor substrate satisfies the specifications of the semiconductor device. Thus, the method for manufacturing the semiconductor device is stopped.

  A layout pattern creation method excluding transfer to a semiconductor substrate from a semiconductor device manufacturing method can be expressed by a layout pattern creation program executable by a computer as a procedure. By causing the computer to execute this layout pattern creation, it is possible to implement a layout pattern creation method that excludes the transfer to the semiconductor substrate from the semiconductor device manufacturing method.

  In the first embodiment, conventionally readable design rules are defined on a model basis in the same manner as in circuit simulation and the like. The model base here is a transfer function between the design layout patterns D1 and D2 including lithography / process / OPC / PPC (process proximity effect correction) and the transfer layout pattern D3 transferred onto the semiconductor substrate. Can be defined. In the first embodiment, in addition to the model base, a layout migration technique for correcting a layout pattern as an input and a layout optimization technique are described. By introducing model-based design rules as in the first embodiment, the complexity and incompleteness of design rules associated with miniaturization can be avoided. Further, the layout design TAT and quality can be improved by semi-automatically correcting the design layout data D1. In addition, the burden on OPC / PPC can be reduced.

  In step S5 in FIG. 2, the optimization unit 6 in FIG. 1 may determine whether or not the score Zm has the highest score Zm. If it is the maximum value, the process proceeds to step S7, and if it is not the maximum value, the process proceeds to step S6. Specifically, the loop may be rotated until the score Zm converges. The converged score Zm is the highest value. Further, the area of the design layout pattern D1 may be allowed to increase, and the increase amount of the area increase may be scored as a deduction factor for the score Zm according to the yield model. The optimization unit 6 maximizes the score Zm including the deduction factor.

  As shown in FIG. 9, the semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment in FIG. The difference is that step S5 is changed to step S14.

  The achievement target using the semiconductor device manufacturing method according to the second embodiment is the design layout pattern D1 or the OPC layout pattern that satisfies the determination criterion Zo and the score Zm of 5 (σ) or more in step S5 of the first embodiment. And Therefore, in step S3 in FIG. 9, only the transfer layout pattern D3 in FIG. 5C in which the inter-surface distance Z that is the determination reference Zo is 5 (σ) is calculated by simulation.

  In step S14, it is determined whether the defective portions P1 to P4 of the transfer layout pattern D3 are negative. If there is a defective part, the process proceeds to step S6, and if there is no defective part, the process proceeds to step S7. The subsequent steps can be performed in the same manner as in the first embodiment. That is, if there is a defective part as shown in FIG. 5C, a loop composed of steps S2, S3, S14, and S6 is executed until the condition in step S14 is satisfied.

  According to the semiconductor device manufacturing method of the second embodiment, the quantification in step S3 and the optimization in step S5 can be performed more easily and in a shorter time than in the first embodiment, and the same effects as in the first embodiment can be obtained. be able to.

  As shown in FIG. 10, the semiconductor device manufacturing method according to the third embodiment is different from the semiconductor device manufacturing method according to the first embodiment in FIG. 2 in that steps S <b> 15 and S <b> 8 to S <b> 12 are added. The difference is that a divided layout pattern storage unit 18 and a database storage unit 16 are added.

  First, step S1 is performed in the same manner as in the first embodiment, and the design layout pattern storage unit 11 inputs the design layout pattern D1.

  Next, in step S15, the dividing unit 7 in FIG. 1 divides the design layout pattern D1 into a plurality of divided layout patterns D6. The individual sizes of the divided layout pattern D6 are set so that the OPC on one side of the layout pattern includes the range in which the effect is exerted, and the region in the range from the side to about 500 nm. Therefore, specifically, the individual size of the divided layout pattern D6 is desirably a square having a side of 1 μm or a rectangle larger than the square.

  Steps S2, S5, and S6 are performed for each of the divided layout patterns D6, and are different in that they are not performed on the design layout pattern D1 including one as in the first embodiment. The contents of the implementation are steps S2, S5, and S6, which are the same as those in the first and second embodiments. When the divided layout pattern D6 satisfying the condition is determined in step S5, the process proceeds to step S8.

  In step S8, the database creation unit 17 in FIG. 1 generates the database D7 and stores it in the database storage unit 16. In the database D7, the divided layout pattern D6 and the layout pattern D2 obtained by OPC of the divided layout pattern D6 or the modified layout pattern D4 obtained by modifying the layout patterns D6 and D2 are related to each other so as to be searchable. ing.

  In step S9, the search unit 8 in FIG. 1 searches the database D7. A search is made for a divided layout pattern D6 that is made into a database that matches a divided layout pattern D6 that is not made into a database. If they do not coincide with each other, the process returns to step S2, and OPC is performed on the divided layout pattern D6 that has not been databased, transformed, or databased. If they match, the process proceeds to step S10.

  In step S10, the extraction unit 9 of FIG. 1 extracts the modified layout pattern D4 corresponding to the divided layout pattern D6 that is databased and matches the divided layout pattern D6 that is not databased from the database D7. To do. The extracted modified layout pattern D4 can be treated as modified modified layout data of a divided layout pattern D6 that has not been databased.

  In step S11, the dividing unit 7 determines whether or not the corrected layout data has been set for all the divided layout patterns D6. If not set, the process returns to step S2, and the process is executed for the divided layout pattern D6 for which the modified layout pattern D4 cannot be set. If it has been set, the process proceeds to step S12.

  In step S12, the synthesizing unit 10 in FIG. 1 synthesizes a plurality of modified layout patterns D4 to generate a modified layout pattern D4 corresponding to the entire design layout pattern D1.

  Finally, step S7 is performed in the same manner as in the first embodiment, and a transfer layout pattern D3 is formed on the semiconductor substrate by transferring the design layout pattern D1 or the modified layout pattern D4 of the OPC layout pattern D2.

  In addition, when implementing the manufacturing method of the semiconductor device which concerns on Example 3 after the 2nd time, since the existing database can be utilized, without performing step S2, S3, S5, S8 after the division | segmentation of step S15, Pattern matching by database search in step S9 can be performed.

  In the third embodiment, not only the same effects as in the first embodiment can be obtained, but also the burden on OPC / PPC and the like can be reduced by introducing a database creation method compared to the first embodiment. .

It is a block diagram of the preparation apparatus of the correction layout pattern which concerns on embodiment. 3 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. This is a design layout pattern. This is an OPC layout pattern. It is a transfer layout pattern by simulation. It is a figure for demonstrating the calculation method of the expected value of a yield. It is a figure for demonstrating the method to deform | transform a design layout pattern or the layout pattern by which OPC was carried out. This is a modified layout pattern. It is a transfer layout pattern by simulation using a corrected layout pattern. 6 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment. 9 is a flowchart of a method for manufacturing a semiconductor device according to Example 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Layout pattern creation apparatus 2 OPC part 3 Simulator 4 Deformation part 5 Quantification part 6 Optimization part 7 Dividing part 8 Search part 9 Extraction part 10 Composition part 11 Design layout pattern memory | storage part 12 Specification / spec memory | storage part 13 of semiconductor device 13 OPC layout pattern storage unit 14 Transfer layout pattern storage unit 15 Modified layout pattern storage unit 16 Database storage unit 17 Database creation unit

Claims (5)

Quantify the likelihood of wiring failure in the design layout pattern of a semiconductor device by lithography and process as a score,
The quality of the design layout pattern is determined based on the score,
If the pass / fail judgment is good, a transfer layout pattern obtained by transferring the design layout pattern is formed on a semiconductor substrate. The score is
The minimum inter-surface distance at which the defect occurs in the transfer layout pattern in the inter-surface distance, where the standard deviation of the inter-surface distance between the surface of the semiconductor substrate and the imaging surface of the lithography is a distance unit. A method for manufacturing a semiconductor device according to claim 1. In the pass / fail judgment,
3. The transfer layout pattern based on the lithography and the process is created from the design layout pattern by simulation, and the presence / absence of the defect is determined in the transfer layout pattern. Semiconductor device manufacturing method.   4. The semiconductor according to claim 1, wherein if the pass / fail judgment is negative, the design layout pattern is deformed so that the score changes in a direction in which the defect is less likely to occur. Device manufacturing method. In a layout pattern creation program executed by a computer that can use the transfer layout pattern from a simulator that creates a transfer layout pattern based on lithography and process using a design layout pattern of a semiconductor device,
Quantifying as a score the likelihood of defects in the design layout pattern due to the lithography and the process based on the transfer layout pattern;
A layout pattern creation program for causing the computer to execute a procedure for determining whether or not the design layout pattern is acceptable based on the score.

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