JP2006268738A - Information processing apparatus, correction program creation method and correction program creation program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To create a correction program for carrying out processing different from one stored in a ROM. <P>SOLUTION: A microcomputer comprises a ROM storing a control program including a branch point address, a first register to which the branch point address is set, and an instruction output circuit for executing an instruction different from next one if an address of an instruction to be executed by a CPU matches the branch point address set to the first register, wherein the ROM stores a correction program generation program for causing the CPU to carry out, when the branch point address is inputted (S03), the step of writing the branch point address into an EEPROM (S04), the step of accepting an address and a setting value in a second register different from the first register (S05), the step of writing into the EEPROM an instruction for setting the second register into the accepted setting value (S06), and the step of writing into the EEPROM an instruction to return to an address next to the branch point address (S07). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, a correction program generation method, and a correction program generation program, and in particular, an information processing apparatus that generates a program for causing a CPU to execute processing different from a program stored in a read-only memory, and correction program generation The present invention relates to a method and a correction program generation program.

  Conventionally, many electric products are equipped with microcomputers. This microcomputer includes a central processing unit (CPU) for calculation, a read-only memory (ROM) in which a program is recorded, and a random access memory (RAM) used as a work area. The CPU executes calculations according to programs stored in the ROM.

  The program stored in the ROM cannot be changed after the ROM is made. On the other hand, at the present time when the product development period is very short, it is desired to produce the ROM early, and the program stored in the ROM must be determined at an early stage.

  However, the product specifications may be changed after the ROM production is started, and in this case, it is difficult to change the program stored in the ROM. Therefore, a technique for executing a program that is partially different from the program stored in the ROM is described in Japanese Patent Application Laid-Open No. 08-95946 (Patent Document 1). Japanese Patent Laid-Open No. 08-95946 has the following description. The figure numbers have been changed.

  Referring to FIG. 5, fetch pointer 1 is a 16-bit counter indicating the address of a program to be fetched from ROM 3 or RAM 4 to instruction queue 15. The address bus 2 is a 16-bit bus for transferring address data, and the data bus 11 is for transferring data.

  The ROM 3 is a read-only memory and corresponds to a memory space of addresses 0000H to EFFFH (H represents a hexadecimal number), and a program is stored therein. The RAM 3 is a readable / writable memory and corresponds to the memory space of addresses F000H to EFFFH.

  The memory 14 arranged outside stores the head address of the bug portion and the correction program.

  The serial interface 10 fetches the start address of the bug portion in the memory 14 and the correction program into the microcomputer 13.

  The register 6 stores and stores the head address of the bug portion taken in via the serial interface 10 and the data bus 11.

  The comparison circuit 5 compares the contents of the register 6 with the contents of the fetch pointer 1 input via the address bus 2, and if they match each other, the comparison circuit 5 is set to the high level, and if they do not match, Outputs a selection signal 12 at a low level.

  The branch instruction output circuit 9 outputs a branch instruction to the address F000H on the RAM 4.

  The selection circuit 8 outputs the branch instruction from the branch instruction output circuit 9 to the instruction queue 15 when the selection signal 12 from the comparison circuit 5 is high level (= active), and the selection signal 12 is low level (= inactive). In this case, the program on the ROM 3 or RAM 4 is output to the instruction queue 15.

  The instruction queue 15 is a 5-byte buffer in which an instruction prefetched (prefetched) while the CPU 7 executes an instruction is stored.

  The CPU 7 takes out the instruction from the instruction queue 15, decodes the instruction with an instruction decoder unit (not shown), and executes the decoded instruction with an execution unit (not shown).

  Here, as shown in the memory map of FIG. 6, it is assumed that the program exists at addresses 1000H to 7FFFH on the ROM 3, and a bug exists at addresses 4000H to 400FH.

  Referring to FIG. 6, the program start address 1000H is set in the vector table 0000H for setting the program start address. Thus, after the microcomputer 13 is released from the reset, the address 1000H becomes the fetch pointer 1 And execution of the program is started from the address 1000H.

  Assuming the existence of a bug, a routine for fetching the start address of the bug part and the correction program from the memory 14 into the microcomputer 13 is inserted into the initialization part of the program via the serial interface 10 in advance. .

  By executing this initialization portion, the bug portion start address 4000H and the correction program are fetched from the memory 14 into the microcomputer 13, and the bug portion start address fetched into the microcomputer 13 is set in the register 6 and corrected. The program is stored after the address F000H of the RAM 4.

  Thereafter, the CPU 7 continues to execute the program on the ROM 3 until the fetch pointer 1 reaches the head address of the bug portion.

  When the fetch pointer 1 reaches the head address of the bug part, that is, when the contents of the fetch pointer 1 and the register 6 match each other, the comparison circuit 5 outputs a high level selection signal 12 and the selection circuit 8 selects the selection signal. 12, the program on the ROM 3 is switched to the output of the branch instruction output circuit 9 and the branch instruction is output to the instruction queue 15.

  Here, since the branch instruction output circuit 9 outputs the branch instruction “BR! F000H” to the address F000H, the CPU 7 receives and executes the branch instruction from the instruction queue 15.

  Generally, the contents of the instruction queue are cleared by the execution of the branch instruction, and the contents of the instruction queue 15 are cleared by the branch instruction. The fetch pointer 1 is set to F000H, and the correction program on the RAM 4 is executed by the CPU 7 as shown in FIG.

  By putting the branch instruction “BR! 4010H” to address 4010H in the last part of the correction program, after executing the correction program, the program returns to the program on the original ROM 3 and the original program is executed. .

However, the microcomputer described in Japanese Patent Application Laid-Open No. 08-95946 needs to have a development environment such as a facility for developing a program stored in a ROM and a compiler. If the development environment is not in place, it is impossible to find out the position of the instruction address to be branched from the program stored in the ROM and the position of the instruction address to be restored. Furthermore, there is a problem that it is difficult to generate a correction program.
Japanese Patent Application Laid-Open No. 08-95946

  The present invention has been made to solve the above-described problems, and one of the objects of the present invention is a modification for executing processing different from the program regardless of the development environment of the program stored in the ROM. An information processing apparatus capable of easily generating a program, a correction program generation method, and a correction program generation program are provided.

  In order to achieve the above-described object, according to one aspect of the present invention, an information processing device sequentially reads a read-only memory storing a program including at least one branch point address and an instruction stored in the read-only memory. When the central processing unit to be executed, the nonvolatile memory, the first register in which the branch point address is set, and the address of the instruction executed by the central processing unit match the branch point address set in the first register The information processing apparatus includes a branching unit that executes an instruction different from the next instruction scheduled to be executed by the central processing unit, and a receiving unit that receives a signal from the outside. When the address is input, the step of writing the input branch point address to the nonvolatile memory, the address of the second register different from the first register, and the set value A step of writing to the nonvolatile memory an instruction for setting the second register of the received address to the received set value, and an instruction to return to the address next to the branch point address is written to the nonvolatile memory. A correction program generating program for causing the central processing unit to execute the steps is stored.

  Preferably, the read-only memory further stores an initialization program for causing the central processing unit to execute a step of setting the branch point address in the first register when the branch point address is stored in the nonvolatile memory.

  Preferably, the correction program generation program associates the predetermined branch point information with at least one branch point address, and is associated with the accepted branch point information in response to acceptance of the branch point information. Identifying a branch point address.

  According to another aspect of the present invention, a correction program generation method includes a read-only memory that stores a program including at least one branch point address, and a central processing unit that sequentially reads and executes instructions stored in the read-only memory. The central processing unit executes when the non-volatile memory, the first register in which the branch point address is set, and the address of the instruction executed by the central processing unit match the branch point address set in the first register A correction program generation method executed by an information processing apparatus having a branching unit for executing an instruction different from the next instruction to be executed and a receiving unit for receiving a signal from the outside, which is stored in a read-only memory When the branch point address is input, the modified program generation program is configured to write the input branch point address to the nonvolatile memory. Receiving an address and a set value of a second register different from the first register; writing an instruction for setting the second register at the received address to the received set value in the nonvolatile memory; And causing the central processing unit to execute a step of writing an instruction for returning to the address next to the branch point address to the nonvolatile memory.

  According to still another aspect of the present invention, a correction program generation program includes a read-only memory that stores a program including at least one branch point address, and a central processing unit that sequentially reads and executes instructions stored in the read-only memory And when the address of the instruction executed by the central processing unit matches the branch point address set in the first register, the central processing unit A correction program generation program that is executed by an information processing apparatus including a branching unit that executes an instruction different from the next instruction to be executed and a receiving unit that receives a signal from the outside, the read-only memory When the branch point address is stored and the branch point address is input, the step of writing the input branch point address to the nonvolatile memory; and the first register Receiving an address and a set value of another second register, writing an instruction for setting the second register of the received address to the received set value in the nonvolatile memory, and a branch point address The central processing unit is caused to execute a step of writing an instruction for returning to the next address to the nonvolatile memory.

  According to the present invention, when a branch point address is inputted, the branch point address is written into the nonvolatile memory, and when the address and the set value of the second register different from the first register are accepted, the branch point address is accepted. An instruction for setting the register at the specified address to the set value is written into the nonvolatile memory, and an instruction for returning to the instruction address next to the branch point is written into the nonvolatile memory. Therefore, it is possible to provide an information processing apparatus, a correction program generation method, and a correction program generation program capable of easily generating a correction program for executing processing different from the program recorded in the read-only memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a surveillance camera system in one embodiment of the present invention. In FIG. 1, the same members as those shown in FIG. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  The surveillance camera system 100 includes a surveillance camera 100 and a personal computer 110. In the figure, an example is shown in which one monitoring camera 100 and one personal computer 110 are shown. However, a plurality of monitoring cameras 100, a plurality of personal computers 110, or a plurality of both may be used. Also good. Since the personal computer 110 is a general computer and its hardware configuration and functions are well known to those skilled in the art, the description thereof will not be repeated here. Instead of the personal computer 110, a dedicated monitoring device for controlling the monitoring camera 100 may be used.

The surveillance camera 100 is an information processing apparatus, and includes a microcomputer 13 for controlling the whole and an EEPROM (Electronically Erasable and Programmable) connected to the serial interface 10 of the microcomputer 13.
Read Only Memory (A) 14A, lens 21, CCD (Charge Coupled Device) 22, and CDS (Correlated Double Sampling) / AGC (Auto Gain) to which an electrical signal output from the CCD 22 is input.
Control) circuit 23 and a digital signal processor (DSP) 24.

  Although the microcomputer 13 is connected to the memory 14 in FIG. 5, here, the microcomputer 13 is connected to the EEPROM 14 </ b> A as a specific example of the memory 14. In FIG. 5, one register 6 and one branch instruction output circuit 9 are shown. However, in this embodiment, there are one or more groups of the register 6 and the branch instruction output circuit 9. The number of sets of the register 6 and the branch instruction output circuit 9 is the same as or more than the number of correction programs in order to generate a plurality of correction programs to be described later.

  The microcomputer 13 controls the lens 21 so as to adjust the focus, change the imaging magnification, and change the pan and tilt imaging directions. The CCD 22 is a photoelectric conversion element that receives light transmitted through the lens 21 and outputs an electrical signal. A signal output from the CCD 22 is output to the CDS / AGC circuit 23.

  The CDS / AGC circuit 23 executes a process for suppressing noise in the electrical signal output from the CCD 22 and a process for controlling the gain of the electrical signal. The CDS / AGC circuit 23 is controlled by the microcomputer 13. Specifically, a coefficient value used in a process for suppressing noise is given from the microcomputer 13 to the CDS / AGC circuit 23. The CDS / AGC circuit 23 executes a process of suppressing noise of the electric signal using the given coefficient value. An initial value in gain control is given from the microcomputer 13 to the CDS / AGC circuit 23. The CDS / AGC circuit 23 starts gain control from the given initial value.

  The DSP 24 performs image processing and outputs the electrical signal whose noise is removed and gain-controlled by the CDS / AGC 23. The DSP 24 is controlled by the microcomputer 13. Specifically, a video signal control register is set from the microcomputer 13. The video signal control register is a register for setting shooting parameters.

  The control program stored in the ROM 3 included in the microcomputer 13 stores a coefficient value and an initial value for controlling the CDS / AGC circuit 23 and a value for controlling the DSP 24. The value for controlling the DSP 24 is a value for setting in the video signal control register. Here, these values are collectively referred to as setting values.

  Monitoring camera 100 is connected to personal computer 110. The monitoring camera 100 and the personal computer 110 may be either serial connection or parallel connection, or may be connected via a local area network (LAN). Further, these connections may be either wired or wireless.

  The personal computer 110 can control the surveillance camera 100 by transmitting a command signal to the surveillance camera 100. Specific examples of the command signal include a command signal for changing the shooting direction of the lens 21 and a command signal for changing the zoom magnification of the lens 21. Video captured by the monitoring camera 100 is transmitted from the DSP 24 to the personal computer 110. Therefore, the personal computer 110 can display the video received from the monitoring camera 100, record it on the hard disk, and the like.

  In the surveillance camera system in the present embodiment, by transmitting a predetermined set value from the personal computer 110 to the microcomputer 13, the microcomputer 13 uses a set value different from the set value stored in the ROM 3. Generate a correction program to control. The ROM 3 of the microcomputer 13 stores in advance a correction program generation program for generating this correction program.

  Although the surveillance camera 100 includes the EEPROM 14A, another nonvolatile semiconductor memory such as a flash memory, a magnetic recording medium, a magneto-optical recording medium, or the like may be used instead of the EEPROM 14A.

  In surveillance camera 100 in the present embodiment, a program is stored in ROM 3 in advance. Specifically, the ROM 3 includes a control program for controlling the lens 21, the CDS / AGC 23, and the DSP, a correction program generation program for generating a correction program for executing processing different from the control program, The initialization program is stored. The program stored in advance in the ROM 3 is different in that it includes a correction program generation program and a branch point is determined in advance in the control program.

  The branch point determined in advance in the control program is information for determining when to execute the correction program, and indicates one address of the control program. This branch point is determined when the control program is created. In order to specify the branch point, the address of the control program itself can be used, but here, branch point designation information is used. The branch point designation information is information for designating a branch point of the control program. The branch point designation information includes information for specifying the order of branch points or the type of processing of the control program.

  FIG. 2 is a diagram for explaining branch point designation information. FIG. 2A is a diagram illustrating an example when the branch point designation information is set to the order of branch points. Referring to FIG. 2A, the branch point designation information is shown in order, and the order is determined when the control program is created. The order indicates the order of branch points, and the smaller the control program address, the earlier the order. Here, the process name “activation process (parameter setting)” is associated with the order “1” of the branch point designation information. An instruction for setting the value of the fetch pointer 1 in the array variable X [1] is described in the address of the control program specified by this branch point. Further, the process name “timer process” is associated with the order “2” of the branch point designation information. An instruction for setting the value of the fetch pointer 1 to the array variable X [2] is described in the address of the control program specified by this branch point. Furthermore, the process name “interrupt process” is associated with the order “3” of the branch point designation information. An instruction for setting the value of the fetch pointer 1 in the array variable X [3] is described in the address of the control program specified by this branch point.

  Therefore, when the control program is executed by the CPU 7 of the microcomputer 13, the address of the control program at the branch point is set in the array variable X [i] (i is a natural number). When the order “i” of the branch point designation information is input, the microcomputer 13 can obtain the address of the branch point control program from the value of the array variable X [i] in the i order. Here, the order is 1 to 3, but it may be more or less.

  FIG. 2B is a diagram showing an example when the branch point designation information is information specifying the type of processing of the control program. Referring to FIG. 2B, the branch point designation information is indicated by a variable name. The variable name is determined when the control program is created corresponding to the process name. Here, the process name “activation process (parameter setting)” is associated with the variable name “KIDOU” of the branch point designation information. An instruction for setting the value of the fetch pointer 1 to the variable KIDOU is described in the address of the control program specified by this branch point. Further, the process name “timer process” is associated with the variable name “TIMER” of the branch point designation information. In the address of the control program specified by this branch point, an instruction for setting the value of the fetch pointer 1 in the variable TIMER is described. Further, the process name “interrupt process” is associated with the variable name “WARIKOMI” of the branch point designation information. At the address of the control program specified by this branch point, an instruction for setting the value of the fetch pointer 1 in the variable WARIKOMI is described.

  Therefore, when the control program is executed by the CPU 7 of the microcomputer 13, the address of the branch point control program is set in each variable. When the variable name is input, the microcomputer 13 can acquire the address of the control program at the branch point from the variable value of the variable name. In this example, the number of variables is KIDOU, TIMER, and WSRIKOMI. However, the number of variables may be larger or smaller. Furthermore, the variable name can be arbitrarily determined.

  FIG. 3 is a flowchart showing the flow of the correction program generation program stored in the ROM 3. This correction program generation program is executed by the CPU 7 of the microcomputer 13 and is executed upon occurrence of an interrupt when a communication command is received from the personal computer 110 connected thereto. That is, the correction program generation program is a program executed by the CPU 7 of the microcomputer on condition that a communication command is received from the personal computer 110 connected to the outside.

  Referring to FIG. 3, when a communication command is received from the outside of CPU 7 (step S01), the correction program generation program determines whether the received communication command is a command for instructing start of generation of the correction program. Is determined (step S02). If true, the process proceeds to step S03, and if false, the process ends. If it is false, the received communication command is an instruction to execute another process, so that a program corresponding to the other process is executed.

  In step S03, a branch point is received. Here, the address of the control program itself may be received as a branch point, or branch point designation information may be received. In the next step S04, the address of the control program corresponding to the branch point received in step S03 is acquired and written to a predetermined address in the EEPROM 14A. The address of the control program corresponding to the branch point is the address when the received branch point is the address of the control program itself. When the received branch point is branch point designation information, the address set in the array variable X [i] from the order i of the branch point designation information or the variable (KIDOU, TIMER, WARIKOMI) of the branch point designation information It is an address set to. The reason why the address to be written in the EEPROM 14A is a predetermined address is that the branch point address needs to be read out to the register 6 by the initialization process described later.

  In step S05, in order to change the value of the register, an address for specifying the register (setting register) and the changed value (setting value) are received. The address and setting value of the setting register are received from the personal computer 110. When there are a plurality of registers whose values are to be changed, the setting register addresses and setting values are received from the personal computer 110 by the number of registers to be changed, and step S05 is repeated.

  In the next step S06, an instruction for setting the setting value in the setting register from the setting register address and the setting value received in step S05 is written in the EEPROM 14A. The area where the instruction is written is determined in advance. When the CPU 7 executes an initialization process, which will be described later, in this initialization process, a program stored in a predetermined area of the EEPROM 14A is read to the RAM 4. In this way, an initialization program is created so that the initialization process is executed by the CPU 7. Therefore, when the initialization program is executed by the CPU 7, the correction program is recorded in a predetermined area of the EEPROM 14A so that the correction program is read into the RAM. If a plurality of setting register addresses and setting values are received in step S05, the commands are written in the order received.

  In the next step S07, a return instruction for returning from the correction program to the control program is written in the EEPROM 14A. The return address is preferably the address next to the address of the control program determined based on the branch point in step S04. Note that a return address may be received from the personal computer 110 and a return command for returning to the address may be written. The correction program is composed of one or more instructions written in step S06 and the return instruction written in step S07.

  In the next step S08, it is determined whether or not an end command indicating that the generation of the correction program is to be ended is received. If true, the process proceeds to step S08, and if false, the process returns to step S03. When returning to step S03, a correction program corresponding to another branch point is generated. In this case, the address of the EEPROM 14A for writing the address of the control program corresponding to the branch point in step S04 is written after the second time, and becomes a different address every time step S04 is executed. Similarly, the address of the EEPROM 14A for writing the correction program in steps S05 and S06 is written after the second time, and becomes a different address every time step S05 is executed.

  That is, the correction program is generated for each branch point, and the address of the control program corresponding to the branch point and the correction program are written in the EEPROM 14A for each branch point. In other words, a plurality of correction programs can be generated, and each of the generated correction programs is stored in the EEPROM 14A in association with the address of the control program corresponding to the branch point. Further, the address of the control program corresponding to the branch point written in the EEPROM 14A and the correction program are written in a predetermined position in the EEPROM 14A. When initialization processing described later is executed by the CPU 7, in order to set the address of the control program corresponding to the branch point in the register 6, it is necessary to read from the EEPROM 14A, and a correction program corresponding to the branch point is stored in the RAM 4 This is because it is necessary to read from the EEPROM 14 in order to read the data. Accordingly, the addresses of the EEPROM 14A are associated with the addresses of the control programs corresponding to the plurality of correction programs and the plurality of branch points.

  In step S09, initialization processing is executed. Thereafter, the process ends. As a result, the process returns to the position where the interruption occurred in step S01.

  FIG. 4 is a flowchart showing a flow of initialization processing executed in step S09 of FIG. This initialization process is the same as the initialization process executed by the microcomputer described in the prior art. Referring to FIG. 4, in the initialization process, first, data stored in EEPROM 14A is read (step S11). Here, it is determined whether or not the correction program is stored in a predetermined area of the EEPROM 14A (step S12). As described above, the correction program and the address of the control program corresponding to the branch point are stored in association with each other. Since a plurality of correction programs can be generated, the presence / absence of a correction program is determined based on all addresses at which the plurality of correction programs are to be recorded. If at least one correction program is stored, it is determined that the correction program is stored, and the process proceeds to step S13. If no correction program is stored, the process ends. Here, it is determined whether or not the correction program is recorded, but it may be determined whether or not the address of the control program corresponding to the branch point is recorded.

  In step S13, the address of the control program corresponding to the branch point is set in the register 6. In the next step S14, the correction program stored in the EEPROM 14A is copied to a predetermined area of the RAM 4. The predetermined area is determined by the branch instruction output from the branch instruction output circuit 9. For example, if the instruction output from the branch instruction output circuit 9 is a branch instruction to the address F000H of the RAM 4, the correction program is stored after the address F000H. When there are a plurality of correction programs, the registers 6 and branch instruction output circuits 9 corresponding to the number of the correction programs are required, and therefore the address of the control program stored in the EEPROM 14A is set in the corresponding register 6. Each of the plurality of correction programs is copied after the address of the RAM 4 determined based on the branch instruction output from the corresponding branch instruction output circuit 9.

  As a result, the comparison circuit 5 compares the address of the fetch pointer 1 with the address of the register 6, and when the two match, the instruction output from the branch instruction output circuit 9 is executed in the selection circuit 8. The correction program stored at the address of the RAM 4 determined by the branch instruction output from the branch instruction output circuit 9 is executed by the CPU 7.

  As described above, in the surveillance camera according to the present embodiment, the branch point address is determined when the control program is created, and the address itself is recorded, or the branch point is determined from the branch point information as the branch point address. An instruction for obtaining the address is written in the control program. Therefore, in response to the designation of the branch point from the personal computer 110 being accepted as the control program address itself or the branch point information, the address of the control program corresponding to the branch point is written to a predetermined address in the EEPROM 14A. It is. For this reason, even if the development environment for the control program is not in place and the address for branching the control program cannot be known, the recorded branch point address itself or branch point information is designated from the personal computer 110. As a result, the CPU 12 executing the correction program generation program can easily obtain the branch point address of the control program.

  When the address of the setting register and its set value are received from the personal computer 110, an instruction for setting the register of the received address to the set value is written into the EEPROM 14A, and the control program corresponding to the branch point is written. An instruction to return to the address next to the address is written in EEPROM 14A. When the control program is created, it is recorded by which instruction the register and the value set therein are referenced. When the correction program is generated, the address of the setting register and its set value are designated from the personal computer 110. be able to. For this reason, even if the development environment for the control program is not prepared, it is possible to easily generate a correction program for executing the control program on the CPU 12 and changing the value set in the register.

  Further, the address of the control program is set in the register 6 by the initialization process, and the correction program is copied to a predetermined area of the RAM 4. For this reason, it is possible to easily generate a correction program for causing the CPU 7 to execute processing different from the program recorded in the ROM 3.

  Specific examples of the change in the register value include a change in parameters used for processing related to image quality such as color reproduction, luminance adjustment, automatic gain control (AGC), and a parameter used for noise suppression processing executed by the CDS / AGC 23. The change of the imaging parameters used in the process executed by the DSP 24 can be applied. Furthermore, even when these parameters are fixed by the program of the ROM 3, it is possible to set parameters suitable for the environment where the monitoring camera 100 is installed. For example, it is effective when the surveillance camera 100 is installed in an installation environment where shooting with backlighting increases, an environment where the amount of light is relatively small, such as a corridor and a basement.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure showing the schematic structure of the surveillance camera system in one of the embodiments of the invention. It is a figure for demonstrating branch point designation | designated information. It is a flowchart which shows the flow of the correction program production | generation program memorize | stored in ROM. It is a flowchart which shows the flow of the initialization process performed by step S09 of FIG. It is a block diagram which shows the structure of the conventional microcomputer. It is a figure which shows the memory map of the conventional microcomputer.

Explanation of symbols

  1 fetch pointer, 2 address bus, 5 comparison circuit, 6 register, 8 selection circuit, 9 branch instruction output circuit, 10 serial interface, 11 data bus, 12 selection signal, 13 microcomputer, 14A EEPROM, 15 instruction queue, 21 lens , 22 CCD, 23 CDS / AGC, 24 DSP, 100 surveillance camera, 110 personal computer.

Claims (5)

A read only memory storing a program including at least one branch point address;
A central processing unit that sequentially reads and executes instructions stored in the read-only memory;
Non-volatile memory;
A first register in which the branch point address is set;
A branch that executes an instruction different from the next instruction scheduled to be executed by the central processing unit when the address of the instruction executed by the central processing unit matches the branch point address set in the first register Means,
An information processing apparatus comprising a receiving means for receiving a signal from the outside,
The read-only memory is
When the branch point address is input, writing the input branch point address to the nonvolatile memory;
Receiving an address and a set value of a second register different from the first register;
Writing an instruction to the non-volatile memory to set the second register at the accepted address to the accepted set value;
An information processing apparatus that stores a correction program generation program that causes the central processing unit to execute a step of writing an instruction for returning to an address next to the branch point address to the nonvolatile memory. The read-only memory is
The initialization program for causing the central processing unit to execute the step of setting the branch point address in the first register when the branch point address is stored in the nonvolatile memory is further stored. Information processing device. The correction program generating program associates predetermined branch point information with the at least one branch point address;
The information processing apparatus according to claim 1, further comprising: specifying a branch point address associated with the accepted branch point information in response to acceptance of the branch point information. A read only memory storing a program including at least one branch point address;
A central processing unit that sequentially reads and executes instructions stored in the read-only memory;
Non-volatile memory;
A first register in which the branch point address is set;
A branch for executing an instruction different from the next instruction scheduled to be executed by the central processing unit when the address of the instruction executed by the central processing unit coincides with a branch point address set in the first register Means,
A correction program generation method that is executed by an information processing apparatus including a receiving unit that receives a signal from the outside,
The correction program generation program stored in the read-only memory is
When the branch point address is input, writing the input branch point address to the nonvolatile memory;
Receiving an address and a set value of a second register different from the first register;
Writing an instruction to the non-volatile memory to set the second register at the accepted address to the accepted set value;
A correction program generation method that causes the central processing unit to execute a step of writing an instruction for returning to an address next to the branch point address to the nonvolatile memory. A read only memory storing a program including at least one branch point address;
A central processing unit that sequentially reads and executes instructions stored in the read-only memory;
Non-volatile memory;
A first register in which the branch point address is set;
A branch that executes an instruction different from the next instruction scheduled to be executed by the central processing unit when the address of the instruction executed by the central processing unit matches the branch point address set in the first register Means,
A correction program generation program executed by an information processing apparatus including a receiving unit that receives a signal from outside,
Stored in the read-only memory,
When the branch point address is input, writing the input branch point address to the nonvolatile memory;
Receiving an address and a set value of a second register different from the first register;
Writing an instruction to the non-volatile memory to set the second register at the accepted address to the accepted set value;
A correction program generation program that causes the central processing unit to execute a step of writing an instruction for returning to the address next to the branch point address to the nonvolatile memory.

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