JP2006261642A - Field effect transistor and method of fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in a parasitic resistance in a hetero interface of a field effect transistor having a hetero-junction so as to improve transistor characteristics such as high-frequency characteristics. <P>SOLUTION: On an undoped GaN buffer layer 2, there are formed an n-type AlGaN electron-donor layer 3, and an n-type InAlGaN cap layer 4 successively. On the n-type InAlGaN cap layer 4, Ti/Al ohmic electrodes 5 serve as a source electrode and a drain electrode, and are formed in contact with the n-type InAlGaN cap layer 4. In the interface of the n-type AlGaN electron-donor layer 3 and the n-type InAlGaN cap layer 4, the bottoms of the conduction bands of the two layers substantially are uninterrupted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor that can be used as a high-power high-frequency transistor and a method for manufacturing the same.

Group III-V nitride represented by GaN compound semiconductor _{(In x Al y Ga 1-} xy N ( where 0 ≦ x ≦ 1,0 ≦ y ≦ 1), hereinafter referred to as InAlGaN) is wider bandgap ( For example, the band gap of GaN has 3.4 eV) at room temperature and has a very large breakdown electric field and saturation electron velocity, and therefore has attracted attention as a material for high-power high-speed electronic devices. In particular, in a heterojunction structure in which an AlGaN film is laminated on a GaN film (hereinafter referred to as an AlGaN / GaN heterostructure), a strong polarization electric field on the (0001) plane causes high electrons near the heterojunction interface in the GaN film. Accumulating in concentration, so-called two-dimensional electron gas is formed. Since this two-dimensional electron gas is spatially separated from donor impurities added to the AlGaN film, it exhibits high electron mobility. Furthermore, the GaN-based material has a high so-called saturation drift velocity, and in a high electric field region of about 1 × 10 ⁵ V / cm, for example, is twice as high as the GaAs-based material currently popular as a high-frequency transistor material. Since it has the above electron velocity and has a large band gap and a large dielectric breakdown electric field, it is expected to be applied to a high-frequency / high-power device.

However, the field effect transistor (HEFT: Heterojunction Field Effect Transistor) having an AlGaN / GaN heterostructure has not yet achieved the high frequency characteristics expected from the material properties. One of the causes is a large parasitic resistance due to the ohmic resistance. This will be specifically described below. As a characteristic index of HEFT, cutoff frequency f _T and mutual conductance g _m can be mentioned, and there is a relationship represented by the following (formula 1).

f _T = g _m / (2πL _g ) (Formula 1)
Here, L _g is the gate length. As is clear from (Equation 1), in order to improve the cutoff frequency f _T , it is important to increase the mutual conductance g _m . In consideration of the parasitic resistance, g _m is expressed by the following (formula 2).

g _m = g _{m int} / (1 + R _s · g _{m int} ) (Formula 2)
Here, g _{m int} is intrinsic transconductance, which depends on the material and structure. R _s is a parasitic resistance from the ohmic electrode to the channel and is called a source resistance. As can be seen from (Equation 2), the mutual conductance g _m increases as the source resistance R _s decreases, and as a result, the cutoff frequency f _T also increases. Therefore, in order to improve the high frequency characteristics of HEFT, it is necessary to reduce the parasitic resistance.

  In the AlGaN / GaN-based HEFT, it is difficult to reduce contact resistance because an ohmic electrode is formed on AlGaN having a large forbidden band width (that is, a band gap). Therefore, a method has been used in which a cap layer made of a material having a small forbidden band width is sandwiched between an electrode and AlGaN, thereby reducing contact resistance. Conventionally, GaN has been used as such a cap layer (see Non-Patent Document 1). However, according to this method, since there is a difference between the polarization of GaN and the polarization of AlGaN, the potential barrier between GaN and AlGaN is raised. As a result, the parasitic resistance at the GaN / AlGaN interface increases, and as a result, there is a problem that the high frequency characteristics deteriorate.

  In order to cope with this problem, Patent Document 1 proposes a structure in which InAlGaN having a composition lattice-matched with GaN and having a polarization larger than that of AlGaN is used for the cap layer.

  FIG. 9A is a cross-sectional configuration diagram of a conventional field effect transistor disclosed in Patent Document 1. FIG. As shown in FIG. 9A, an undoped GaN buffer layer 102 is formed on a sapphire substrate 101 by epitaxial growth. A two-dimensional electron gas 107 is generated above the undoped GaN buffer layer 102, whereby the upper portion of the undoped GaN buffer layer 102 functions as a channel layer of the field effect transistor. On the undoped GaN buffer layer 102, an n-type AlGaN electron supply layer 103 and an n-type InAlGaN cap layer 104 are sequentially formed by epitaxial growth. In a predetermined region of the n-type InAlGaN cap layer 104, a recess reaching the n-type AlGaN electron supply layer 103 is formed, and the Pd—Si (alloy of Pd and Si) shot serving as a gate electrode is formed in the recess. A key electrode 106 is formed. Further, on both sides of the Schottky electrode 106 on the n-type InAlGaN cap layer 104, Ti / Al (having a laminated structure of a Ti layer and an Al layer) ohmic electrode 105 serving as a source electrode and a drain electrode is formed. Yes.

FIG. 9B shows changes in the composition of Al and In along the line YY ′ in FIG. 9A, and FIG. 9C shows the change in FIG. 9A. The change of the potential energy of the electron along the YY ′ line is shown.
T.Egawa et al., Recessed gate AlGaN / GaN modulation-doped field-effect transistors on sapphire, Applied Physics Letters Vol.76 P121-P123, USA, American Institute of physics, January 3, 2000 JP 2002-289837 A

  However, in the conventional field effect transistor disclosed in Patent Document 1, as shown in FIG. 9C, a large potential barrier exists at the InAlGaN / AlGaN interface, thereby increasing the parasitic resistance. There was a problem.

  In view of the above, an object of the present invention is to suppress an increase in parasitic resistance at a heterointerface in a field effect transistor having a heterojunction, thereby improving transistor characteristics such as high-frequency characteristics.

The inventors of the present application have studied the cause of the generation of a large potential barrier at the InAlGaN / AlGaN interface of the conventional field effect transistor, and as a result, have obtained the following knowledge. That is, the inventors of the present invention have examined the crystal growth conditions of the InAlGaN layer in detail and, as a result of optimization, the bowing parameter of InAlGaN is 2 to 3 times that of a conventionally known value (about 1 eV). I found it big. FIG. 10 shows the results of evaluation of the forbidden band width of In _0.09 Al _0.32 Ga _0.59 N by the cathodoluminescence (CL) method. Here, the forbidden band width Eg _InAlGaN of _InAlGaN is expressed by the following (formula 3).

Eg _InAlGaN = In composition × Eg _InN + Al composition × Eg _AlN + Ga composition × Eg _GaN
−C × (In composition + Al composition) × Ga composition (Formula 3)
Here, Eg _InN , Eg _AlN , and Eg _GaN are forbidden bandwidths of InN, AlN, and GaN, respectively, and C is a bowing parameter. As described above, the bowing parameter of InAlGaN was conventionally considered to be about 1 eV, but the bowing parameter obtained from the result shown in FIG. 10 is 2.3 eV. FIG. 11 shows the results of examining the forbidden band width Eg and the bowing parameter for a plurality of InAlGaN samples containing In _0.09 Al _0.32 Ga _0.59 N. The above evaluation results mean that even if the Al composition and In composition in InAlGaN are increased, the forbidden bandwidth is not so large. As a result, even if InAlGaN having the composition shown in Patent Document 1 is used as the cap layer, a large potential barrier exists at the InAlGaN / AlGaN interface as shown in FIG. The problem of increasing will arise.

  Based on the above findings, the inventors of the present application eliminate the potential barrier between the cap layer and the AlGaN layer by changing the Al composition of the AlGaN layer, thereby suppressing an increase in parasitic resistance at the heterointerface. The idea was to improve device characteristics such as high-frequency characteristics. That is, the present invention sets the difference between the lower ends of the respective conduction bands as small as possible at the interface between the AlGaN layer and the InAlGaN layer, in other words, sets the lower ends of the respective conduction bands to be substantially continuous. It is.

Specifically, the field-effect transistor according to the present invention includes a nitride semiconductor _{layer, In x Al y Ga 1-} xy N layer formed on the nitride semiconductor layer (where 0 <x <1, 0 <y <1, 0 and <x + y <1), and the _{in x Al y Ga 1-xy} N layer formed on and the _{in x Al y Ga 1-xy} N layer in contact with the source electrode and the drain electrode comprising, at the interface between the said nitride semiconductor layer _{in x Al y Ga 1-xy} N layer, the lower end of each of the conduction band is substantially continuous.

According to the field effect transistor of the present _{invention, In x Al y Ga 1-} xy N layer (hereinafter referred to as InAlGaN layer) ^{On, 3 × 10 -6 Ω · cm} 2 or less very low resistance ohmic electrodes ( Source electrode and drain electrode) can be formed. In addition, since the lower end of the conduction band of the InAlGaN layer serving as the cap layer and the lower end of the conduction band of the nitride semiconductor layer serving as the electron supply layer are continuous, a potential barrier at the interface between the nitride semiconductor layer and the InAlGaN layer is provided. Since the resistance can be lowered, parasitic resistance can be greatly reduced, and transistor characteristics such as high-frequency characteristics can be improved.

In the field effect transistor of the present invention, the polarization of _{In x Al y Ga 1-xy} N layer is preferably greater than the polarization of the polarization equal to or the nitride semiconductor layer of the nitride semiconductor layer.

  In this way, it is possible to suppress the generation of a depletion layer at the interface between the nitride semiconductor layer and the InAlGaN layer, thereby further suppressing an increase in potential barrier at the interface. Further, since a high concentration of electrons can be supplied to the channel layer, not only the parasitic resistance due to the potential barrier but also the parasitic resistance due to the channel resistance can be reduced.

In the field effect transistor of the present invention, it is preferable that the lattice constants are substantially equal at the interface between the nitride semiconductor layer and the In _x Al _y Ga _{1 -xy} N layer.

  In this case, since the InAlGaN layer can be formed thick, the resistance of the InAlGaN layer can be further reduced, and therefore, the parasitic resistance can be further reduced.

In the field effect transistor of the present invention, it is preferable that the forbidden band widths are substantially equal at the interface between the nitride semiconductor layer and the In _x Al _y Ga _{1 -xy} N layer.

  In this case, the difference in electron affinity between the nitride semiconductor layer and the InAlGaN layer, that is, the potential barrier is considered to be proportional to the difference in the forbidden band width between the nitride semiconductor layer and the InAlGaN layer. Since the barrier can be made very small, an increase in parasitic resistance caused by the potential barrier can be further suppressed.

In the field effect transistor of the present invention, the nitride semiconductor layer includes Al, Al composition in the nitride semiconductor layer is separated from the interface between the said nitride semiconductor layer _{In x Al y Ga 1-xy} N layer It is preferable to change so that it may become large according to this.

  In this way, the lower ends of the respective conduction bands can be reliably continued at the interface between the nitride semiconductor layer and the InAlGaN layer. Therefore, since the potential barrier at the interface can be eliminated, an increase in parasitic resistance can be reliably suppressed. The Al composition in the nitride semiconductor layer may increase linearly as the distance from the interface increases. Further, the Al composition in the nitride semiconductor layer may increase stepwise as the distance from the interface increases. Furthermore, the Al composition in the nitride semiconductor layer may increase in a convex quadratic curve shape as the distance from the interface increases.

In the field effect transistor of the present invention, between the nitride semiconductor layer and the _{In x Al y Ga 1-xy} N layer, a multilayer film and the GaN layer and the AlGaN layer are laminated at least one cycle or more alternately Furthermore, it is preferable to provide.

  In this way, the effective potential barrier between the InAlGaN layer and the nitride semiconductor layer can be reduced, an increase in parasitic resistance due to the potential barrier can be suppressed, and the interface between the InAlGaN layer and the nitride semiconductor layer can be suppressed. It is also possible to reduce the resistance in the direction parallel to.

In the field effect transistor of the present invention, a multilayer in which another InAlGaN layer and an AlGaN layer are alternately stacked at least one period or more between the nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer. It is preferable to further comprise a membrane.

  In this way, the effective potential barrier between the InAlGaN layer and the nitride semiconductor layer can be reduced, an increase in parasitic resistance due to the potential barrier can be suppressed, and the interface between the InAlGaN layer and the nitride semiconductor layer can be suppressed. It is also possible to reduce the resistance in the direction parallel to.

In the field effect transistor of the present invention, the nitride semiconductor layer has a pulse-like profile in a direction perpendicular to the interface between the nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer. It is preferable to have a region to which an impurity contributing to the conductivity type of the nitride semiconductor layer is added.

In this case, the conduction band is pushed down by the addition of impurities, so that electrons easily pass through the potential barrier. Therefore, since the influence of the potential barrier can be reduced, an increase in parasitic resistance can be further suppressed. In this case, it is preferable that the peak concentration of the impurity in the region is 1 × 10 ¹⁹ atoms / cm ³ or more.

In the field effect transistor of the present invention, the in a predetermined area of the _{In x Al y Ga 1-xy} N layer, said recess reaching the nitride semiconductor layer is formed, further the gate electrode formed in the recess You may have.

The first field effect transistor manufacturing method according to the present invention includes a step of forming a first nitride semiconductor layer on a substrate, and the first nitride semiconductor on the first nitride semiconductor layer. forming a second nitride semiconductor layer is larger bandgap than _{layer, in x Al y Ga 1-} xy N layer on the second nitride semiconductor layer (where 0 <x <1, 0 <y <1,0 <forming a x + y <1), in a predetermined area of the _{in x Al y Ga 1-xy} N layer, forming a recess reaching said second nitride semiconductor layer When a step of forming a gate electrode in the recess, on said _{in x Al y Ga 1-xy} N layer, forming a source electrode and a drain electrode in contact with said _{in x Al y Ga 1-xy} N layer and a step, at the interface between the said second nitride semiconductor layer _{in x Al y Ga 1-xy} N layer, its The lower end of the conduction band of, respectively is substantially continuous.

According to the first method for producing a field effect transistor, an extremely low resistance ohmic electrode (source electrode and drain electrode) of 3 × 10 ⁻⁶ Ω · cm ² or less can be formed on the InAlGaN layer. Further, since the lower end of the conduction band of the InAlGaN layer serving as the cap layer and the lower end of the conduction band of the second nitride semiconductor layer serving as the electron supply layer are continuous, the second nitride semiconductor layer and the InAlGaN layer are Since the potential barrier at the interface can be lowered, parasitic resistance can be greatly reduced, and transistor characteristics such as high-frequency characteristics can be improved.

The second field effect transistor manufacturing method according to the present invention includes a step of forming a first nitride semiconductor layer on a substrate, and the first nitride semiconductor on the first nitride semiconductor layer. A step of forming a second nitride semiconductor layer having a larger forbidden band width than the layer; a step of forming a mask layer on a predetermined region of the second nitride semiconductor layer; and a step of covering the mask layer. _{in x Al y Ga 1-xy} N layer on the second nitride semiconductor layer is not (where 0 <x <1,0 <y < 1,0 <x + y <1) selectively forming a If, by removing the mask layer, and forming a recess reaching said second nitride semiconductor layer, forming a gate electrode in the recess, the _{in x Al y Ga 1-xy} N on the layer, a source electrode and a drain electrode in contact with said _{in x Al y Ga 1-xy} N layer And a step of forming.

According to the second method for producing a field effect transistor, an extremely low resistance ohmic electrode (source electrode and drain electrode) of 3 × 10 ⁻⁶ Ω · cm ² or less can be formed on the InAlGaN layer. In addition, since the recess for forming the gate electrode can be formed without damaging the channel portion, an increase in parasitic resistance due to the channel resistance can be suppressed.

In the second field effect transistor manufacturing method, the mask layer may be made of SiO ₂ .

In the second method for fabricating a field effect transistor, the thickness of the mask layer is the In _x Al _y Ga preferably greater than the thickness of the _1-xy N layer.

  In this way, since the InAlGaN layer can be prevented from being formed on the mask layer, the size of the recess formed by removing the mask layer can be precisely controlled. Therefore, since a fine gate electrode can be formed, the channel length can be shortened, so that the parasitic resistance due to the channel resistance can be reduced.

In the second method for fabricating a field effect transistor, at the interface between the said second nitride semiconductor layer _{In x Al y Ga 1-xy} N layer, is the lower end of each of the conduction band is substantially continuous preferable.

  In this case, since the lower end of the conduction band of the InAlGaN layer serving as the cap layer and the lower end of the conduction band of the second nitride semiconductor layer serving as the electron supply layer are continuous, the second nitride semiconductor layer Since the potential barrier at the interface with the InAlGaN layer can be lowered, parasitic resistance can be greatly reduced, and transistor characteristics such as high-frequency characteristics can be improved.

In this case, or in the first field effect transistor manufacturing method, the second nitride semiconductor layer contains Al, and in the step of forming the second nitride semiconductor layer, the second nitride semiconductor layer is formed. It is preferable to change the Al composition in the layer so as to increase as the distance from the interface between the second nitride semiconductor layer and the In _x Al _y Ga _{1 -xy} N layer increases.

  In this way, the lower end of each conduction band can be reliably continued at the interface between the second nitride semiconductor layer and the InAlGaN layer. Therefore, since the potential barrier at the interface can be eliminated, an increase in parasitic resistance can be reliably suppressed. In the step of forming the second nitride semiconductor layer, the Al composition in the nitride semiconductor layer may be increased linearly with distance from the interface. In the step of forming the second nitride semiconductor layer, the Al composition in the nitride semiconductor layer may be increased stepwise as the distance from the interface increases. Furthermore, in the step of forming the second nitride semiconductor layer, the Al composition in the nitride semiconductor layer may be increased in a convex quadratic curve shape as the distance from the interface increases.

The method for manufacturing the first or second field effect transistor further includes a step of performing a heat treatment on the substrate after the step of forming the source electrode and the drain electrode, and the temperature of the heat treatment is the In it is preferably lower than the formation temperature of the _x Al _y Ga _1-xy N layer.

  By doing so, it is possible to suppress the deterioration of the crystallinity of the InAlGaN layer due to the heat treatment and maintain high crystallinity, and thus it is possible to suppress an increase in parasitic resistance.

In the manufacturing method of the first or second field effect transistor, after the step of forming the _{In x Al y Ga 1-xy} N layer, the n-type conductivity type in the _{In x Al y Ga 1-xy} N layer the impurities to provide a step of concentration of the impurities in the top of the _{in x Al y Ga 1-xy} N layer is added so as to be higher than the other portions, after the step, the in _x Al _y Ga ₁ It is preferable to further _{include a} step of performing a heat treatment on the substrate at a temperature lower than the formation temperature of the _-xy N layer.

  In this way, since the impurity concentration of the InAlGaN layer can be increased, the resistance of the InAlGaN layer can be reduced. In addition, since deterioration of the crystallinity of the InAlGaN layer due to heat treatment can be suppressed and high crystallinity can be maintained, parasitic resistance can be reduced.

  According to the present invention, an increase in parasitic resistance at the heterointerface between the nitride semiconductor layer and the InAlGaN layer can be suppressed, so that device characteristics such as high-frequency characteristics can be greatly improved.

(First embodiment)
Hereinafter, a field effect transistor and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a cross-sectional configuration diagram of a field effect transistor according to the first embodiment.

  As shown in FIG. 1A, an undoped GaN buffer layer 2 is formed on a sapphire substrate 1 by epitaxial growth. A two-dimensional electron gas 7 is generated above the undoped GaN buffer layer 2, whereby the upper portion of the undoped GaN buffer layer 2 functions as a channel layer of the field effect transistor. On the undoped GaN buffer layer 2, an n-type AlGaN electron supply layer 3 and an n-type InAlGaN cap layer 4 are sequentially formed by epitaxial growth. In a predetermined region of the n-type InAlGaN cap layer 4, a recess reaching the n-type AlGaN electron supply layer 3 is formed. On the n-type AlGaN electron supply layer 3 exposed in the recess, a gate electrode and A Pd—Si (alloy of Pd and Si) Schottky electrode 6 is formed. Further, on both sides of the Schottky electrode 6 on the n-type InAlGaN cap layer 4, Ti / Al (having a laminated structure of a Ti layer and an Al layer) ohmic electrode 5 serving as a source electrode and a drain electrode is formed. Yes.

The undoped GaN buffer layer 2 has a thickness of, for example, 2500 nm, the n-type AlGaN electron supply layer 3 has a thickness of, for example, 25 nm, and the n-type InAlGaN cap layer 4 has a thickness of, for example, 50 nm. The impurity concentration of the n-type AlGaN electron supply layer 3 is, for example, about 4.0 × 10 ¹⁸ atoms / cm ³ , and the impurity concentration of the n-type InAlGaN cap layer 4 is, for example, about 1.0 × 10 ¹⁹ atoms / cm ^3. It is.

  FIG. 1B is a diagram showing changes in the composition of each of Al and In along the line XX ′ in FIG. 1A, and FIG. It is a figure which shows the change of the potential energy of the electron along -X 'line. As shown in FIG. 1B, the feature of the present embodiment is that the Al composition in the n-type AlGaN electron supply layer 3 changes along the film thickness direction. Specifically, at the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4, the forbidden band widths Eg are substantially equal, in other words, at the interface, the respective conduction bands. The Al composition in the n-type AlGaN electron supply layer 3 is changed so as to increase with increasing distance from the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 so that the lower end of the n-type AlGaN electron supply layer 3 is substantially continuous. Yes. Thereby, as shown in FIG.1 (c), the potential barrier of an InAlGaN / AlGaN interface can be eliminated completely.

In the present embodiment, when, for example, In _0.09 Al _0.42 Ga _0.59 N (Eg = 3.68 eV, thickness 50 nm) is used as the n-type InAlGaN cap layer 4, the n-type AlGaN electron supply layer 3 is AlGaN (thickness) whose composition changes from Al _0.15 Ga _0.85 N (Eg = 3.68 eV) to Al _0.25 Ga _0.75 N (Eg = 3.91 eV) from the n-type InAlGaN cap layer 4 side toward the undoped GaN buffer layer 2 side 25nm), the above-mentioned effects are obtained.

In the present embodiment, when, for example, In _0.10 Al _0.47 Ga _0.43 N (Eg = 3.81 eV, thickness 50 nm) is used as the n-type InAlGaN cap layer 4, the n-type AlGaN electron supply layer 3 is AlGaN (thickness) whose composition changes from Al _0.21 Ga _0.79 N (Eg = 3.81 eV) to Al _0.25 Ga _0.75 N (Eg = 3.91 eV) from the n-type InAlGaN cap layer 4 side toward the undoped GaN buffer layer 2 side 25 nm), the above-mentioned effect is obtained.

In the present embodiment, the Al composition in the n-type AlGaN electron supply layer 3 is increased linearly as the distance from the interface with the n-type InAlGaN cap layer 4 increases (gradient composition), as shown in FIG. However, instead of this, as shown in FIG. 14, for example, it may be increased stepwise (stepped composition) as the distance from the interface increases. In this case, since the average Al composition of the n-type AlGaN electron supply layer 3 can be increased as compared with the gradient composition, the generated carrier concentration is increased, thereby reducing the parasitic resistance. be able to. In addition, the effect of the conduction band discontinuity that occurs in the stepwise composition can be reduced by reducing the amount of discontinuity at each stage. Specifically, when, for example, In _0.09 Al _0.42 Ga _0.59 N (Eg = 3.68 eV, thickness 50 nm) is used as the n-type InAlGaN cap layer 4, the first n-type AlGaN electron supply layer 3 is used as the first n-type InAlGaN cap layer 4. Al _0.18 Ga _0.82 N (Eg = 3.75 eV, thickness 8 nm) as the second stage and Al _0.22 Ga _0.78 N (Eg = 3.83 eV, thickness 8 nm) as the second stage and the third stage. By using a step-like composition AlGaN (total thickness 25 nm) made of Al _0.25 Ga _0.75 N (Eg = 3.91 eV, thickness 9 nm), the above-described effects are obtained. When, for example, In _0.10 Al _0.47 Ga _0.43 N (Eg = 3.81 eV, thickness 50 nm) is used as the n-type InAlGaN cap layer 4, the n-type AlGaN electron supply layer 3 is Al _0.22 Ga _0.78 N (Eg = 3.83 eV, thickness 5 nm) and Al _0.24 Ga _0.76 N (Eg = 3.86 eV, thickness 5 nm) as the second stage and Al _0.25 Ga as the third stage. By using a step-like composition AlGaN (total thickness 25 nm) composed of _0.75 N (Eg = 3.91 eV, thickness 15 nm), the above-described effects are obtained. The InAlGaN band gap value was calculated with a bowing parameter of 2.6, and the AlGaN band gap value was calculated with a bowing parameter of 1.0.

  In the present embodiment, the Al composition in the n-type AlGaN electron supply layer 3 increases in a convex quadratic curve as the distance from the interface with the n-type InAlGaN cap layer 4 increases, for example, as shown in FIG. It may be made to be (a quadratic functional composition). In this case, since the average Al composition of the n-type AlGaN electron supply layer 3 can be increased as compared with the gradient composition, the generated carrier concentration is increased, thereby reducing the parasitic resistance. be able to. In addition, although the conduction band is inclined in the direction that prevents the movement of electrons in the n-type AlGaN electron supply layer 3 as compared with the stepped composition, the conduction band discontinuity like the stepped composition does not occur. The influence resulting from the discontinuity can be suppressed.

  Hereinafter, conditions required for the composition of the InAlGaN layer used for the cap layer 4 will be described.

First, in order to form a thick InAlGaN layer, that is, to reduce parasitic resistance by reducing the resistance of the InAlGaN layer, it is necessary to lattice match the InAlGaN layer serving as the cap layer 4 and the GaN layer serving as the buffer layer 2. is there. Normally, the lattice constant of the electron supply layer (AlGaN layer) 3 and the lattice constant of the underlying buffer layer 2 are set to be equal. Conditions for lattice matching of the InAlGaN layer and the GaN layer are as follows. InAlGaN lattice constant a _InAlGaN is expressed by the following (formula 4).

a _InAlGaN = In composition × a _InN + Al composition × a _AlN + Ga composition × a _GaN
... (Formula 4)
Here, a _InN , a _AlN , and a _GaN are lattice constants of InN, AlN, and GaN, respectively. From the condition that the lattice constant a _{InAlGaN of InAlGaN} is equal to the lattice constant of GaN, the following (Formula 5) is derived.

Al composition = 4.66 × In composition (Formula 5)
That is, it is preferable that the Al composition and the In composition in the InAlGaN layer used for the cap layer 4 satisfy the relationship represented by (Formula 5). In this way, the forbidden band width of the InAlGaN layer can be freely changed in the region indicated by the dotted line in FIG. FIG. 2 shows the relationship between the forbidden band width and the lattice constant in the group III-V nitride compound semiconductor.

Next, generation of a depletion layer at the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 is suppressed to further suppress an increase in potential barrier at the interface, and a high concentration of electrons is supplied to the channel layer. In order to reduce the parasitic resistance due to the channel resistance, the InAlGaN layer needs to have a polarization higher than that of the AlGaN layer that is the electron supply layer 3. For this purpose, it is required that the Al composition and the In composition in the InAlGaN layer satisfy the relationship described below. That is, the polarization is given as the sum of the spontaneous polarization P _sp inherent to the material and the piezo polarization P _pe generated when the lattice is distorted due to an external force or the like. Here, the spontaneous polarization P _sp and the piezo polarization P _pe are expressed by the following (formula 6) and (formula 7), respectively (reference: Journal Of Applied Physics Vol.87, P334-P336).

P _sp = In composition × P _{sp InN} + Al composition × P _{sp AlN} + Ga composition × P _{sp GaN}
... (Formula 6)
P _pe = e ₃₃ · d _z + e ₃₁ · (d _x + d _y ) (Expression 7)
Here, P _{sp InN} , P _{sp AlN} , and P _{sp GaN} are spontaneous polarizations of InN, AlN, and GaN, respectively, e ₃₁ and e ₃₃ are piezo coefficients, and d _x and _dy are (0001) planes of the lattice. The amount of displacement in the inward direction, and d _z is the amount of displacement in the direction perpendicular to the (0001) plane of the lattice. FIG. 3 shows the In composition dependence of the magnitude of polarization generated in the InAlGaN layer, which is obtained from (Expression 6) and (Expression 7). Here, in consideration of lattice matching between InAlGaN and GaN, calculation was performed according to (Equation 5) assuming that the Al composition is 4.66 times the In composition. FIG. 3 also shows the magnitude of polarization generated in an AlGaN layer having an Al composition of 20% as an example of the AlGaN layer used for the electron supply layer 3. As shown in FIG. 3, in order to make the polarization generated in the InAlGaN layer used for the cap layer 4 equal to or higher than the polarization generated in the AlGaN layer used for the electron supply layer 3, the In composition is set to 8% or more. The Al composition may be set to 37% or more which is 4.66 times the In composition.

  FIG. 4 shows the current-voltage characteristics of the field effect transistor according to this embodiment (solid line). In FIG. 4, the vertical axis indicates the drain current per unit gate width, and the horizontal axis indicates the drain voltage. For reference, FIG. 4 also shows the current-voltage characteristics of the conventional field effect transistor shown in FIG. 9A (broken line). As shown in FIG. 4, according to the field effect transistor of this embodiment, the rise of the drain current is clearly improved as compared with the conventional field effect transistor. This is because in the conventional field effect transistor, a potential barrier is formed at the interface between the cap layer and the electron supply layer, whereas in the present embodiment, the potential barrier is not formed.

  As described above, according to the field effect transistor of the present embodiment, the n-type InAlGaN cap layer 4 and the n-type AlGaN electron supply layer 3 whose Al composition changes along the film thickness direction are stacked. The structure is used. For this reason, the lower end of each conduction band can be made substantially continuous at the heterointerface between the cap layer 4 and the electron supply layer 3. Therefore, since the potential barrier at the hetero interface between the cap layer 4 and the electron supply layer 3 can be lowered, it is possible to suppress an increase in parasitic resistance, thereby greatly improving device characteristics such as high-frequency characteristics. Become.

Further, according to the field effect transistor of the present embodiment, on the n-type InAlGaN cap layer 4, a very low resistance ohmic electrode 5 (being a source electrode and a drain electrode) of 3 × 10 ⁻⁶ Ω · cm ² or less. Can be formed.

  FIG. 12 is a diagram showing the results of investigation by the inventors of the present invention on the relationship between the work function of metal for AlGaN, GaN, and InAlGaN and the Schottky barrier height φ. As shown in FIG. 12, for InAlGaN, φ is very small for any metal. This suggests that the electron affinity of InAlGaN is large. Since any metal is used, φ becomes small, so that an ohmic electrode can be easily formed on n-type InAlGaN.

  FIG. 13 is a diagram showing the results of investigation by the inventors of the present invention on the current-voltage characteristics of GaN and InAlGaN when Mo (molybdenum) is used for the Schottky electrode. As shown in FIG. 13, rectification is observed for the current-voltage characteristic (broken line) of GaN, whereas current flows for both positive and negative biases for the current-voltage characteristic (solid line) of InAlGaN. And no rectification is seen. This shows that an ohmic electrode having a very low resistance can be formed on n-type InAlGaN.

  Hereinafter, a method for manufacturing the field effect transistor of this embodiment shown in FIG. 1A will be described.

  5A to 5D are cross-sectional views showing respective steps of the method for manufacturing the field effect transistor of this embodiment.

First, as shown in FIG. 5A, an undoped GaN buffer layer 2 and n-type AlGaN are formed on the (0001) surface of the sapphire substrate 1 by metal organic chemical vapor deposition (MOCVD). The electron supply layer 3 and the n-type InAlGaN cap layer 4 are formed in order. Note that the forbidden band width of the n-type AlGaN electron supply layer 3 is larger than that of the undoped GaN buffer layer 2. Further, each of the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 is doped with Si using SiH ₄ gas. Further, when the n-type AlGaN electron supply layer 3 is formed, the Al composition is changed in the film thickness direction. Specifically, the Al composition in the n-type AlGaN electron supply layer 3 is changed so as to increase as the distance from the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 increases. Thus, the forbidden band width of the n-type AlGaN electron supply layer 3 and the forbidden band width of the n-type InAlGaN cap layer 4 are set to be substantially the same at the InAlGaN / AlGaN hetero interface.

Subsequently, a photoresist (not shown) having a stripe-shaped opening is formed on the n-type InAlGaN cap layer 4. Here, the width of the stripe is, for example, about 5 μm. Next, as shown in FIG. 5B, the n-type InAlGaN cap layer 4 is selectively formed by inductively coupled plasma (ICP) etching using, for example, Cl ₂ gas using the photoresist as a mask. By removing, a recess (concave portion) exposing the n-type AlGaN electron supply layer 3 is formed.

Next, as shown in FIG. 5 (c), Ti / Al ohmic electrodes 5 serving as source and drain electrodes are formed on both sides of the recess on the n-type InAlGaN cap layer 4 by, for example, electron beam evaporation and lift-off. Form. Thereafter, heat treatment is performed in an N ₂ atmosphere at 600 ° C., for example, in order to reduce the contact resistance. Here, it is preferable that the heat treatment temperature be lower than the formation temperature of the n-type InAlGaN cap layer 4. In this way, the crystallinity deterioration of the n-type InAlGaN cap layer 4 caused by the heat treatment can be suppressed and high crystallinity can be maintained, so that an increase in parasitic resistance can be suppressed.

  Next, as shown in FIG. 5D, on the n-type AlGaN electron supply layer 3 exposed in the recess, Pd—Si (Pd and Si) serving as a gate electrode is formed by, for example, electron beam evaporation and lift-off. Alloy) Schottky electrode 6 is formed. Thereby, the field effect transistor of this embodiment shown to Fig.1 (a) can be completed.

  According to the field effect transistor manufacturing method of the present embodiment described above, the field effect transistor of the present embodiment shown in FIG. 1A is obtained, and therefore the potential at the heterointerface between the cap layer 4 and the electron supply layer 3 is obtained. Since the barrier can be lowered, an increase in parasitic resistance can be suppressed, thereby making it possible to greatly improve device characteristics such as high-frequency characteristics.

  In the method of manufacturing the field effect transistor of this embodiment, after adding the n-type InAlGaN cap layer 4, when an impurity providing an n-type conductivity is added to the n-type InAlGaN cap layer 4, the n-type InAlGaN cap layer is added. It is preferable that the impurity concentration in the uppermost part of 4 is higher than that in the other parts. Moreover, it is preferable to perform heat treatment at a temperature lower than the formation temperature of the n-type InAlGaN cap layer 4 after the addition of impurities. In this way, since the impurity concentration of the n-type InAlGaN cap layer 4 can be increased, the contact resistance between the Ti / Al ohmic electrode 5 and the n-type InAlGaN cap layer 4 can be lowered and the n-type InAlGaN cap layer can be reduced. 4 resistance can be lowered. Moreover, since the deterioration of the crystallinity of the n-type InAlGaN cap layer 4 due to the heat treatment can be suppressed and the high crystallinity can be maintained, the parasitic resistance can be reduced.

(Modification of the first embodiment)
Hereinafter, a method of manufacturing a field effect transistor according to a modification of the first embodiment of the present invention will be described with reference to the drawings. This modification is a method for manufacturing the field effect transistor according to the first embodiment shown in FIG.

  6A to 6F are cross-sectional views showing respective steps of the method for manufacturing the field effect transistor of the present modification. In the first embodiment, in the step shown in FIG. 5B, the n-type InAlGaN cap layer 4 is etched to form a recess that becomes a gate electrode formation region. In this modification, as will be described later, the recess is formed by regrowing the n-type InAlGaN cap layer 4 after masking the gate electrode formation region on the n-type AlGaN electron supply layer 3.

First, as shown in FIG. 6A, an undoped GaN buffer layer 2 and an n-type AlGaN electron supply layer 3 are sequentially formed on the (0001) plane of the sapphire substrate 1 by MOCVD. Note that the forbidden band width of the n-type AlGaN electron supply layer 3 is larger than that of the undoped GaN buffer layer 2. The n-type AlGaN electron supply layer 3 is doped with Si using SiH ₄ gas. Further, when the n-type AlGaN electron supply layer 3 is formed, the Al composition is changed in the film thickness direction. Specifically, the Al composition in the n-type AlGaN electron supply layer 3 changes so as to increase as the distance from the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 (see FIG. 6C) increases. Let Thus, the forbidden band width of the n-type AlGaN electron supply layer 3 and the forbidden band width of the n-type InAlGaN cap layer 4 are made substantially the same at the InAlGaN / AlGaN hetero interface. In other words, at the InAlGaN / AlGaN hetero interface, the lower end of the conduction band of the n-type AlGaN electron supply layer 3 and the lower end of the conduction band of the n-type InAlGaN cap layer 4 are substantially continuous.

Next, on the n-type AlGaN electron supply layer 3, SiO 100 having a thickness of about 100 nm is formed by, for example, a vapor deposition method using SiH ₄ gas and O ₂ gas, specifically, a CVD (Chemical Vapor Depositon) method. _Two films are formed. Subsequently, in order to process the SiO ₂ film into a stripe shape having a width of, for example, 5 μm, the SiO ₂ film is selectively etched using a hydrofluoric acid (HF) aqueous solution with a photoresist as a mask, for example. As shown in FIG. 6B, the SiO ₂ mask 8 is formed.

Here, the thickness of the SiO ₂ film to be the SiO ₂ mask 8 is preferably larger than the thickness of the n-type InAlGaN cap layer 4 to be formed later. In this way, the dimensions of the recess (concave portion) formed by the removal of the SiO ₂ mask 8 it is possible to prevent the n-type InAlGaN cap layer 4 is formed, after the process on the SiO ₂ mask 8 Can be precisely controlled. Therefore, since a fine gate electrode can be formed, the channel length can be shortened, so that the parasitic resistance due to the channel resistance can be reduced.

Next, as shown in FIG. 6C, the growth of the InAlGaN layer is started from a portion not covered with the SiO ₂ mask 8 in the n-type AlGaN electron supply layer 3 by using, for example, the MOCVD method. A type InAlGaN cap layer 4 is formed. Note that the thickness of the n-type InAlGaN cap layer 4 is smaller than the thickness of the n-type AlGaN electron supply layer 3. Subsequently, as shown in FIG. 6 (d), the SiO ₂ mask 8 is removed using, for example, a hydrofluoric acid (HF) aqueous solution to form a (concave portion) reaching the n-type AlGaN electron supply layer 3. .

Next, similarly to the process shown in FIG. 5C of the first embodiment, as shown in FIG. 6E, on both sides of the recess on the n-type InAlGaN cap layer 4, for example, electron beam evaporation is performed. And Ti / Al ohmic electrode 5 used as a source electrode and a drain electrode is formed by lift-off. Thereafter, heat treatment is performed in an N ₂ atmosphere at 600 ° C., for example, in order to reduce the contact resistance. Here, it is preferable that the heat treatment temperature be lower than the formation temperature of the n-type InAlGaN cap layer 4. In this way, the crystallinity deterioration of the n-type InAlGaN cap layer 4 caused by the heat treatment can be suppressed and high crystallinity can be maintained, so that an increase in parasitic resistance can be suppressed.

  Next, similarly to the step shown in FIG. 5D of the first embodiment, as shown in FIG. 6F, on the n-type AlGaN electron supply layer 3 in the recess, for example, electron beam evaporation and By lift-off, a Pd—Si (an alloy of Pd and Si) Schottky electrode 6 to be a gate electrode is formed. Thereby, the field effect transistor of this embodiment shown to Fig.1 (a) can be completed.

  According to this modification, the same effect as that of the first embodiment can be obtained. In addition, since a recess for forming the gate electrode can be formed in the lower region of the gate electrode that becomes the channel portion without causing damage due to etching, transistor characteristics such as an increase in parasitic resistance due to the channel resistance. It becomes possible to prevent degradation of the.

In this modification, SiO ₂ is used as the material of the mask 8, but instead of this, other materials that can obtain a selectivity with the III-V nitride compound semiconductor may be used.

(Second Embodiment)
Hereinafter, a field effect transistor and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 is a cross-sectional configuration diagram of a field effect transistor according to the second embodiment. In FIG. 7, the same components as those in the first embodiment shown in FIG. The second embodiment differs from the first embodiment in that, as will be described later, another InAlGaN layer and an AlGaN layer are alternately stacked at least one period or more directly under the n-type InAlGaN cap layer 4. A multilayer film is provided, and a delta-doped layer (n-type AlGaN electron supply) is formed on the n-type AlGaN electron supply layer 3 (Al composition changes along the film thickness direction as in the first embodiment). A region to which an impurity contributing to the conductivity type of the n-type AlGaN electron supply layer 3 is added so as to generate a pulse-like profile in a direction perpendicular to the interface between the layer 3 and the n-type InAlGaN cap layer 4. It is that.

As shown in FIG. 7, on the undoped GaN buffer layer 2 on the sapphire substrate 1, an AlN spacer layer 11 and an n-type AlGaN electron supply layer 3 are formed by epitaxial growth. A two-dimensional electron gas 7 is generated above the undoped GaN buffer layer 2, whereby the upper portion of the undoped GaN buffer layer 2 functions as a channel layer of the field effect transistor. A SiO ₂ mask 20 is provided below the undoped GaN buffer layer 2. On the n-type AlGaN electron supply layer 3, there is a multilayer film 10 in which, for example, an n-type InAlGaN thin film having a thickness of 1.5 nm and an n-type AlGaN thin film having a thickness of 1.5 nm, for example, are alternately stacked, for example, seven periods. Is formed. An n-type InAlGaN cap layer 4 is formed on the multilayer film 10 by epitaxial growth. In a predetermined region of the n-type InAlGaN cap layer 4, a recess reaching the n-type AlGaN electron supply layer 3 is formed. On the n-type AlGaN electron supply layer 3 exposed in the recess, a gate electrode and A Pd—Si (alloy of Pd and Si) Schottky electrode 6 is formed. Further, on both sides of the Schottky electrode 6 on the n-type InAlGaN cap layer 4, Ti / Al (having a laminated structure of a Ti layer and an Al layer) ohmic electrode 5 serving as a source electrode and a drain electrode is formed. Yes.

  Also in this embodiment, the Al composition in the n-type AlGaN electron supply layer 3 changes along the film thickness direction. Specifically, the forbidden band widths Eg are substantially equal at the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 (in this embodiment, the multilayer film 10 is interposed in the interface). In other words, the Al composition in the n-type AlGaN electron supply layer 3 is changed between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap so that the lower ends of the respective conduction bands are substantially continuous at the interface. It changes so that it may become large as it leaves | separates from the interface with the layer 4 (refer FIG.1 (b)). As a result, the potential barrier at the InAlGaN / AlGaN interface can be completely eliminated (see FIG. 1C).

Further, a delta doped layer 9 is formed in a region near the multilayer film 10 in the n-type AlGaN electron supply layer 3. The impurity concentration of the delta doped layer 9 is about 1 × 10 ¹⁹ atoms / cm ³ or more.

Further, the thickness of the undoped GaN buffer layer 2 is, for example, 2500 nm, the thickness of the AlN spacer layer 11 is, for example, 1 nm, the thickness of the n-type AlGaN electron supply layer 3 is, for example, 25 nm, and the thickness of the delta-doped layer 9 For example, the thickness is 5 nm or less, the thickness of the multilayer film 10 is 21 nm, for example, and the thickness of the n-type InAlGaN cap layer 4 is 50 nm, for example. The impurity concentration of the n-type AlGaN electron supply layer 3 is, for example, about 4.0 × 10 ¹⁸ atoms / cm ³ , and the impurity concentration of the delta doped layer 9 is, for example, 1 × 10 ¹⁹ atoms / cm ³ or more. The impurity concentration of the entire 10 is, for example, about 1.0 × 10 ¹⁹ atoms / cm ³ , and the impurity concentration of the n-type InAlGaN cap layer 4 is, for example, about 1.0 × 10 ¹⁹ atoms / cm ³ .

  According to the field effect transistor of the present embodiment, the forbidden band width Eg at the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 (in this embodiment, the multilayer film 10 is interposed in the interface). In other words, the Al composition in the n-type AlGaN electron supply layer 3 is changed so that the lower ends of the respective conduction bands are substantially continuous at the interface. For this reason, since the potential barrier at the hetero interface between the cap layer 4 and the electron supply layer 3 can be lowered, an increase in parasitic resistance can be suppressed, and thereby device characteristics such as high-frequency characteristics can be greatly improved. become.

  Further, according to the field effect transistor of the present embodiment, the delta doped layer 9 is provided in the n-type AlGaN electron supply layer 3. For this reason, since the conduction band of the n-type AlGaN electron supply layer 3 is pushed down by the addition of impurities, electrons easily pass through the potential barrier. That is, since it becomes possible to eliminate the influence of the potential barrier, the increase in parasitic resistance can be further suppressed.

  Further, according to the field effect transistor of this embodiment, a multilayer film in which an InAlGaN layer and an AlGaN layer are alternately stacked at least one period or more between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4. 10 is provided. For this reason, the influence of the potential barrier between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 can be suppressed, an increase in parasitic resistance due to the potential barrier can be suppressed, and the horizontal direction (n-type AlGaN Parasitic resistance in the direction parallel to the interface between the electron supply layer 3 and the n-type InAlGaN cap layer 4) can be greatly reduced.

  Further, according to the field effect transistor of the present embodiment, since the AlN spacer layer 11 is interposed between the undoped GaN buffer layer 2 and the n-type AlGaN electron supply layer 3, alloy scattering is suppressed. Electron mobility is improved, thereby reducing parasitic resistance due to channel resistance.

  As described above, the field effect transistor according to this embodiment includes the n-type InAlGaN cap layer 4 in which the multilayer film 10 in which the InAlGaN layers and the AlGaN layers are alternately stacked at least one period is provided directly below, and the delta doping. Since the layer is provided and the n-type AlGaN electron supply layer 3 in which the Al composition changes along the film thickness direction, an increase in parasitic resistance at the heterointerface between the cap layer 4 and the electron supply layer 3 can be suppressed, As a result, it is possible to greatly improve element characteristics such as high-frequency characteristics.

  Hereinafter, a method for manufacturing the field effect transistor of this embodiment shown in FIG. 7 will be described.

  8A to 8F are cross-sectional views showing respective steps of the method for manufacturing the field effect transistor of this embodiment.

First, as shown in FIG. 8A, an undoped GaN buffer layer 2 is grown partway on the (0001) plane of the sapphire substrate 1 by MOCVD. Subsequently, a SiO ₂ film having a thickness of about 100 nm is formed on the undoped GaN buffer layer 2 by, for example, a vapor deposition method (specifically, a CVD method) using SiH ₄ gas and O ₂ gas. Subsequently, hydrofluoric acid (HF, for example, using a photoresist as a mask so as to form a plurality of SiO ₂ stripes having a width of 10 μm by providing a plurality of stripe-shaped openings having a width of 5 μm, for example, in the SiO ₂ film. ) Selectively etch the SiO ₂ film using an aqueous solution. Thereby, the SiO ₂ mask 20 is formed.

Subsequently, as shown in FIG. 8B, GaN is regrown from the surface of the undoped GaN buffer layer 2 not covered with the SiO ₂ mask 20 by, for example, MOCVD, so that an undoped layer having a desired thickness is obtained. The GaN buffer layer 2 is completed. In this MOCVD method GaN growth process by, since GaN crystal growth in the form of lateral growth on the SiO ₂ mask 20 is advanced, the threading dislocation density is greatly reduced than on SiO ₂ mask 20, as a result, 10 ⁶ A dislocation density on the order of cm ⁻² is obtained. Subsequently, the AlN spacer layer 11 and the n-type AlGaN electron supply layer 3 are sequentially formed on the undoped GaN buffer layer 2 by, eg, MOCVD. Note that the forbidden band width of the n-type AlGaN electron supply layer 3 is larger than that of the undoped GaN buffer layer 2. Each of the n-type AlGaN electron supply layers 3 is doped with Si using SiH ₄ gas.

Here, in the middle of forming the n-type AlGaN electron supply layer 3, the supply of the source gas is temporarily stopped, and as shown in FIG. 8C, the delta doped layer 9 is formed by flowing only SiH ₄ gas, and thereafter The formation of the n-type AlGaN electron supply layer 3 is resumed by restarting the supply of the source gas. Note that when the n-type AlGaN electron supply layer 3 is formed, the Al composition is changed in the film thickness direction. Specifically, the Al composition in the n-type AlGaN electron supply layer 3 is changed so as to increase as the distance from the interface between the n-type AlGaN electron supply layer 3 and the n-type InAlGaN cap layer 4 increases. Thus, the forbidden band width of the n-type AlGaN electron supply layer 3 and the forbidden band width of the n-type InAlGaN cap layer 4 are set to be substantially the same at the InAlGaN / AlGaN hetero interface.

Next, as shown in FIG. 8C, on the n-type AlGaN electron supply layer 3, for example, an n-type InAlGaN thin film having a thickness of 1.5 nm and an n-type AlGaN thin film having a thickness of 1.5 nm, for example, are alternately arranged. After the multilayer film 10 having a structure in which at least one period is stacked on the multilayer film 10 by epitaxial growth, the n-type InAlGaN cap layer 4 is formed on the multilayer film 10. The n-type InAlGaN cap layer 4 is doped with Si using SiH ₄ gas.

Subsequently, a photoresist (not shown) having a stripe-shaped opening is formed on the n-type InAlGaN cap layer 4. Here, the width of the stripe is, for example, about 5 μm. Next, using the photoresist as a mask, the n-type InAlGaN cap layer 4 is selectively removed by inductively coupled plasma (ICP) etching using, for example, Cl ₂ gas, as shown in FIG. A recess (concave portion) exposing the n-type AlGaN electron supply layer 3 is formed. At this time, the recess is formed so that the n-type AlGaN electron supply layer 3 located deeper than the delta doped layer 9 is exposed.

Next, as shown in FIG. 8 (e), Ti / Al ohmic electrodes 5 to be source and drain electrodes are formed on both sides of the recess on the n-type InAlGaN cap layer 4 by, for example, electron beam evaporation and lift-off. Form. Thereafter, heat treatment is performed in an N ₂ atmosphere at 600 ° C., for example, in order to reduce the contact resistance. Here, it is preferable that the heat treatment temperature be lower than the formation temperature of the n-type InAlGaN cap layer 4. In this way, the crystallinity deterioration of the n-type InAlGaN cap layer 4 caused by the heat treatment can be suppressed and high crystallinity can be maintained, so that an increase in parasitic resistance can be suppressed.

  Next, as shown in FIG. 8F, on the n-type AlGaN electron supply layer 3 exposed in the recess, Pd—Si (Pd and Si) serving as a gate electrode is formed by, for example, electron beam evaporation and lift-off. Alloy) Schottky electrode 6 is formed. Thereby, the field effect transistor of this embodiment shown in FIG. 7 can be completed.

  According to the field effect transistor manufacturing method of the present embodiment described above, the field effect transistor of the present embodiment shown in FIG. 7 is obtained, and therefore the potential barrier at the heterointerface between the cap layer 4 and the electron supply layer 3 is lowered. Therefore, it is possible to suppress an increase in parasitic resistance, thereby greatly improving element characteristics such as high-frequency characteristics.

  In the method of manufacturing the field effect transistor of this embodiment, after adding the n-type InAlGaN cap layer 4, when an impurity providing an n-type conductivity is added to the n-type InAlGaN cap layer 4, the n-type InAlGaN cap layer is added. It is preferable that the impurity concentration in the uppermost part of 4 is higher than that in the other parts. Moreover, it is preferable to perform heat treatment at a temperature lower than the formation temperature of the n-type InAlGaN cap layer 4 after the addition of impurities. In this way, since the impurity concentration of the n-type InAlGaN cap layer 4 can be increased, the contact resistance between the Ti / Al ohmic electrode 5 and the n-type InAlGaN cap layer 4 can be lowered and the n-type InAlGaN cap layer can be reduced. 4 resistance can be lowered. Moreover, since the deterioration of the crystallinity of the n-type InAlGaN cap layer 4 due to the heat treatment can be suppressed and the high crystallinity can be maintained, the parasitic resistance can be reduced.

  In this embodiment, the multilayer film 10 is a multilayer film in which InAlGaN layers and AlGaN layers are alternately stacked for at least one cycle. Instead, the GaN layers and AlGaN layers are alternately stacked. The same effect can be obtained even when a multilayer film formed by laminating at least one period is used.

  In the first or second embodiment, the undoped GaN buffer layer 2 and the n-type AlGaN electron supply layer 3 are grown on the (0001) plane of the sapphire substrate 1. Is not particularly limited. For example, a plane orientation having an off-angle with respect to a representative plane such as the (0001) plane may be used.

In the first or second embodiment, the sapphire substrate 1 is used, but instead of this, SiC, GaN, AlN, Si, GaAs, ZnO, MgO, ZrB ₂ , LiGaO ₂ , LiAlO ₂ , GaP, Even when a substrate made of InP or a mixed crystal of at least two of them is used, a nitride semiconductor having excellent crystallinity can be epitaxially grown as in the present embodiment.

  In the first or second embodiment, the epitaxial growth layers (such as the GaN buffer layer 2 and the n-type AlGaN electron supply layer 3) constituting the field effect transistor have any composition ratio as long as desired device characteristics can be realized. Or may include any multilayer structure. Further, the crystal growth method of the epitaxial growth layer is not limited to the MOCVD method, and for example, a molecular beam epitaxy (MBE) method or a hydride vapor phase epitaxy (HVPE) method may be used. . In addition, layers formed by different crystal growth methods may be included in the epitaxial growth layer. The epitaxial growth layer may contain a group V element such as As or P or a group III element such as B as a constituent element. Further, the epitaxial growth layer is not limited to the GaN-based semiconductor layer, and a GaAs-based semiconductor layer or an InP-based semiconductor layer may be used.

  Specifically, in the first or second embodiment, GaN and AlGaN are used as the buffer layer 2 and the electron supply layer 3, respectively. Instead, GaN and AlN, InAlGaN and AlN, or InGaN and GaN. May be used.

  The present invention relates to a field effect transistor and a manufacturing method thereof, and when applied to a high-frequency high-power transistor, suppresses an increase in parasitic resistance at a heterointerface between a nitride semiconductor layer and an InAlGaN layer, thereby improving device characteristics such as high-frequency characteristics It can be greatly improved and is very useful.

FIG. 1A is a cross-sectional configuration diagram of a field effect transistor according to the first embodiment of the present invention, and FIG. 1B shows Al and XX ′ lines in FIG. It is a figure which shows the change of each composition of In, and FIG.1 (c) is a figure which shows the change of the potential energy of the electron along the XX 'line | wire of Fig.1 (a). FIG. 2 is a diagram showing the relationship between the forbidden band width and the lattice constant in the III-V nitride compound semiconductor. FIG. 3 is a diagram showing the In composition dependence of the magnitude of polarization occurring in the InAlGaN layer. FIG. 4 is a diagram showing current-voltage characteristics of the field effect transistor according to the first embodiment of the present invention and the conventional field effect transistor. 5A to 5D are cross-sectional views showing respective steps of the method for manufacturing the field effect transistor according to the first embodiment of the present invention. 6 (a) to 6 (f) are cross-sectional views showing respective steps of a method for manufacturing a field effect transistor according to a modification of the first embodiment of the present invention. FIG. 7 is a cross-sectional configuration diagram of a field effect transistor according to the second embodiment of the present invention. FIGS. 8A to 8F are cross-sectional views showing respective steps of a method for manufacturing a field effect transistor according to a modification of the second embodiment of the present invention. FIG. 9A is a cross-sectional configuration diagram of a conventional field effect transistor, and FIG. 9B shows changes in the respective compositions of Al and In along the line YY ′ in FIG. 9A. FIG. 9C is a diagram showing a change in potential energy of electrons along the line YY ′ in FIG. 9A. FIG. 10 is a diagram showing a result of evaluation of the forbidden band width of In _0.09 Al _0.32 Ga _0.59 N by the cathodoluminescence (CL) method by the present inventors. FIG. 11 is a diagram showing the results of investigation of the forbidden band width Eg and the bowing parameter by the inventors of the present invention for a plurality of InAlGaN samples. FIG. 12 is a diagram showing the results of investigation by the inventors of the present invention on the relationship between the work function of metal for AlGaN, GaN, and InAlGaN and the Schottky barrier height φ. FIG. 13 is a diagram showing the results of investigation by the inventors of the present invention on the current-voltage characteristics of GaN and InAlGaN when Mo is used as a Schottky electrode. FIG. 14 is a diagram showing a modification of the change in the composition of each of Al and In along the line X-X ′ in FIG. FIG. 15 is a diagram showing a modification of the change in the composition of each of Al and In along the line X-X ′ in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 Undoped GaN buffer layer 3 N-type AlGaN electron supply layer 4 n-type InAlGaN cap layer 5 Ti / Al ohmic electrode 6 Pd-Si Schottky electrode 7 Two-dimensional electron gas 8 SiO ₂ mask 9 Delta-doped layer 10 Multilayer film 11 AlN spacer layer 20 SiO ₂ mask

Claims (24)

A nitride semiconductor layer;
The nitride semiconductor layer _{In x Al y Ga 1-xy} N layer formed on the (where 0 <x <1,0 <y < 1,0 <x + y <1),
It said _{In x Al y Ga 1-xy} N layer is formed on the and the _{In x Al y Ga 1-xy} N layer and a source electrode and a drain electrode in contact with,
Wherein said nitride semiconductor layer an In _x Al _y at the interface between the Ga _1-xy N layer, the field-effect transistor the lower end of each of the conduction band, characterized in that the substantially continuous. The field effect transistor according to claim 1.
Wherein an In _x Al _y polarization of Ga _1-xy N layer, field effect transistor being greater than the polarization of the polarization equal to or the nitride semiconductor layer of the nitride semiconductor layer. The field effect transistor according to claim 1 or 2,
Wherein said nitride semiconductor layer an In _x Al _y at the interface between the Ga _1-xy N layer, field effect transistors, each of the lattice constant is equal to or substantially equal. The field effect transistor according to any one of claims 1 to 3,
Wherein said nitride semiconductor layer an In _x Al _y at the interface between the Ga _1-xy N layer, field effect transistors, each of the forbidden band width is equal to or substantially equal. The field effect transistor according to any one of claims 1 to 4,
The nitride semiconductor layer includes Al,
The Al composition in the nitride semiconductor layer, the field-effect transistor, characterized in that has changed so as to increase with distance from the interface between the said nitride semiconductor layer _{In x Al y Ga 1-xy} N layer. The field effect transistor according to claim 5,
The field effect transistor according to claim 1, wherein the Al composition in the nitride semiconductor layer increases linearly with distance from the interface. The field effect transistor according to claim 5,
The field effect transistor according to claim 1, wherein the Al composition in the nitride semiconductor layer increases stepwise as the distance from the interface increases. The field effect transistor according to claim 5,
The field effect transistor according to claim 1, wherein the Al composition in the nitride semiconductor layer increases in a convex quadratic curve as the distance from the interface increases. The field effect transistor according to any one of claims 1 to 8,
Between the nitride semiconductor layer and the _{In x Al y Ga 1-xy} N layer, and characterized in that the GaN layer and the AlGaN layer is further provided with a multilayer film formed by stacking at least one cycle or more alternately Field effect transistor. The field effect transistor according to any one of claims 1 to 8,
A multilayer film in which another InAlGaN layer and an AlGaN layer are alternately stacked at least one period or more between the nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer; A characteristic field effect transistor. The field effect transistor according to any one of claims 1 to 10,
The nitride semiconductor layer has a conductivity type of the nitride semiconductor layer so as to generate a pulse-like profile in a direction perpendicular to an interface between the nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer. A field effect transistor having a region to which an impurity that contributes to silicon is added. The field effect transistor of claim 11, wherein
The field effect transistor according to claim 1, wherein a peak concentration of the impurity in the region is 1 × 10 ¹⁹ atoms / cm ³ or more. The field effect transistor according to any one of claims 1 to 12,
The In the _x Al _y Ga _1-xy N predetermined area of the layer, the recess reaching the nitride semiconductor layer is formed,
The field effect transistor further comprising a gate electrode formed in the recess. Forming a first nitride semiconductor layer on a substrate;
Forming a second nitride semiconductor layer having a forbidden band width larger than that of the first nitride semiconductor layer on the first nitride semiconductor layer;
Forming a _{In x Al y Ga 1-xy} N layer on the second nitride semiconductor layer (where 0 <x <1,0 <y < 1,0 <x + y <1),
In a predetermined area of the _{In x Al y Ga 1-xy} N layer, and forming a recess reaching said second nitride semiconductor layer,
Forming a gate electrode in the recess;
Wherein an In the _x Al _y Ga _1-xy N layer, and forming a source electrode and a drain electrode in contact with said _{In x Al y Ga 1-xy} N layer,
A method of manufacturing a field effect transistor, wherein the lower end of each conduction band is substantially continuous at an interface between the second nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer. Forming a first nitride semiconductor layer on a substrate;
Forming a second nitride semiconductor layer having a forbidden band width larger than that of the first nitride semiconductor layer on the first nitride semiconductor layer;
Forming a mask layer on a predetermined region of the second nitride semiconductor layer;
An In _x Al _y Ga _1-xy N layer (where 0 <x <1, 0 <y <1, 0 <x + y <1) is formed on the second nitride semiconductor layer not covered with the mask layer. Selectively forming, and
Forming a recess reaching the second nitride semiconductor layer by removing the mask layer;
Forming a gate electrode in the recess;
Said In _x Al _y Ga on the _1-xy N layer, the In _x Al _y Ga field effect transistor, characterized by comprising a _1-xy N forming a source electrode and a drain electrode in contact with layer Manufacturing method. The method of manufacturing a field effect transistor according to claim 15,
The method of manufacturing a field effect transistor, wherein the mask layer is made of SiO ₂ . In the manufacturing method of the field effect transistor according to claim 15 or 16,
Method of manufacturing a field effect transistor the thickness of the mask layer may be greater than the thickness of the _{In x Al y Ga 1-xy} N layer. In the manufacturing method of the field effect transistor of any one of Claims 15-17,
A method of manufacturing a field effect transistor, wherein the lower end of each conduction band is substantially continuous at an interface between the second nitride semiconductor layer and the In _x Al _y Ga _1-xy N layer. In the manufacturing method of the field effect transistor according to claim 14 or 18,
The second nitride semiconductor layer includes Al;
In the step of forming the second nitride semiconductor layer, the interface between the Al composition of the second nitride semiconductor layer, wherein said second nitride semiconductor layer _{In x Al y Ga 1-xy} N layer A method of manufacturing a field effect transistor, wherein the field effect transistor is changed so as to increase as the distance from the device increases. The method of manufacturing a field effect transistor according to claim 19,
In the step of forming the second nitride semiconductor layer, the Al composition in the second nitride semiconductor layer is increased linearly with increasing distance from the interface. The method of manufacturing a field effect transistor according to claim 19,
A method of manufacturing a field effect transistor, wherein in the step of forming the second nitride semiconductor layer, the Al composition in the second nitride semiconductor layer is increased stepwise as the distance from the interface increases. The method of manufacturing a field effect transistor according to claim 19,
In the step of forming the second nitride semiconductor layer, the Al composition in the second nitride semiconductor layer is increased in a convex quadratic curve shape as the distance from the interface increases. Effect transistor manufacturing method. In the manufacturing method of the field effect transistor of any one of Claims 14-22,
A step of performing a heat treatment on the substrate after the step of forming the source electrode and the drain electrode;
The method of manufacturing a field effect transistor, wherein a temperature of the heat treatment is lower than a formation temperature of the In _x Al _y Ga _1-xy N layer. In the manufacturing method of the field effect transistor of any one of Claims 14-23,
Said In _x Al _y Ga later than _1-xy N layer forming a said _{In x Al y Ga 1-xy} N layer impurities to provide the n-type conductivity type, the _{In x Al y Ga 1-xy} N a step of concentration of the impurities in the top layer is added to be higher than other portions, after the step, the substrate with the in _x Al _y Ga temperature lower than the formation temperature of _1-xy N layer And a step of performing a heat treatment on the field effect transistor.

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