JP2006243525A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve cost reduction and yield by enabling high quality image display in a pixel circuit by n-channel TFT. <P>SOLUTION: The pixel circuit is composed of an organic EL element, one holding capacity, and 5 N-channel thin film transistors comprising a sampling transistor, a drive transistor, a switching transistor, and first and second detection transistors. The pixel circuit comprises a bootstrap function (characteristic variation compensation function) of a holding capacity for compensating the variation of a threshold voltage of the drive transistor and time passage deterioration of the organic EL element. I-V characteristics of the current drive type organic EL element compensate secular change and the threshold voltage variation of the drive transistor. Additionally, a scanning line (a gate line WSL of the sampling transistor) for performing conduction control of the sampling transistor is shared as the gate line of the first detection transistor T4 of the pixel circuit of a line separated from a prescribed line number. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device having a pixel array in which pixel circuits formed at portions where signal lines and a required number of scanning lines intersect are arranged in a matrix, and particularly as an organic electroluminescent element (organic) as a light emitting element. The present invention relates to a display device using an EL element.

JP 2003-255856 A JP 2003-271095 A

An image display device using an organic EL element as a pixel has been developed. Since the organic EL element is a self-luminous element, it has advantages such as higher image visibility than a liquid crystal display, no need for a backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough (so-called current control type).
In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor: TFT) provided in the pixel circuit.

FIG. 11 shows a block diagram of a general active matrix organic EL display device.
This display device includes a pixel array unit 103 in which pixel circuits 100 are arranged in an m × n matrix, a horizontal selector 101, a light scanner 102, and a signal line to which a signal corresponding to luminance information is supplied. DTL1, DTL2,..., Scanning lines WSL1, WSL2,.

FIG. 12 shows a simplest configuration example of the pixel circuit 100 shown in FIG. As shown in the figure, the pixel circuit 100 includes a sampling transistor Ts using an n-channel TFT, a storage capacitor C10, a drive transistor Td using a p-channel TFT, and the organic EL element 1. The pixel circuit 100 is arranged at the intersection of the signal line DTL and the scanning line WSL, the signal line DTL is connected to the drain of the sampling transistor Ts, and the scanning line WSL is connected to the gate of the sampling transistor Ts.
The drive transistor Td and the organic EL element 1 are connected in series between the power supply potential Vcc and the ground potential GND. That is, the source of the drive transistor 1 is connected to the power supply potential Vcc, while the cathode of the organic EL element (light emitting element) 1 is connected to the ground potential GND. In general, the organic EL element 1 is represented by a diode symbol because of its rectifying property. On the other hand, the sampling transistor Ts and the storage capacitor C10 are connected to the gate of the drive transistor Td. The gate-source voltage of the drive transistor Td is represented by Vgs.

In the pixel circuit 100, when the scanning line WSL is first selected and a signal is applied to the signal line DTL, the sampling transistor Ts is turned on and the signal is written into the holding capacitor C10. The signal potential written in the storage capacitor C10 becomes the gate potential of the drive transistor Td. When the scanning line WSL is not selected, the signal line DTL and the drive transistor Td are electrically disconnected, but the gate potential Vgs of the drive transistor Td is stably held by the holding capacitor C10. A drive current flows through the drive transistor Td and the organic EL element 1 from the power supply potential Vcc toward the ground potential GND.
At this time, the current Ids flowing through the drive transistor Td and the organic EL element 1 has a value corresponding to the gate-source voltage Vgs of the drive transistor Td, and the organic EL element 1 emits light with luminance corresponding to the current value.
That is, in the case of this pixel circuit 100, the gate applied voltage of the drive transistor Td is changed by each input of the signal potential from the signal line DTL into the holding capacitor C10, thereby controlling the value of the current flowing through the organic EL element 1 and developing the color. Is obtained.

Since the source of the drive transistor Td by the p-channel TFT is connected to the power supply Vcc and is always designed to operate in the saturation region, the drive transistor Td has a constant current source having the value shown in the following formula 1. Become.
Ids = (1/2) · μ · (W / L) · Cox · (Vgs−Vth) ² (Equation 1)
Where Ids is a current flowing between the drain and source of a transistor operating in the saturation region, μ is mobility, W is a channel width, L is a channel length, Cox is a gate capacitance, and Vth is a threshold voltage of the transistor.
As is apparent from Equation 1, in the saturation region, the drain current Ids of the transistor is controlled by the gate-source voltage Vgs. The drive transistor Td shown in FIG. 12 operates as a constant current source because Vgs is kept constant, and can emit the organic EL element 1 with constant luminance.

  Here, FIG. 13 shows the change with time of the current-voltage (IV) characteristics of the organic EL element. The curve indicated by the solid line indicates the characteristics in the initial state, and the curve indicated by the broken line indicates the characteristics after change with time. In general, the IV characteristics of an organic EL element deteriorate as time passes as shown in the figure. In the pixel circuit 100 of FIG. 12, the drain voltage of the drive transistor Td changes as the organic EL element 1 changes with time. However, in the pixel circuit 100 of FIG. 12, since the gate-source voltage Vgs is constant as described above, a certain amount of current flows through the organic EL element 1, and the light emission luminance does not change. That is, stable gradation control can be performed.

The pixel circuit 100 shown in FIG. 12 is configured using a p-channel type drive transistor Td. However, if the pixel circuit 100 can be configured using an n-channel type TFT, conventional amorphous silicon (a-Si) can be used in TFT fabrication. ) Process can be used. As a result, the cost of the TFT substrate can be reduced, and development is expected.
FIG. 14 is a circuit diagram showing a configuration in which the drive transistor Td, which is the p-channel TFT of the pixel circuit 100 shown in FIG. 12, is replaced with an n-channel TFT. As shown in the figure, the pixel circuit 100 in this case includes an n-channel TFT, which includes a sampling transistor Ts, a drive transistor Td, a storage capacitor C10, and an organic EL element 1.
In this pixel circuit 100, the drain side of the drive transistor Td is connected to the power supply potential Vcc, and the source is connected to the anode of the organic EL element 1, forming a source follower circuit.

However, when the drive transistor Td is replaced with an n-channel TFT in this way, the source is connected to the organic EL element 1, and therefore, the gate-source gap is changed with the aging of the organic EL element 1 as shown in FIG. The voltage Vgs changes. As a result, the amount of current flowing through the organic EL element 1 changes, and as a result, the light emission luminance changes. That is, appropriate gradation control cannot be performed.
In addition, in the active matrix organic EL display, in addition to the characteristic variation of the organic EL element 1, the threshold voltage of the n-channel TFT constituting the pixel circuit 100 also changes with time. As is clear from the above-described equation 1, when the threshold voltage Vth of the drive transistor Td varies, the drain current Ids changes. As a result, even if the same gate voltage Vgs is applied, the light emission luminance changes due to the fluctuation of the threshold voltage Vth. For this reason, the light emission luminance also changes for each pixel.
When the pixel circuit 100 is configured by n-channel TFTs, the current amount varies due to deterioration with time of the organic EL element 1 and variation or variation in the threshold voltage of the drive transistor Td as described above. There has been a problem that it is impossible to realize an image display.

  Therefore, an object of the present invention is to realize a display device and a display method capable of displaying a high-quality image even when a pixel circuit using an n-channel TFT is used. A further object is to make the circuit configuration more efficient.

  The display device of the present invention is a display device having a pixel array in which pixel circuits formed at portions where signal lines and a required number of scanning lines intersect are arranged in a matrix, each pixel circuit having an organic electroluminescence The device includes a device, a storage capacitor, and five n-channel thin film transistors including a sampling transistor, a drive transistor, first and second detection transistors, and a switching transistor. In this pixel circuit, the storage capacitor is connected between the source and gate of the drive transistor, the organic electroluminescence element is connected between the source of the drive transistor and a predetermined cathode potential, and the drive transistor The first detection transistor is connected between the source of the transistor and the first fixed potential, the second detection transistor is connected between the gate of the drive transistor and the second fixed potential, and the drive transistor The sampling transistor is connected between the gate and the signal line, and the switching transistor is connected between the drain of the drive transistor and a predetermined power supply potential. The sampling transistor, the first and second detection transistors, and the switching transistor are configured to be conductively controlled by corresponding scanning lines, and the sampling transistors in each pixel circuit in each row are electrically connected. The scanning line to be controlled is shared with the scanning line for controlling the conduction of the first detection transistor in each pixel circuit in another row that is a predetermined number of rows away from the row.

The pixel circuit includes the first and second detection transistors in a state in which the switching transistor is turned on in the non-light-emitting period in one light-emitting cycle of the organic electroluminescence element including a light-emitting period and a non-light-emitting period. Is turned on, the first detection transistor is turned off to detect a threshold voltage of the drive transistor, and a threshold detection operation for holding the detected potential in the storage capacitor is started. After the threshold detection operation is finished, only the sampling transistor is turned on, so that the writing operation for sampling the input signal from the signal line to the storage capacitor is started. In this case, the predetermined number of rows is the number of rows obtained by adding 1 to the number of rows corresponding to the number of horizontal cycles in the period from the start of the threshold detection operation to the start of the writing operation.
Further, the scanning lines provided for the sampling transistor and the first detection transistor are scanned in the same way from both sides of the scanning line wiring by a pair of scanning line driving means interposed on both sides of the pixel array. A pulse is applied.

That is, in the present invention, the pixel circuit includes an organic EL element, one storage capacitor, and five n-channel thin film transistors including a sampling transistor, a drive transistor, a switching transistor, and first and second detection transistors. Yes. This pixel circuit has a storage strap bootstrap function (characteristic variation compensation function) that compensates for fluctuations in the threshold voltage of the drive transistor and deterioration over time of the organic EL element. Even if the IV characteristic changes with time, the light emission luminance can be kept constant. Further, the threshold voltage of the drive transistor is detected by the first and second detection transistors, and the change with the passage of time is compensated in a circuit, so that the organic EL element can be driven stably.
In addition, a scanning line for controlling the conduction of the sampling transistor (a gate line of the sampling transistor) and a scanning line for controlling the conduction of the first detection transistor in the pixel circuit separated by a predetermined number of rows (the gate line of the first detection transistor) ) Is shared. This eliminates the need to provide the gate line of the first detection transistor independently.

According to the present invention, the pixel circuit is composed of an organic EL element, one storage capacitor, and five n-channel thin film transistors including a sampling transistor, a drive transistor, a switching transistor, and first and second detection transistors. By providing this pixel circuit with a bootstrap function, it is possible to drive the organic EL element stably even with the deterioration of the organic EL element over time or the threshold voltage fluctuation of the drive transistor, and as a display device using a pixel circuit with an n-channel TFT. Therefore, it is possible to realize a high-quality display image.
Thereby, all the transistors are composed of n-channel TFTs, a source follower is possible, and a circuit configuration capable of anode connection can be put into practical use. For this reason, it is possible to introduce a general amorphous silicon process, and cost reduction can be promoted.

In the present invention, the scanning circuit for controlling the conduction of the sampling transistor and the scanning line for controlling the conduction of the first detection transistor are shared in the pixel circuits constituting the matrix pixel array. In other words, the scanning line serving as the gate line of the sampling transistor in the pixel circuit in a certain row is also used as the gate line of the first detection transistor in the pixel circuit in a row separated by a predetermined number of rows.
With this configuration, the number of scanning lines arranged for the pixel array can be greatly reduced, and the configuration of the pixel array can be simplified, the cost of the display panel can be reduced, the size can be reduced, or the yield can be increased. it can.
In addition, since the scanning line driving circuit for the sampling transistor and the scanning line driving circuit for the first detection transistor are shared, the configuration of the scanning line driving circuit can be reduced, which also simplifies the circuit, reduces the cost, High yield is promoted.

  Conversely, when the scanning line driving circuit for the scanning line for the sampling transistor and the first detection transistor is arranged on both sides of the pixel array, and the same scanning pulse is applied to the scanning line from both sides, It is possible to prevent image quality defects due to the delay of the scanning pulse on the gate line. In particular, when the scanning line is long and the influence of the delay becomes noticeable as in a large display device, it is preferable to adopt such a method, which is useful for increasing the screen size and the definition of the display device.

Hereinafter, embodiments of the display device of the present invention will be described. For convenience of explanation, first, a display device configuration and a pixel circuit as a reference example not corresponding to the present invention will be described, and then the embodiment of the present invention will be described. A display device and a pixel circuit will be described. That is, it demonstrates in the following order.
[1. Display device as a reference example]
[2. Display device of first embodiment]
[3. Display device according to second embodiment]

[1. Display device as a reference example]

The configuration and operation of a display device as a reference example will be described with reference to FIGS. The configuration of the display device and the pixel circuit in this reference example is different from that of the embodiment, but the operation of the pixel circuit of the reference example described here is the same as the operation of the pixel circuit of the embodiment described later. The same.

FIG. 6 shows a configuration of a display device of a reference example. As will be described later, this display device includes a pixel circuit having a bootstrap function that is a compensation function for characteristic variation of an organic EL element that is a light emitting element and threshold voltage fluctuation of a drive transistor.
As shown in FIG. 6, this display device includes a pixel array unit 20 in which pixel circuits 10 are arranged in a matrix of m rows × n columns, a horizontal selector 11, a drive scanner 12, a write scanner 13, a first AZ scanner 14, A second AZ scanner 15 is provided.
Also, signal lines DTL-1, DTL-2,..., Which are selected by the horizontal selector 11 and supply video signals corresponding to luminance information as input signals to the pixel circuit 10, are arranged in the column direction with respect to the pixel array unit 20. Has been. The signal lines DTL-1, DTL-2,... Are arranged by the number of columns of the pixel circuits 10 arranged in a matrix in the pixel array unit 20.
Further, the scanning lines WSL-1, WSL-2,..., Scanning lines DSL-1, DSL-2,..., Scanning lines AZL1-1, AZL1-2,. , Scanning lines AZL2-1, AZL2-2, ... are arranged. Each of these scanning lines is arranged by the number of rows of the pixel circuits 10 arranged in a matrix in the pixel array unit 20.
The scanning lines WSL (WSL-1, WSL-2,...) Are selectively driven by the write scanner 13.
The scanning lines DSL (DSL-1, DSL-2,...) Are selectively driven by the drive scanner 12.
The scanning lines AZL1 (AZL1-1, AZL1-2, ...) are selectively driven by the first AZ scanner 14.
The scanning lines AZL2 (AZL2-1, AZL2-2, ...) are selectively driven by the second AZ scanner 15.
The drive scanner 12, the write scanner 13, the first AZ scanner 14, and the second AZ scanner 15 each select a selection pulse (scanning pulse) for each scanning line at a predetermined timing set based on the input start pulse sp and clock ck. give.

A configuration example of the pixel circuit 10 in such a display device will be described with reference to FIG.
For simplification, FIG. 7 shows only one pixel circuit 10 arranged at a portion where the signal line DTL and the scanning lines WSL, DSL, AZL1, and AZL2 intersect.
The pixel circuit 10 includes an organic EL element 1 that is a light emitting element, one holding capacitor C1, a sampling transistor T1, a drive transistor T5, a switching transistor T3, a first detection transistor T4, and a second detection transistor T2. And five n-channel thin film transistors.

The storage capacitor C1 has one terminal connected to the source of the drive transistor T5 and the other terminal connected to the gate of the drive transistor T5. In the figure, the source node of the drive transistor T5 is shown as a node Nd1, and the gate node of the drive transistor T5 is shown as a node Nd2. Therefore, the storage capacitor C1 is connected between the node Nd1 and the node Nd2.
The light emitting element of the pixel circuit 10 is, for example, the organic EL element 1 having a diode structure, and includes an anode and a cathode. The anode of the organic EL element 1 is connected to the source (node Nd1) of the drive transistor T5, and the cathode is connected to a predetermined cathode potential Vcat. Note that the organic EL element 1 includes a capacitive component between the anode and the cathode, and this capacitive component may be indicated as Cel in the drawings described later.

The source of the first detection transistor T4 is connected to the first fixed potential Vss, the drain is connected to the source (node Nd1) of the drive transistor T5, and the gate is connected to the scanning line AZL1.
The second detection transistor T2 has a source connected to the second fixed potential Vofs, a drain connected to the gate (node Nd2) of the drive transistor T5, and a gate connected to the scanning line AZL2.
The sampling transistor T1 has one end connected to the signal line DTL, the other end connected to the gate (node Nd2) of the drive transistor T5, and the gate connected to the scanning line WSL.
The switching transistor T3 has a drain connected to the power supply potential Vcc, a source connected to the drain of the drive transistor T5, and a gate connected to the scanning line DSL.

The sampling transistor T1 operates when selected by the scanning line WSL, samples the input signal Vsig from the signal line DTL, and holds it in the holding capacitor C1 via the node Nd2.
The drive transistor T5 drives the organic EL element 1 by current according to the signal potential held in the holding capacitor C1.
The switching transistor T3 becomes conductive when selected by the scanning line DSL, and supplies current from the power supply potential Vcc to the drive transistor T5.
The first and second detection transistors T4 and T2 are made conductive by being selected at a predetermined timing by the scanning lines AZL1 and AZL2, respectively. The first and second detection transistors T4 and T2 are turned on / off by detecting the threshold voltage Vth of the drive transistor T5 prior to current driving of the organic EL element 1, and detecting the threshold voltage Vth in advance. It is executed in association with an operation (threshold detection operation) for holding the threshold voltage in the holding capacitor C1.

As a condition for guaranteeing the normal operation of the pixel circuit 10, the fixed potential Vss is set lower than the level obtained by subtracting the threshold voltage Vth of the drive transistor T5 from the fixed potential Vofs. That is, Vss <Vofs−Vth.
The fixed potential Vss is set smaller than the sum of the threshold voltage Vel of the organic EL element 1 and the cathode potential Vcat (Vss <Vthel + Vcat).
The fixed potential Vofs is set smaller than the sum of the threshold voltage Vth of the drive transistor T5, the threshold voltage Vthel of the organic EL element 1, and the cathode voltage Vcat (Vofs <Vth + Vthel + Vcat).
For example, the fixed potential Vofs is a ground potential, and the fixed potential Vss is a negative potential so as to satisfy the above conditions.

Operations performed in the configuration of the pixel circuit 10 of FIG. 7 will be described with reference to FIGS.
FIG. 8 shows a timing chart of the scanning lines AZL1, AZL2, DSL, and WSL. As can be seen from the above configuration, this is the on / off timing of the detection transistor T4, the detection transistor T2, the switching transistor T3, and the sampling transistor T1, respectively. FIG. 8 also shows changes in the gate voltage (node Nd2) and source voltage (node Nd1) of the drive transistor T5. 9 and 10 show equivalent circuits at each time point.

  The timing chart of FIG. 8 represents one cycle in which the organic EL element 1 as a light emitting element is driven to emit light, that is, one frame period of image display. One frame period is composed of a non-light emission period and a light emission period of the organic EL element 1, and for example, a time point tm11 is an end timing of the previous one frame and a start timing of the current one frame.

In the period up to the time tm11, that is, the period immediately before the end of the previous frame, the scanning lines AZL1, AZL2, and WSL are at the low level, while the scanning line DSL is at the high level. Accordingly, as shown in FIG. 9A, the switching transistor T3 is in the on state, while the sampling transistor T1 and the detection transistors T2 and T4 are in the off state.
At this time, the drive transistor T5 causes the drive current Ids to flow according to the voltage between the nodes Nd2 and Nd1, thereby causing the organic EL element 1 to emit light. At this time, the source potential of the drive transistor T5 (the potential of the node Nd1) is held at a predetermined operating point.
Since the drive transistor T5 is set to operate in the saturation region, the current Ids flowing through the organic EL element 1 takes the value expressed by the above-described equation 1 according to the gate-source voltage Vgs of the drive transistor T5. .

One frame period starts from time tm11. At this time, the scanning lines AZL1 and AZL2 both rise from the low level to the high level. As a result, as shown in FIG. 9B, both the detection transistors T4 and T2 are switched from the off state to the on state.
As a result, the node Nd2 rapidly decreases to the fixed potential Vofs, and the node Nd1 also rapidly decreases to the fixed potential Vss. That is, the gate voltage of the drive transistor T5 is charged to Vofs and the source voltage is charged to Vss. As described above, since Vss <Vofs−Vth is set, the drive transistor T5 maintains the on state, and the drain current Ids ′ flows.
At this time, the gate-source voltage Vgs of the drive transistor T5 takes a value of Vofs−Vss, and the current Ids ′ corresponding thereto corresponds to the fixed potential Vss from the power supply Vcc side as indicated by a broken line in FIG. 9B. Will flow to the side.
Further, in order to make the organic EL element 1 emit no light, the voltage Vel (= node Nd1 potential) applied to the organic EL element 1 is smaller than the sum of the threshold voltage Vthel and the cathode voltage Vcat of the organic EL element 1 as described above. Since the voltage values of the fixed potentials Vofs and Vss are set so that current does not flow, no current flows through the organic EL element 1, and therefore, the light emitting state is not achieved.
Note that either of the detection transistors T2 and T4 may be turned on first after the time tm11.

At time tm12, a threshold detection operation for the bootstrap function is started. Therefore, the scanning line AZL1 is returned from the high level to the low level, and the detection transistor T4 is turned off as shown in FIG. 9C.
Since the equivalent circuit of the organic EL element 1 is represented by a diode and a capacitance, as long as Vel ≦ Vcat + Vthel (the leakage current of the organic EL element 1 is considerably smaller than the current flowing through the drive transistor T5), the current of the drive transistor T5 Is used to charge the storage capacitor C1 and the capacitor Cel of the organic EL element 1.
At this time, since the current path of the drain current Ids ′ flowing through the drive transistor T5 is interrupted, the voltage Vel (= node Nd1 potential) applied to the organic EL element 1 increases with time as shown in FIG.
After a certain time has elapsed, the gate-source voltage Vgs of the drive transistor T5 takes the threshold voltage Vth. At this time, the voltage applied to the organic EL element 1 is Vel = Vofs−Vth ≦ Vcat + Vthel.
At this time, the potential difference Vth appearing between the node Nd1 and the node Nd2 is held in the holding capacitor C1. That is, as the threshold detection operation, the threshold voltage Vth of the drive transistor T5 is detected and held in the storage capacitor C1.

Next, at time tm13, the scanning line DSL is set to the low level, and the switching transistor T3 is turned off as shown in FIG. As a result, the current Ids ′ does not flow, and the threshold value detection operation is terminated at this point.
Thereafter, at time tm14, the scanning line AZL2 is set to the low level, and the detection transistor T2 is turned off as shown in FIG.

Next, at time tm15, the scanning line WSL is set to the high level, the sampling transistor T1 is turned on as shown in FIG. 10B, and the signal voltage Vsig from the signal line DTL is written into the holding capacitor C1. . As a result, the gate voltage of the drive transistor T5 is set to the signal voltage Vsig from the signal line DTL.
At this time, the gate-source voltage Vgs of the drive transistor T5 is determined by the holding capacitor C1, the parasitic capacitance Cel of the organic EL element 1, and the parasitic capacitance C2 of the drive transistor T5 as shown in Equation 2.
Vgs = (Cel / (Cel + C1 + C2)). (Vsig−Vofs) + Vth
... (Formula 2)
However, since the parasitic capacitance Cel is larger than the capacitances C1 and C2, the gate-source voltage Vgs of the drive transistor T5 is approximately Vsig + Vth.

After the time tm16 when the writing of the signal voltage Vsig from the signal line DTL is completed, the scanning line DSL is set to the high level at the time tm17, and the switching transistor T3 is turned on as shown in FIG. The drain voltage of the drive transistor T5 is raised to the power supply voltage.
Since the gate-source voltage Vgs of the drive transistor T5 is constant due to the action of the storage capacitor C1, the drive transistor T5 causes the constant current Ids ″ to flow through the organic EL element 1, and the potential of the node Nd1 causes the current to flow through the organic EL element 1. The voltage rises to the flowing voltage, and the organic EL device 1 emits light, that is, the light emission period in the current frame starts.

The operation of the pixel circuit 10 as the reference example of FIG. 2 is as described above. Also in the pixel circuit 10 of FIG. 2, the IV characteristic of the organic EL element 1 changes as the light emission time increases. . Therefore, the potential of the node Nd1 also changes.
However, in the above operation, the gate-source voltage V5 of the drive transistor T5
Since gs is maintained at a constant value, the current flowing through the organic EL element 1 does not change. Therefore, even if the IV characteristic of the organic EL element 1 deteriorates, the constant current Ids always flows and the luminance of the organic EL element 1 does not change. For this reason, a high-quality display image can be realized as a display device using a pixel circuit using n-channel TFTs.

However, there are disadvantages in the circuit configuration as follows.
Consider a scanning line arranged for the pixel circuit 10. Each pixel circuit 10 in the pixel array unit 20 is provided with four scanning lines WSL, DSL, AZL1, and AZL2. Considering the entire pixel array unit 20 in which the pixel circuits 10 are provided in a matrix of m rows × n columns, the number of scanning lines is (4 × m).
Further, as shown in FIG. 6, in order to drive four types of scanning lines (gate lines), four scanning line driving circuits of the drive scanner 12, the write scanner 13, the first AZ scanner 14, and the second AZ scanner 15 are necessary. become.
These are disadvantageous from the viewpoint of simplification of circuit configuration, cost reduction, and improvement of yield.

[2. Display device of first embodiment]

Therefore, as an embodiment of the present invention, a display device that achieves the same effect as the above reference example while reducing the number of scanning lines and the scanning line driving circuit is realized.

FIG. 1 shows a configuration of a display device according to an embodiment. This display device also includes a pixel circuit having a bootstrap function that is a compensation function for the characteristic variation of the organic EL element, which is a light emitting element, and the threshold voltage variation of the drive transistor.
As shown in FIG. 1, this display device includes a pixel array unit 20 in which pixel circuits 10 are arranged in a matrix of m rows × n columns, a horizontal selector 11, a drive scanner 12, a write scanner 13, and an AZ scanner 16. Prepare.
In FIG. 1, the pixel circuit 10 arranged in a matrix in the pixel array unit 20 is given a row number to its reference. That is, the n pixel circuits in the first row are the pixel circuits 10-1, the n pixel circuits in the x row are the pixel circuits 10-x, the n pixel circuits in the y row are the pixel circuits 10-y, and finally. The n pixel circuits in the m-th row, which is a row, are shown as a pixel circuit 10-m.

As the signal line DTL selected by the horizontal selector 11 and supplying a video signal corresponding to the luminance information as an input signal to the pixel circuit 10, signal lines DTL-1... DTL-n are the same as in FIG. The pixel array unit 20 is arranged in the column direction.
In the case of FIG. 1, the scanning lines arranged in the row direction with respect to the pixel array unit 20 are three lines of scanning lines WSL, DSL, and AZL.
That is, the scanning lines DSL-1... DSL-m are arranged as the scanning lines DSL that are selectively driven by the drive scanner 12.
Further, scanning lines WSL-1... WSL-m are arranged as scanning lines WSL that are selectively driven by the light scanner 13.
Further, scanning lines AZL-1... AZL-m are arranged as scanning lines AZL selectively driven by the AZ scanner 16. The AZ scanner 16 corresponds to the second AZ scanner in the example of FIG. 6, and the scanning line AZL in FIG. 1 corresponds to the scanning line AZL2 in the example of FIG.

  The drive scanner 12, the write scanner 13, and the AZ scanner 16 give selection pulses (scanning pulses) to the scanning lines at predetermined timings set based on the input start pulse sp and clock ck, respectively.

In the configuration of the embodiment of FIG. 1, as compared with the reference example of FIG. 6, the independent scanning line driving circuit and the scanning line corresponding to the first AZ scanner 14 and the scanning line AZL1 are not provided.
Here, as shown in FIG. 1, the scanning line WSL-1 for each pixel circuit 10-1 in the first row is also introduced into each pixel circuit 10-x in the xth row. This functions as the scanning line AZL1 described in FIGS. 6 and 7 for each pixel circuit 10-x in the x-th row.
Note that “x” in the x-th row is x = 1 + q. In other words, it is assumed that the row that is q rows away from the first row is the x-th row.
As will be described with reference to FIG. 3, it is assumed that r rows are arranged between the first row and the x-th row, and q = r + 1.

The scanning line WSL-x for each pixel circuit 10-x in the x-th row is also introduced into each pixel circuit 10-y in the y-th row. This functions as the scanning line AZL1 described in FIGS. 6 and 7 for each pixel circuit 10-y in the y-th row. y = x + q.
The scanning line WSL-x for each pixel circuit 10-y in the y-th row is also introduced into each pixel circuit 10- (y + q) in the (y + q) -th row (not shown). This functions as the scanning line AZL1 described in FIGS. 6 and 7 for each pixel circuit 10- (y + q) in the (y + q) th row.
For each pixel circuit 10-m in the m-th row that is the last row, the scanning line WSL- (m-q) for the pixel circuit 10- (m-q) in the (m-q) -th row (not shown). Is introduced so as to function as the scanning line AZL1 described in FIGS.
For each pixel circuit 10-1 in the first row, a scanning line WSL- (m + 1-q) for the pixel circuit 10- (m + 1-q) in the (m + 1-q) row (not shown) is shown in FIG. 6. It is introduced so as to function as the scanning line AZL1 described in FIG.

  That is, in this example, the scanning line WSL for a certain row is shared as a scanning line corresponding to the scanning line AZL1 described in the reference example of FIGS.

FIG. 2 shows one pixel circuit 10-x in the x-th row.
The pixel circuit 10-x includes an organic EL element 1 which is a light emitting element, one holding capacitor C1, a sampling transistor T1, a drive transistor T5, a switching transistor T3, and first and second detection transistors T2 and T4. These five n-channel thin film transistors are the same as those in the reference example shown in FIG.
However, the gate of the first detection transistor T4 is connected to the scanning line WSL-1 provided for each pixel circuit 10-1 in the first row.
Further, the scanning line WSL-x serving as the gate line of the sampling transistor T1 is also a gate line of the detection transistor T4 in the pixel circuit 10-y in the y-th row.

That is, the configuration of the pixel circuit 10 of the embodiment is as follows.
The storage capacitor C1 has one terminal connected to the source (node Nd1) of the drive transistor T5 and the other terminal connected to the gate (node Nd2) of the drive transistor T5.
The anode of the organic EL element 1 which is a light emitting element is connected to the source (node Nd1) of the drive transistor T5, and the cathode is connected to a predetermined cathode potential Vcat.
The source of the first detection transistor T4 is connected to the first fixed potential Vss, the drain is connected to the source (node Nd1) of the drive transistor T5, and the gate is connected to the scanning line WSL of the row preceding q rows. It is connected.
The second detection transistor T2 has a source connected to the second fixed potential Vofs, a drain connected to the gate (node Nd2) of the drive transistor T5, and a gate connected to the scanning line AZL.
The sampling transistor T1 has one end connected to the signal line DTL, the other end connected to the gate (node Nd2) of the drive transistor T5, and the gate connected to the scanning line WSL provided for the row. Yes.
The switching transistor T3 has a drain connected to the power supply potential Vcc, a source connected to the drain of the drive transistor T5, and a gate connected to the scanning line DSL.

In the example of the pixel circuit 10-x in FIG. 2, the operation of the pixel circuit 10-x operates when the sampling transistor T1 is selected by the scanning line WSL-x, and the input signal Vsig from the signal line DTL. Is stored in the storage capacitor C1 via the node Nd2.
The drive transistor T5 drives the organic EL element 1 by current according to the signal potential held in the holding capacitor C1.
The switching transistor T3 conducts when selected by the scanning line DSL-x, and supplies a current from the power supply potential Vcc to the drive transistor T5.
The first and second detection transistors T4 and T2 are made conductive by being selected at a predetermined timing by the scanning lines AZL-x and WSL-1. The first and second detection transistors T4 and T2 are turned on / off by detecting the threshold voltage Vth of the drive transistor T5 prior to current driving of the organic EL element 1, and detecting the threshold voltage Vth in advance. It is executed in association with an operation (threshold detection operation) for holding the threshold voltage in the holding capacitor C1.

The details of the operation of each pixel circuit 10 in such an embodiment are basically the same as those described with reference to FIGS. 3, 4 and 5, and therefore redundant description is avoided. Here, the gate line of the transistor T 4 is avoided. 3 will be described with reference to FIG. 3.
3A, 3B, and 3C show scanning pulses for the transistors T4, T2, T3, and T1 of the pixel circuit 10-1, the pixel circuit 10-x, and the pixel circuit 10-y, respectively. This scan pulse waveform is the same as the scan pulse for each of the transistors T4, T2, T3, and T1 described in FIG.
In the pixel circuit 10-1, the pixel circuit 10-x, and the pixel circuit 10-y, the transistors T4, T2, T3, and T1 are controlled by the scanning pulses of FIGS. 3A, 3B, and 3C, respectively. The operations described in FIGS. 9 and 10 are performed.

Here, as shown in FIG. 3A, the pulse of the scanning line WSL-1 that causes the sampling transistor T1 to conduct in order for the pixel circuit 10-1 to perform the writing operation is directly applied to the pixel circuit 10 of FIG. This is a pulse for conducting the -x detection transistor T4.
Further, the pulse of the scanning line WSL-x that causes the sampling transistor T1 to conduct in order for the pixel circuit 10-x of FIG. 3B to perform the writing operation is directly applied to the detection transistor of the pixel circuit 10-y of FIG. This is a pulse for conducting T4.
The pulse for turning on the detection transistor T4 in the pixel circuit 10-1 in FIG. 3A is the scanning line WSL- that turns on the sampling transistor T1 in the pixel circuit 10- (m + 1-q) in the (m + 1-q) th row. (M + 1-q) pulses are used.

Here, “H” in the period rH shown in FIG. 3 represents one horizontal period, and therefore “r” is from when the detection transistor T4 is turned off in a certain pixel circuit 10 until the writing operation is started. The number of horizontal periods in the period.
In this example, the threshold detection operation is started when the detection transistor T4 is turned off. The write operation is started when the sampling transistor T1 is turned on.
Q is q = r + 1, that is, the period qH is a horizontal period obtained by adding 1H to the period from when the threshold value detection operation is started in a certain pixel circuit 10 until the writing operation is started. . Therefore, “q” is a number obtained by adding 1 to the number corresponding to the number of horizontal cycles in the period from the start of the threshold detection operation to the start of the writing operation.
That is, “q” as the number of rows described above is a number obtained by adding 1 to the number of horizontal cycles in a period from when a threshold value detection operation is started in a certain pixel circuit 10 until the writing operation is started. Is the number of rows.
As described above, if a period rH (H is one horizontal period) shown in FIG. 3 is between the off timing of the detection transistor T4 and the on timing of the sampling transistor T1 in a certain pixel circuit, the sampling transistor of a certain row The conduction period of T1 coincides temporally with the conduction period of the detection transistors T4 in the rows separated by q rows (q = r + 1). For example, the conduction period of the sampling transistor T1 in the x-th row and the conduction period of the detection transistor T4 in the y-th row (y = x + q) separated by q rows coincide in time.
This is illustrated in FIG. 3, and therefore, as described above, the gate line (WSL) of the sampling transistor T1 of a certain pixel circuit 10 is shared as the gate line of the detection transistor T4 of the pixel circuit 10 separated by q rows. It can be done.

  The sampling transistor T1 is a transistor that is turned on for 1H as a writing period. As described with reference to FIG. 3, the detection transistor T4 is a transistor that charges the source potential of the drive transistor T5 to the potential Vss immediately before the threshold detection period, and the ON period of the detection transistor T4 has no problem as the 1H period in one frame. . For this reason, there is no problem in sharing the gate line as described above.

According to such an embodiment, the number of scanning lines (gate lines) input from the outside of the pixel array unit 20 can be greatly reduced, and the scanning lines corresponding to the first AZ scanner 14 shown in FIG. Since no driving circuit is required, the number of scanning line driving circuits can be reduced.
Therefore, in the example of the embodiment, after obtaining the same effect as the above-described reference example, it is possible to realize a reduction in cost and a high yield as a display device.

[3. Display device according to second embodiment]

A second embodiment will be described.
As described above, if the scanning line WSL is shared as the gate line of the sampling transistor T1 and the gate line of the detection transistor T4, the load on the scanning line WSL increases. Further, when a display device including a large display panel having a large vertical and horizontal size is considered, the length of the scanning line becomes long.
Under such circumstances, the signal delay of the scanning pulse due to the load of the scanning line WSL tends to affect the image quality.
For example, FIGS. 4A and 4B show scanning pulses on the scanning line WSL. The waveform shown as the input side in this figure is input to the leftmost pixel of the pixel array unit 20 when the write scanner 13 that drives the scanning line WSL is arranged on the left side of the pixel array unit 20 as shown in FIG. The waveform shown as the reverse input side is the scan pulse waveform input to the rightmost pixel of the pixel array unit 20.
In any case, the scan pulse on the scan line WSL as shown in FIG. 4A inevitably causes the waveform on the reverse side of the input to be delayed, but if the load is large and the delay amount is large, As shown in FIG. 4B, the waveform of the scanning pulse becomes dull, and for example, the writing operation due to the conduction of the transistor T1 cannot be performed normally. This causes image quality defects such as ghosts.

Therefore, as a second embodiment, a light scanner 17 is provided on the opposite side of the write scanner 13, that is, on the right side of the pixel array section 20, as shown in FIG. The write scanner 17 is supplied with a clock ck and a start pulse sp in common with the write scanner 13. The scanning lines WSL-1... WSL-m are given scanning pulses by the light scanners 13 and 17 from the left and right ends thereof.
By doing so, for example, the pixel circuit at the right end of the pixel array unit 20 also becomes the input side of the scan pulse, and a scan pulse with a large dullness as shown in FIG. 4B is not input.
That is, by driving the scanning line WSL by the write scanners 13 and 17 on both sides, it is possible to prevent any pixel circuit 10 from having a large delay of the scanning pulse, thereby executing normal pixel circuit operation. Therefore, it is possible to eliminate image quality defects. This makes it possible to make an appropriate technique for sharing the gate lines of the sampling transistor T1 and the detection transistor T4 from the viewpoint of increasing the screen size and increasing the definition.

1 is a block diagram of a display device according to a first embodiment of the present invention. It is a circuit diagram of a pixel circuit of an embodiment. It is explanatory drawing of the scanning pulse of embodiment. It is explanatory drawing of the delay of a scanning pulse. It is a block diagram of the display apparatus of the 2nd Embodiment of this invention. It is a block diagram of the display apparatus of a reference example. It is a circuit diagram of a pixel circuit of a reference example. It is explanatory drawing of operation | movement as embodiment and a reference example. It is an equivalent circuit diagram of each time in operation of an embodiment and a reference example. It is an equivalent circuit diagram of each time in operation of an embodiment and a reference example. It is a block diagram of the conventional organic electroluminescence display. It is a circuit diagram of a pixel circuit of a conventional organic EL display device. It is explanatory drawing of the time-dependent change of organic EL display. It is a circuit diagram of a pixel circuit of a conventional organic EL display device.

Explanation of symbols

1 organic EL element, 10 pixel circuit, 11 horizontal selector, 12 drive scanner, 13, 17 write scanner, 16 AZ scanner, C1 holding capacitor, T1 sampling transistor, T2, T4 detection transistor, T3 switching transistor, T5 drive transistor, WSL , DSL, AZL Scan line, DTL signal line

Claims (3)

A display device having a pixel array in which pixel circuits formed at portions where signal lines and a required number of scanning lines intersect are arranged in a matrix,
Each pixel circuit includes an organic electroluminescence element, a storage capacitor, and five n-channel thin film transistors including a sampling transistor, a drive transistor, first and second detection transistors, and a switching transistor,
The storage capacitor is connected between the source and gate of the drive transistor,
The organic electroluminescence element is connected between the source of the drive transistor and a predetermined cathode potential,
The first sensing transistor is connected between a source of the drive transistor and a first fixed potential;
The second detection transistor is connected between the gate of the drive transistor and a second fixed potential;
The sampling transistor is connected between the gate of the drive transistor and the signal line,
The switching transistor is connected between the drain of the drive transistor and a predetermined power supply potential,
The sampling transistor, the first and second detection transistors, and the switching transistor are configured to be conductively controlled by corresponding scanning lines, respectively.
A scanning line for controlling the conduction of the sampling transistors in the pixel circuits in each row is shared with a scanning line for controlling the conduction of the first detection transistors in the pixel circuits in other rows separated from the row by a predetermined number of rows. A display device characterized by that. In the non-light-emitting period in one light-emission cycle of the organic electroluminescence element consisting of a light-emitting period and a non-light-emitting period,
After the first and second detection transistors are turned on in a state where the switching transistor is turned on, the first detection transistor is turned off to detect a threshold voltage of the drive transistor, A threshold detection operation for holding the detected potential in the holding capacitor is started,
After the threshold detection operation is finished, only the sampling transistor is turned on, so that a writing operation for sampling an input signal from the signal line into the storage capacitor is started,
The predetermined number of rows is the number of rows obtained by adding 1 to the number of rows corresponding to the number of horizontal cycles in a period from the start of the threshold detection operation to the start of the writing operation. The display device according to claim 1.   The scanning lines provided for the sampling transistor and the first detection transistor are subjected to the same scanning pulse from both sides of the scanning line wiring by a pair of scanning line driving means provided on both sides of the pixel array. The display device according to claim 1, wherein the display device is applied.

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