JP2006196705A - Method for forming circuit element and multilayer circuit element - Google Patents
Method for forming circuit element and multilayer circuit element Download PDFInfo
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- JP2006196705A JP2006196705A JP2005006816A JP2005006816A JP2006196705A JP 2006196705 A JP2006196705 A JP 2006196705A JP 2005006816 A JP2005006816 A JP 2005006816A JP 2005006816 A JP2005006816 A JP 2005006816A JP 2006196705 A JP2006196705 A JP 2006196705A
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
本発明は、多層回路素子（パッケージ）の各層を構成する回路素子（チップ）の裏面にも回路を形成する方法に関する。 The present invention relates to a method of forming a circuit on the back surface of a circuit element (chip) constituting each layer of a multilayer circuit element (package).
図６は現在のパッケージの断面図である。このパッケージはベース上に３段のチップを上段のチップほどその面積が小さくなるものを選定して積み重ね、食み出た部分を利用してチップの回路とベースの回路とをワイヤボンディングで接続している。 FIG. 6 is a cross-sectional view of the current package. In this package, three stages of chips on the base are selected and stacked so that the upper chip has a smaller area, and the chip circuit and the base circuit are connected by wire bonding using the protruding part. ing.
また、図６に示した構造では上段のチップの面積が小さくなって実装効率が落ちるので、図７に示すように、チップ間にチップよりも小面積のスペーサを介在させて隙間を形成し、この隙間を利用してワイヤボンディングで接続している。 Further, in the structure shown in FIG. 6, since the area of the upper chip is reduced and the mounting efficiency is lowered, as shown in FIG. 7, a gap is formed by interposing a spacer having a smaller area than the chip between the chips, The gap is used for connection by wire bonding.
上述したパッケージではワイヤボンディングにおける伝送速度が遅く、高速且つ大容量の伝送が必要なデバイスでは大きな問題となっている。そこで、図８に示す構造のパッケージが提案されている。このパッケージはチップに貫通電極を形成してワイヤボンディングを廃止している。 The package described above has a low transmission speed in wire bonding, which is a big problem in devices that require high speed and large capacity transmission. Therefore, a package having a structure shown in FIG. 8 has been proposed. This package eliminates wire bonding by forming a through electrode on the chip.
一方、チップの製造法としては特許文献１〜３に開示される方法が知られている。
特許文献１に開示される方法は、先ず半導体ウェーハの回路（素子）形成面（Ａ面）に保護テープを貼り付け、これを反転して半導体ウェーハの裏面（Ｂ面）をグラインダーで研削して薄板化し、この薄板化した半導体ウェーハの裏面をダイシングフレームに保持されているダイシングテープ上に固定し、この状態で半導体ウェーハの回路（素子）形成面（Ａ面）を覆っている保護テープを剥離し、この後ダイシング装置によって各チップ毎に切り離すようにしている。
On the other hand, methods disclosed in Patent Documents 1 to 3 are known as chip manufacturing methods.
In the method disclosed in Patent Document 1, first, a protective tape is applied to a circuit (element) forming surface (A surface) of a semiconductor wafer, and this is reversed and the back surface (B surface) of the semiconductor wafer is ground with a grinder. The back surface of the thinned semiconductor wafer is fixed on a dicing tape held by a dicing frame, and the protective tape covering the circuit (element) formation surface (A surface) of the semiconductor wafer is peeled off in this state. Thereafter, each chip is separated by a dicing apparatus.
また特許文献２には、保護テープの代わりに窒化アルミニウム−窒化硼素気孔焼結体にラダー型シリコーンオリゴマーを含浸せしめた保護基板を用い、この保護基板と半導体ウェーハとを熱可塑性フィルムを用いて接着する内容が開示されている。 In Patent Document 2, a protective substrate in which a ladder type silicone oligomer is impregnated into an aluminum nitride-boron nitride pore sintered body is used instead of the protective tape, and the protective substrate and the semiconductor wafer are bonded using a thermoplastic film. The contents to be disclosed are disclosed.
また特許文献３には、保護基板として半導体ウェーハと実質的に同一の熱膨張率のアルミナ、窒化アルミニウム、窒化硼素、炭化珪素などの材料を用い、また保護基板と半導体ウェーハとを接着する接着剤としてポリイミドなどの熱可塑性樹脂を用い、この接着剤の適用法として、１０〜１００μｍの厚さのフィルムとする方法或いは接着剤樹脂溶液をスピンコートし、乾燥させて２０μｍ以下のフィルムにする方法が提案されている。
図８に示したワイヤボンディングを省略したパッケージとするにはチップの裏面にも回路（貫通電極用の穴）を形成する必要がある。特許文献１に開示される方法においては基板表面に保護テープを貼っているだけであるので基板を薄くするとその後の取り扱いが困難となる。そのため基板を十分に薄くすることができず、せいぜい１２５μｍ〜１５０μｍの厚みである。 In order to obtain a package in which the wire bonding shown in FIG. 8 is omitted, it is necessary to form a circuit (hole for through electrode) on the back surface of the chip. In the method disclosed in Patent Document 1, only a protective tape is applied to the surface of the substrate, so that the subsequent handling becomes difficult if the substrate is thinned. Therefore, the substrate cannot be made sufficiently thin, and the thickness is 125 μm to 150 μm at most.
ＩＣカードや携帯電話の薄型化、小型化、軽量化が要求されており、この要求を満たすためには組み込まれるパッケージの薄厚化が必要とされ、チップの厚さも２５μｍ〜５０μｍにしなければならない。しかしながら保護テープを用いていると現状の厚さ以下に研削するのは困難である。また保護テープを用いた場合には剥離の際に半導体ウェーハに割れや欠けが生じやすい。また保護テープだけでは薄膜化した半導体ウェーハを支えることができないため、搬送は人手によって行わなければならず自動化することができない。 IC cards and mobile phones are required to be thinner, smaller, and lighter, and in order to satisfy these requirements, it is necessary to reduce the thickness of the package to be incorporated, and the thickness of the chip must also be 25 μm to 50 μm. However, if a protective tape is used, it is difficult to grind the thickness below the current thickness. Further, when a protective tape is used, the semiconductor wafer is likely to be cracked or chipped during peeling. Further, since the thinned semiconductor wafer cannot be supported only by the protective tape, the conveyance must be performed manually and cannot be automated.
また特許文献２や特許文献３に開示されるように、保護テープの代わりにアルミナ、窒化アルミニウム、窒化硼素、炭化珪素などを保護基板（サポートプレート）として用いれば、薄板化ができ、ハンドリングや搬送の自動化が可能になる。 Further, as disclosed in Patent Document 2 and Patent Document 3, if a protective substrate (support plate) such as alumina, aluminum nitride, boron nitride, or silicon carbide is used instead of the protective tape, the thickness can be reduced, and handling or transportation can be performed. Can be automated.
しかしながら、保護基板と半導体ウェーハとを一旦乾燥した熱可塑性フィルムを接着手段として用いているため、熱可塑性フィルムを柔らくするための加熱工程が必要となり、また、フィルム状の接着剤を用いると接着強度に部分的なバラツキが生じ、研削の際に剥がれたり、逆にダイシングの際に剥離しにくい箇所が現れるなどの欠点がある。 However, since a thermoplastic film that has once dried the protective substrate and the semiconductor wafer is used as the bonding means, a heating step is required to soften the thermoplastic film. There are some disadvantages such as partial variations in strength, peeling off during grinding, and conversely, parts that are difficult to peel off appear during dicing.
更に、熱可塑性フィルムの耐熱性も問題となる。即ち、裏面に回路を形成する工程では、メタライズ、エッチング或いはアッシングと言った加熱工程が必須であるが、熱可塑性フィルムの耐熱性が劣るとこれらの工程を施すことができない。 Furthermore, the heat resistance of the thermoplastic film is also a problem. That is, in the process of forming a circuit on the back surface, a heating process such as metallization, etching or ashing is essential, but these processes cannot be performed if the heat resistance of the thermoplastic film is inferior.
上記課題を解決すべく本発明に係る回路素子の形成方法は、回路を形成した基板の表面に剛性を有するサポートプレートを貼り付け、この状態で基板の裏面を研削して薄板化し、次いで基板の裏面に回路を形成し、この回路を形成した裏面にダイシングテープを貼り合わせ、この後、基板の表面からサポートプレートを剥離し、個々の素子に切断するようにした。 In order to solve the above problems, a circuit element forming method according to the present invention is characterized in that a rigid support plate is attached to the surface of a substrate on which a circuit is formed, and the back surface of the substrate is ground and thinned in this state. A circuit was formed on the back surface, and a dicing tape was bonded to the back surface on which the circuit was formed. After that, the support plate was peeled off from the surface of the substrate and cut into individual elements.
前記サポートプレートを貼り付けるにあたっては、基板の回路形成面に接着剤液を塗布した後、当該接着剤液をオーブン又はホットプレートで乾燥せしめる。また、必要な厚さを得るために、接着剤液の塗布と予備乾燥を複数回繰り返すようにしてもよい。 In attaching the support plate, an adhesive solution is applied to the circuit forming surface of the substrate, and then the adhesive solution is dried in an oven or a hot plate. Further, in order to obtain a necessary thickness, the application of the adhesive liquid and the preliminary drying may be repeated a plurality of times.
また、半導体ウェーハなどの基板の回路形成面に接着剤液をスピンコータで塗布すると周縁部に一段高くなったビード部ができる場合がある。この場合には、当該接着剤液を予備乾燥する前に、ビード部を溶剤によって除去することが好ましい。 Further, when an adhesive liquid is applied to a circuit forming surface of a substrate such as a semiconductor wafer with a spin coater, a bead portion that is raised one step at a peripheral portion may be formed. In this case, it is preferable to remove the bead portion with a solvent before the adhesive liquid is pre-dried.
前記サポートプレートとしては剛性を有し厚み方向に多数の貫通穴が形成したガラス製のプレートが考えられる。貫通穴を形成したサポートプレートを用いると、貫通穴を介して溶剤をサポートプレートと基板との間の接着剤に接触させてサポートプレートを基板から剥離することができる。従来ではサポートプレート（ガラス板）側から紫外線を照射し接着テープの粘着力を低下せしめてサポートプレートと基板とを剥離していたため、耐熱性に優れた接着テープを使用することができず、そのため裏面に回路形成工程を施すことができなかったが、多数の貫通穴が形成されたサポートプレートを用いることで、耐熱性に優れた接着剤を使用することができるので、裏面への回路形成が可能になる。 As the support plate, a glass plate having rigidity and a large number of through holes formed in the thickness direction can be considered. When the support plate in which the through hole is formed is used, the support plate can be peeled from the substrate by bringing the solvent into contact with the adhesive between the support plate and the substrate through the through hole. In the past, UV light was applied from the support plate (glass plate) side to reduce the adhesive strength of the adhesive tape, and the support plate and the substrate were peeled off, making it impossible to use adhesive tape with excellent heat resistance. Although the circuit formation process could not be performed on the back side, it is possible to use an adhesive with excellent heat resistance by using a support plate in which a large number of through holes are formed. It becomes possible.
前記接着剤としては、研磨時に水を使用するので非水溶性の高分子化合物が好ましく、またＤＡＦ（ダイアタッチフィルム）の貼り付けなどの高温処理工程があるため軟化点が高いことが望ましい。以上の点を考慮すると、ノボラック樹脂，エポキシ樹脂、アミド樹脂、シリコーン樹脂、アクリル樹脂、ウレタン樹脂、ポリスチレン、ポリビニルエーテル、ポリ酢酸ビニルおよびその変性物またはそれらの混合物を溶剤に溶解したものが挙げられる。中でもアクリル系樹脂材料は２００℃以上の耐熱性があり、発生するガスも少なく、クラックが発生し難いので好ましい。またノボラック樹脂もスカムがなく、耐熱性、発生ガス量及びクラックの発生についてはアクリル系樹脂材料に劣るが、軟化点が高く、接着後の剥離についても溶剤剥離が容易な点で好ましい。これに加えて成膜時のクラック防止に可塑剤を混合してもよい。 As the adhesive, water is used at the time of polishing, so that a water-insoluble polymer compound is preferable, and a high softening point is desirable because there is a high-temperature treatment step such as attaching DAF (die attach film). Considering the above points, novolak resins, epoxy resins, amide resins, silicone resins, acrylic resins, urethane resins, polystyrene, polyvinyl ether, polyvinyl acetate and modified products thereof, or mixtures thereof can be mentioned. . Among them, the acrylic resin material is preferable because it has a heat resistance of 200 ° C. or higher, generates less gas, and hardly generates cracks. In addition, novolak resin has no scum and is inferior to acrylic resin material in terms of heat resistance, amount of generated gas, and generation of cracks, but is preferable in terms of high softening point and easy peeling of the solvent after bonding. In addition to this, a plasticizer may be mixed to prevent cracks during film formation.
また、溶剤としては上記物質を溶解でき、また均一にウェーハに成膜できるものが望ましく、例えばアセトン、メチルエチルケトン、シクロヘキサン、メチルイソアミルケトン、２−ヘプタノンなどのケトン類；エチレングリコール、プロピレングリコール、ジエチレングリコール、エチレングリコールモノアセテート、プロピレングリコールモノアセテート、ジエチレングリコールモノアセテートあるいはこれらのモノメチルエーテル、モノエチルエーテル、モノプロピルエーテル、モノブチルエーテルまたはモノフェニルエーテル等の多価アルコール類およびその誘導体；ジオキサンのような環式エーテル類；および乳酸エチル、酢酸メチル、酢酸エチル、酢酸ブチル、ピルビン酸メチル、ピルビン酸エチル、メトキシプロピオン酸メチル、エトキシプロピオン酸エチル等のエステル類、ベンゼン、トルエン、キシレン等の芳香族炭化水素類を挙げることができる。これらは単独で用いてもよいし、２種以上を混合して用いてもよい。特にエチレングリコール、プロピレングリコール、ジエチレングリコール、エチレングリコールモノアセテート、プロピレングリコールモノアセテート、ジエチレングリコールモノアセテートあるいはこれらのモノメチルエーテル、モノエチルエーテル、モノプロピルエーテル、モノブチルエーテルまたはモノフェニルエーテル等の多価アルコール類およびその誘導体が好ましい。また膜厚の均一性を向上させるためにこれらに活性剤を添加してもよい。 Further, as the solvent, those capable of dissolving the above substances and capable of uniformly forming a film on the wafer are desirable. For example, ketones such as acetone, methyl ethyl ketone, cyclohexane, methyl isoamyl ketone, 2-heptanone; ethylene glycol, propylene glycol, diethylene glycol, Polyhydric alcohols such as ethylene glycol monoacetate, propylene glycol monoacetate or diethylene glycol monoacetate or their monomethyl ether, monoethyl ether, monopropyl ether, monobutyl ether or monophenyl ether and their derivatives; cyclic ethers such as dioxane And ethyl lactate, methyl acetate, ethyl acetate, butyl acetate, methyl pyruvate, ethyl pyruvate, methyl methoxypropionate Esters such as ethyl ethoxypropionate, benzene, toluene, aromatic hydrocarbons such as xylene. These may be used alone or in combination of two or more. In particular, polyhydric alcohols such as ethylene glycol, propylene glycol, diethylene glycol, ethylene glycol monoacetate, propylene glycol monoacetate, diethylene glycol monoacetate or their monomethyl ether, monoethyl ether, monopropyl ether, monobutyl ether or monophenyl ether and the like Derivatives are preferred. In order to improve the uniformity of the film thickness, an activator may be added thereto.
また接着剤を取り除くための剥離液としては、上記の溶剤に加え、メタノール、エタノール、プロパノール、イソプロパノール、ブタノールなどの一価アルコール類、γ−ブチロラクトンなどの環状ラクトン類、ジエチルエーテルやアニソールなどのエーテル類、ジメチルホルムアルデヒド、ジメチルアセトアルデヒドなどを使用してもよい。特に好ましいものは比較的溶解速度が速いメタノールが挙げられる。 In addition to the above solvents, the stripping solution for removing the adhesive includes monohydric alcohols such as methanol, ethanol, propanol, isopropanol and butanol, cyclic lactones such as γ-butyrolactone, ethers such as diethyl ether and anisole. Dimethylformaldehyde, dimethylacetaldehyde, etc. may be used. Particularly preferred is methanol having a relatively high dissolution rate.
また、前記裏面への回路の形成は貫通電極を形成する工程を含むようにすれば、得られた回路素子を積層することで多層回路素子（パッケージ）が得られる。 If the circuit formation on the back surface includes a step of forming a through electrode, a multilayer circuit element (package) can be obtained by stacking the obtained circuit elements.
本発明によれば、半導体ウェーハ等の基板を薄板化する際に、テープではなく剛性を有するサポートプレートにて支持するようにしたので、ハンドリングや搬送の自動化が可能になる。 According to the present invention, when a substrate such as a semiconductor wafer is thinned, it is supported by a rigid support plate instead of a tape, so that handling and conveyance can be automated.
また接着剤として耐熱性に優れた材料を使用できるので、裏面への回路形成が可能になる。特に裏面に貫通電極を形成することで従来よりも大幅に厚みを小さくしたパッケージを製造することができ、携帯電話やコンピュータに組み込むパッケージの薄型化、小型化、軽量化が図れ、或いはＩＣカードや非接触ＩＣカード自体の薄型化、小型化、軽量化も図れる。 In addition, since a material having excellent heat resistance can be used as the adhesive, it is possible to form a circuit on the back surface. In particular, by forming a through-electrode on the back surface, it is possible to manufacture a package with a thickness that is significantly smaller than conventional packages, making it possible to reduce the thickness, size, and weight of a package incorporated into a mobile phone or a computer, The non-contact IC card itself can be reduced in thickness, size and weight.
以下に本発明の実施の形態を添付図面に基づいて説明する。図１は本発明に係る回路素子の形成方法の概略を説明した図、図２は回路素子の形成方法のうち裏面への回路形成の一例を詳細に説明した図である。 Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram for explaining an outline of a method for forming a circuit element according to the present invention, and FIG. 2 is a diagram for explaining in detail an example of circuit formation on the back surface of the method for forming a circuit element.
本発明にあっては先ず、半導体ウェーハＷの回路（素子）形成面に接着剤液を塗布する。塗布には例えばスピンナーを用いる。接着剤液としてはアクリル系樹脂またはノボラックタイプのフェノール樹脂系材料とする。 In the present invention, first, an adhesive solution is applied to the circuit (element) forming surface of the semiconductor wafer W. For example, a spinner is used for coating. The adhesive liquid is an acrylic resin or a novolac type phenolic resin material.
次いで、上記の接着剤液をオーブン又はホットプレートを用いて乾燥させて接着剤層１とする。接着剤層１の厚みは半導体ウェーハＷの表面に形成した回路の凹凸に応じて決定する。尚、一回の塗布では必要な厚みを出せない場合には、塗布と乾燥を複数回繰り返して行う。この場合、最上層以外の接着剤層の乾燥は接着剤に流動性を残さないように乾燥の度合いを強める。 Next, the above adhesive liquid is dried using an oven or a hot plate to form an adhesive layer 1. The thickness of the adhesive layer 1 is determined according to the unevenness of the circuit formed on the surface of the semiconductor wafer W. In addition, when a required thickness cannot be obtained by one application, application and drying are repeated a plurality of times. In this case, drying of the adhesive layers other than the uppermost layer increases the degree of drying so as not to leave fluidity in the adhesive.
また、スピンナーを用いて接着剤液を塗布した場合には、乾燥後にあっても半導体ウェーハＷのエッジ部には盛上りが生じている。この盛上りについては後工程のプレスで潰してもよいが、処理液で盛上りの部分を除去してもよい。 Further, when the adhesive liquid is applied using a spinner, the edge portion of the semiconductor wafer W rises even after drying. This swell may be crushed by a subsequent press, but the swell may be removed with a treatment liquid.
以上によって所定厚みの接着剤層１が形成された半導体ウェーハＷにサポートプレート２を貼り付ける。サポートプレート２は図３に示すように半導体ウェーハＷよりも若干大径か同径のガラス板で、直径０．５ｍｍの貫通穴３が０．７ｍｍピッチで形成されている。 The support plate 2 is attached to the semiconductor wafer W on which the adhesive layer 1 having a predetermined thickness is formed as described above. As shown in FIG. 3, the support plate 2 is a glass plate having a diameter slightly larger than or equal to that of the semiconductor wafer W, and through holes 3 having a diameter of 0.5 mm are formed at a pitch of 0.7 mm.
上記サポートプレート２を半導体ウェーハＷの接着剤層１の上に重ね、図４に示す貼り付け機５を用いて貼り付ける。貼り付け装置５は減圧チャンバー２１を備えている。この減圧チャンバー２１は配管２２を介して真空引き装置につながり、また一側面には搬入・搬出用の開口２３が形成され、この開口２３をシャッター２４で開閉するようにしている。 The support plate 2 is overlaid on the adhesive layer 1 of the semiconductor wafer W and pasted using the pasting machine 5 shown in FIG. The affixing device 5 includes a decompression chamber 21. The decompression chamber 21 is connected to a vacuuming device via a pipe 22, and an opening 23 for carrying in / out is formed on one side surface, and the opening 23 is opened and closed by a shutter 24.
シャッター２４はシリンダユニット２５にて昇降動せしめられ、上昇した位置で側方からプッシャー２６にて押圧することで、シャッター２４の内側面に設けたシールが開口２３の周囲に密に当接し、チャンバー２１内を気密に維持する。またプッシャー２６を後退させシャッター２４を下降させることで、開口２３が開となり、この状態で搬送装置を用いてウェーハＷとサポートプレート２との積層体を出し入れする。 The shutter 24 is moved up and down by the cylinder unit 25 and pressed by the pusher 26 from the side at the raised position, so that the seal provided on the inner surface of the shutter 24 comes into close contact with the periphery of the opening 23, and the chamber 21 is kept airtight. Further, the pusher 26 is retracted and the shutter 24 is lowered to open the opening 23. In this state, the stacked body of the wafer W and the support plate 2 is taken in and out using the transfer device.
前記チャンバー２１内には前記積層体を圧着する保持台２７と押圧板２８が配置されている。保持台２７は炭化珪素（ＳｉＣ）からなり押圧板２８はアルミナ（Ａｌ２Ｏ３）からなる。尚、セラミックス焼結体にて押圧板を構成し、このセラミックス焼結体に排気管を接続する構成も考えられるが、この構成にすると十分に接着剤中のガスが抜けないおそれがある。 A holding base 27 and a pressing plate 28 for pressure-bonding the laminate are disposed in the chamber 21. The holding table 27 is made of silicon carbide (SiC), and the pressing plate 28 is made of alumina (Al 2 O 3 ). In addition, although the structure which comprises a press board with a ceramic sintered compact and connects an exhaust pipe to this ceramic sintered compact is also considered, there exists a possibility that the gas in an adhesive agent may not fully escape if this structure is used.
前記保持台２７には貫通孔２９が形成され、この貫通孔２９に昇降ピン３０が挿通している。この昇降ピン３０はチャンバー２１の下方に設けられたシリンダユニット３１で昇降動するプレート３２に取り付けられている。 A through hole 29 is formed in the holding table 27, and an elevating pin 30 is inserted into the through hole 29. The elevating pins 30 are attached to a plate 32 that moves up and down by a cylinder unit 31 provided below the chamber 21.
また、前記保持台２７にはヒータ３３が埋設され、このヒータ３３によって前記積層体を２００℃程度まで加熱し、一旦硬化した接着剤を柔らかくする。尚ヒータは押圧板２８側に設けてもよい。 A heater 33 is embedded in the holding table 27, and the laminated body is heated to about 200 ° C. by the heater 33 to soften the adhesive once cured. The heater may be provided on the pressing plate 28 side.
一方、前記押圧板２８はバックプレート３４に保持され、このバックプレート３４はチャンバー１１を貫通する軸３５の下端に取り付けられている。この軸３５の中間部にはフランジ３６が設けられ、このフランジ３６とチャンバー１１上面との間に蛇腹３７が取り付けられ、チャンバー２１内の気密状態を維持している。 On the other hand, the pressing plate 28 is held by a back plate 34, and the back plate 34 is attached to the lower end of a shaft 35 that penetrates the chamber 11. A flange 36 is provided at an intermediate portion of the shaft 35, and a bellows 37 is attached between the flange 36 and the upper surface of the chamber 11 to maintain an airtight state in the chamber 21.
また前記チャンバー２１からは上方にフレーム３８が伸び、このフレーム３８にサーボモータ３９が支持され、このサーボモータ３９によって回転せしめられるスクリューネジ４０に昇降体４１のナット部４２が螺合し、この昇降体４１にボールジョイント４３を介して前記軸３５の上端部が支持されている。更に、軸３５の側方には軸３５の上下位置を検出するセンサ４４を配置している。 A frame 38 extends upward from the chamber 21, a servo motor 39 is supported on the frame 38, and a nut portion 42 of the elevating body 41 is screwed into a screw screw 40 rotated by the servo motor 39, and the elevating and lowering is performed. An upper end portion of the shaft 35 is supported on the body 41 via a ball joint 43. Further, a sensor 44 for detecting the vertical position of the shaft 35 is disposed on the side of the shaft 35.
以上において半導体ウェーハＷとサポートプレート２の積層体を圧着するには、
先ず押圧板２８の平行度の調整を行う。平行度を出すには、ボールジョイント４３のボルトを緩めボールジョイント４３をフリーの状態にする。そして、この状態のまま押圧板２８を自重で下降せしめ、押圧板２８の下面を保持台２７の上面に当接させる。この時点で保持台２７と押圧板２８とは平行になる。次いで、ボルトを締め付けボールジョイント４３を固定した後、押圧板２８を上昇せしめる。
In order to crimp the laminated body of the semiconductor wafer W and the support plate 2 in the above,
First, the parallelism of the pressing plate 28 is adjusted. In order to obtain parallelism, the bolt of the ball joint 43 is loosened so that the ball joint 43 is in a free state. In this state, the pressing plate 28 is lowered by its own weight, and the lower surface of the pressing plate 28 is brought into contact with the upper surface of the holding table 27. At this time, the holding table 27 and the pressing plate 28 are in parallel. Next, after tightening the bolt and fixing the ball joint 43, the pressing plate 28 is raised.
平行度の調整は毎回行う必要はなく、適当な回数ごとに行う。また、上記では積層体を挟まずに平行度の調整を行ったが、圧着する積層体と同一厚みの板材を保持台２７と押圧板２８との間に介在させて平行度を調整してもよい。 The degree of parallelism does not need to be adjusted every time, but is adjusted every appropriate number of times. In the above, the parallelism is adjusted without sandwiching the laminated body. However, the parallelism can be adjusted by interposing a plate material having the same thickness as the laminated body to be crimped between the holding base 27 and the pressing plate 28. Good.
以上によって平行度の調整が終了したら、窒素ガスがパージされて大気圧状態にあるチャンバー２１の開口２３をシャッター２４を下げることで開とする。そして、図示しない搬送装置で半導体ウェーハＷとサポートプレート２の積層体をチャンバー２１内に入れ、ピン３０上に受け渡し、シャッター２４で開口２３を閉じ、チャンバー２１内を気密な状態にする。図４はこの状態を示している。 When the adjustment of the parallelism is completed as described above, the opening 23 of the chamber 21 which is purged with nitrogen gas and is in the atmospheric pressure state is opened by lowering the shutter 24. Then, the stacked body of the semiconductor wafer W and the support plate 2 is put into the chamber 21 by a transfer device (not shown), transferred onto the pins 30, the opening 23 is closed by the shutter 24, and the inside of the chamber 21 is made airtight. FIG. 4 shows this state.
次いでチャンバー２１内を減圧し、シリンダユニット３１を駆動してピン３０を下げ、積層体を１５０℃程度まで加熱されている保持台１７上に載置する。 Next, the inside of the chamber 21 is depressurized, the cylinder unit 31 is driven, the pin 30 is lowered, and the stacked body is placed on the holding table 17 heated to about 150 ° C.
上記と並行して、サーボモータ３９を駆動して押圧板２８を予め設定した位置まで降下せしめ、保持台２７と押圧板２８との間で積層体を加圧する。この状態で約１分間保持して基板Ｗとサポートプレート２とを熱圧着する。 In parallel with the above, the servo motor 39 is driven to lower the pressing plate 28 to a preset position, and the laminate is pressed between the holding base 27 and the pressing plate 28. In this state, the substrate W and the support plate 2 are thermocompression bonded by holding for about 1 minute.
この後、押圧板２８を上昇せしめた後に窒素ガスをパージしてチャンバー２１内を大気圧に戻し、シャッター２４を下げ、熱圧着せしめられた積層体をチャンバー２１外へ搬出する。
尚、上記実施例ではチャンバー２１内の減圧状態を大気圧に戻す前に押圧板２８を上昇せしめるようにしたが、先にチャンバー２内を大気圧に戻し、この後押圧板２８を上昇せしめにてもよい。
Thereafter, the pressure plate 28 is raised and then purged with nitrogen gas to return the inside of the chamber 21 to atmospheric pressure, the shutter 24 is lowered, and the laminated body that has been thermocompression bonded is carried out of the chamber 21.
In the above embodiment, the pressure plate 28 is raised before the reduced pressure in the chamber 21 is returned to atmospheric pressure. However, the pressure inside the chamber 2 is first returned to atmospheric pressure, and then the pressure plate 28 is raised. May be.
サポ−トプレート２の上から溶剤としてのアルコールを注いで接着剤を溶解させる。図５は溶剤供給手段の具体例を示し、この例にあっては溶剤供給手段を溶剤供給プレート５０の下面にＯリング５１を設けている。溶剤供給プレート５０には溶剤（剥離液）供給管５２及び溶剤排出管５３が接続されている。而して、図５（ａ）の状態から溶剤供給プレート５０を降下させ、図５（ｂ）に示すように、サポートプレート２の上面にＯリング５１を介して溶剤供給プレート５０を重ね、次いでサポートプレート２、Ｏリング５１及び溶剤供給プレート５０で囲まれる空間に溶剤供給管４２から溶剤を供給し、サポートプレート２に形成した貫通孔３を介して接着剤層１を溶解し除去する。 Alcohol as a solvent is poured from above the support plate 2 to dissolve the adhesive. FIG. 5 shows a specific example of the solvent supply means. In this example, the solvent supply means is provided with an O-ring 51 on the lower surface of the solvent supply plate 50. A solvent (separating liquid) supply pipe 52 and a solvent discharge pipe 53 are connected to the solvent supply plate 50. Thus, the solvent supply plate 50 is lowered from the state of FIG. 5A, and as shown in FIG. 5B, the solvent supply plate 50 is overlaid on the upper surface of the support plate 2 via the O-ring 51. A solvent is supplied from a solvent supply pipe 42 to a space surrounded by the support plate 2, the O-ring 51 and the solvent supply plate 50, and the adhesive layer 1 is dissolved and removed through the through holes 3 formed in the support plate 2.
このように、Ｏリング５１によって溶剤が供給される空間を制限することで、溶剤がダイシングテープに極力溶剤がかかることを防げる。またテープにアルコールが触れた場合、アルコールによって溶解したテープののりがウェーハ表面を汚染する懸念があるが、この機構ではそれを防止することができる。 Thus, by limiting the space where the solvent is supplied by the O-ring 51, the solvent can prevent the solvent from being applied to the dicing tape as much as possible. Further, when alcohol touches the tape, there is a concern that the glue of the tape dissolved by the alcohol contaminates the wafer surface, but this mechanism can prevent this.
この後、貼り付け機５から一体化した半導体ウェーハＷとサポートプレート２を取り外し、半導体ウェーハＷの裏面（Ｂ面）をグラインダー１０で研削し、半導体ウェーハＷを薄板化する。尚、研削によってグラインダー１０と半導体ウェーハＷとの間に生じる摩擦熱を抑えるために水を半導体ウェーハＷの裏面に供給しつつ行う。ここで、前記接着剤は水に不溶（アルコールに可溶）なものを選定しているため、研削の際に半導体ウェーハＷからサポートプレート２が剥がれることがない。 Thereafter, the integrated semiconductor wafer W and the support plate 2 are removed from the pasting machine 5, and the back surface (B surface) of the semiconductor wafer W is ground by the grinder 10, thereby thinning the semiconductor wafer W. In order to suppress frictional heat generated between the grinder 10 and the semiconductor wafer W due to grinding, water is supplied to the back surface of the semiconductor wafer W. Here, since the adhesive is selected from those insoluble in water (soluble in alcohol), the support plate 2 is not peeled off from the semiconductor wafer W during grinding.
この薄板化した半導体ウェーハＷの裏面（Ｂ面）に回路を形成する。回路形成の詳細は図２に基づいて以下に詳細に説明する。
先ず、半導体ウェーハＷの裏面にレジストを塗布し、露光・現像を施してパターンを形成する。次いで半導体ウェーハＷ（Ｓｉ）を酸化膜が露出するまでエッチングし、更にボトム酸化膜もエッチングにて除いてＡ面側に形成されている回路を露出させ、前記レジストをアッシングにて除去し薬品洗浄することでコンタクトホールとする。
A circuit is formed on the back surface (B surface) of the thinned semiconductor wafer W. Details of the circuit formation will be described below in detail with reference to FIG.
First, a resist is applied to the back surface of the semiconductor wafer W, and exposure / development is performed to form a pattern. Next, the semiconductor wafer W (Si) is etched until the oxide film is exposed, and the bottom oxide film is also removed by etching to expose the circuit formed on the A side, and the resist is removed by ashing and chemical cleaning. As a result, a contact hole is formed.
次いで、コンタクトホール表面にデポジション法にて酸化膜を形成した後、Ａ面側の回路にかかる部分の酸化膜をエッチングにて除去し、薬品洗浄した後にバリアシード（ＴｉＮ／Ｃｕ）を形成する。次いで、Ｃｕメッキを施しドライフィルム（レジストフィルム）を貼り付け、露光・現像にてパターンを形成し、エッチングした後にレジストフィルムを除去して裏面側の回路が形成される。 Next, after forming an oxide film on the surface of the contact hole by a deposition method, the oxide film in the portion on the A-side circuit is removed by etching, and after chemical cleaning, a barrier seed (TiN / Cu) is formed. . Next, Cu plating is applied, a dry film (resist film) is attached, a pattern is formed by exposure and development, and after etching, the resist film is removed to form a circuit on the back side.
以上の如くして裏面（Ｂ面）に回路を形成したならば、積層した際の上下の回路の導通を図るべく、はんだボールを搭載し、更に裏面をダイシングテープ１１上に固定する。このダイシングテープ１１は粘着性を有するとともにフレーム１２に保持されている。 When the circuit is formed on the back surface (B surface) as described above, solder balls are mounted and the back surface is fixed on the dicing tape 11 in order to make the upper and lower circuits conductive when stacked. The dicing tape 11 has adhesiveness and is held by the frame 12.
この後、前記したように、サポートプレート２の上からアルコール（特に低分子アルコール）を注ぎ、接着剤層１を溶解し除去する。この場合、フレーム１２を図示しないスピンナーにて回転せしめることで、アルコールを短時間のうちに接着剤層１の全面に行き渡らせることができる。 Thereafter, as described above, alcohol (particularly low molecular alcohol) is poured from above the support plate 2 to dissolve and remove the adhesive layer 1. In this case, the alcohol can be spread over the entire surface of the adhesive layer 1 in a short time by rotating the frame 12 with a spinner (not shown).
図１に戻って、接着剤層１を溶解してサポートプレート２を取り外した後、ダイシング装置１３によって半導体ウェーハＷをチップサイズに切断する。切断後は、ダイシングテープ１１に紫外線を照射し、ダイシングテープ１１の粘着力を低下せしめて、切断したチップを取り出す。 Returning to FIG. 1, after the adhesive layer 1 is dissolved and the support plate 2 is removed, the semiconductor wafer W is cut into chips by the dicing apparatus 13. After cutting, the dicing tape 11 is irradiated with ultraviolet rays, the adhesive strength of the dicing tape 11 is reduced, and the cut chip is taken out.
上記によって得られたチップを積層することで、ワイヤボンディングのないパッケージが得られる。 By stacking the chips obtained as described above, a package without wire bonding can be obtained.
１…接着剤層、２…サポートプレート、３…貫通穴、５…貼り付け機、１０…グラインダー、１１…ダイシングテープ、１２…フレーム、１３…ダイシング装置、２１…減圧チャンバー、２２…配管、２３…開口、２４…シャッター、２５…シリンダユニット、２６…プッシャー、２７…保持台、２８…押圧板、２９…貫通孔、３０…昇降ピン、３１…シリンダユニット、３２…プレート、３３…ヒータ、３４…バックプレート、３５…軸、３６…フランジ、３７…蛇腹、３８…フレーム、３９…サーボモータ、４０…スクリューネジ、４１…昇降体、４２…ナット部、４３…ボールジョイント、４４…センサ、５０…溶剤供給プレート、５１…Ｏリング、５２…溶剤（剥離液）供給管、５３…溶剤排出管、Ｗ…半導体ウェーハ。 DESCRIPTION OF SYMBOLS 1 ... Adhesive layer, 2 ... Support plate, 3 ... Through-hole, 5 ... Pasting machine, 10 ... Grinder, 11 ... Dicing tape, 12 ... Frame, 13 ... Dicing apparatus, 21 ... Decompression chamber, 22 ... Piping, 23 ... Opening, 24 ... Shutter, 25 ... Cylinder unit, 26 ... Pusher, 27 ... Holding base, 28 ... Pressing plate, 29 ... Through hole, 30 ... Elevating pin, 31 ... Cylinder unit, 32 ... Plate, 33 ... Heater, 34 ... back plate, 35 ... shaft, 36 ... flange, 37 ... bellows, 38 ... frame, 39 ... servo motor, 40 ... screw screw, 41 ... elevating body, 42 ... nut part, 43 ... ball joint, 44 ... sensor, 50 ... Solvent supply plate, 51 ... O-ring, 52 ... Solvent (peeling liquid) supply pipe, 53 ... Solvent discharge pipe, W ... Semiconductor wafer.
Claims (6)
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| JP2005006816A JP2006196705A (en) | 2005-01-13 | 2005-01-13 | Method for forming circuit element and multilayer circuit element |
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