JP2006164835A - Micro electron source device and flat display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a micro electron source device having a good electron emission characteristic and causing no bright spot on a display and to provide a flat display device. <P>SOLUTION: In this micro electron source device, a cathode electrode 11, an insulation layer 13, and a gate electrode 14 are laminated sequentially on a substrate 10. The micro electron source device is provided with an aperture part 15, which is formed through the gate electrode 14 and an insulation layer 13, and a micro electron source layer 12 formed in the bottom part of the aperture part 15 and provided with a conductive matrix 12b and a carbon nanotube 12a embedded in the matrix 12b while protruding its one end. The aperture part 15 is a substantially column shaped hole, and the micro electron source layer 12 is a doughnut-shaped layer concentric with the circular bottom part of the aperture part 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a micro electron source device and a flat display device such as an FED using the micro power source device.

  Display measures such as television receivers and information terminal equipment respond to the demands for thinner, lighter, larger screens, and higher-definition displays, from CRTs that are limited in weight and thickness to flat display devices (flat panels). Development to shift to display devices) has been actively conducted. A liquid crystal panel is widely used as a flat panel display device for information terminal equipment. However, since it is difficult to increase brightness and size, home television receivers are still in the development stage.

  On the other hand, a field emission display (hereinafter abbreviated as FED) is being developed for betting on a large-sized flat panel display device because of its merit that high-resolution and high-luminance color display can be performed with low power consumption. The FED is a device that displays a desired pattern, characters, and symbols by exciting a phosphor to emit light when a chip-type cathode that emits electrons collides with electrons emitted from the cathode.

  The known FED has a structure in which an emitter array panel composed of a cathode connected to a plurality of row wirings and a gate connected to a plurality of column wirings and an anode panel coated with a phosphor are stacked with an insulating spacer interposed therebetween. (For example, see Patent Documents 1 and 2.)

  The emitter array panel is a row wiring / column wiring that forms a matrix according to a desired number of pixels by a CVD method, an etching method, a vacuum deposition method, a sputtering method, or a photolithographic method on a dielectric plate such as glass or a Si plate. A plurality of cathode chips per pixel and a gate electrode having holes corresponding to cathode chips insulated from the cathode chips by a dielectric are formed and formed.

  The anode panel is made by depositing a transparent electrode such as ITO on a dielectric plate such as glass, and shielding red (R), green (G), and blue (B) phosphors corresponding to each pixel. It is created by applying stripes through a lattice.

  In a conventional field emission display, electron emission emitters are arranged two-dimensionally, lead electrodes and cathode voltage wiring are arranged in a matrix, and phosphors are emitted by electrons emitted from the cathode tip by a strong electric field. A method of shining is used.

  Conventional metal emitters such as W have been used. Recently, DLC (diamond-like carbon) is a material that enables emission at a low threshold by lowering the work function of the emitter material. And other carbon materials are attracting attention.

  Further, an attempt to emit electrons from a flat surface without forming an emitter structure as in the prior art has been disclosed (see, for example, Non-Patent Document 1). Particularly, a carbon-based structure having a fine structure called a carbon nanotube is excellent. It has attracted attention because of its excellent electron emission characteristics (see, for example, Non-Patent Document 2). Furthermore, a method has been proposed in which an electron emission source (micro electron source device) is formed by mixing with a conductive material taking advantage of the characteristics of these carbon nanotubes (see, for example, Patent Document 3). By using carbon nanotubes, it is possible to realize a micro-electron source device having a stable electron emission with a low threshold voltage and a low drive voltage.

U.S. Pat. No. 4,908,539 JP-A-61-217883 Japanese Patent Laid-Open No. 2003-229044 Proceedings of the 60th Annual Meeting of the Japan Society of Applied Physics p.631 (lecture number 2P-H-6) Proceedings of the 60th Annual Meeting of the Japan Society of Applied Physics p.632 (Lecture No. 2P-H-11)

  However, when the above-mentioned micro electron source device is used in a flat display device, a problem that a bright spot appears on the display occurs. If there is even one bright spot because human recognition sensitivity is higher than black spot, it becomes a fatal defect as a display.

  The present invention has been made in view of the above-described problems in the prior art, and an object of the present invention is to provide a micro-electron source device and a flat display device with good electron emission characteristics that do not generate bright spots on a display. .

  The inventors investigated the cause of the occurrence of bright spots. When a voltage was applied to the anode electrode that is the counter electrode, the electric field component of the anode voltage that could not be cut off by the gate electrode that was the electron extraction electrode in the micro electron source device was mainly An electron emission source having a low threshold voltage of a micro electron source layer disposed on the cathode electrode at the bottom of the gate hole (opening), for example, a carbon nanotube having a high height serves as a stray source to emit electrons. I figured out that it appeared as a bright spot on the display. In view of this, the present invention has been accomplished by paying careful attention to the fact that an electric field component whose voltage cannot be cut off by the gate electrode is applied to the central region of the cathode electrode at the bottom of the opening.

  That is, the present invention provided to solve the above-described problem is that a cathode electrode, an insulating layer, and a gate electrode are sequentially stacked on a substrate, and an opening formed through the gate electrode and the insulating layer; In the micro-electron source device comprising a conductive matrix formed at the bottom of the opening and a micro-electron source layer composed of a carbon nanotube embedded in the matrix with one end protruding, the opening has a substantially cylindrical shape. The micro-electron source device is a micro-electron source device, wherein the micro-electron source layer is a donut-shaped layer concentric with the circular bottom of the opening.

Here, the inner diameter region of the minute electron source layer is preferably a region on the minute electron source layer which cannot be cut off by the gate electrode with respect to an electric field component generated when an anode voltage is applied as a flat display device.
The ratio of the depth of the opening to the bottom diameter is preferably 1: 6 or more.

  In order to solve the above problems, the present invention provides a substrate in which a cathode electrode, an insulating layer, and a gate electrode are sequentially stacked, and an opening formed through the gate electrode and the insulating layer, and the opening In the micro electron source device comprising a conductive matrix formed at the bottom of the part and a micro electron source layer made of carbon nanotubes embedded in the matrix with one end protruding, the opening has a substantially rectangular cross-sectional shape It is a groove, and the micro electron source layer is a band-shaped layer extending in the longitudinal direction of the groove having a hollow slit in the center in the width direction of the groove. Item 4).

Here, the slit region of the micro electron source layer is preferably a region on the micro electron source layer that cannot be cut off by the gate electrode with respect to an electric field component generated when an anode voltage is applied as a flat display device.
The ratio of the depth of the opening to the groove width is preferably 1: 6 or more.

  The present invention provided to solve the above problems includes a cathode panel in which a plurality of the micro electron source devices according to any one of claims 1 to 6 are formed on a plane, and a fluorescence facing the micro electron source device. A flat display device comprising a body layer and an anode panel having an anode electrode.

According to the micro-electron source device of the present invention, the micro-electron source layer is formed in a donut shape or a band shape with slits, so that the central region is made hollow in advance so as not to emit electrons, so that the stray source can be reduced. Can do.
In addition, it is conceivable to selectively remove the carbon nanotube as the electron emission source only in the middle of the cathode electrode at the bottom of the opening after forming the minute electron source layer (CNT removal process). As a manufacturing process, the generation of bright spots can be suppressed without increasing the number of processes. it can. Furthermore, it is difficult to selectively remove carbon nanotubes in the CNT removal process, and the reliability as a micro electron source device may be reduced. According to the present invention, however, the brightness is reduced without reducing the reliability. Point suppression is possible.
Further, according to the flat display device of the present invention, the minute power source layer is formed in a donut shape or a strip shape with a slit so that the central region is previously hollow so as not to emit electrons. Occurrence can be suppressed.

The first embodiment of the micro electron source device according to the present invention will be described below.
FIG. 1 is a schematic diagram showing the configuration of the first embodiment of the micro-electron source device of the present invention.
The micro-electron source device of the present invention includes an insulating substrate (for example, a glass substrate) 10 that becomes a base of the cathode panel 1 in a flat display device, and a cathode electrode 11 that is sequentially formed on the substrate 10 in a laminated state. The insulating layer 13 and the gate electrode 14, the opening (gate hole) 15 formed in the gate electrode 14 and the insulating layer 13, and the donut-shaped micro electron source layer 12 formed at the bottom of the opening 15 are configured. Has been.
Although only one doughnut-shaped micro-electron source layer 12 is shown in the drawing, a plurality of micro-electron source layers are formed on one cathode electrode 11 line as one subpixel when used for a display device. 12 are arranged side by side.

  The cathode electrode 11 and the gate electrode 14 are conductive films made of a conductive material. For example, a chromium (Cr) layer having a thickness of about 0.2 μm formed by a sputtering method.

  The micro-electron source layer 12 is formed by processing a composite layer containing carbon nanotubes 12a and a binder material (matrix) 12b. The carbon nanotubes 12a are embedded in a conductive matrix 12b, and the carbon nanotubes 12a Is in a state of protruding from the matrix 12b. The micro electron source layer 12 has a donut shape concentric with the circular bottom of the opening 15 (FIG. 1B).

  As the carbon nanotube main body, for example, a carbon nanotube main body having a very long tube structure (fibrous) having an average diameter of 1 nm and an average length of 1 μm is used. Alternatively, for example, carbon nanofibers having a fiber structure with an average diameter of 30 nm and an average length of 1 μm may be used.

  The matrix 12b constituting the micro electron source layer 12 is preferably made of a binder containing an organometallic compound containing at least one of In, Sn, Zn, and Al.

  The inner diameter region of the micro-electron source layer 12 is a hollow region in which the carbon nanotubes 12a and the matrix 12b do not exist and there is no electron emission, and the electric field component generated when an anode voltage is applied as a flat display device This is a region on the minute electron source layer 12 that cannot be cut off.

The inner diameter ID may be set based on an area in which the electric field component of the anode voltage on the micro-electron source layer 12 cannot be cut off by the gate electrode 14 (an area that cannot be cut off) in advance. Factors such as the diameter D of the opening 15, the depth d ₁ , the anode voltage, the gate voltage, and the distance between the anode electrode and the cathode electrode influence the uncut-off region.
When the screen size corresponds to a display device having a diagonal size of 40 inches or less, the inner diameter ID is preferably 5 to 30 μm.

The insulating layer 13 is an interlayer insulating film made of, for example, silicon oxide (SiO ₂ ).

  The opening 15 includes a first opening 15A formed in the gate electrode 14 and a second opening 15B formed in the insulating layer 13 so as to communicate with the first opening 15A. It is a substantially cylindrical hole and is a space through which electrons emitted from the minute electron source layer 12 pass. As long as the shape of the hole is circular at the top (gate electrode 14 side) and the bottom (cathode electrode 11 side), the side surface of the hole (that is, the wall surface of the insulating layer 13) is not affected as long as it does not obstruct the passage of emitted electrons. Any shape may be used.

The ratio (aspect ratio) between the depth d ₁ of the opening 15 and the bottom diameter D is preferably 1: 6 or more. When the aspect ratio is smaller than 1: 6, bright spots on the display are likely to be generated, which is not preferable.

The micro electron source device of the present invention is manufactured by the following procedure.
(S11) A conductive film 11L for forming a cathode electrode is formed on the substrate 10 (FIG. 2A). The conductive film 11L is made of, for example, Cr having a thickness of 0.2 μm formed by a sputtering method. Further, a resistance layer is formed on the conductive film 11L as necessary. The resistance layer is a thin film that serves to stabilize the discharge current to the micro-electron source layer 12 described later made of, for example, amorphous Si, SiCN, etc. having a film thickness of 0.2 μm formed by sputtering.

(S12) Next, a carbon nanotube dispersion liquid is applied as an electron emitter material on the cathode electrode, that is, on a desired region of the conductive film 11L. Application may be any method such as spraying or spin coating.
The carbon nanotube dispersion liquid is a mixture of a plurality of carbon nanotubes, a binder containing an organometallic compound containing at least one of In, Sn, Zn, and Al, and a volatile solvent (for example, butyl acetate). It was prepared. An example of a composition in the case of preparing by dispersing organotin and organoindium compounds (ITO solution) and carbon nanotubes, which are thermally decomposable organometals, in a volatile solvent such as butyl acetate is shown below.

(Carbon nanotube dispersion)
-Binder (ITO solution): 10 to 50% by weight of solid content
Carbon nanotube: 0.01-20% by weight
Solvent (butyl acetate): 30 to 80% by weight
Dispersant (for example, sodium dodecyl sulfate): 0.1 to 5% by weight

  As described above, a dispersant may be added in order to improve the dispersibility of the carbon nanotubes, or ultrasonic treatment may be performed. In addition, it is assumed that either aqueous or non-aqueous diluents may be added to the diluent, but the dispersant changes accordingly. Also, the carbon nanotubes may have a tube structure with an average diameter of 1 nm and an average length of 1 μm, for example, and those produced by an arc discharge method may be used.

(S13) After the carbon nanotube dispersion liquid is applied, a composite layer 12L in which the carbon nanotubes are dispersed and embedded in a conductive matrix made of a binder by firing is formed (FIG. 2B). ). For example, the firing may be performed in the following two stages.
(First firing)
・ Atmosphere: Air ・ Temperature: 350 ℃
・ Time: 30 minutes (second firing)
・ Atmosphere: Nitrogen ・ Temperature: 500 ℃
・ Time: 30 minutes

(S14) Next, the composite layer 12L is processed into a donut shape. Specifically, after a resist material layer is formed on the entire surface by spin coating, a mask layer in which the surface other than the region to be left in the composite layer 12L is exposed is formed based on the lithography technique. At this time, the mask layer is formed so that, for example, five doughnut-shaped composite layers 12L having an outer diameter of 65 μm and an inner diameter of 20 μm are arranged in one subpixel.
Next, the exposed composite layer 12L region is etched using, for example, HCl under the conditions of an etching temperature of 10 to 60 ° C. and an etching time of 10 seconds to 30 minutes (FIG. 2C).

  If carbon nanotubes exist outside the desired region after the above treatment, the carbon nanotubes are etched using oxygen plasma or an oxidizing solution. Examples of etching conditions at this time are shown below.

(Oxygen plasma etching)
・ Equipment: RIE
-Introducing gas: oxygen-containing gas-Plasma excitation power: 500W
Bias power: 0 to 150 W (DC or RF is acceptable, but RF is preferred)
・ Time: 10 seconds or more

(Oxidation solution etching)
-Solution: KMnO ₄
-Temperature: 20-80 ° C
・ Time: 10 seconds to 20 minutes

(S15) Next, the conductive film 11L is etched by a known photolithography technique and reactive ion etching (RIE) to form a striped cathode electrode 11 (FIG. 2D). At this point, a plurality of cathode lines are formed on the substrate 10.

(S16) An interlayer insulating film 13L is formed on the substrate 10 so as to cover the stacked portion of the cathode electrode 11 and the composite layer 12L, and a gate electrode made of, for example, 0.2 μm thick Cr is formed on the interlayer insulating film 13L. A forming conductive film 14L is formed (FIG. 3E). For example, a 12 μm-thick interlayer insulating film 13L made of, for example, SiO ₂ is formed on the entire surface of the substrate 10 by CVD using TEOS (tetraethoxysilane) as a source gas, and then Cr is formed on the interlayer insulating film 13L. The conductive film 14L made of may be formed by a sputtering method.

(S17) A resist mask layer is formed on the conductive film 14L, and a predetermined portion of the conductive film 14L is etched by reactive ion etching (RIE) using the resist mask layer, whereby the interlayer insulating film 13L is formed. A stripe-shaped gate electrode 14 is formed, and a first opening 15A penetrating through the gate electrode 14 is formed (FIG. 3F). At this time, the gate electrode 14 is processed into a stripe shape substantially orthogonal to the cathode electrode 11 on the interlayer insulating film 13L. That is, a plurality of gate lines orthogonal to the cathode line are formed. Further, the etched portion of the conductive film 14L exposes the interlayer insulating film 13L.

(S18) Next, the second opening 15B is exposed so that the composite layer 12L is exposed through dry etching such as reactive ion etching (RIE) through the first opening 15A of the gate electrode 14 in the interlayer insulating film 13L. Form. Thereby, an opening (gate hole) 15 including the first and second openings 15A and 15B is obtained (FIG. 3G).

  The micro-electron source device must be an assembly in which electron emission can be selected for each pixel. For this purpose, one subpixel is formed at a portion where the cathode electrode 11 and the gate electrode 14 serving as the electron extraction electrode are orthogonally overlapped. The openings 15 are for constituting the subpixel, and are formed as, for example, a substantially cylindrical hole having a diameter of 60 μm, and five openings are formed per subpixel. In this case, the aspect ratio of the opening 15 is 1: 5. Further, several tens of openings 15 are formed in one pixel.

(S19) Next, the matrix of the upper part of the composite layer 12L exposed at the bottom of the opening 15 is weakened (FIG. 4 (h)). As a technique for weakening the upper layer portion of the composite layer 12L, an etching method (light etching) such as wet etching or dry etching can be preferably used. For example, light etching may be performed under the conditions of an etchant: 10% HCl aqueous solution and an etching time of 5 to 60 seconds. By selectively removing the matrix material at the upper layer portion of the composite layer 12L by this etching, a large number of carbon nanotubes can be exposed on the surface.

(S1a) Thereafter, the carbon nanotubes are aligned so that the carbon nanotubes stand up substantially vertically on the surface of the etched composite layer 12L. Specifically, for example, after a film made of an acrylic resin (not shown) is pasted on the gate electrode 14 on the substrate 10, the film is cured by UV irradiation, and then the cured film is peeled off. 10, the longitudinal direction of the carbon nanotubes is oriented substantially perpendicularly. The direction for aligning the carbon nanotubes is a direction substantially perpendicular to the surface direction of the substrate 10. At this time, a large number of carbon nanotubes are exposed on the surface of the composite layer 12L. Therefore, a large number of carbon nanotubes can be vertically oriented by attaching and peeling the film. As a result, the carbon nanotubes 12a are embedded in the conductive matrix 12b, and the one end of the carbon nanotubes 12a becomes the minute electron source layer 12 protruding from the matrix 12b (FIG. 4 (i)).

  In addition to the method of applying and peeling off the adhesive tape as described above, the carbon nanotube alignment treatment method can be applied, for example, by applying a voltage to the cathode electrode 11 so that the cathode electrode 11 and the carbon nanotube have the same polarity. It is also possible to electrify and vertically align the carbon nanotubes in a state of being separated from each other by the repulsive force associated therewith.

  In this way, an insulating substrate (for example, a glass substrate) 10 which becomes the base of the cathode panel 1 in the flat display device, the cathode electrode 11, the insulating layer 13 formed in order on the substrate 10 in a laminated state, Microelectrons constituted by a gate electrode 14, an opening (gate hole) 15 formed in the gate electrode 14 and the insulating layer 13, and a donut-shaped microelectron source layer 12 formed at the bottom of the opening 15. The source device is completed.

Next, a second embodiment of the micro electron source device according to the present invention will be described.
FIG. 5 is a schematic diagram showing the configuration of the second embodiment of the micro-electron source device according to the present invention.
The micro-electron source device of the present invention includes an insulating substrate (for example, a glass substrate) 30 that serves as a base of the cathode panel 1 in a flat display device, and a cathode electrode 31 that is sequentially formed on the substrate 30 in a laminated state. The insulating layer 33 and the gate electrode 34, the opening (gate hole) 35 formed in the gate electrode 34 and the insulating layer 33, and the micro electron source layer 32 formed at the bottom of the opening 35 are configured. . In the drawing, the minute electron source layer 32 shows a state corresponding to one sub-pixel of the display device.
The constituent material of the micro electron source device is the same as that of the micro electron source device of the first embodiment. Hereinafter, differences from the first embodiment will be described.

  The micro-electron source layer 32 is a band-shaped layer extending in the longitudinal direction of the groove of the opening 35, and has a hollow slit at the center in the width direction of the groove. (FIG. 5B).

  The slit region of the micro-electron source layer 32 is a hollow region in which the carbon nanotubes 32a and the matrix 32b are not present and there is no electron emission, and the electric field component generated when an anode voltage is applied as a flat display device in the gate electrode. This is a region on the minute electron source layer 32 that cannot be cut off.

The slit width S is preferably set based on an area in which the electric field component of the anode voltage on the micro-electron source layer 32 cannot be cut off by the gate electrode 34 (an area that cannot be cut off). Factors such as the groove width W, the depth d ₂ , the anode voltage, the gate voltage, and the distance between the anode electrode and the cathode electrode affect the uncut-off region.
When the screen size corresponds to a display device having a diagonal size of 40 inches or less, the slit width S is preferably 5 to 30 μm.

  The opening 35 has a cross-sectional shape composed of a first opening formed in the gate electrode 34 and a second opening formed in the insulating layer 33 in a state communicating with the first opening. It is a substantially rectangular groove and is a space through which electrons emitted from the minute electron source layer 32 pass. The shape of the groove is not limited so long as the top part (gate electrode 34 side) and the bottom part (cathode electrode 31 side) are rectangular. Any shape may be used.

The ratio between the depth d ₂ and the slit width W of the opening 35 (the aspect ratio), 1: is preferably 6 or more. When the aspect ratio is smaller than 1: 6, bright spots on the display are likely to be generated, which is not preferable.

  The micro electron source device of the second embodiment is manufactured in the same procedure as in the first embodiment, but the micro electron source layer 32 is processed into a band-like layer having slits, and the opening 35 has a cross-sectional shape. It differs in that it is processed into a substantially rectangular groove. Specifically, step S24 shown below is performed instead of step S14 in the first embodiment, and steps S27 and 28 are performed instead of steps S17 and S18.

(S24) The composite layer 32L is processed into a band shape having a hollow slit at the center in the width direction. Specifically, after a resist material layer is formed on the entire surface by spin coating, a mask layer in which the surface other than the region to be left in the composite layer 32L is exposed is formed based on the lithography technique. At this time, for example, the mask layer is formed so that one band-shaped composite layer 32L having a slit having a band width of 65 μm and a slit width of 20 μm is arranged in one subpixel.
Next, the exposed composite layer 32L region is etched using HCl, for example, at an etching temperature of 10 to 60 ° C. and an etching time of 10 seconds to 30 minutes.

(S27) A resist mask layer is formed on the conductive film 34L, and a predetermined portion of the conductive film 34L is etched by reactive ion etching (RIE) using the resist mask layer, whereby the interlayer insulating film 33L is formed. A stripe-shaped gate electrode 34 is formed, and a first opening 35A penetrating the gate electrode 34 is formed. At this time, the gate electrode 34 is processed into a stripe shape substantially orthogonal to the cathode electrode 31 on the interlayer insulating film 33L. That is, a plurality of gate lines orthogonal to the cathode line are formed. In addition, the interlayer insulating film 33L is exposed at the etched portion of the conductive film 34L.

(S28) Next, the second opening 35B is exposed so that the composite layer 32L is exposed by dry etching such as reactive ion etching (RIE) through the first opening 35A of the gate electrode 34. Form. Thereby, the opening part 35 which consists of 1st, 2nd opening part 35A, 35B and whose cross-sectional shape is a substantially rectangular groove | channel is obtained.

  Processes other than those described above are the same as those in the first embodiment except that the reference numerals of the components are changed corresponding to those in the second embodiment. Finally, the micro electron source device shown in FIG. Is completed.

Thereafter, the flat display device is assembled. Specifically, the anode panel 2 and the cathode panel 1 are disposed so that the phosphor layer 22 and the micro electron source device face each other, and the anode panel 2 and the cathode panel 1 (more specifically, the substrate 21 and the substrate 21). 10) are joined to each other at the peripheral edge via the frame 3. At the time of joining, frit glass is applied to the joining part of the frame 3 and the anode panel 2 and the joining part of the frame 3 and the cathode panel 1, and the anode panel 2, the cathode panel 1 and the frame 3 are bonded together. Then, after the frit glass is dried by preliminary baking, main baking is performed at about 450 ° C. for 10 to 30 minutes. Thereafter, the space surrounded by the anode panel 2, the cathode panel 1, the frame 3 and the frit glass is exhausted through the through hole and the tip tube, and when the pressure in the space reaches about 10 ⁻⁴ Pa, the tip tube is removed. Seal by heat melting. In this way, the space surrounded by the anode panel 2, the cathode panel 1, and the frame 3 can be evacuated. Thereafter, wiring with necessary external circuits is performed to complete the flat display device shown in FIG.

FIG. 6 is a sectional view showing an example of the panel structure of the flat display device according to the present invention.
As shown in FIG. 6, the cathode panel (cathode substrate) 1 and the anode panel (anode substrate) 2 are arranged to face each other with a predetermined gap therebetween, and the panels 1 and 2 are integrated by a frame 3. As a result, a single panel structure (display panel) for image display is constructed.

  A plurality of micro electron source devices of the present invention are formed on the cathode panel 1. A plurality of these micro electron source devices are formed in a two-dimensional matrix in the effective area of the cathode panel 1 (area that actually functions as a display portion). Here, an example is shown in which the micro electron source device of the first embodiment is formed, but the micro electron source device of the second embodiment may be formed.

  As shown in FIG. 7, the cathode electrode 11 is formed in a stripe shape so as to form a plurality of cathode lines. The gate electrode 14 is formed in a stripe shape so as to form a plurality of gate lines intersecting (orthogonal) with each cathode line.

  On the other hand, the anode panel 2 includes a transparent substrate 21 serving as a base, a phosphor layer 22 and a black matrix 23 formed on the transparent substrate 21, and a transparent substrate 21 covering the phosphor layer 22 and the black matrix 23. And an anode electrode 24 formed thereon. The phosphor layer 22 includes a phosphor layer 22R for red light emission, a phosphor layer 22G for green light emission, and a phosphor layer 22B for blue light emission. The black matrix 23 is formed between the phosphor layers 22R, 22G, and 22B for emitting each color. The anode electrode 24 is formed in a laminated state over the entire effective area of the anode panel 2 so as to face the electron-emitting devices of the cathode panel 1.

  The cathode panel 1 and the anode panel 2 are joined to each other at the outer peripheral portion (peripheral portion) via the frame 3. In addition, a vacuum exhaust through-hole 16 is provided in the ineffective area of the cathode panel 1 (area outside the effective area and not actually functioning as a display portion). A tip tube 17 that is sealed after evacuation is connected to the through hole 16. However, since FIG. 6 shows the assembly completion state of the display device, the tip tube 17 has already been sealed. 6 and 7, the display of a pressure-resistant substrate (spacer) interposed in the gap portion between the panels 1 and 2 is omitted.

  In the display device having the panel structure configured as described above, a relative negative voltage is applied to the cathode electrode 11 from the cathode electrode control circuit 18, and a relative positive voltage is applied to the gate electrode 14 from the gate electrode control circuit 19. A positive voltage higher than that of the gate electrode 11 is applied to the anode electrode 24 from the anode electrode control circuit 20. In such a display device, when an image is actually displayed, for example, a scanning signal is input from the cathode electrode control circuit 18 to the cathode electrode 11 and a video signal is input from the gate electrode control circuit 19 to the gate electrode 14. Alternatively, a video signal is input from the cathode electrode control circuit 18 to the cathode electrode 11, and a scanning signal is input from the gate electrode control circuit 19 to the gate electrode 14.

  As a result, a voltage is applied between the cathode electrode 11 and the gate electrode 14, thereby concentrating the electric field on the sharpened portion of the minute electron source layer 12 (the tip portion of the carbon nanotube 12 a), thereby causing electrons by the quantum tunnel effect. Is released from the micro-electron source layer 12 into the vacuum through the energy barrier. The electrons thus emitted are attracted to the anode electrode 24, move to the anode panel 2 side, and collide with the phosphor layer 22 (22R, 22G, 22B) on the transparent substrate 21. As a result, the phosphor layer 22 is excited by the collision of electrons and emits light, so that a desired image can be displayed on the display panel by controlling the light emission position in units of pixels.

  Even when a voltage is applied to the anode electrode 24, the generation of bright spots on the display can be suppressed by the micro electron source device of the present invention.

  Examples of the present invention are shown below. In addition, a present Example is an illustration and the scope of the present invention is not limited to this.

Example 1
The micro-electron source device was manufactured by the following procedure.
(S31) A Cr layer having a thickness of 0.2 μm was formed by sputtering as the conductive film 11L for forming the cathode electrode on the substrate 10 which is a glass substrate (FIG. 2A).

(S32) Next, a carbon nanotube dispersion liquid having the following composition was spray applied to a desired region of the conductive film 11L.
(Carbon nanotube dispersion)
-Binder (ITO solution): Solid content 2% by weight
Carbon nanotube: 0.2% by weight
Dispersant (sodium dodecyl sulfate): 0.1% by weight
・ Solvent (Butyl acetate): Residue

(S33) After applying the carbon nanotube dispersion, firing was performed under the following conditions to form a composite layer 12L (FIG. 2B).
(First firing)
・ Atmosphere: Air ・ Temperature: 350 ℃
・ Time: 30 minutes (second firing)
・ Atmosphere: Nitrogen ・ Temperature: 500 ℃
・ Time: 30 minutes

(S34) Next, after a resist material layer is formed on the entire surface of the composite layer 12L by spin coating, a mask layer having an exposed surface other than the region to be left in the composite layer 12L is exposed based on the lithography technique. Formed. At this time, the mask layer was formed so that five doughnut-shaped composite layers 12L having an outer diameter of 65 μm and an inner diameter of 20 μm were arranged in one subpixel.
Next, the exposed composite layer 12L region was etched using HCl to process the composite layer 12L into a donut shape (FIG. 2C).

(S35) Next, the conductive film 11L was etched by a known photolithography technique and reactive ion etching (RIE) to form a striped cathode electrode 11 (FIG. 2D).

(S36) On the substrate 10, an interlayer insulating film 13L made of SiO ₂ is formed by CVD using TEOS (tetraethoxysilane) as a source gas so as to cover the laminated portion of the cathode electrode 11 and the composite layer 12L, Further, a conductive film 14L for forming a gate electrode made of Cr having a thickness of 0.2 μm was formed on the interlayer insulating film 13L (FIG. 3E). At this time, three types of samples were produced in which the thickness of the interlayer insulating film 13L was changed to 7, 10, and 20 μm.

(S37) A resist mask layer is formed on the conductive film 14L, and a predetermined portion of the conductive film 14L is etched by reactive ion etching (RIE) using the resist mask layer, whereby the interlayer insulating film 13L is formed. A stripe-shaped gate electrode 14 was formed, and a first opening 15A penetrating the gate electrode 14 was formed (FIG. 3F).

(S38) Next, through the first opening 15A of the gate electrode 14, the interlayer insulating film 13L is dry-etched by reactive ion etching (RIE) to form the second opening 15B so that the composite layer 12L is exposed. Formed. As a result, an opening (gate hole) 15, which is a substantially cylindrical hole composed of the first and second openings 15 </ b> A and 15 </ b> B having a diameter of 60 μm, was obtained (FIG. 3G).

(S39) Next, the matrix of the upper portion of the composite layer 12L exposed at the bottom of the opening 15 was weakened by wet etching using an etchant: 10% aqueous HCl (FIG. 4 (h)).

(S3a) Thereafter, the carbon nanotubes are aligned so that the carbon nanotubes stand up almost vertically on the surface of the etched composite layer 12L, thereby obtaining a micro electron source device (FIG. 4 (i)). ).

A flat display device having the configuration shown in FIG. 6 was assembled using this micro electron source device sample, and bright spots generated on the display (transparent substrate 21) were visually observed under the following conditions, and the number was counted. .
・ Observation screen size: 2 inches diagonal ・ Distance between anode and cathode: 1.1 mm
・ Anode voltage: 6.6 kV
・ Gate voltage: 42V
・ Cathode voltage: GND

(Example 2)
A sample was fabricated according to the second embodiment of the micro electron source device. That is, in the first embodiment, the following steps S44, 47, and 48 are performed instead of the steps S34, 37, and 38, respectively, and the flat display device is assembled and evaluated under the same conditions as in the first embodiment. went.

(S44) After a resist material layer was formed on the entire surface of the composite layer 32L by spin coating, a mask layer was formed on the entire surface of the composite layer 32L other than the region to be left, based on the lithography technique. At this time, the mask layer was formed so that a band-shaped composite layer 32L having a slit with a band width of 65 μm and a slit width of 20 μm was formed as one subpixel.
Next, the exposed composite layer 32L region was etched using HCl, and the composite layer 32L was processed into a strip shape having a slit.

(S47) A resist mask layer is formed on the conductive film 34L, and a predetermined portion of the conductive film 34L is etched by reactive ion etching (RIE) using the resist mask layer, whereby the interlayer insulating film 33L is formed. A stripe-shaped gate electrode 34 was formed, and a first opening which was a groove penetrating the gate electrode 34 was formed.

(S48) Next, the second opening is formed so that the composite layer 32L is exposed through dry etching processing of the interlayer insulating film 33L through the first opening of the gate electrode 34 by reactive ion etching (RIE). . As a result, an opening portion 35 having a substantially rectangular groove in cross section formed by the first and second opening portions having a groove width of 60 μm was obtained.

(Comparative example)
In Example 1, the micro electron source layer has a conventional shape (circular shape), the opening has a diameter of 20 μm, and the insulating layer has a thickness of 2.5, 3.5, and 7 μm. The flat display device was assembled under the same conditions as in No. 1 and evaluated.

The results are shown in Table 1.
In each of Examples 1 and 2, an excellent suppression effect of the bright spot was recognized as compared with the comparative example. The point was zero.

It is the schematic which shows the structure in 1st Embodiment of the micro electron source device which concerns on this invention. It is a manufacturing-process figure (1) of the micro electron source device of this invention. It is a manufacturing process figure (2) of the micro electron source device of this invention. It is a manufacturing-process figure (3) of the micro electron source apparatus of this invention. It is the schematic which shows the structure in 2nd Embodiment of the micro electron source device which concerns on this invention. It is sectional drawing which shows the structure of the flat type display apparatus which uses the micro electron source device of this invention. It is the schematic which shows the structure of the flat type display apparatus which uses the micro electron source device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Cathode panel, 2 ... Anode panel, 10, 30 ... Board | substrate, 11, 31 ... Cathode electrode, 11L, 14L ... Conductive film, 12, 32 ... Micro electron source layer , 12L ... Composite layer, 12a, 32a ... Carbon nanotube, 12b, 32b ... Matrix, 13, 33 ... Insulating layer, 13L ... Interlayer insulating film, 14, 34 ... Gate electrode , 15, 35 ... opening, 15A ... first opening, 15B ... second opening, 16 ... through hole, 17 ... tip tube, 18 ... cathode electrode Control circuit, 19 ... Gate electrode control circuit, 20 ... Anode electrode control circuit, 21 ... Transparent substrate, 22, 22R, 22G, 22B ... Phosphor layer, 23 ... Black matrix, 24 ... Anode electrode

Claims (7)

A cathode electrode, an insulating layer, and a gate electrode are sequentially stacked on a substrate, an opening formed through the gate electrode and the insulating layer, a conductive matrix formed at the bottom of the opening, and one end In a micro electron source device comprising a micro electron source layer composed of carbon nanotubes embedded in the matrix in a protruding state,
The micro electron source device, wherein the opening is a substantially cylindrical hole, and the micro electron source layer is a donut-shaped layer concentric with a circular bottom of the opening.   2. An inner diameter region of the minute electron source layer is a region on the minute electron source layer that cannot be cut off by a gate electrode with respect to an electric field component generated when an anode voltage is applied as a flat display device. The micro electron source device described in 1.   2. The micro-electron source device according to claim 1, wherein a ratio between the depth of the opening and the bottom diameter is 1: 6 or more. A cathode electrode, an insulating layer, and a gate electrode are sequentially stacked on the substrate. An opening formed through the gate electrode and the insulating layer, a conductive matrix formed at the bottom of the opening, and one end In a micro electron source device comprising a micro electron source layer composed of carbon nanotubes embedded in the matrix in a protruding state,
The opening is a groove having a substantially rectangular cross section, and the micro-electron source layer is a band-shaped layer extending in the longitudinal direction of the groove with a hollow slit in the center in the width direction of the groove. A micro-electron source device.   5. The slit region of the micro electron source layer is a region on the micro electron source layer that cannot be cut off by a gate electrode with respect to an electric field component generated when an anode voltage is applied as a flat display device. The micro electron source device described in 1.   5. The micro-electron source device according to claim 4, wherein the ratio of the depth of the opening to the groove width is 1: 6 or more.   A micro electron source device according to any one of claims 1 to 6, comprising a plurality of cathode panels formed on a plane, and an anode panel having a phosphor layer and an anode electrode facing the micro electron source device. A flat display device characterized by the above.

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